Semiconductor device and manufacturing method thereof
By forming deep trenches and grooves on the substrate surface and alternating layers of conductive and dielectric materials within them, the problem of increasing the etching contact hole process window when improving capacitance is solved, achieving a balance between capacitance improvement and successful etching.
Patent Information
- Application Number
- CN202511072746.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-07
AI Technical Summary
How can we increase the capacitance of deep trench capacitors while simultaneously increasing the process window for etching contact holes to prevent the upper or lower electrode from being etched through, thus reducing the process window for etching contact holes?
Deep trenches and grooves are formed on the substrate surface, and conductive material layers and dielectric material layers are formed alternately. The number of conductive material layers decreases in the direction of the grooves and is electrically isolated by the dielectric material layers. Contact plugs contact the conductive material layers to form contact areas. The projection of the contact areas is located in the grooves or the difference in vertical distance from the substrate surface is not greater than the thickness of the dielectric material layers.
While increasing the capacitance of deep trench capacitors, the process window for etching contact holes is increased to prevent the conductive material layer from being etched through, thus ensuring the successful formation of the etched contact holes.
Smart Images
Figure CN120916446A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. BACKGROUND
[0002] A deep trench capacitor (DTC) includes a lower plate, a dielectric material layer and an upper plate stacked from bottom to top, the lower plate, the dielectric material layer and the upper plate are formed in a deep trench in a substrate and extend to the substrate outside the deep trench, and the lower plate extends to the periphery of the upper plate, and a contact plug is formed on the upper plate and the lower plate outside the periphery of the upper plate. In order to improve the capacitance value of the deep trench capacitor, the thickness of the upper plate and the lower plate cannot be too thick. In addition, since the top surface of the upper plate is higher than the top surface of the lower plate, in order to enable the bottom of the contact hole where all the contact plugs are located to fall in the corresponding upper plate and lower plate at the same time, the thickness of the upper plate and the lower plate cannot be too thin, otherwise too much over-etching during etching to form the contact hole will cause the upper plate or the lower plate to be etched through, thereby reducing the process window of etching the contact hole.
[0003] Therefore, how to improve the capacitance value of the deep trench capacitor while increasing the process window of etching the contact hole is a problem to be solved. SUMMARY
[0004] The purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, which can improve the capacitance value of the deep trench capacitor while increasing the process window of etching the contact hole.
[0005] To achieve the above-mentioned purpose, the present application provides a semiconductor device, comprising:
[0006] a substrate, a first surface of the substrate is formed with a deep trench and at least one groove, the depth of the deep trench is greater than the depth of the at least one groove;
[0007] a conductive material layer and a dielectric material layer are alternately formed in the deep trench to form a deep trench capacitor, and the conductive material layer and the dielectric material layer extend to the substrate outside the deep trench and into the groove, the adjacent conductive material layers are electrically isolated by the dielectric material layer, and the number of layers of the conductive material layer decreases after passing through the groove from the deep trench to a direction away from the deep trench;
[0008] a contact plug, which is in contact with each layer of the conductive material layer to form a contact area, the projection of at least one of the contact areas on the adjacent conductive material layers is located in the projection of the groove, and the vertical distance between the contact areas on the adjacent conductive material layers and the first surface of the substrate is zero, or the difference is not greater than the thickness of the dielectric material layer between the adjacent conductive material layers.
[0009] Optionally, the number of the grooves is at least two, and the at least two grooves are sequentially arranged and sequentially reduced in depth from the deep trench to a direction away from the deep trench, and the number of the conductive material layers in the at least two grooves is sequentially reduced.
[0010] Optionally, the at least two grooves are arranged in a spaced manner or are communicated.
[0011] Optionally, the conductive material layer in the contact region farthest away from the deep trench is the conductive material layer closest to the substrate and located on the substrate.
[0012] Optionally, the semiconductor device further comprises:
[0013] an interlayer dielectric layer formed on a side of the first surface of the substrate and covering the deep trench capacitor, the contact plug penetrating through the interlayer dielectric layer, and the deep trench and the interlayer dielectric layer surface above the grooves being flush.
[0014] Optionally, the semiconductor device further comprises:
[0015] an isolation layer formed between the bottommost conductive material layer and the substrate.
[0016] The application also provides a manufacturing method of a semiconductor device, comprising:
[0017] providing a substrate;
[0018] forming a deep trench and at least one groove on a first surface of the substrate, the deep trench having a depth greater than that of the at least one groove;
[0019] forming conductive material layers and dielectric material layers, the conductive material layers and the dielectric material layers being alternately formed in the deep trench to form a deep trench capacitor, and the conductive material layers and the dielectric material layers extending to the substrate outside the deep trench and into the groove, the adjacent conductive material layers being electrically isolated by the dielectric material layers, and the number of the conductive material layers being reduced after passing through the groove from the deep trench to a direction away from the deep trench;
[0020] forming a contact plug, the contact plug being in contact with each of the conductive material layers to form a contact region, a projection of at least one of the contact regions on the adjacent conductive material layers being located within a projection of the groove, and a vertical distance difference between the contact regions on the adjacent conductive material layers and the first surface of the substrate being zero or not greater than a thickness of the dielectric material layer between the adjacent conductive material layers.
[0021] Optionally, the number of the grooves is at least two, and the at least two grooves are sequentially arranged and sequentially reduced in depth from the deep trench to a direction away from the deep trench, and the number of layers of the conductive material in the at least two grooves is sequentially reduced.
[0022] Optionally, the at least two grooves are arranged in a spaced manner or are communicated.
[0023] Optionally, the layer of the conductive material in the contact region farthest away from the deep trench is the layer of the conductive material closest to the substrate and located on the substrate.
[0024] Optionally, before forming the contact plug, the method further comprises:
[0025] forming an interlayer dielectric layer on the first surface of the substrate and covering the deep trench capacitor, the contact plug penetrating through the interlayer dielectric layer, and the surface of the interlayer dielectric layer above the deep trench and the groove being flush with each other.
[0026] Optionally, before forming the layer of the conductive material and the layer of the dielectric material, the method further comprises:
[0027] forming an isolation layer conformally formed in the deep trench and extending to the substrate outside the deep trench and in the groove.
[0028] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:
[0029] 1. The semiconductor device of the present application comprises: a substrate, a first surface of the substrate being formed with a deep trench and at least one groove, the deep trench being deeper than the at least one groove; a layer of conductive material and a layer of dielectric material, sequentially and alternately formed in the deep trench to form a deep trench capacitor, and the layer of conductive material and the layer of dielectric material extending to the substrate outside the deep trench and in the groove, adjacent layers of the conductive material being electrically isolated by the layer of dielectric material, and the number of layers of the conductive material being reduced after passing through the groove from the deep trench to a direction away from the deep trench; and a contact plug, respectively contacting each layer of the conductive material to form a contact region, a projection of at least one of the contact regions on adjacent layers of the conductive material being located in a projection of the groove, and a vertical distance between the contact regions on adjacent layers of the conductive material and the first surface of the substrate being zero or not more than the thickness of the layer of dielectric material between adjacent layers of the conductive material. Thus, the capacitance of the deep trench capacitor is increased, and the process window of etching a contact hole is also increased.
[0030] 2、The semiconductor device manufacturing method of the present application, comprising: providing a substrate; forming a deep trench and at least one recess on a first surface of the substrate, the deep trench having a depth greater than that of the at least one recess; forming layers of conductive material and layers of dielectric material, the layers of conductive material and the layers of dielectric material being alternately formed in the deep trench to form a deep trench capacitor, and the layers of conductive material and the layers of dielectric material extending onto the substrate outside the deep trench and into the recess, the layers of conductive material being electrically isolated from each other by the layers of dielectric material, and the number of layers of conductive material being reduced after passing through the recess from the deep trench to a direction away from the deep trench; and forming contact plugs, the contact plugs being in contact with the layers of conductive material to form contact regions, a projection of at least one of the contact regions on adjacent layers of conductive material being located within a projection of the recess, and a vertical distance between the contact regions on adjacent layers of conductive material and the first surface of the substrate being zero or not greater than a thickness of the layers of dielectric material between adjacent layers of conductive material. Thus, the capacitance of the deep trench capacitor is increased, and the process window for etching a contact hole is also increased. BRIEF DESCRIPTION OF DRAWINGS
[0031] Figure 1 is a structural schematic diagram of a semiconductor device according to an embodiment of the present application;
[0032] Figure 2 is a structural schematic diagram of a semiconductor device according to another embodiment of the present application;
[0033] Figure 3 is a flowchart of a semiconductor device manufacturing method according to an embodiment of the present application;
[0034] Figures 4a to 4e is Figure 3 a device schematic diagram in the semiconductor device manufacturing method shown in FIG. 8.
[0035] wherein the accompanying Figures 1 to 4e drawings are explained as follows:
[0036] 10 - substrate; 11 - deep trench; 12 - recess; 13 - isolation layer; 14 - layer of conductive material; 15 - layer of dielectric material; 16 - interlayer dielectric layer; 161 - first oxide layer; 162 - etching stop layer; 163 - second oxide layer; 17 - contact plug; 171 - contact hole. DETAILED DESCRIPTION
[0037] To make the objectives, advantages and features of the present application clearer, the semiconductor device and the manufacturing method thereof according to the present application are described in further detail below. It should be noted that the accompanying drawings are very simplified and use non-precise proportions, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.
[0038] One embodiment of the present application provides a semiconductor device, comprising: a substrate, a first surface of the substrate is formed with a deep trench and at least one recess, a depth of the deep trench is greater than a depth of the at least one recess; a layer of conductive material and a layer of dielectric material are alternately formed in the deep trench to form a deep trench capacitor, and the layer of conductive material and the layer of dielectric material extend to the substrate outside the deep trench and into the recess, adjacent layers of the conductive material are electrically isolated by the layer of dielectric material, a number of layers of the conductive material decreases after passing through the recess from a direction pointing away from the deep trench; a contact plug is in contact with each layer of the conductive material to form a contact region, a projection of at least one of the contact regions on adjacent layers of the conductive material is located within a projection of the recess, a vertical distance between the contact regions on adjacent layers of the conductive material and the first surface of the substrate is zero, or the difference between the vertical distances is not greater than a thickness of the layer of dielectric material between adjacent layers of the conductive material.
[0039] Reference will now be made to Figure 1 and Figure 2 the semiconductor device provided by the present embodiment will be described in detail, Figure 1 and Figure 2 is also a schematic longitudinal sectional view.
[0040] In one embodiment, the semiconductor device can be an interposer or the like. In other embodiments, the semiconductor device can also be other devices other than an interposer.
[0041] The substrate 10 has a first surface and a second surface opposite to each other.
[0042] The first surface of the substrate 10 is formed with a deep trench 11 and at least one recess 12, a depth of the deep trench 11 is greater than a depth of the at least one recess 12.
[0043] The substrate 10 can be made of any suitable material known to those skilled in the art, for example, can be at least one of the following materials: silicon, germanium, germanium silicon, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide, or semiconductor on insulator (SOI, such as silicon on insulator), etc.
[0044] In one embodiment, a groove (not shown) can also be formed in the substrate 10 as an alignment mark, so that the alignment mark can be used for alignment when subsequent devices such as deep trench capacitors are manufactured.
[0045] The depth of the deep trench 11 is greater than the depth of the groove; the depth of the recess 12 is less than, equal to, or greater than the depth of the groove.
[0046] Conductive material layer 14 and dielectric material layer 15 are alternately formed in the deep trench 11 to form a deep trench capacitor. The conductive material layer 14 and the dielectric material layer 15 extend to the substrate 10 on the periphery of the deep trench 11 and into the groove 12. Adjacent conductive material layers 14 are electrically isolated from each other by the dielectric material layer 15. From the deep trench 11 to the direction away from the deep trench 11, the number of conductive material layers 14 decreases after passing through the groove 12.
[0047] like Figure 1 and Figure 2 As shown, in two adjacent conductive material layers 14, the lower conductive material layer 14 extends to the periphery of the upper conductive material layer 14, that is, the area of the lower conductive material layer 14 extending to the periphery of the deep trench 11 and the recess 12 is greater than the area of the upper conductive material layer 14 extending to the periphery of the deep trench 11 and the recess 12. The dielectric material layer 15 may be located only between two adjacent conductive material layers 14; the dielectric material layer 15 between two adjacent conductive material layers 14 may also extend to the lower conductive material layer 14 on the periphery of the upper conductive material layer 14.
[0048] In one embodiment, the topmost conductive material layer 14 or the topmost dielectric material layer 15 fills the deep trench 11; or, in another embodiment, the topmost conductive material layer 14 or the topmost dielectric material layer 15 does not fill the deep trench 11.
[0049] The conductive material layer 14 is any conductive material known to those skilled in the art. Preferably, the conductive material layer 14 is at least one of a metal, a metal nitride, and polycrystalline silicon.
[0050] The dielectric material layer 15 can be any insulating material known to those skilled in the art. Preferably, the dielectric material layer 15 is made of a material with a dielectric constant greater than 7.9 (7.9 is the dielectric constant of silicon nitride), such as a metal oxide material, to achieve a higher capacitance density in the deep trench capacitor. It should be noted that the dielectric material layer 15 can also be made of other materials such as silicon oxide or silicon oxynitride.
[0051] In one embodiment, the conductive material layer 14 has N layers, and the number of grooves 12 is N or N-1, where N is a positive integer and N≥2.
[0052] In an embodiment, the number of the grooves 12 is at least two, the at least two grooves 12 are arranged in sequence and the depths of the at least two grooves 12 are reduced in sequence from the deep trench 11 to the direction away from the deep trench 11, and the number of layers of the conductive material layer 14 in the at least two grooves 12 is also reduced in sequence, wherein the number of layers is reduced by at least one layer, and the number of layers reduced by each groove 12 can be the same or different, and is arranged according to requirements. Figure 1 As shown in FIG. 2, the number of layers of the conductive material layer 14 is two, the number of the grooves 12 is one, and the number of layers of the conductive material layer 14 is reduced from two to one after passing through the groove 12 from the deep trench 11 to the direction away from the deep trench 11. Figure 2 As shown in FIG. 3, the number of layers of the conductive material layer 14 is three, the number of the grooves 12 is two, the number of layers of the conductive material layer 14 is reduced from three to two after passing through the first groove 12 from the deep trench 11 to the direction away from the deep trench 11, and the number of layers of the conductive material layer 14 is reduced from two to one after passing through the second groove 12.
[0053] The at least two grooves 12 are arranged in a spaced manner or are communicated.
[0054] The semiconductor device further comprises an isolation layer 13 formed between the bottommost conductive material layer 14 and the substrate 10, and used to isolate the substrate 10 from the bottommost conductive material layer 14.
[0055] The material of the isolation layer 13 can be at least one of silicon oxide, silicon oxynitride, and silicon nitride.
[0056] The contact plug 17 is in contact with each layer of the conductive material layer 14 to form a contact region, the projection of at least one of the contact regions on the adjacent conductive material layer 14 is located within the projection of the groove 12, and the difference between the vertical distances of the contact regions on the adjacent conductive material layers 14 from the first surface of the substrate 10 is zero, or the difference is not greater than the thickness of the dielectric material layer 15 between the adjacent conductive material layers 14.
[0057] As shown in FIG. 2, the number of layers of the conductive material layer 14 is two, the number of the grooves 12 is one, and the number of layers of the conductive material layer 14 is reduced from two to one after passing through the groove 12 from the deep trench 11 to the direction away from the deep trench 11. Figure 1 As shown in FIG. 3, the number of layers of the conductive material layer 14 is three, the number of the grooves 12 is two, the number of layers of the conductive material layer 14 is reduced from three to two after passing through the first groove 12 from the deep trench 11 to the direction away from the deep trench 11, and the number of layers of the conductive material layer 14 is reduced from two to one after passing through the second groove 12.
[0058] As shown in Figure 2 The number of layers of the conductive material layers 14 is three, and the contact plugs 17 are in contact with the three layers of the conductive material layers 14 to form three contact regions. From the deep trench 11 to the direction away from the deep trench 11, the contact plug 17 is in contact with the upper layer of the conductive material layer 14 in the first groove 12 to form a first contact region, the contact plug 17 is in contact with the middle layer of the conductive material layer 14 in the second groove 12 to form a second contact region, and the contact plug 17 is in contact with the lower layer of the conductive material layer 14 on the substrate 10 outside the two grooves 12 to form a third contact region. The projection of the first contact region is located in the projection of the first groove 12, the projection of the second contact region is located in the projection of the second groove 12, and the projection of the third contact region is located on the substrate 10 outside the two grooves 12. The projection in this application refers to the projection on the first surface of the substrate 10. The number of contact regions formed on the same layer of the conductive material layer 14 is not specifically limited, that is, the number of the first contact region, the second contact region, and the third contact region is at least one. The vertical distance between the first contact region and the second contact region from the first surface of the substrate 10 is zero, or the difference is not greater than the thickness of the dielectric material layer 15 between the upper layer of the conductive material layer 14 and the middle layer of the conductive material layer 14; the vertical distance between the second contact region and the third contact region from the first surface of the substrate 10 is zero, or the difference is not greater than the thickness of the dielectric material layer 15 between the middle layer of the conductive material layer 14 and the lower layer of the conductive material layer 14.
[0059] In an embodiment, one groove 12 corresponds to one contact region, or one groove 12 corresponds to at least two contact regions.
[0060] The conductive material layer 14 in the contact region farthest from the deep trench 11 is the conductive material layer 14 closest to the substrate 10 and located on the substrate 10, or the conductive material layer 14 in the contact region farthest from the deep trench 11 is the conductive material layer 14 closest to the substrate 10 and located in the projection of the groove 12.
[0061] The contact plug 17 can also be electrically connected to a metal interconnection structure (not shown) so that a voltage can be applied to the corresponding conductive material layer 14 through the metal interconnection structure and the contact plug 17.
[0062] When the next one of the conductive material layers 14 of the two adjacent ones of the conductive material layers 14 extends to the periphery of the previous one of the conductive material layers 14, the contact plug 17 is formed on the portion of the next one of the conductive material layers 14 extending to the periphery of the previous one of the conductive material layers 14 and on the topmost one of the conductive material layers 14.
[0063] If the dielectric material layer 15 between the next one of the conductive material layers 14 of the two adjacent ones of the conductive material layers 14 also extends to the next one of the conductive material layers 14 at the periphery of the previous one of the conductive material layers 14, the contact plug 17 also penetrates the dielectric material layer 15 on the next one of the conductive material layers 14 at the periphery of the previous one of the conductive material layers 14 to contact the next one of the conductive material layers 14.
[0064] The semiconductor device further comprises an interlayer dielectric layer 16 formed on the first surface side of the substrate 10 and covering the deep trench capacitor, the contact plug 17 penetrating the interlayer dielectric layer 16 to electrically connect with the corresponding conductive material layer 14.
[0065] When the topmost one of the conductive material layers 14 or the dielectric material layer 15 does not fill the deep trench 11, the interlayer dielectric layer 16 seals the deep trench 11. The interlayer dielectric layer 16 can fill or not fill the deep trench 11.
[0066] The contact plug 17 is formed in the interlayer dielectric layer 16, and the interlayer dielectric layer 16 exposes the top surface of the contact plug 17.
[0067] Other dielectric layers (not shown) can also be formed on the interlayer dielectric layer 16, and the metal interconnection structure is formed in the other dielectric layers.
[0068] The surface of the interlayer dielectric layer 16 above the deep trench 11 and the recess 12 is flush with the surface of the interlayer dielectric layer 16 above the periphery of the deep trench 11 and the recess 12. In an embodiment, the interlayer dielectric layer 16 comprises at least two stacked insulating layers, and preferably the top surfaces of the insulating layers at the same layer above the deep trench 11, above the recess 12, and above the periphery of the deep trench 11 and the recess 12 are flush.
[0069] In the embodiment shown in FIGS. 1A and 1B, the interlayer dielectric layer 16 comprises a first oxide layer 161, an etching stop layer 162, and a second oxide layer 163 stacked from bottom to top, and the top surfaces of the first oxide layer 161, the etching stop layer 162, and the second oxide layer 163 above the deep trench 11, above the recess 12, and above the periphery of the deep trench 11 and the recess 12 are flush. Figure 1 and Figure 2 In the embodiment shown in FIGS. 1A and 1B, the interlayer dielectric layer 16 comprises a first oxide layer 161, an etching stop layer 162, and a second oxide layer 163 stacked from bottom to top, and the top surfaces of the first oxide layer 161, the etching stop layer 162, and the second oxide layer 163 above the deep trench 11, above the recess 12, and above the periphery of the deep trench 11 and the recess 12 are flush.
[0070] The interlayer dielectric layer 16 can include one or a combination of at least two of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, and NDC (Nitrogen doped Silicon Carbide), BPSG (Boron Phosphorus Silicate Glass), USG (Undoped Silicate Glass), SOG (Spin-on-glass), etc.
[0071] As can be seen from the above, in the semiconductor device provided by the present application, since the first surface of the substrate 10 is formed with the at least one recess 12, the number of layers of the conductive material layer 14 is reduced after passing through the recess 12 in the direction away from the deep trench 11 from the deep trench 11, and since the contact plug 17 is in contact with each layer of the conductive material layer 14 to form a contact region, the projection of at least one of the contact regions on the adjacent conductive material layer 14 is located within the projection of the recess 12, the vertical distance between the contact region on the adjacent conductive material layer 14 and the first surface of the substrate 10 is zero, or the difference is not greater than the thickness of the dielectric material layer 15 between the adjacent conductive material layers 14, that is, the height of each layer of the conductive material layer 14 except the bottom layer in contact with the contact plug 17 is reduced, so that the top surface of each layer of the conductive material layer 14 in contact with each contact plug 17 is flush or close to flush, thereby enabling the etching to stop in the conductive material layer 14 contacted by each contact plug 17 when etching all the contact holes 171 at the same time, avoiding the conductive material layer 14 being etched through due to the thickness of the conductive material layer 14 being too thin when the thickness of the conductive material layer 14 is thinned to increase the capacitance of the deep trench capacitor, so that the process window of etching the contact hole 171 is increased while increasing the capacitance of the deep trench capacitor.
[0072] In addition, since the first surface of the substrate 10 is formed with the at least one recess 12, the conductive material layer 14 and the dielectric material layer 15 also extend into the recess 12, so that the area of the conductive material layer 14 within the unit area of the substrate 10 is increased, thereby increasing the capacitance of the deep trench capacitor.
[0073] An embodiment of the present application provides a manufacturing method of a semiconductor device, wherein the features represented by the same names are referred to the above content, which will not be repeated here. Referring to Figure 3 As can be seen from the above, the manufacturing method of the semiconductor device includes: Figure 3
[0074] Step S1, providing a substrate;
[0075] Step S2, forming a deep trench and at least one recess on the first surface of the substrate, the deep trench having a depth greater than that of the at least one recess;
[0076] Step S3, forming layers of conductive material and layers of dielectric material, the layers of conductive material and the layers of dielectric material being formed in the deep trench in sequence and alternately to form a deep trench capacitor, and the layers of conductive material and the layers of dielectric material extending onto the substrate outside the periphery of the deep trench and into the recess, adjacent layers of conductive material being electrically isolated by the layers of dielectric material, the number of layers of conductive material being reduced after passing through the recess in a direction away from the deep trench;
[0077] Step S4, forming contact plugs, the contact plugs respectively contacting the layers of conductive material to form contact regions, a projection of at least one of the contact regions on adjacent layers of conductive material being located within a projection of the recess, the vertical distance between the contact regions on adjacent layers of conductive material and the first surface of the substrate being zero, or the difference in vertical distance between the contact regions on adjacent layers of conductive material and the first surface of the substrate being not greater than the thickness of the layers of dielectric material between adjacent layers of conductive material.
[0078] Reference will now be made to Figure 1 , Figure 2 and Figures 4a to 4e to describe in detail the method of manufacturing a semiconductor device according to the present embodiment, Figure 1 , Figure 2 and Figures 4a to 4e are also schematic longitudinal cross-sectional views, Figures 4a to 4e and Figure 1 are schematic views of steps of forming a semiconductor device.
[0079] According to step S1, a substrate 10 is provided.
[0080] The substrate 10 has opposite first and second surfaces.
[0081] According to step S2, a deep trench 11 and at least one recess 12 are formed on the first surface of the substrate 10, the deep trench 11 having a depth greater than that of the at least one recess 12, as shown in Figure 4a .
[0082] In an embodiment, a trench (not shown) can also be formed in the substrate 10 before forming the deep trench 11, for use as an alignment mark to enable alignment with the alignment mark when subsequently manufacturing devices such as deep trench capacitors.
[0083] Preferably, the trench and the recess 12 can be etched simultaneously to simplify the process steps. In this case, the same phase shift mask (PSM mask) can be used when performing the corresponding photolithography step, while the depths of the trench and the recess 12 are different.
[0084] In other embodiments, the trench and the recess 12 can be etched separately, in which case different masks are used when performing the corresponding photolithography steps.
[0085] According to step S3, as shown in FIG. 3, a layer of conductive material 14 and a layer of dielectric material 15 are formed, which are alternately arranged in the deep trench 11 to form a deep trench capacitor, and the layer of conductive material 14 and the layer of dielectric material 15 extend to the substrate 10 outside the deep trench 11 and into the recess 12. The layers of conductive material 14 are electrically isolated by the layer of dielectric material 15 between adjacent layers of conductive material 14. The number of layers of conductive material 14 decreases as the layers of conductive material 14 move away from the deep trench 11 through the recess 12. Figure 4b
[0086] The layer of conductive material 14 and the layer of dielectric material 15 are formed by deposition and etching processes known in the art.
[0087] Before the layer of conductive material 14 and the layer of dielectric material 15 are formed, the method for manufacturing the semiconductor device further includes forming an isolation layer 13, which is conformally formed in the deep trench 11 and extends to the substrate 10 outside the deep trench 11 and into the recess 12. The isolation layer 13 is used to isolate the substrate 10 from the bottom layer of the layer of conductive material 14.
[0088] The number of recesses 12 is at least two, which are arranged in sequence and have depths that decrease in sequence as the layers of conductive material 14 move away from the deep trench 11 through the recess 12. The number of layers of conductive material 14 in the at least two recesses 12 also decreases in sequence.
[0089] The at least two recesses 12 are arranged in isolation or in communication.
[0090] According to step S4, as shown in FIG. 4, the isolation layer 13 is removed, and the layer of conductive material 14 and the layer of dielectric material 15 are formed, which are alternately arranged in the deep trench 11 to form a deep trench capacitor, and the layer of conductive material 14 and the layer of dielectric material 15 extend to the substrate 10 outside the deep trench 11 and into the recess 12. The layers of conductive material 14 are electrically isolated by the layer of dielectric material 15 between adjacent layers of conductive material 14. The number of layers of conductive material 14 decreases as the layers of conductive material 14 move away from the deep trench 11 through the recess 12. Figure 1 Figure 2 Figure 4e As shown, contact plugs 17 are formed, and each contact plug 17 contacts each of the conductive material layers 14 to form a contact area. The projection of at least one of the contact areas on adjacent conductive material layers 14 is located within the projection of the groove 12. The difference in vertical distance between the contact areas on adjacent conductive material layers 14 and the first surface of the substrate 10 is zero, or the difference is not greater than the thickness of the dielectric material layer 15 between adjacent conductive material layers 14.
[0091] The conductive material layer 14 in the contact area furthest from the deep trench 11 is the conductive material layer 14 closest to the substrate 10 and is located on the substrate 10.
[0092] Before forming the contact plug 17, as Figure 4c As shown, the method for manufacturing the semiconductor device further includes: forming an interlayer dielectric layer 16 on one side of the first surface of the substrate 10 and covering the deep trench capacitor, wherein the contact plug 17 penetrates the interlayer dielectric layer 16 to be electrically connected to the corresponding conductive material layer 14.
[0093] The steps of forming the contact plug 17 may include: as follows Figure 4d As shown, the interlayer dielectric layer 16 is etched to form a contact hole 171, which penetrates the interlayer dielectric layer 16 and exposes the corresponding conductive material layer 14; as Figure 4e As shown, conductive material is filled into the contact hole 171 to form the contact plug 17, and the interlayer dielectric layer 16 exposes the top surface of the contact plug 17.
[0094] Other dielectric layers (not shown) may also be formed on the interlayer dielectric layer 16, and a metal interconnect structure (not shown) may be electrically connected to the contact plug 17. The metal interconnect structure is formed in the other dielectric layers, so that a voltage can be applied to the corresponding conductive material layer 14 through the metal interconnect structure and the contact plug 17.
[0095] The deep trench 11 is flush with the surface of the interlayer dielectric layer 16 above the recess 12, and also flush with the surface of the interlayer dielectric layer 16 above the substrate 10 surrounding the deep trench 11 and the recess 12. In one embodiment, the interlayer dielectric layer 16 comprises at least two stacked insulating layers, preferably flush with the top surfaces of the insulating layers of the same layer above the deep trench 11, above the recess 12, and above the substrate 10 surrounding the deep trench 11 and the recess 12. A planarization process may be performed on each insulating layer after its formation to ensure that the top surfaces of each insulating layer are flush.
[0096] From the above, in the method for manufacturing the semiconductor device, by forming the at least one recess 12 on the first surface of the substrate 10, the conductive material layers 14 and the dielectric material layers 15 are alternately formed in the deep trench 11 and extend to the periphery of the deep trench 11 on the substrate 10 and in the recess 12. The number of the conductive material layers 14 is reduced after passing through the recess 12 from the deep trench 11 to a direction away from the deep trench 11. The contact regions are formed by the contact plugs 17 contacting the conductive material layers 14 respectively. The projection of at least one of the contact regions on the adjacent conductive material layers 14 is located in the projection of the recess 12. The vertical distance between the contact regions on the adjacent conductive material layers 14 and the first surface of the substrate 10 is zero or not more than the thickness of the dielectric material layer 15 between the adjacent conductive material layers 14. The height of each of the conductive material layers 14 except the bottom layer contacting the contact plug 17 is reduced, so that the top surface of each of the conductive material layers 14 contacting the contact plug 17 is flush or close to flush. Thus, when etching the contact holes 171 in which the contact plugs 17 are located, the etching can be stopped in the conductive material layers 14 contacting the contact plugs 17, so that the thickness of the conductive material layers 14 can be reduced to increase the capacitance of the deep trench capacitor without being etched through.
[0097] In addition, the conductive material layers 14 and the dielectric material layers 15 extend into the recess 12 formed on the first surface of the substrate 10, so that the area of the conductive material layers 14 in the unit area of the substrate 10 is increased, and the capacitance of the deep trench capacitor is increased.
[0098] The above description is only a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application. Any modification or change made by those skilled in the art based on the above disclosure is within the scope of the claims of the present application.
Claims
1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate, a first surface of which is formed with a deep trench and at least one recess, the deep trench having a depth greater than that of the at least one recess; a layer of conductive material and a layer of dielectric material are alternately formed in the deep trench to form a deep trench capacitor, and the layer of conductive material and the layer of dielectric material extend to the substrate outside the deep trench and into the recess, adjacent layers of the layer of conductive material are electrically isolated by the layer of dielectric material, and the number of layers of the layer of conductive material decreases after passing through the recess from a direction pointing away from the deep trench; a contact plug is in contact with each layer of the layer of conductive material to form a contact region, a projection of at least one of the contact regions on adjacent layers of the layer of conductive material is located within a projection of the recess, and a difference in vertical distance between the contact regions on adjacent layers of the layer of conductive material and the first surface of the substrate is zero or not greater than the thickness of the layer of dielectric material between adjacent layers of the layer of conductive material.
2. The semiconductor device of claim 1, wherein, The number of recesses is at least two, and the at least two recesses are sequentially arranged and have depths decreasing in sequence from a direction pointing away from the deep trench, and the number of layers of the layer of conductive material in the at least two recesses also decreases in sequence.
3. The semiconductor device of claim 2, wherein, The at least two recesses are arranged in a spaced-apart manner or are connected.
4. The semiconductor device of claim 2, wherein, The layer of conductive material in the contact region farthest from the deep trench is the layer of conductive material closest to the substrate and located on the substrate.
5. The semiconductor device of claim 1, wherein, The semiconductor device further comprises: an interlayer dielectric layer formed on one side of the first surface of the substrate and covering the deep trench capacitor, the contact plug penetrating through the interlayer dielectric layer, and the surface of the interlayer dielectric layer above the deep trench and the recess being flush.
6. The semiconductor device of claim 1, wherein, The semiconductor device further comprises: an isolation layer formed between the bottommost layer of the layer of conductive material and the substrate.
7. A method of manufacturing a semiconductor device, characterized by The semiconductor device comprises: providing a substrate; forming a deep trench and at least one recess on a first surface of the substrate, the deep trench having a depth greater than that of the at least one recess; forming a layer of conductive material and a layer of dielectric material, the layer of conductive material and the layer of dielectric material being alternately formed in the deep trench to form a deep trench capacitor, and the layer of conductive material and the layer of dielectric material extending to the substrate outside the deep trench and into the recess, adjacent layers of the layer of conductive material being electrically isolated by the layer of dielectric material, and the number of layers of the layer of conductive material decreasing after passing through the recess from a direction pointing away from the deep trench; forming a contact plug in contact with each layer of the layer of conductive material to form a contact region, a projection of at least one of the contact regions on adjacent layers of the layer of conductive material being located within a projection of the recess, and a difference in vertical distance between the contact regions on adjacent layers of the layer of conductive material and the first surface of the substrate being zero or not greater than the thickness of the layer of dielectric material between adjacent layers of the layer of conductive material.
8. The method of manufacturing a semiconductor device according to Claim 7, wherein The number of the recesses is at least two, the at least two recesses are sequentially arranged and sequentially reduced in depth from the deep trench to a direction away from the deep trench, and the number of the conductive material layers in the at least two recesses is sequentially reduced.
9. The method of manufacturing a semiconductor device according to Claim 8, wherein The at least two recesses are arranged in a spaced manner or are communicated.
10. The method of manufacturing a semiconductor device according to Claim 8, wherein The conductive material layer in the contact region farthest away from the deep trench is a conductive material layer closest to the substrate and located on the substrate.
11. The method of manufacturing a semiconductor device according to Claim 7, wherein Before forming the contact plug, the method for manufacturing the semiconductor device further comprises: forming an interlayer dielectric layer on a side of the first surface of the substrate and covering the deep trench capacitor, the contact plug penetrating through the interlayer dielectric layer, and the deep trench and the interlayer dielectric layer surface above the recess being flush.
12. The method of manufacturing a semiconductor device according to Claim 7, wherein Before forming the conductive material layer and the dielectric material layer, the method for manufacturing the semiconductor device further comprises: forming an isolation layer, the isolation layer being conformally formed in the deep trench and extending to the substrate on the periphery of the deep trench and in the recess.