Gallium nitride transistor and method of manufacture

Abstract

The application discloses a gallium nitride transistor and a preparation method thereof. The gallium nitride transistor comprises a composite substrate layer and a gallium nitride auxiliary layer and a functional layer which are arranged on the composite substrate layer in a stack mode. The composite substrate layer comprises a base substrate and an epitaxial layer, and the base substrate and the epitaxial layer are monocrystalline silicon carbide layers. The resistivity of the epitaxial layer is higher than that of the base substrate. The composite silicon carbide substrate composed of a low-cost low-resistivity silicon carbide substrate and an epitaxially grown high-resistivity silicon carbide layer can combine the properties of high-resistivity, high thermal conductivity and high mechanical strength of silicon carbide and greatly reduce the material cost. That is, the gallium nitride transistor with the composite silicon carbide substrate structure provided by the application is more cost-effective than a uniform semi-insulating silicon carbide substrate, and all ideal material properties of silicon carbide suitable for high-frequency and high-power applications are retained.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a gallium nitride transistor and its fabrication method. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN-HEMTs) are widely used in numerous power electronics applications. GaN-HEMT structures can be epitaxially grown on various substrate materials via MOCVD, such as AlN, GaN, Si, SiC, and sapphire. The performance of these devices is heavily dependent on the substrate material; for example, sapphire substrates offer better dynamic on-resistance performance, while SiC substrates provide better heat dissipation. In practice, the choice of device substrate material depends on many factors, including cost, size (2 to 12 inches), inherent material properties (warp resistance, resistivity, and thermal conductivity of thicker GaN epitaxial layers), and the final device's electrical performance and thermal management.

[0003] Currently, the SiC substrates with sizes of 4 to 8 inches are suitable for mass production, enabling the fabrication of GaN HEMT devices for RF front-ends and PA applications, with optimal thermal management through the SiC substrate.

[0004] However, using SiC substrates results in very high manufacturing costs for the entire device due to the limitations of the material itself (costing 2 to 20 times more than Si). Summary of the Invention

[0005] The purpose of this application is to provide a gallium nitride transistor and its fabrication method, which reduces costs while ensuring transistor performance.

[0006] To achieve the above objectives, this application provides the following solution:

[0007] In a first aspect, this application provides a gallium nitride transistor, comprising:

[0008] A composite substrate layer and auxiliary and functional layers stacked on the composite substrate layer;

[0009] The composite substrate layer includes a base substrate and an epitaxial layer, wherein the base substrate and the epitaxial layer are single-crystal silicon carbide layers, and the resistivity of the epitaxial layer is higher than that of the base substrate.

[0010] Optionally, in some embodiments, the gallium nitride transistor has a 3C, 4H, or 6H lattice structure in the composite substrate layer of the single-crystal silicon carbide.

[0011] Optionally, in some embodiments, the thickness of the base substrate in the composite substrate layer of the gallium nitride transistor is greater than the thickness of the epitaxial layer.

[0012] Optionally, in some embodiments, the gallium nitride transistor has an epitaxial layer comprising one or more silicon carbide layers, wherein the resistivity of each silicon carbide layer in the multilayer silicon carbide layers increases sequentially from the substrate to the auxiliary layer.

[0013] Optionally, in some embodiments, the thickness of each silicon carbide layer in the epitaxial layer of the gallium nitride transistor is 5~50 μm.

[0014] Optionally, in some embodiments, the thickness of the substrate of the gallium nitride transistor is 300~1000μm, and the total thickness of the epitaxial layer is 5~300μm.

[0015] Optionally, in some embodiments, the auxiliary layer of the gallium nitride transistor is a buffer layer, and the functional layer includes a channel layer and a barrier layer stacked on the buffer layer, as well as a source, gate, and drain patterned on the barrier layer.

[0016] On the other hand, this application provides a method for fabricating a gallium nitride transistor, the method being used to fabricate a gallium nitride transistor as described in the first aspect, the method comprising:

[0017] An epitaxial layer of single-crystal silicon carbide is formed on a substrate of single-crystal silicon carbide, wherein the resistivity of the substrate is less than the resistivity of the epitaxial layer.

[0018] An auxiliary layer and a functional layer are sequentially stacked on the epitaxial layer.

[0019] According to the specific embodiments provided in this application, the following technical effects are disclosed:

[0020] This application provides a gallium nitride (GaN) transistor and its fabrication method. The transistor substrate is configured as a composite substrate layer comprising a low-resistivity base substrate and a high-resistivity epitaxial layer. The presence of a low-resistivity silicon carbide layer in the base substrate significantly reduces the material cost of the substrate portion. Furthermore, the high-resistivity epitaxial layer formed on the low-resistivity base substrate ensures the electrical and thermal management performance of the device substrate. In other words, the structure provided in this application, through a composite SiC substrate composed of a low-cost, low-resistivity SiC substrate and an epitaxially grown high-resistivity SiC layer, allows the device to combine the high resistivity, high thermal conductivity, and high mechanical strength properties of silicon carbide while significantly reducing material costs. Therefore, the GaN transistor with the composite SiC substrate structure provided in this application is more cost-effective than that with a uniform semi-insulating SiC substrate and retains all the ideal material properties of SiC suitable for high-frequency and high-power applications. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a gallium nitride transistor in related technologies;

[0022] Figure 2 This is a schematic diagram of the structure of a gallium nitride transistor according to some embodiments of this application;

[0023] Figure 3 This is a schematic diagram of the structure of a gallium nitride transistor according to some embodiments of this application;

[0024] Figure 4 This is a schematic flowchart illustrating a gallium nitride transistor fabrication method according to some embodiments of this application. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0026] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] As can be understood, the device structure of a gallium nitride transistor (GaN HEMT) mainly includes a substrate, a buffer layer, a channel layer, and a barrier layer. Common types include depletion-mode and enhancement-mode transistors.

[0028] In depletion-mode gallium nitride (GaN) transistors, a Si substrate is typically used as the substrate, with a high-resistivity GaN crystal layer grown on the Si substrate as the channel layer. An aluminum nitride (AlGaN) insulating layer is usually added between the GaN layer and the Si substrate as a buffer layer to isolate the device from the substrate. The AlGaN layer is located between the GaN layer and the gate, source, and drain electrodes. A two-dimensional electron gas (2DEG) with high electron mobility and low resistance is generated between the AlGaN and GaN layers. At zero gate voltage, the device is in the on-state due to the strong polarization effect of the nitride.

[0029] Enhancement-mode GaN HEMTs are P-type gate structures, meaning a positively charged P-type GaN gate is grown on an AlGaN barrier layer. The P-type GaN layer can pull up the energy band of the AlGaN barrier layer, effectively depleting the 2DEG to achieve normally-off characteristics. When a sufficient positive gate-source voltage (VGS) is applied, the internal electric field of the P-GaN layer is weakened, the 2DEG concentration increases, forming a conduction channel, and the device turns on; when VGS decreases and falls below the threshold voltage, the channel turns off.

[0030] like Figure 1As shown, regardless of whether it is depletion-mode or enhancement-mode, the GaN HEMT device structure in the related technology is fabricated on a uniform substrate material (Si, SiC, AlN, GaN or sapphire) with a uniform resistivity distribution.

[0031] When cost is the primary consideration, in order to reduce device cost, low-cost silicon or sapphire will be chosen as the substrate, which ultimately results in higher vertical leakage and poorer dynamic on-resistance performance (devices with silicon substrates) or poorer heat dissipation (devices with sapphire substrates).

[0032] This application aims to reduce device cost while ensuring device performance and avoid the constraint of substrate cost on device performance. The provided single-crystal silicon carbide composite substrate (a composite SiC substrate consisting of a low-cost, low-resistivity SiC substrate and an epitaxially grown high-resistivity SiC layer) transistor device combines all the necessary material properties, such as high resistivity (semi-insulating SiC > 10). 6 The high thermal conductivity (SiC > Si > Sapphire) and high mechanical strength (SiC > Sapphire > Si) ultimately enable the growth of GaN HEMT device structures on them at low cost.

[0033] Figure 2 The diagram shown is a schematic diagram of the structure of a GaN HEMT according to some embodiments of this application.

[0034] like Figure 2 As shown, the structure may include:

[0035] A composite substrate layer and auxiliary and functional layers stacked on the composite substrate layer;

[0036] The composite substrate layer includes a base substrate and an epitaxial layer, wherein the base substrate and the epitaxial layer are single-crystal silicon carbide layers, and the resistivity of the epitaxial layer is higher than that of the base substrate.

[0037] Specifically, in this embodiment of the application, in order to reduce the cost of gallium nitride transistor devices and ensure their substrate performance, such as electrical performance and thermal management performance, a composite substrate structure is provided. That is, the structure of the transistor may include a composite substrate layer, an auxiliary layer disposed on the composite substrate layer, and a functional layer disposed on the auxiliary layer.

[0038] The composite substrate layer may include a base substrate and an epitaxial layer, both of which are single-crystal silicon carbide layers to ensure the stability of the structure between each layer.

[0039] Furthermore, the resistivity of the silicon carbide forming the substrate is lower than that of the silicon carbide forming the epitaxial layer.

[0040] For example, the resistivity of the substrate can be 400 Ω·m, and the resistivity of the epitaxial layer can be 10 Ω·m. 6 Ω·m or above. The resistivity of the substrate and epitaxial layer mentioned above is only for illustrative purposes and can be flexibly adjusted according to the actual application requirements of the device.

[0041] That is, the substrate in this structure can be replaced with an inexpensive commercial SiC substrate with any background resistivity (e.g., resistivity > 10). 5 A semi-insulating single-crystal SiC epitaxial layer (e.g., thickness > 5 μm, resistivity > 10 Ω·m) is then grown on the starting SiC substrate. 6 Ω·m).

[0042] It is understood that in the gallium nitride transistors of this application, the device substrate is configured as a composite substrate layer comprising a low-resistivity base substrate and a high-resistivity epitaxial layer. The presence of a low-resistivity silicon carbide layer in the base substrate significantly reduces the material cost of the substrate portion. Furthermore, the high-resistivity epitaxial layer formed on the low-resistivity base substrate ensures the electrical and thermal management performance of the device substrate. In other words, the structure provided in this application, through a composite SiC substrate composed of a low-cost, low-resistivity SiC substrate and an epitaxially grown high-resistivity SiC layer, allows the device to combine the high resistivity, high thermal conductivity, and high mechanical strength properties of silicon carbide while significantly reducing material costs.

[0043] The gallium nitride transistor with the composite SiC substrate structure provided in this application embodiment is more cost-effective than a uniform semi-insulating SiC substrate, while retaining all the ideal material properties of SiC suitable for high-frequency and high-power applications.

[0044] Optionally, in some embodiments of this application, the single-crystal silicon carbide in the composite substrate layer has a 3C, 4H, or 6H lattice structure, thereby enabling good lattice matching between the substrate and the epitaxial layer, as well as between the epitaxial layer and the auxiliary layer, ensuring the structural stability of the transistor.

[0045] In other words, the basic structural unit of single-crystal silicon carbide consists of C atoms and Si atoms forming a Si-C tetrahedron. The coordination number of both Si and C atoms is 4, meaning that each C atom is surrounded by 4 Si atoms and each Si atom is surrounded by 4 C atoms.

[0046] Correspondingly, in SiC crystals, the Si-C double atomic layers are stacked along the

[0001] direction. Due to the small difference in bond energy between layers, different connection modes are easily generated between atomic layers, resulting in SiC having a variety of crystal forms.

[0047] In the embodiments of this application, the silicon carbide crystal form of the substrate and the epitaxial layer can be selected as 4H-SiC, that is, a 4H crystal structure stacked in the order of "ABCB". This ensures that the crystal forms of the two are well matched when the epitaxial layer is grown on the substrate, so as to ensure the stability of the structure.

[0048] Alternatively, in other embodiments, the single-crystal silicon carbide in the composite substrate layer can be selected with a 3C or 6H lattice structure, which can also ensure good matching of crystal forms between layers to ensure structural stability.

[0049] Furthermore, for auxiliary layers, i.e. buffer layers in gallium nitride transistors, such as aluminum nitride formed on epitaxial layers, when used as buffer layers, the good matching of compound structures between layers can also be achieved through the crystal structure of single-crystal silicon carbide.

[0050] Optionally, in some embodiments of this application, in order to effectively reduce costs, the thickness of the base substrate in the composite substrate layer is greater than the thickness of the epitaxial layer.

[0051] For example, the thickness of the base substrate in this composite substrate layer can be 350 μm, and the total thickness of the epitaxial layer can be 10 μm.

[0052] It is understandable that the thickness of the base substrate and the epitaxial layer in a composite substrate can be determined according to the actual situation. That is, the thickness of both can be flexibly adjusted according to the performance requirements of the device and the cost indicators.

[0053] Optionally, in some embodiments of this application, in order to further reduce device cost and ensure device performance, the epitaxial layer may include one or more silicon carbide layers, and the resistivity of each silicon carbide layer increases sequentially from the substrate to the auxiliary layer.

[0054] Specifically, in this embodiment, the epitaxial layer can be configured as a multilayer composite structure, that is, it can be configured as a single-layer or multi-layer silicon carbide stacked structure, and the resistivity of each silicon carbide layer gradually increases from the substrate to the auxiliary layer, thereby achieving maximum cost savings, and ensuring that the resistivity of the single-crystal silicon carbide in the top layer of the substrate meets the device performance requirements.

[0055] For example, in some embodiments, the thickness of the silicon carbide layer in the stack can be set to 10 μm, and the resistivity can gradually increase from the substrate to the functional layer.

[0056] Furthermore, in some embodiments, the resistivity of the silicon carbide layer adjacent to the auxiliary layer is the highest, which can be 10. 6 It is above Ω·m and decreases sequentially as it approaches the substrate.

[0057] It is understood that the gallium nitride transistor provided in this application embodiment achieves maximum cost limitation by setting the epitaxial layer as a multilayer composite structure with gradually increasing resistivity. That is, this structure ensures that the top GaN epitaxial layer has the highest possible resistivity, so that the resistivity of the single crystal silicon carbide on the top layer of the substrate meets the device performance requirements.

[0058] Optionally, such as Figure 2 and Figure 3 As shown, in this gallium nitride transistor structure, the auxiliary layer is a buffer layer, and the functional layer may include a channel layer and a barrier layer stacked on the buffer layer, as well as a source, gate and drain patterned on the barrier layer.

[0059] For example, in some embodiments, the buffer layer can be a gallium nitride layer or an aluminum nitride layer, that is, as an auxiliary layer to separate the device substrate and functional layer, so as to alleviate lattice mismatch and thermal stress between the substrate and the channel layer GaN, and reduce dislocation density.

[0060] That is, the channel layer on the buffer layer can be a high-resistivity gallium nitride layer (e.g., a resistivity of 10). 6 Ω·m).

[0061] The AlGaN barrier layer is located between the channel layer and the gate, source, and drain electrodes, thereby generating a two-dimensional electron gas with high electron mobility and low resistance between the barrier layer and the channel layer. That is, at zero gate voltage, the device is in the conducting state due to the extremely strong polarization effect of gallium nitride.

[0062] On the other hand, in some embodiments of this application, a method for fabricating gallium nitride transistors is also provided, which is used to fabricate gallium nitride transistors of the above embodiments.

[0063] like Figure 4 As shown, the method may include the following steps:

[0064] S1, forming a single-crystal silicon carbide epitaxial layer on a single-crystal silicon carbide substrate, wherein the resistivity of the substrate is less than the resistivity of the epitaxial layer.

[0065] S2, auxiliary layers and functional layers are sequentially stacked on the epitaxial layer to form an auxiliary layer and a functional layer.

[0066] Specifically, a single-crystal silicon carbide epitaxial layer can first be formed on a single-crystal silicon carbide substrate. For example, the epitaxial layer can be formed on the substrate using metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).

[0067] In some embodiments, multiple layers of single-crystal silicon carbide with gradually increasing resistivity can be formed on the substrate to form a composite epitaxial layer structure.

[0068] Furthermore, a buffer layer can be grown on the epitaxial layer. For example, an AlN or low-temperature GaN buffer layer (with a thickness of several hundred nm) can be grown first to alleviate the lattice mismatch and thermal stress between the substrate and the channel layer GaN, and reduce the dislocation density.

[0069] Furthermore, a channel layer (GaN) can be grown on the buffer layer, such as an intrinsic GaN layer with high resistivity (thickness can be 1~3μm), to serve as a channel for electron transport.

[0070] Furthermore, a barrier layer (AlGaN) can be grown on the channel layer. For example, an AlGaN layer (with a thickness of 10~30nm and an Al composition of 20%~30%) can be grown on the GaN channel layer to form a two-dimensional electron gas (2DEG) at the heterogeneous interface.

[0071] Finally, the electrode structures of drain, source, and gate can be formed sequentially using photolithography.

[0072] It is understood that the gallium nitride transistor with the composite SiC substrate structure provided in this application embodiment is more cost-effective than a uniform semi-insulating SiC substrate and retains all the ideal material properties of SiC suitable for high-frequency and high-power applications. The three-part (or more-part) composite SiC substrate can also have different resistivities in each layer, as long as the top has the highest possible resistivity where the GaN epitaxial layer is grown.

[0073] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0074] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A gallium nitride transistor, characterized by, Comprise: A composite substrate layer and a gallium nitride auxiliary layer and a functional layer stacked on the composite substrate layer; The composite substrate layer comprises a base substrate and an epitaxial layer, the base substrate and the epitaxial layer are monocrystalline silicon carbide layers, the thickness of the base substrate in the composite substrate layer is greater than the thickness of the epitaxial layer, the monocrystalline silicon carbide in the composite substrate layer is a 3C, 4H or 6H lattice structure, and the resistivity of the epitaxial layer is higher than the resistivity of the base substrate; The epitaxial layer comprises a single layer or multiple layers of silicon carbide layers, and the resistivity of each layer of silicon carbide in the multiple layers of silicon carbide layers increases sequentially from the base substrate to the auxiliary layer; The thickness of each silicon carbide layer in the epitaxial layer is 5-10 μm, and the total thickness of the epitaxial layer is 10-40 μm.

2. The gallium nitride transistor of claim 1, wherein, The thickness of the base substrate is 300-1000 μm.

3. The gallium nitride transistor of claim 1, wherein, The auxiliary layer is a buffer layer, and the functional layer comprises a channel layer and a barrier layer stacked on the buffer layer, and a source electrode, a gate electrode and a drain electrode patterned on the barrier layer.

4. A method for preparing a gallium nitride transistor, the method being used for preparing the gallium nitride transistor according to any one of claims 1-3, and the method comprising: forming an epitaxial layer of monocrystalline silicon carbide on a base substrate of monocrystalline silicon carbide, the resistivity of the base substrate being less than the resistivity of the epitaxial layer; sequentially stacking an auxiliary layer and a functional layer on the epitaxial layer.

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