Liquid crystal display substrate, preparation method and display device
By combining graphene with a high dielectric constant metal oxide layer to form a heterojunction in a liquid crystal display substrate, the problem of lack of band gap in the graphene active layer is solved, achieving a display effect with high switching ratio and low power consumption, which is suitable for flexible display devices.
Patent Information
- Application Number
- CN202511072407.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-31
- Publication Date
- 2025-11-07
AI Technical Summary
In existing liquid crystal display technology, the graphene active layer lacks a band gap, making it impossible to effectively control the current, resulting in a low switching ratio and difficulty in meeting the display requirements of high resolution and low power consumption. At the same time, the poor compatibility between graphene materials and flexible substrates limits the realization of flexible displays.
A graphene layer was prepared by chemical deposition and combined with a metal oxide layer with a dielectric constant ≥10 to form a heterojunction. The strong electric field modulation effect of the high dielectric constant material was used to induce an artificial band gap in the graphene. Combined with the design of a flexible substrate, the channel current could be precisely controlled.
It significantly improves the switching ratio to the order of 10³-10⁵, reduces power consumption by 30%-50%, and makes the device flexible, making it suitable for wearable devices and foldable screens, meeting the needs of emerging display fields.
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Figure CN120916467A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of display devices, and particularly relates to a liquid crystal display substrate, a preparation method and a display device. BACKGROUND
[0002] Since the commercialization and popularization of liquid crystal display (LCD) technology in the 1990s, thin film transistor (TFT) has been used as the core driving component of LCD, with amorphous silicon (a-Si) as the active layer material. Amorphous silicon has dominated the LCD field due to its mature preparation process and low production cost, but its inherent performance defects have seriously restricted the further development of display technology. Specifically, the electron mobility of amorphous silicon is extremely low, usually less than 1 cm 2 / V·s, which leads to insufficient driving capability of TFT devices, making it difficult to meet the performance requirements of low power consumption and high-speed response for new generation display technologies such as 8K and above high resolution, 120Hz and above high refresh rate. With the rapid development of emerging application scenarios such as flexible display and transparent display, the limitations of amorphous silicon material are becoming more and more prominent: first, the preparation of amorphous silicon requires a high-temperature process of more than 300°C, which is seriously incompatible with flexible substrates such as polyimide, and cannot realize flexible display functions such as folding and curling; second, the material itself has insufficient light transmittance, and an additional transparent conductive layer such as indium tin oxide (ITO) is needed, which significantly increases the process complexity and manufacturing cost; third, the carrier mobility of amorphous silicon has reached the physical limit, making it difficult to support the miniaturization and high-performance development of display devices.
[0003] To overcome the performance bottleneck of amorphous silicon, alternative materials such as metal oxides such as indium gallium zinc oxide (IGZO) and low-temperature polycrystalline silicon (LTPS) have been partially commercialized, but there are still technical obstacles that are difficult to overcome. Among them, IGZO material faces the risk of supply chain stability due to its dependence on the rare metal indium (In); while LTPS technology is subject to complex preparation process, high production cost and difficulty in manufacturing large-size panels, which cannot effectively meet the upgrading needs of LCD technology.
[0004] Graphene, as a two-dimensional nanomaterial composed of single-layer carbon atoms, has become a highly potential display material since its discovery in 2004 due to its excellent physical and chemical properties. The material has a specific surface area of more than 10,000 cm 2The super-high electron mobility of 10<7> V / s can provide low-power consumption and low-delay driving performance for high-specification displays such as 8K@240Hz; the low-temperature preparation process below 150 DEG C can be directly compatible with flexible substrates, meeting the manufacturing requirements of foldable and wearable devices; meanwhile, the light transmittance of more than 90% of the single-layer graphene can significantly simplify the screen structure and reduce the use demand of the transparent conductive layer, thereby effectively reducing the production cost and improving the display brightness. However, the practical application of graphene in the field of LCDs still faces many technical challenges, including insufficient band gap regulation stability, poor process compatibility, high cost of large-scale preparation, and lack of industry standards, which need to be solved through technical innovation. SUMMARY
[0005] The present application aims to provide a liquid crystal display substrate, a preparation method and a display device, and aims to solve the problem that the graphene active layer in the prior art has no band gap and cannot effectively control the current.
[0006] To achieve the above application purposes, the technical solutions adopted by the present application are as follows:
[0007] In a first aspect, the present application provides a liquid crystal display substrate, which comprises a flexible substrate, a gate electrode, a gate insulating layer, a composite active layer, a source electrode and a drain electrode, and a passivation layer which are stacked; the composite active layer comprises a graphene layer and a metal oxide layer which is stacked and combined with the graphene layer away from the gate insulating layer, and the dielectric constant of the metal oxide layer is greater than or equal to 10.
[0008] In some embodiments, the metal oxide layer is selected from at least one of an aluminum oxide layer, a hafnium dioxide layer and a zirconium dioxide layer.
[0009] In some embodiments, the thickness of the metal oxide layer is 2-5 nm.
[0010] In some embodiments, the gate electrode comprises a metal layer and a graphene layer which is stacked and combined with the metal layer away from the flexible substrate.
[0011] In some embodiments, the thickness of the metal layer is 100-200 nm, and the thickness of the graphene layer is 0.3-1 nm.
[0012] In some embodiments, the source electrode and the drain electrode are a composite electrode selected from a transparent conductive oxide layer and graphene.
[0013] In some embodiments, the light transmittance of the source electrode and the drain electrode is greater than 95%, and the sheet resistance is less than 50 Ω.
[0014] In some embodiments, the gate insulating layer comprises at least one of aluminum oxide and silicon nitride, and the thickness of the gate insulating layer is 50-100 nm.
[0015] In some embodiments, the passivation layer comprises an insulating layer and a barrier layer, wherein the insulating layer comprises a silicon dioxide layer with a thickness of 100-120 nm, and the barrier layer comprises a silicon nitride layer with a thickness of 100-120 nm.
[0016] In some embodiments, the flexible substrate comprises any one of polyimide, polyethylene naphthalate, and polyethylene, and the thickness of the flexible substrate is 50-100 μm.
[0017] In some embodiments, the gate electrode is disposed on the flexible substrate; the gate insulating layer is disposed on the gate electrode; the composite active layer is disposed on the gate insulating layer; the source electrode and the drain electrode are respectively disposed on both sides of the upper surface of the active layer; and the passivation layer is disposed on the drain electrode, the source electrode, and part of the composite active layer.
[0018] In a second aspect, the present application provides a preparation method of a liquid crystal display substrate, comprising the following steps:
[0019] providing a flexible substrate;
[0020] depositing a conductor material on any surface of the flexible substrate and performing a patterning process to prepare a gate electrode;
[0021] depositing an insulating material on the surface of the gate electrode away from the flexible substrate to prepare a gate insulating layer;
[0022] adopting a chemical deposition method to deposit a graphene layer on the surface of the substrate, transferring the graphene layer to the surface of the gate insulating layer away from the gate electrode, and then depositing a metal oxide material on the surface of the graphene layer away from the gate insulating layer to prepare a metal oxide layer, thereby obtaining a composite active layer;
[0023] depositing a metal material on both sides of the metal oxide layer away from the graphene layer to prepare a drain electrode and a source electrode;
[0024] depositing a passivation layer material to form a passivation layer covering the drain electrode, the source electrode, and part of the composite active layer.
[0025] In a third aspect, the present application provides a display device comprising a display panel, wherein the display panel is a liquid crystal display substrate.
[0026] The liquid crystal display substrate provided by the first aspect of the present application comprises a flexible substrate, a gate electrode, a gate insulating layer, a composite active layer, a source electrode, a drain electrode, and a passivation layer, wherein the composite active layer is a combination of a graphene layer and a high dielectric constant metal oxide layer, the metal oxide layer with a dielectric constant ≥10 forms a heterojunction with the graphene, the strong electric field modulation effect of the high dielectric constant material induces an artificial band gap of about 0.2-0.5 eV in the graphene, and the on-off ratio is significantly improved to 10 3 -10 5The channel current can be precisely controlled. Meanwhile, the graphene has excellent carrier mobility, can be synergized with the high dielectric constant of the metal oxide, and can improve the field effect mobility of the device by 30%-50%, thereby significantly reducing the power consumption. In addition, the device can be combined with a flexible substrate to be bendable, is suitable for flexible display, is beneficial to the bendability of the display device, and meets the needs of emerging display fields such as wearable devices and folding screens.
[0027] The preparation method of the liquid crystal display substrate provided in the second aspect of the present application adopts a chemical deposition method to prepare and transfer the graphene layer, combines the deposition and patterning of other materials, and has clear and reasonable process steps and strong operability. The thickness and shape of each layer of material can be accurately controlled through the method, and the performance consistency and stability of the liquid crystal display substrate are ensured. Meanwhile, the method is compatible with the existing semiconductor manufacturing process, is convenient for large-scale production, reduces production costs, and is conducive to the industrialization of products.
[0028] The display device provided in the third aspect of the present application adopts the above liquid crystal display substrate, can use the substrate on the display device, ensures that the display device has the characteristics of lightness, thinness, bendability, high image quality, low power consumption, long service life and the like, can meet the market demand for high-performance display devices, and improves the market competitiveness and user experience of products. BRIEF DESCRIPTION OF DRAWINGS
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0030] Figure 1 is a schematic diagram of the liquid crystal display substrate provided in the embodiments of the present application;
[0031] 1-flexible substrate, 2-metal layer, 3-graphene layer, 4-gate insulating layer, 5-graphene layer, 6-metal oxide layer, 7-drain / source, 8-insulating layer, 9-barrier layer. DETAILED DESCRIPTION
[0032] In order to make the technical problems, technical solutions and beneficial effects of the present application more clearly understood, the present application will be further described in detail in combination with embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0033] In the present application, the term "and / or" describes the association relationship of the associated objects, which means that there can be three kinds of relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. Wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it.
[0034] In the present application, "at least one" means one or more, and "multiple" means two or more. "At least one" or the like means any combination of these items, including any combination of single or multiple items. For example, "at least one of a, b, or c", or "at least one of a, b, and c", can mean a, b, c, a-b (i.e. a and b), a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.
[0035] It should be understood that the size of the sequence number of the above-mentioned processes in various embodiments of the present application does not mean the order of execution, and part or all of the steps can be executed in parallel or in sequence. The execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
[0036] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.
[0037] The weight of the related components mentioned in the embodiments of the present application can not only refer to the specific content of each component, but also represent the weight ratio relationship between each component. Therefore, as long as the content of the related components in the embodiments of the present application is enlarged or reduced in proportion, it is within the scope disclosed in the embodiments of the present application. Specifically, the mass in the embodiments of the present application can be μg, mg, g, kg and other mass units commonly known in the chemical field.
[0038] The terms "first", "second" are only used for description purposes, to distinguish objects such as substances from each other, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. For example, without departing from the scope of the embodiments of the present application, the first XX can also be referred to as the second XX, and similarly, the second XX can also be referred to as the first XX. Therefore, the features limited by "first" and "second" can explicitly or implicitly include one or more of the features.
[0039] Traditional graphene as an active layer presents the following core problems: First, the band structure of natural graphene is a linear Dirac cone, with the valence band and conduction band directly contacting at the Dirac point, resulting in no inherent band gap (Eg≈0eV); Second, it has a low on / off ratio, leading to significant leakage current (Ioff) in the field-effect transistor (FET) even in the off state. The on / off ratio (Ion / Ioff) is typically below 10, which cannot meet the basic requirements of display driving circuits (>10). 3 Furthermore, due to the lack of a band gap, the gate voltage is difficult to effectively control the carrier concentration, making it impossible to achieve reliable switching of the transistor.
[0040] Based on the above problems, the first aspect of the embodiments of this application provides a liquid crystal display substrate, such as... Figure 1 As shown, the liquid crystal display substrate includes a flexible substrate 1, a gate, a gate insulating layer 4, a composite active layer, a source and a drain, and a passivation layer stacked together; the composite active layer includes a graphene layer 5 and a metal oxide layer 6 stacked and bonded to the graphene layer away from the gate insulating layer 4, and the dielectric constant of the metal oxide layer 6 is ≥10.
[0041] The liquid crystal display substrate provided in the first aspect of this application comprises a flexible substrate 1, a gate, a gate insulating layer 4, a composite active layer, a source and a drain, and a passivation layer, all stacked together. The composite active layer is a combination of a graphene layer 5 and a high-dielectric-constant metal oxide layer 6. The metal oxide layer 6, with a dielectric constant ≥ 10, forms a heterojunction with the graphene. Utilizing the strong electric field modulation effect of the high-dielectric-constant material, an artificial bandgap of approximately 0.2-0.5 eV is induced in the graphene, significantly improving the on / off ratio to 10. 3 -10 5 This allows for precise control of the channel current at the order of magnitude. Simultaneously, graphene's excellent carrier mobility, combined with the high dielectric constant of metal oxides, enhances the field-effect mobility of the device by 30%-50%, significantly reducing power consumption. Furthermore, its use with a flexible substrate 1 enables the device to bend, making it suitable for flexible displays and improving the flexibility of display devices, thus meeting the needs of emerging display fields such as wearable devices and foldable screens.
[0042] Furthermore, the composite active layer includes a graphene layer 5 and a metal oxide layer 6 stacked on the graphene layer away from the gate insulating layer 4, and the dielectric constant of the metal oxide layer 6 is ≥10.
[0043] In some embodiments, the graphene layer 5 is a single-layer graphene. With the application of graphene, the mobility can be improved and the power consumption can be reduced, and the graphene can be combined with the flexible substrate 1 to ensure a bending radius of less than 1 mm, which can meet the needs of foldable devices; in addition, the single-layer graphene has a light transmittance of more than 900%, which can simplify the screen structure, reduce the cost, and increase the brightness; further, the graphene can support a more dense pixel array, which is conducive to the application in emerging scenarios such as VR / AR, and at the same time, the graphene has the characteristics of electrical conductivity and thermal conductivity, which can integrate the touch layer and the heat dissipation layer, reduce the module stacking, and promote the development of ultra-thin displays.
[0044] In some embodiments, the metal oxide layer 6 is selected from at least one of an aluminum oxide layer, a hafnium dioxide layer, and a zirconium dioxide layer. The above-mentioned materials all have high dielectric constants, which can synergistically act with graphene to further optimize the electrical properties of the composite active layer; at the same time, they have stable chemical properties and strong corrosion resistance, which can effectively improve the stability and service life of the liquid crystal display substrate, reduce display failures caused by changes in material properties, and reduce product maintenance costs.
[0045] In some specific embodiments, the metal oxide layer 6 is selected from an aluminum oxide layer, which forms a strong electric field at the interface with graphene, induces an artificial band gap of about 0.1-0.2 eV in graphene through quantum confinement effect, and the oxygen vacancies in the aluminum oxide can introduce localized electronic states to further modulate the electronic structure of graphene, optimize the band gap width and carrier concentration, while maintaining high mobility and flexible adaptability.
[0046] In some specific embodiments, the metal oxide layer 6 is selected from a hafnium dioxide layer, which induces a band gap width of 0.3-0.5 eV, which is significantly higher than that of Al2O3 (0.1-0.2 eV) and ZrO2 (0.2-0.3 eV), and has a higher on-off ratio; and the interface defect density of the hafnium dioxide layer with graphene is lower than that of ZrO2, which has less effect on the intrinsic properties of graphene and higher mobility; at the same time, the hafnium dioxide layer has a wider amorphous window and is more stable in high-temperature processes, which is suitable for high-performance device manufacturing.
[0047] In some specific embodiments, the metal oxide layer 6 is selected from a zirconium dioxide layer, which forms an extremely strong electric field at the interface with graphene, induces an artificial band gap of about 0.2-0.3 eV in graphene through quantum confinement effect, and the high dielectric constant (ε≈20-25) of the zirconium dioxide layer leads to a highly uneven distribution of surface charges, which produces a strong local potential difference on the surface of graphene, destroys the symmetry of graphene, and thus opens a wider band gap, which can greatly improve the on-off ratio, and at the same time, ensures high thermal stability, which is conducive to maintaining stability during the processing process.
[0048] In some embodiments, the thickness of the metal oxide layer 6 is 2-5 nm. Providing the metal oxide layer 6 with a suitable thickness can ensure good combination of the metal oxide layer 6 and the graphene layer 5, fully exert the synergistic effect of the two, take into account the band gap induction and the carrier tunneling effect, and avoid the cost increase and the process difficulty increase due to the over-thickness, and the performance instability problem due to the over-thin thickness, so as to balance the cost and the process, improve the performance-price ratio and the market competitiveness of the product. If the metal oxide layer 6 is too thick, the communication resistance will increase, and if the metal oxide layer 6 is too thin, the band gap induction will not be sufficient. In some specific embodiments, the thickness of the metal oxide layer 6 includes but is not limited to 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, and the like typical but non-limiting values.
[0049] In some embodiments, the gate electrode includes the metal layer 2 and the graphene layer 3 stacked and combined on the metal layer 2 away from the flexible substrate 1. When the gate electrode includes the metal layer 2 and the graphene layer 3 stacked and combined on the metal layer 2 away from the flexible substrate 1, the metal layer 2 provides good electrical conductivity, and the graphene layer 3 can further reduce the gate resistance and improve the electrical conductivity of the gate electrode to accelerate the signal transmission speed.
[0050] In some specific embodiments, the metal layer 2 is selected from a copper layer.
[0051] In some embodiments, the thickness of the metal layer 2 is 100-200 nm, and the thickness of the graphene layer 3 is 0.3-1 nm. The thickness range can ensure that the gate electrode has suitable resistance and mechanical strength, which can meet the electrical performance requirements and maintain the structural stability during the manufacturing and use processes to reduce display defects caused by the gate electrode problems.
[0052] In some specific embodiments, the thickness of the metal layer 2 includes but is not limited to 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, 160 nm, 170 nm, 180 nm, 190 nm, 200 nm, and the like typical but non-limiting values.
[0053] In some embodiments, the source electrode and the drain electrode are selected from a composite electrode of a transparent conductive oxide layer and graphene. The source electrode and the drain electrode are selected from a composite electrode of a transparent conductive oxide layer and graphene, which combines the high light transmittance of the transparent conductive oxide and the high electrical conductivity of the graphene.
[0054] In some embodiments, the light transmittance of the source electrode and the drain electrode is >95%, and the sheet resistance is <50Ω. The source electrode and the drain electrode have a light transmittance of >95% and a sheet resistance of <50Ω, which can achieve good light transmission effect, meet the display requirements, reduce the resistance, reduce the signal transmission loss, and improve the display quality and response speed of the display substrate; at the same time, the design of the composite electrode can also enhance the stability and reliability of the electrode.
[0055] In some embodiments, the gate insulating layer 4 comprises at least one of aluminum oxide and silicon nitride. The gate insulating layer 4 comprises at least one of aluminum oxide and silicon nitride, which have good insulation properties, can effectively isolate the gate from the composite active layer, prevent leakage, and ensure normal operation of the device.
[0056] In some embodiments, the gate insulating layer 4 has a thickness of 50-100 nm, which can optimize the gate capacitance and improve the electrical performance of the device while ensuring insulation performance. In some specific embodiments, the thickness of the gate insulating layer 4 includes but is not limited to typical but non-limiting values such as 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, etc.
[0057] In some embodiments, the passivation layer comprises an insulating layer 8 and a barrier layer 9, wherein the insulating layer 8 comprises a silicon dioxide layer with a thickness of 100-120 nm, and the barrier layer 9 comprises a silicon nitride layer with a thickness of 100-120 nm. The passivation layer comprises an insulating layer 8 (silicon dioxide layer, thickness 100-120 nm) and a barrier layer 9 (silicon nitride layer, thickness 100-120 nm), the insulating layer 8 can protect the internal structure from electrical interference, and the barrier layer 9 can effectively block harmful substances such as water vapor and oxygen from the outside, preventing internal materials from oxidizing and getting wet, and improving the environmental adaptability and service life of the liquid crystal display substrate.
[0058] In some embodiments, the flexible substrate 1 comprises any one of polyimide, polyethylene naphthalate, and polyethylene, and the thickness of the flexible substrate 1 is 50-100 μm. The flexible substrate 1 comprises any one of polyimide, polyethylene naphthalate, and polyethylene, which have good flexibility, mechanical strength, and chemical stability, and can meet the bending, folding, and other use requirements of the flexible display substrate; the thickness of the flexible substrate 1 is 50-100 μm, which allows the substrate to have sufficient strength while maintaining the lightweight characteristics, facilitating integration with other components, and being conducive to the lightweight design of the display device and expanding the product application scenarios.
[0059] In some specific embodiments, the thickness of the flexible substrate 1 includes but is not limited to typical but non-limiting values such as 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, 100 μm, etc.
[0060] In some embodiments, the gate electrode is disposed on the flexible substrate 1; the gate insulating layer 4 is disposed on the gate electrode; the composite active layer is disposed on the gate insulating layer 4; the source electrode and the drain electrode are respectively disposed on both sides of the upper surface of the active layer; and the passivation layer is disposed on the drain electrode, the source electrode, and part of the composite active layer.
[0061] By reasonable layering structure design, the components of the liquid crystal display substrate can be matched with each other, the accuracy and stability of the current conduction path are ensured, and stable image display is realized. Meanwhile, the ordered structure design is convenient for process control in the preparation process, and the production efficiency and product yield are improved.
[0062] The second aspect of the embodiment of the present application provides a preparation method of a liquid crystal display substrate, including the following steps.
[0063] S01. providing a flexible substrate 1;
[0064] S02. depositing a conductor material on any surface of the flexible substrate 1 and performing patterning treatment to prepare a gate electrode;
[0065] S03. depositing an insulating material on the surface of the gate electrode away from the flexible substrate 1 to prepare a gate insulating layer 4;
[0066] S04. depositing a graphene layer 5 on the surface of the substrate by using a chemical deposition method, transferring the graphene layer 5 to the surface of the gate insulating layer 4 away from the gate electrode, and depositing a metal oxide material on the surface of the graphene layer 5 away from the gate insulating layer 4 to prepare a metal oxide layer 6, to obtain a composite active layer;
[0067] S05. depositing a metal material on both sides of the metal oxide layer 6 away from the graphene layer 5 to prepare a drain electrode 7 and a source electrode 7;
[0068] S06. depositing a passivation layer material to form a passivation layer covering the drain electrode 7, the source electrode 7 and part of the composite active layer.
[0069] The preparation method of the liquid crystal display substrate provided by the second aspect of the embodiment of the present application adopts the chemical deposition method to prepare and transfer the graphene layer 5, combines the deposition and patterning treatment of other materials, and has clear and reasonable process steps and strong operability. The thickness and shape of each layer of material can be accurately controlled by the method, the performance consistency and stability of the liquid crystal display substrate are ensured, the method is compatible with the existing semiconductor manufacturing process, is convenient for mass production, reduces the production cost, and is conducive to the industrialization and popularization of products.
[0070] In step S01, the flexible substrate 1 is provided.
[0071] In some embodiments, the provided flexible substrate 1 needs to be pretreated. The pretreatment can include the following steps: first, cleaning: acetone is used to dissolve the oil and organic residues on the surface of the flexible substrate 1, and ultrasonic treatment is performed for 5 minutes; isopropyl alcohol is used to remove polar contaminants, and ultrasonic treatment is performed for 5 minutes; deionized water is used to flow wash the remaining solvents for 1 minute; and finally, drying treatment is performed; wherein the power of the ultrasonic treatment is 100-110 W, and nitrogen is used for purging treatment;
[0072] Second, oxygen plasma surface activation treatment: the treatment conditions are as follows: the gas is O2 with a purity of 99.999%; the plasma is excited with a power of 100 W; the treatment time is 1-2 min; and the pressure is 0.1-0.3 Torr.
[0073] Third, surface flattening treatment: PMMA is used as a temporary filling layer; PMMA is spin-coated with parameters of 3000 rpm / 30 s and a thickness of 300 nm; heat curing treatment is performed after spin coating; and chemical mechanical polishing treatment is performed, in which the polishing liquid is silica colloid with a particle size of 50 nm and a pH of 10, the pressure is 3 psi, the rotation speed is 60 rpm, and the time is 1 min.
[0074] Fourth, heat treatment: heat treatment is performed in a nitrogen environment with a temperature ramping speed of 60 ℃ / 30 min to 180 ℃ in stages to eliminate internal stress.
[0075] In step S02, a conductor material is deposited on any surface of the flexible substrate 1, and patterning treatment is performed to prepare a gate electrode.
[0076] In some embodiments, a copper layer is deposited on any surface of the flexible substrate 1 by a magnetron sputtering method, and a graphene layer 3 is laminated on the surface of the copper layer away from the flexible substrate 1. In some embodiments, the thickness of the copper layer is 100-200 nm, and the thickness of the graphene layer 3 is 0.3-1 nm.
[0077] In some embodiments, the specific preparation method of the copper layer deposited on any surface of the flexible substrate 1 by the magnetron sputtering method includes the following steps: providing an inert atmosphere; using a high-purity copper target (99.999%) as the target material; setting the substrate temperature to 25-80 ℃; setting the sputtering power to 100-150 W; controlling the deposition rate to 10-20 nm / min; setting the working pressure to 3-5 mTorr; and setting the deposition time to about 5-10 min. The thickness of the copper layer is 100-200 nm.
[0078] In some embodiments, the specific preparation method of the graphene layer 3 laminated on the surface of the copper layer away from the flexible substrate 1 includes the following steps: using multi-cavity low-temperature plasma enhanced CVD; setting the growth zone temperature to 135 ℃; first, pre-treating the copper surface: performing plasma activation with H2 at 50 W and 200 mTorr for 5 min; second, growing graphene: providing a gas flow of CH4:Ar:H2=10:100:5 sccm; setting the growth time to 60 min; setting the pressure to 5-8 mTorr; and third, cooling: cooling at a rate gradient of 10 ℃ / min to 80 ℃ under argon protection.
[0079] Further, a patterning process is performed. In some embodiments, the patterning process includes: sequentially performing a gate lithography, a gate etching, and a gate photoresist stripping.
[0080] In some embodiments, in the step of the gate lithography, a photoresist is first spin-coated, wherein the photoresist is a hydrofluoric acid-based negative photoresist, the spin-coating speed is 3000 rpm, the pre-baking temperature is 95°C, and the time is 60 seconds; a photoresist with a thickness of 1.1-1.3 μm is obtained; an exposure machine is used to perform exposure under the condition of 100 mJ / cm2; a mask is then performed, and a developer is used to develop for 60 seconds at a temperature of 23°C; and the photoresist is then rinsed with ionized water for 30 seconds. 2
[0081] In some embodiments, in the step of the gate etching, a graphene etching is first performed, wherein oxygen plasma is used to perform etching treatment under the condition of 50 W and 50 mTorr for 30 seconds; a copper etching is then performed, wherein an etching solution of ferric chloride with a concentration of 0.5 mol / L or an etching solution of ammonium sulfate with a concentration of 0.1 mol / L is used to perform etching treatment for 2-3 minutes; and the gate etching is completed.
[0082] In some embodiments, the gate photoresist stripping can be performed by a wet stripping or a dry stripping, and the specific operation process is a conventional technical method in the art, which is not described herein.
[0083] In step S03, an insulating material is deposited on the surface of the gate away from the flexible substrate 1 to prepare a gate insulating layer 4.
[0084] In some embodiments, the gate insulating layer 4 can be prepared by a chemical vapor deposition method.
[0085] In step S04, a graphene layer 5 is deposited on the surface of the substrate by a chemical deposition method, the graphene layer 5 is transferred to the surface of the gate insulating layer 4 away from the gate, a metal oxide layer 6 is prepared by depositing a metal oxide material on the surface of the graphene layer 5 away from the gate insulating layer 4, and a composite active layer is obtained.
[0086] In some embodiments, a single-layer graphene is grown by a chemical vapor deposition method, and the specific steps include: first, the copper surface is pretreated by using H2, 50 W, and 200 mTorr for plasma activation for 5 minutes; second, the graphene is grown by controlling the temperature to be 135°C, and growing for 60 minutes under the condition of a gas flow of CH4:Ar:H2=10:100:5 sccm and a pressure of 5-8 mTorr; and third, the graphene is cooled by gradient cooling to 80°C at a rate of 10°C / min under the protection of argon.
[0087] In some embodiments, the PMMA-assisted non-destructive transfer of graphene is adopted, and the preparation method comprises the following steps: providing a copper foil after etching treatment, and arranging a PMMA layer on the surface of the copper foil; transferring a single-layer graphene to the surface of the PMMA layer, and then combining the graphene with the gate insulating layer 4, and removing the PMMA material; and combining the graphene layer 5 on the surface of the gate insulating layer 4 away from the gate.
[0088] In some embodiments, the step of depositing a metal oxide material on the surface of the graphene layer 5 away from the gate insulating layer 4 to prepare a metal oxide layer 6 comprises the following steps:
[0089] First, after the graphene layer 5 is transferred to the gate insulating layer 4, the surface is cleaned with oxygen plasma to remove organic residues; second, atomic layer deposition is performed by using a device including an ALD system, the deposition temperature is set to 80-120℃, trimethylaluminum (TMA) and water vapor (H2O) are used as precursors, the pulse time is controlled to be 0.1s and 0.2s respectively, the cycle parameter is set to 20-50 cycles, and nitrogen gas is used for purging treatment, which is purged for 10s after each pulse to prevent gas phase reaction; in the atomic layer deposition reaction, the single-cycle growth thickness is about 0.1nm, and the total thickness is controlled to be 2-5nm; third, annealing treatment: annealing at 150℃ for 30min in a nitrogen atmosphere to improve the density of Al2O3 and reduce the interface state defects.
[0090] In some embodiments, after the metal oxide layer 6 is prepared, a patterning treatment is further included. In some embodiments, the patterning treatment comprises the following steps: sequentially performing composite active layer photolithography, composite active layer etching, and photoresist stripping.
[0091] In some embodiments, in the step of composite active layer photolithography, the following steps are included: performing impurity removal cleaning treatment, and performing photoresist spin coating, wherein the photoresist uses positive photoresist, hexamethyldisilazane is coated, the spin coating speed is 3000rpm, the spin coating time is 30s, the spin coating rotation speed is 4000rpm, the pre-baking temperature is 100℃, and the pre-baking time is 90s; an exposure machine is used to perform exposure under the condition of 120mJ / cm 2 ; then a mask is used, and development is performed using a developing solution, the development time is 60s, the temperature is 23℃, after development, the wafer is rinsed with ionized water for 10s and dried with nitrogen, and then the wafer is baked at 110℃ for 120s.
[0092] In some embodiments, in the step of composite active layer etching, the following steps are included: first, dry etching Al2O3 using a BCl3 / Cl2 mixed gas with a volume ratio of 4:1; and then dry etching graphene using an O2 / Ar mixed gas with a volume ratio of 1:3.
[0093] In some embodiments, the specific step of photoresist stripping includes soaking in stripping liquid at 60℃ for 10 minutes, and ultrasonic treatment at 40 kHz and 100 W for 30 seconds.
[0094] In step S05, metal materials are deposited on both sides of the metal oxide layer 6 away from the graphene layer 5 to prepare the drain 7 and the source 7.
[0095] In some embodiments, the specific preparation method includes: first, preparing electrode ink, mixing ITO nanoparticles with a particle size of 20 nm and graphene sheets with a lateral size of 5 μm in ethylene glycol solvent, ultrasonic treatment at a power of 500 W for 30 minutes, and ball milling treatment for 2 hours to obtain the electrode ink, wherein the electrode ink includes ITO nanoparticles with a solid content of 40 wt% and graphene sheets with a solid content of 0.5 wt%.
[0096] In a vacuum environment, a piezoelectric inkjet printer is provided, the nozzle diameter is 30 μm; the droplet volume is controlled to be 10 pL, the substrate temperature is 60℃, and the line width is ≤20 μm for patterning treatment; solidification is performed at 80℃ for 10 minutes, at 120℃ for 20 minutes, and at 150℃ for 10 minutes; and the drain 7 and the source 7 are prepared.
[0097] In step S06, a passivation layer material is deposited to form a passivation layer covering the drain 7, the source 7, and part of the composite active layer.
[0098] In some embodiments, a plasma-enhanced chemical vapor deposition device is provided, SiH4 with a flow rate of 50 sccm and N2O with a flow rate of 150 sccm are used as precursors, a SiO2 layer with a thickness of 100 nm is deposited at a power of 300 W and a pressure of 100 Pa; then SiH4 with a flow rate of 40 sccm and NH3 with a flow rate of 120 sccm are used as precursors, a SiN x layer with a thickness of 100 nm is deposited at a power of 350 W and a pressure of 150 Pa; and then annealing is performed at 150℃ for 1 hour in a nitrogen atmosphere to eliminate hydrogen bond defects and improve passivation effect.
[0099] In the preparation process, the low-temperature CVD and the roll-to-roll process of graphene can reduce energy consumption and meet the trend of green manufacturing.
[0100] The third aspect of the embodiments of the present application provides a display device, which comprises a display panel.
[0101] The display device provided by the third aspect of the embodiments of the present application adopts the above-mentioned liquid crystal display substrate, which can be used in the display device, so that the display device has the characteristics of lightness, thinness, bendability, high image quality, low power consumption, long service life and the like, can meet the market demand for high-performance display devices, and improve the market competitiveness and user experience of products.
[0102] The application will be described in connection with specific embodiments.
[0103] Embodiment 1
[0104] A liquid crystal display substrate and a preparation method thereof
[0105] The liquid crystal display substrate comprises a flexible substrate 1, a gate electrode, a gate insulating layer 4, a composite active layer, a source electrode and a drain electrode, and a passivation layer which are stacked; the composite active layer comprises a graphene layer 5 and a metal oxide layer 6 which is stacked and combined with the graphene layer 5 away from the gate insulating layer 4, and the dielectric constant of the metal oxide layer 6 is greater than or equal to 10; the metal oxide layer 6 is selected from an aluminum oxide layer, and the thickness of the graphene layer 5 is 0.3 nm; the gate electrode comprises a copper layer and a graphene layer 5 which is stacked and combined with the copper layer away from the flexible substrate 1, the thickness of the copper layer is 100 nm, and the thickness of the graphene layer 5 is 0.3 nm; the source electrode and the drain electrode are selected from a composite electrode of ITO and graphene; the gate insulating layer 4 comprises aluminum oxide, and the thickness is 100 nm; the passivation layer comprises an insulating layer 8 and a barrier layer 9, wherein the insulating layer 8 comprises a silicon dioxide layer, and the thickness is 100 nm; the barrier layer 9 comprises a silicon nitride layer, and the thickness is 100 nm; the flexible substrate 1 is selected from polyimide, and the thickness is 50 μm.
[0106] The preparation method comprises the following steps:
[0107] (1) providing a flexible substrate 1;
[0108] ① cleaning the substrate: acetone is used to dissolve the oil and organic residues on the surface of the flexible substrate 1, and ultrasonic treatment is performed for 5 minutes; isopropyl alcohol is used to remove the polar contaminants, and ultrasonic treatment is performed for 5 minutes; deionized water is used to flow wash the residual solvents for 1 minute; and finally drying treatment is performed; wherein the power of the ultrasonic treatment is 100-110 W, and nitrogen is used for purging treatment;
[0109] ② performing oxygen plasma surface activation treatment: the treatment conditions are as follows: the gas is O2 with a purity of 99.999%, the power of the excited plasma is 100 W, the treatment time is 1-2 min, and the pressure is 0.1-0.3 Torr;
[0110] ③ performing surface flattening treatment: PMMA is used as a temporary filling layer, and PMMA is spin-coated, and the parameters are 3000 rpm / 30 seconds, and the thickness is 300 nm; after spin-coating, heat curing treatment is performed; and then chemical mechanical polishing treatment is performed, wherein the polishing liquid is silica colloid with a particle size of 50 nm and a pH of 10, the pressure is 3 psi, the rotation speed is 60 rpm, and the time is 1 minute.
[0111] ④Heat treatment: heat treatment is carried out in a nitrogen environment according to the temperature rising speed ladder of 60℃ / 30min to 180℃, and internal stress is eliminated.
[0112] (2) Depositing a conductor material on any surface of the flexible substrate 1 and performing a patterning process to prepare a gate electrode;
[0113] ① The specific preparation method of depositing a copper layer on any surface of the flexible substrate 1 by the method of magnetron sputtering includes: providing an inert atmosphere, using a high-purity copper target (99.999%) as the target material, setting the substrate temperature to 25-80℃, setting the sputtering power to 100-150W, controlling the deposition rate to 10-20nm / min, setting the working pressure to 3-5mTorr, and setting the deposition time to about 5-10 minutes;
[0114] ② The specific preparation method of stacking the graphene layer 3 on the surface of the copper layer away from the flexible substrate 1 includes: using multi-cavity low-temperature plasma enhanced CVD, and setting the growth zone temperature to 135℃; first, pre-treating the copper surface: using H2 to perform plasma activation at 50W and 200mTorr for 5 minutes; second, graphene growth: providing a gas flow of CH4:Ar:H2=10:100:5sccm; the growth time is 60 minutes; the pressure is 5-8mTorr; third, cooling: cooling at a rate gradient of 10℃ / min to 80℃ under argon protection.
[0115] ③ Sequentially performing gate lithography, gate etching, and gate photoresist stripping.
[0116] In the step of gate lithography, first, spin coating photoresist, wherein the photoresist is a hydrofluoric acid-based negative photoresist, the spin coating speed is 3000rpm, the pre-baking temperature is 95℃, and the time is 60 seconds; a photoresist with a thickness of 1.1-1.3μm is obtained; then, using an exposure machine to perform exposure under the condition of 100mJ / cm 2 ; and then, using a developer to develop, the developing time is 60 seconds, and the temperature is 23℃; after developing, rinsing with ionized water for 30 seconds.
[0117] In the step of gate etching, first, graphene etching is performed using oxygen plasma under the condition of 50W and 50mTorr for 30 seconds; then, copper etching is performed using ferric chloride etching solution with a concentration of 0.5mol / L or ammonium sulfate etching solution with a concentration of 0.1mol / L for 2-3 minutes; and then, gate etching is completed.
[0118] Then, dry stripping is performed.
[0119] (3) depositing an insulating material on the surface of the gate away from the flexible substrate 1 by chemical vapor deposition to prepare a gate insulating layer 4;
[0120] (4) depositing a graphene layer 5 on the surface of the substrate by chemical deposition, transferring the graphene layer 5 to the surface of the gate insulating layer 4 away from the gate, and depositing a metal oxide material on the surface of the graphene layer 5 away from the gate insulating layer 4 to prepare a metal oxide layer 6, thereby obtaining a composite active layer;
[0121] ① Single-layer graphene is grown by chemical vapor deposition, and the specific steps include: first, the copper surface is pretreated by plasma activation for 5 minutes under the condition of H2, 50W, and 200mTorr; the second step is graphene growth, and the temperature is controlled at 135℃, and the graphene is grown for 60 minutes under the condition of gas flow: CH4: Ar: H2=10: 100: 5sccm, and pressure of 5-8mTorr; the third step is cooling, and the argon protection is adopted to perform gradient cooling to 80℃ at a rate of 10℃ / min; and single-layer graphene is prepared;
[0122] ② PMMA-assisted lossless transfer of graphene is adopted, and the preparation method includes: providing a copper foil after etching treatment, and setting a PMMA layer on the surface of the copper foil; after the single-layer graphene is transferred to the surface of the PMMA layer, the single-layer graphene is combined with the gate insulating layer 4, and the PMMA material is removed; and the graphene layer 5 is combined on the surface of the gate insulating layer 4 away from the gate;
[0123] ③ In the step of depositing a metal oxide material on the surface of the graphene layer 5 away from the gate insulating layer 4 to prepare a metal oxide layer 6, the specific steps include: after the graphene layer 5 is transferred to the gate insulating layer 4, the surface is cleaned with oxygen plasma to remove organic residues; secondly, atomic layer deposition is performed, an equipment including an ALD system is adopted, the deposition temperature is set to 80-120℃, trimethylaluminum (TMA) and water vapor (H2O) are used as precursors, the pulse time is controlled to be 0.1 second and 0.2 second respectively, the cycle parameter is set to 20-50 cycles, and nitrogen gas is used for blowing treatment after each pulse to prevent gas phase reaction; in the atomic layer deposition reaction, the single-cycle growth thickness is about 0.1nm, and the total thickness is controlled to be 2-5nm; thirdly, annealing treatment: annealing at 150℃ for 30 minutes in a nitrogen atmosphere to improve the density of Al2O3 and reduce the interface state defects;
[0124] ④ After the metal oxide layer 6 is prepared, patterning treatment is further included; specifically, the patterning treatment includes: sequentially performing composite active layer photolithography, composite active layer etching, and photoresist stripping;
[0125] The step of composite active layer photoetching includes: performing impurity removal cleaning treatment, and performing photoresist spin coating, wherein the photoresist is positive photoresist, hexamethyldisilazane is coated, the spin coating speed is 3000 rpm, the spin coating time is 30 s, the spin coating rotation speed is 4000 rpm, the pre-baking temperature is 100 DEG C, and the pre-baking time is 90 s; the exposure machine is used to perform exposure under the condition of 120 mJ / cm 2 ; then, mask is performed, development is performed by using a developing solution, the development time is 60 s, the development temperature is 23 DEG C, after development, ion water is used to rinse for 10 s, nitrogen blowing is performed, and then, baking is performed at 110 DEG C for 120 s.
[0126] The step of composite active layer etching includes: first, BCl3 / Cl2 mixed gas with a volume ratio of 4:1 is used to perform dry etching on Al2O3, and then, O2 / Ar mixed gas with a volume ratio of 1:3 is used to perform dry etching on graphene.
[0127] The specific steps of photoresist stripping include: soaking in stripping liquid at 60 DEG C for 10 minutes, and ultrasonic treatment under the condition of 40 kHz and 100 W for 30 s.
[0128] (5) depositing metal materials on two sides of the metal oxide layer 6 away from the graphene layer 5 to prepare the drain 7 and the source 7;
[0129] ① first, ITO nanoparticles with a particle size of 20 nm and graphene sheets with a lateral size of 5 μm are uniformly mixed in ethylene glycol solvent, ultrasonic treatment is performed at 500 W power for 30 minutes, and then, ball milling treatment is performed for 2 hours to obtain electrode ink, wherein, the ITO nanoparticles have a solid content of 40 wt%, and the graphene sheets have a solid content of 0.5 wt%.
[0130] ② in a vacuum environment, a piezoelectric inkjet printer is provided, the nozzle diameter is 30 μm, the droplet volume is controlled to be 10 pL, the substrate temperature is 60 DEG C, the line width is ≤20 μm, and pattern processing is performed; solidification is performed at 80 DEG C for 10 minutes, at 120 DEG C for 20 minutes, and at 150 DEG C for 10 minutes; the drain 7 and the source 7 are prepared.
[0131] (6) depositing passivation layer material to form a passivation layer covering the drain 7, the source 7 and part of the composite active layer;
[0132] A plasma enhanced chemical vapor deposition device is provided, SiH4 with a flow rate of 50 sccm and N2O with a flow rate of 150 sccm are used as precursors, the power is 300 W, the pressure is 100 Pa, and a SiO vlayer; again, SiH4with a flow rate of 40 seem and NH3with a flow rate of 120 seem were used as precursors to deposit a SiN layer with a thickness of 100 nm under the conditions of a power of 350 W and a pressure of 150 Pa x ; again, annealing was performed at 150°C for 1 hour in a nitrogen atmosphere to eliminate hydrogen bond defects and improve the passivation effect.
[0133] Example 2
[0134] A liquid crystal display substrate and a method for manufacturing the same
[0135] Compared with Example 1, "the metal oxide layer 6 is selected from an aluminum oxide layer" is modified to "the metal oxide layer 6 is selected from a zirconium dioxide layer", in the manufacturing method, "trimethylaluminum" in step (4) iii is modified to "a zirconium source", and other contents are consistent with Example 1.
[0136] Example 3
[0137] A liquid crystal display substrate and a method for manufacturing the same
[0138] Compared with Example 1, "the metal oxide layer 6 is selected from an aluminum oxide layer" is modified to "the metal oxide layer 6 is selected from a hafnium dioxide layer", in the manufacturing method, "trimethylaluminum" in step (4) iii is modified to "a hafnium source", and other contents are consistent with Example 1.
[0139] Example 4
[0140] A liquid crystal display substrate and a method for manufacturing the same
[0141] Compared with Example 1, "the metal oxide layer 6 is selected from an aluminum oxide layer with a thickness of 2 nm" is modified to "the metal oxide layer 6 is selected from an aluminum oxide layer with a thickness of 3 nm", and other contents are consistent with Example 1.
[0142] Example 5
[0143] A liquid crystal display substrate and a method for manufacturing the same
[0144] Compared with Example 1, "the metal oxide layer 6 is selected from an aluminum oxide layer with a thickness of 2 nm" is modified to "the metal oxide layer 6 is selected from an aluminum oxide layer with a thickness of 4 nm", and other contents are consistent with Example 1.
[0145] Example 6
[0146] A liquid crystal display substrate and a method for manufacturing the same
[0147] Compared with Example 1, "the metal oxide layer 6 is selected from an aluminum oxide layer with a thickness of 2 nm" is modified to "the metal oxide layer 6 is selected from an aluminum oxide layer with a thickness of 5 nm", and other contents are consistent with Example 1.
[0148] Comparative Example 1
[0149] Liquid crystal display substrate and preparation method thereof
[0150] The liquid crystal display substrate comprises a flexible substrate 1, a gate electrode, a gate insulating layer 4, an active layer, a source electrode and a drain electrode, and a passivation layer which are stacked.
[0151] Preparation method
[0152] The flexible substrate 1 is provided.
[0153] A conductor material is deposited on any surface of the flexible substrate 1, and a patterning process is performed to prepare the gate electrode.
[0154] An insulating material is deposited on the surface of the gate electrode away from the flexible substrate 1 to prepare the gate insulating layer 4.
[0155] Silicon dioxide is deposited on the surface of the gate insulating layer 4 away from the gate electrode to prepare the active layer.
[0156] Metal materials are respectively deposited on both sides of the metal oxide layer 6 away from the graphene layer 5 to prepare the source electrode 7 and the drain electrode 7.
[0157] A passivation layer material is deposited to form a passivation layer covering the drain electrode 7, the source electrode 7 and part of the composite active layer.
[0158] Performance test
[0159] 1. Mobility test method:
[0160] ① Sample preparation:
[0161] Typical devices are selected (it is recommended to test ≥20 points to statistically analyze uniformity);
[0162] The source (S), drain (D) and gate (G) electrodes are connected using a probe station (four-probe method to avoid the influence of contact resistance);
[0163] ② VDS is fixed at 0.5V, and VGS is scanned in the range covering the threshold voltage ±20V (for example, -10V→+10V);
[0164] Scanning rate: 0.1V / step, delay time 10ms.
[0165] ③ The linear region transconductance is extracted from the IDS-VGS curve, and the bulk mobility is cross-verified by a Hall effect tester (such as Keithley4200).
[0166] 2. Driving power consumption test method:
[0167] The driving power consumption is the sum of the static power consumption and the static power consumption; wherein,
[0168] Static power consumption test: fixed VGS = 0V, VDS = 5V, record the minimum value of IDS within 1 hour;
[0169] Dynamic power consumption test: measure the average current Iavg under the full white picture (the highest load), calculate: Pdynamic = Iavg·VDD.
[0170] 3. Bending radius test method
[0171] ① Critical bending radius: the minimum bending radius when the device performance attenuation is less than 10%,
[0172] ② Cycle durability: parameter drift rate after repeated bending,
[0173] ③ Static bending test: keep bending for 5 minutes, test the change of mobility and on-off ratio,
[0174] ④ Dynamic bending test: set the bending frequency to 1Hz, the radius to 1mm, and cycle for 10000 times, test the electrical performance after every 1000 times.
[0175] Result analysis
[0176] The liquid crystal display substrate obtained in Example 1 and the liquid crystal display substrate obtained in Comparative Example 1 are compared and analyzed in performance, and the results are shown in Table 1. It can be seen that the active layer structure of the liquid crystal display substrate provided in Example 1 is obviously thinned, which can be thinned by 75%; the mobility performance is improved by about 200 times, the power consumption performance is reduced by 40%, the cost is reduced by 60%, and the flexibility is improved by 10 times.
[0177] Table 1
[0178]
[0179] In summary, the liquid crystal display substrate provided in the embodiments of the application is provided by stacking the flexible substrate 1, the gate electrode, the gate insulating layer 4, the composite active layer, the source electrode and the drain electrode, and the passivation layer, wherein the composite active layer is the combination of the graphene layer 5 and the high dielectric constant metal oxide layer 6, the metal oxide layer 6 with a dielectric constant ≥10 forms a heterojunction with the graphene, the strong electric field modulation effect of the high dielectric constant material induces an artificial band gap of about 0.2-0.5eV in the graphene, and the on-off ratio is significantly improved to 10 3 -10 5The magnitude is realized, and the precise regulation to the channel current is realized. Meanwhile, the graphene has excellent carrier mobility, can be synergized with the high dielectric constant of the metal oxide, makes the field effect mobility of the device increase by 30%-50%, and the power consumption is significantly reduced; and, combined with the flexible substrate 1, the device has the bendability, is suitable for the flexible display, is favorable to the bendability of the display device, meets the needs of the emerging display field such as wearable equipment and folding screen.
[0180] The above only describes the preferred embodiments of the present application and is not used to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A liquid crystal display substrate, characterized by comprising: The liquid crystal display substrate comprises a flexible substrate, a gate electrode, a gate insulating layer, a composite active layer, a source electrode and a drain electrode, and a passivation layer, which are stacked; the composite active layer comprises a graphene layer and a metal oxide layer stacked and combined with the graphene layer away from the gate insulating layer, and the dielectric constant of the metal oxide layer is greater than or equal to 10.
2. The liquid crystal display substrate according to claim 1, wherein The metal oxide layer is selected from at least one of an aluminum oxide layer, a hafnium dioxide layer, and a zirconium dioxide layer.
3. The liquid crystal display substrate according to claim 1, wherein The thickness of the metal oxide layer is 2-5 nm.
4. The liquid crystal display substrate according to any one of claims 1 to 3, characterized by The gate electrode comprises a metal layer and a graphene layer stacked and combined with the metal layer away from the flexible substrate; and / or The thickness of the metal layer is 100-200 nm, and the thickness of the graphene layer is 0.3-1 nm.
5. The liquid crystal display substrate according to any one of claims 1 to 3, wherein The source electrode and the drain electrode are selected from a composite electrode of a transparent conductive oxide layer and graphene; and / or The light transmittance of the source electrode and the drain electrode is greater than 95%, and the sheet resistance is less than 50 Ω.
6. The liquid crystal display substrate according to any one of claims 1 to 3, wherein The gate insulating layer comprises at least one of aluminum oxide and silicon nitride, and the thickness of the gate insulating layer is 50-100 nm; and / or The passivation layer comprises an insulating layer and a barrier layer, wherein the insulating layer comprises a silicon dioxide layer with a thickness of 100-120 nm, and the barrier layer comprises a silicon nitride layer with a thickness of 100-120 nm.
7. The liquid crystal display substrate according to claim 1, wherein The flexible substrate comprises any one of polyimide, polyethylene naphthalate, and polyethylene, and the thickness of the flexible substrate is 50-100 μm.
8. The liquid crystal display substrate according to claim 1, wherein The gate electrode is arranged on the flexible substrate; the gate insulating layer is arranged on the gate electrode; the composite active layer is arranged on the gate insulating layer; the source electrode and the drain electrode are arranged on both sides of the upper surface of the active layer, respectively; and the passivation layer is arranged on the drain electrode, the source electrode, and part of the composite active layer.
9. A method for manufacturing a liquid crystal display substrate according to any one of claims 1 to 8, characterized by, The method comprises the following steps: providing a flexible substrate; depositing a conductor material on any surface of the flexible substrate and performing a patterning process to prepare a gate electrode; depositing an insulating material on the surface of the gate electrode away from the flexible substrate to prepare a gate insulating layer; adopting a chemical deposition method to deposit a graphene layer on the surface of the substrate, transferring the graphene layer to the surface of the gate insulating layer away from the gate electrode, and then depositing a metal oxide material on the surface of the graphene layer away from the gate insulating layer to prepare a metal oxide layer, thereby obtaining a composite active layer; depositing a metal material on both sides of the metal oxide layer away from the graphene layer to prepare a drain electrode and a source electrode; depositing a passivation layer material to form a passivation layer covering the drain electrode, the source electrode, and part of the composite active layer.
10. A display device, characterized by comprising: The display panel is the liquid crystal display substrate according to any one of claims 1-8.
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