Stacked semiconductor device with metal gasket for reduced voltage drop

Abstract

The invention relates to a stacked semiconductor device having a metal gasket for reduced voltage drop. A stacked semiconductor device is described that includes a first die including a first semiconductor substrate and a first interconnect; a second die including a second semiconductor substrate and a second interconnect; a plurality of first bonding pads disposed within the first interconnect stack; a plurality of second bonding pads disposed within the second interconnect stack; and the metal gasket is embedded in the first semiconductor substrate. The plurality of first bonding pads contact the plurality of second bonding pads at a bonding interface to form a plurality of bonding connectors. The metal pad is coupled to a first bond connector included in the plurality of bond connectors. The metal gasket extends laterally between a first pair of bond connectors included in the plurality of bond connectors when the stacked semiconductor device is viewed from a plan view.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to stacked semiconductor devices, and in particular, but not exclusively, to stacked image sensors. BACKGROUND

[0002] Stacked semiconductor devices are complementary metal-oxide-semiconductor (CMOS) devices fabricated by vertically stacking and interconnecting two or more integrated circuits to form a three-dimensional integrated circuit. Advantages of stacked semiconductor devices include reduced footprint and lower operating power compared to conventional two-dimensional integrated circuits. Additionally, the increased dimensionality in the vertical dimension presents new opportunities for the design of CMOS devices.

[0003] Image sensors are a type of CMOS device that have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, and medical, automotive, and other applications. A typical image sensor operates in response to image light reflected from an external scene being incident on the image sensor. The image sensor includes an array of pixels having a light-sensitive element (e.g., a photodiode) that absorbs a portion of the incident image light and generates image charge upon absorbing the image light. The image charge generated by a pixel can be measured as an analog output image signal that varies on a column bit line with the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out from the column bit line as an analog image signal and converted to a digital value to produce a digital image (i.e., image data) representing the external scene.

[0004] As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, etc. (e.g., resolution, power consumption, dynamic range, size, etc.) in as many ways as possible through both device architecture design as well as image acquisition processing. SUMMARY

[0005] In one aspect, the disclosure provides a stacked semiconductor device comprising: a first die including a first semiconductor substrate and a first interconnect stack; a second die including a second semiconductor substrate and a second interconnect stack, wherein the first interconnect stack and the second interconnect stack are disposed between the first semiconductor substrate and the second semiconductor substrate; a plurality of first bond pads disposed within the first interconnect stack and a plurality of second bond pads disposed within the second interconnect stack, wherein the plurality of first bond pads contact the plurality of second bond pads at a bond interface to form a plurality of bond connections, the plurality of bond connections including track connections and signal connections; and a metal pad embedded in the first semiconductor substrate, wherein the metal pad is coupled to a first track connection included in the track connections, and wherein the metal pad extends laterally between a first pair of bond connections in the plurality of bond connections when the stacked semiconductor device is viewed from a plan view.

[0006] In another aspect, the disclosure provides an image sensor comprising: a first die including a first interconnect stack and a plurality of photodiodes disposed within a first semiconductor substrate to form an array of pixel cells; a second die including a second interconnect stack and a second semiconductor substrate having integrated circuitry, wherein the first interconnect stack and the second interconnect stack are disposed between the first semiconductor substrate and the second semiconductor substrate; a plurality of first bond pads disposed within the first interconnect stack and a plurality of second bond pads disposed within the second interconnect stack, wherein the plurality of first bond pads contact the plurality of second bond pads at a bond interface to form a plurality of bond connections, the plurality of bond connections including track connections and signal connections; and a metal pad embedded in the first semiconductor substrate, wherein the metal pad is coupled to a first track connection included in the track connections, and wherein the metal pad extends laterally between a first pair of bond connections in the plurality of bond connections when the image sensor is viewed from a plan view. BRIEF DESCRIPTION OF DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. Not all elements of each figure are necessary for understanding the inventive principles disclosed herein, and as such, not all elements are required to be shown in every figure. The figures are not necessarily drawn to scale, emphasis instead being placed on illustrating the principles described herein.

[0008] Figure 1A A cross-sectional view of a stacked semiconductor device with a metal pad for reduced voltage drop in accordance with embodiments of the disclosure is illustrated.

[0009] Figure 1BIllustrated description of embodiments according to the present disclosure Figure 1A The diagram illustrates a plan view of a stacked semiconductor device with metal pads.

[0010] Figure 2A The illustration shows a cross-sectional view of a stacked semiconductor device having metal pads for reducing voltage drop, according to an embodiment of the present disclosure.

[0011] Figure 2B Illustrated description of embodiments according to the present disclosure Figure 2A The diagram illustrates a plan view of a stacked semiconductor device with metal pads.

[0012] Figure 3A The illustration shows a plan view of a semiconductor device with a metal pad according to an embodiment of the present disclosure, the metal pad comprising a plurality of finger-shaped portions extending from a body portion.

[0013] Figure 3B The illustration shows a plan view of a stacked semiconductor device with a metal pad according to an embodiment of the present disclosure, the metal pad including an extended portion extending from a body portion.

[0014] Figure 3C The illustration shows a plan view of a stacked semiconductor device with a metal pad according to an embodiment of the present disclosure, the metal pad including an extended portion extending from a body portion.

[0015] Figure 4 The illustration shows a plan view of an image sensor having multiple contact pads for reducing IR drop according to an embodiment of the present disclosure.

[0016] Figure 5 This is a functional block diagram of an imaging system according to an embodiment of the present disclosure, the imaging system comprising having Figures 1A to 4 The image sensor with a metal pad for reducing voltage drop is described in the exemplary embodiment.

[0017] Several views throughout the figures correspond to reference characters indicating the respective components. Those skilled in the art will understand that the elements in the figures are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, to aid in understanding the various embodiments of the invention, some elements in the figures may be enlarged relative to others. Additionally, common and well-known elements that are useful or necessary in commercially viable embodiments are not typically depicted to facilitate a less obstructed view of these various embodiments of the invention. Detailed Implementation

[0018] Embodiments of apparatuses, systems, and / or methods related to stacked semiconductor devices with metal pads for reduced voltage drop are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments. One skilled in the relevant art will recognize, however, that the technology described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail in order to avoid obscuring aspects.

[0019] Figure 1A A cross-sectional view 100-A of a stacked semiconductor device 100 with metal pads 106 for reduced voltage drop, in accordance with an embodiment of the present disclosure, is illustrated. The stacked semiconductor device 100 includes a first die 101 and a second die 151. The first die 101 includes a first semiconductor substrate 102 and a first interconnect stack 122. The second die 151 includes a second semiconductor substrate 152 and a second interconnect stack 172. The stacked semiconductor device 100 further includes an isolation trench 105, metal pads 106, an isolation material 108, a first insulating medium 119, a plurality of metal layers 123 including a proximal metal layer 123-1, a distal metal layer 123-N, and zero or more additional metal layers disposed between the proximal metal layer 123-1 and the distal metal layer 123-N, a plurality of vias 124, a plurality of metal lines 125 including metal lines 125-1, 125-2, 125-3, and 125-4, a plurality of metal lines 129 including metal lines 129-1, 129-2, a first bond pad 145 including first bond pads 145-1, 145-2, 145-3, 145-4, 145-5, and 145-6, a second bond pad 155 including second bond pads 155-1, 155-2, 155-3, 155-4, 155-5, and 155-6, circuitry 156, a second insulating medium 169, a plurality of metal layers 173 including a proximal metal layer 173-1, a distal metal layer 173-M, and zero or more additional metal layers disposed between the proximal metal layer 173-1 and the distal metal layer 173-M, a plurality of metal lines 179 including metal lines 179-1 and 179-2, and a plurality of vias 184. Additionally, it should be appreciated that, Figures 1A to 1B The views presented in FIGS. 1-4 can omit certain elements of the stacked semiconductor device 100 to avoid obscuring details of the present disclosure. In other words, not all elements of the stacked semiconductor device 100 can be numbered, illustrated, or otherwise shown in Figures 1A to 1B or throughout other figures of the present disclosure. For example, the stacked semiconductor device 100 can include additional semiconductor substrates and / or interconnect stacks such that the stacked semiconductor device 100 includes more than two dies and more than two interconnect stacks.

[0020] Stacked semiconductor device 100 is a complementary metal-oxide-semiconductor (CMOS) device (e.g., an image sensor, a microprocessor, a memory, an application-specific integrated circuit, other integrated circuits, and / or combinations thereof) formed at least in part by first semiconductor substrate 102 (e.g., included in first die 101) and second semiconductor substrate 152 (e.g., included in second die 151) stacked and coupled together (e.g., electrically and physically) at bonding interface 150 in a stacked-chip scheme implemented via bonding (e.g., oxide bonding, metal bonding, hybrid bonding), silicon connections (e.g., through-silicon vias), other suitable circuit coupling techniques, or combinations thereof.

[0021] Figure 1A The stacked-chip scheme of stacked semiconductor device 100 illustrated in FIG. 1 enables components to be distributed across multiple substrates (e.g., first semiconductor substrate 102 and second semiconductor substrate 152), which can provide various advantages (e.g., in terms of reduced footprint, increased performance, increased density, etc.) for stacked semiconductor device 100. In some embodiments, stacked semiconductor device 100 corresponds to a stacked image sensor in which second semiconductor substrate 152 is utilized to offload components that would traditionally be included in first semiconductor substrate 102. In some embodiments, first die 101 corresponds to a pixel die (when first semiconductor substrate 102 includes photosensitive elements (e.g., a plurality of photodiodes disposed within first semiconductor substrate 102 to form a pixel cell array)), while second die 151 corresponds to a logic die (when circuitry 156 included in or on second semiconductor substrate 152 corresponds to pixel cell circuitry associated with the pixel cell array of first semiconductor substrate 102 (e.g., any one or combination of pixel transistors such as reset transistors, source follower transistors, row select transistors, switchable conversion gain transistors, analog-to-digital circuitry, signal processing circuitry, or other circuitry to facilitate imaging of an external scene with the pixel cell array)). It should be appreciated that offloading at least portions of circuitry associated with the pixel cell array formed in or on first semiconductor substrate 102 advantageously provides additional space on first semiconductor substrate 102 (e.g., to reduce pixel pitch, increase photodiode sensing area relative to total pixel area, increase pixel density, etc.).

[0022] In some embodiments, the additional space can be utilized to improve the performance of the stacked semiconductor device 100. For example, image sensor resolution can be improved by increasing the number of photodiodes per unit area. However, to facilitate pixel size reduction, image sensor resolution increase, and / or image sensor frame rate increase, there is an increased need for additional circuitry to implement increased readout functionality. In some embodiments, additional row decoders and / or bitlines can be necessary to accommodate an increased number of photosensitive elements (e.g., photodiodes), which can be inhibited by critical dimensions (e.g., width of metal lines or traces) for signal and power routing within the first interconnect stack 122 and the second interconnect stack 172 due to limited space. In some embodiments, routing proximate to the bonding interface (e.g., provided by the distal metal layer 123-N within the first interconnect stack 122 and the distal metal layer 173-M within the second interconnect stack 172) can be particularly space-constrained, as routing for power (e.g., to distribute input power such as analog operating voltage AVDD, digital operating voltage DVDD, and / or other supply voltages to circuitry 156 within the second die 151 from the first die 101) and signals (row decoders, bitlines, control signals, functional I / O, general purpose I / O, clocks, etc.) both extend through the bonding interface 150 to interconnect the first die 101 to the second die 151. In some embodiments, the analog operating voltage AVDD can be configured as a pixel reference voltage. However, when critical dimensions of power routing are inhibited, the resistance of the metal lines used for power routing increases and can result in voltage drop or IR drop across the integrated circuit. The effects of IR drop vary depending on the chip design, but can result in performance degradation, timing delays, increased power consumption, or even prevent the semiconductor device from functioning.

[0023] One way to mitigate the problem of IR drop is to increase the number of metal layers within the interconnect stack (e.g., the first interconnect stack 122 and / or the second interconnect stack 172) and / or increase the physical size of the stacked semiconductor device 100 (e.g., lateral dimensions along the X or Y directions of the coordinate system 199), but both solutions result in increased manufacturing costs. Alternatively or additionally, it can be desirable to have reduced device footprint, increased routing density, and / or otherwise facilitate increased bonding connections at the bonding interface 150 (e.g., when the stacked semiconductor device 100 is an image sensor and there is a pixel-level bonding of individual pixels or pixel cells included in the first die 101 to components (e.g., pixel control circuitry) included in the circuitry 156 in or on the second die 151).

[0024] Embodiments of the present disclosure alleviate IR drop by embedding metal pads 106 (e.g., power pads) in the first semiconductor substrate 102 to provide an additional current path for input power to reduce path resistance and thus IR drop. Advantageously, the metal pads 106 are not limited to the same critical dimensions as the metal lines contained in the distal metal layer 123-N within the first interconnect stack 122 or the distal metal layer 173-M within the second interconnect stack 172, and thus the metal pads 106 can have increased width and / or thickness to provide a conductive path with reduced resistance. The metal pads 106 can be formed from Au, Cu, Al, metal alloys, other metals, any other sufficiently conductive material that enables formation of an electrical connection, or combinations thereof and can be compatible with conventional semiconductor device processing and microfabrication techniques.

[0025] In Figure 1A In the illustrated embodiment, the first die 101 is stacked vertically with the second die 151. The first die 101 includes a first semiconductor substrate 102 and a first interconnect stack 122, and the second die 151 includes a second semiconductor substrate 152 and a second interconnect stack 172. The first interconnect stack 122 and the second interconnect stack 172 are coupled together at a bond interface 150 and disposed between the first semiconductor substrate 102 and the second semiconductor substrate 152. The first semiconductor substrate 102 and the second semiconductor substrate 152 can respectively correspond to a portion or the entirety of a semiconductor wafer (e.g., a silicon wafer). In some embodiments, the first semiconductor substrate 102 and / or the second semiconductor substrate 152 includes or is otherwise formed from silicon, a silicon- germanium alloy, germanium, a silicon carbide alloy, an indium gallium arsenide alloy, any other alloy formed from a group III-V compound, combinations thereof, one or more epitaxial layers of the foregoing materials, or a bulk substrate thereof. More particularly, the first semiconductor substrate 102 and / or the second semiconductor substrate 152 can correspond to any semiconductor material or combination of materials that can be doped or otherwise configured to facilitate the formation of integrated circuits (e.g., formation of individual circuit system components such as source / drain regions of transistors, memory elements, photodiodes, etc.). For example, in some embodiments, the first die 101 can correspond to a pixel die that includes an array of pixel cells formed in the first semiconductor substrate 102. The first semiconductor substrate 102 can correspond to one or more epitaxial layers (e.g., P or N doped silicon) formed on a carrier wafer. In this embodiment, photodiodes included in the array of pixel cells can be formed in the one or more epitaxial layers corresponding to the first semiconductor substrate 102, while the carrier wafer can be removed or otherwise thinned during fabrication to form the first die 101, which is then subsequently stacked and interconnected with the second die 151.

[0026] The metal pad 106 is embedded within the first semiconductor substrate 102 (e.g., disposed proximate to the first interconnect stack 122 between a first side 103 of the first semiconductor substrate 102 and a second side 104 of the first semiconductor substrate 102 opposite the first side 103). More specifically, the metal pad 106 is disposed within an isolation trench formed within the first semiconductor substrate 102. The isolation trench 105 is filled with an isolation material 108 (e.g., an oxide-based material such as silicon dioxide or any suitable insulating material that provides electrical isolation between electrical components) that surrounds the metal pad 106 to electrically isolate the metal pad 106 from the substrate material of the first semiconductor substrate 102. The isolation trench 105 includes an opening 111 that extends from the second side 104 and through the isolation material 108 to expose a surface 112 of the metal pad 106. The opening 111 exposes a portion of the metal pad 106 to define a contact window 110 for the metal pad 106 to enable external connection to the metal pad 106 (e.g., a supply voltage 118 that can correspond to an input power such as an operating voltage AVDD for analog circuitry or an operating voltage DVDD for digital circuitry). In some embodiments, the contact window 110 is sized to enable external wiring connections (e.g., via wire bonding) to form external connections between the semiconductor device 100 and external circuitry or external devices.

[0027] As illustrated, the stacked semiconductor device 100 includes a plurality of first bonding pads 145 disposed within the first interconnect stack 122 and a plurality of second bonding pads 155 disposed within the second interconnect stack 172. The plurality of first bonding pads 145 contact the plurality of second bonding pads 155 at the bonding interface 150 to form a plurality of bonding connections, which can individually be referred to as rail connections or signal connections depending on the functionality (e.g., power routing or signal / data transfer, respectively) of a given connection included in the plurality of bonding connections. In embodiments of the present disclosure, individual rail connections included in the plurality of bonding connections are represented by an "X" that extends through pairs of bonding pads included in the plurality of first bonding pads 145 and the plurality of second bonding pads 155 that are directly coupled together at the bonding interface 150. For example, bonding pads 145-1 and 155-1 form a first rail connection RC1, bonding pads 145-2 and 155-2 form a second rail connection RC2, bonding pads 145-3 and 155-3 form a third rail connection RC3, and bonding pads 145-4 and 155-4 form a fourth rail connection RC4. However, it should be appreciated that other connections not explicitly labeled as rail connections (e.g., a bonding connection including bonding pads 145-5 and 155-5 and / or another bonding connection including bonding pads 145-6 and 155-6) can correspond to a rail connection for power routing, a signal connection for data transfer, or both. In some embodiments, the plurality of first bonding pads 145 and the plurality of second bonding pads 155 are vertically aligned, as illustrated. However, in other embodiments, the plurality of first bonding pads 145 and the plurality of second bonding pads 155 can not be vertically aligned. In one embodiment, bonding pads 145-2 and 155-2 forming the second rail connection RC2 can be arranged such that a centerline of bonding pad 145-2 is not aligned with a centerline of bonding pad 155-2. That is, at least a vertical edge of bonding pad 145-2 and a vertical edge of bonding pad 155-2 can not be aligned. In the same or another embodiment, the dimensions of bonding pads 145-2 and 155-2 can be configured to be different.

[0028] In some embodiments, the plurality of bonding connections formed by the plurality of first bonding pads 145 and the plurality of second bonding pads 155 are described as "hybrid bonds." It should be appreciated that the term "hybrid bond" refers to one or more interconnects formed via a direct bond interconnect process by which metal surfaces (e.g., Au, Cu, Al, metal alloys, other metals, and / or combinations thereof of the plurality of first bonding pads 145 and the plurality of second bonding pads 155) disposed within insulating media (e.g., the first insulating media 119 included in the first interconnect stack 122 and the second insulating media 169 included in the second interconnect stack 172) formed on two or more semiconductor substrates (e.g., the first semiconductor substrate 102 and the second semiconductor substrate 152) are placed in direct contact and permanently fixed together. In some embodiments, the metal surfaces are initially bonded together via Van der Waals bonds between the metal surfaces. One or more thermal processes can then be applied to convert the Van der Waals bonds to covalent and / or metallic bonds to permanently fix the two or more semiconductor substrates together. It should be further appreciated that the one or more thermal processes can also form bonds between one or more of the metal surfaces and the insulating media and / or between the insulating media on the two or more semiconductor substrates. However, in other embodiments, other suitable circuit coupling techniques (e.g., through-silicon vias, metal bonding, etc.) can be utilized to form the plurality of bonding connections.

[0029] The first and second interconnect stacks 122, 172 are a hierarchical or stacked structure formed from a plurality of metal layers (e.g., a plurality of metal layers 123 included in the first interconnect stack 122 and a plurality of metal layers 173 included in the second interconnect stack 172) and a plurality of vias (e.g., a plurality of vias 124 included in the first interconnect stack 122 and a plurality of vias 184 included in the second interconnect stack 172) disposed within a corresponding insulating medium (e.g., a first insulating medium 119 included in the first interconnect stack 122 and an insulating medium 169 included in the second interconnect stack 172). The insulating media 119, 169 include one or more insulating layers (e.g., one or more metal- in and / or inter-metal dielectrics such as silicon dioxide, organosilicate glass (e.g., SiCOH), porous SiCOH, other insulating materials, or combinations thereof) that separate individual metal lines (e.g., Au, Al, Cu, W, one or more alloys (e.g., aluminum alloys), other conductive materials, or combinations thereof) included in the plurality of metal layers 123, 173 and individual connection vias (e.g., Au, Al, Cu, W, Ru, one or more alloys (e.g., aluminum alloys), other conductive materials, or combinations thereof) included in the plurality of vias 124, 184. It should be appreciated that individual metal lines positioned in adjacent levels formed from the plurality of metal layers 123, 173 are coupled together through the plurality of vias 124, 184 to facilitate electrical coupling across the substrate by providing power and signal routing through the first and second interconnect stacks 122, 172. It should be appreciated that the term "metal line" included in the plurality of metal layers 123, 173 can otherwise be described as a trace, a line, a pad, and the like, that extends along an x / y direction and / or serves as a contact pad that connects adjacent vias included in the plurality of vias 124, 184.

[0030] As previously discussed, the metal pad 106 provides a reduced resistance path for current to traverse (e.g., laterally along the xy-plane of the coordinate system 199) to mitigate IR drops that can occur in other paths having more restricted (e.g., in terms of width and / or depth) critical dimensions. In the illustrated embodiment, the metal pad 106 is coupled to a first rail connector RC1 formed by the bond pads 145-1 and 155-1, a second rail connector RC2 formed by the bond pads 145-2 and 155-2, a third rail connector RC3 formed by the bond pads 145-3 and 155-3, and a fourth rail connector RC4 formed by the bond pads 145-4 and 155-4. The first rail connector RC1, the second rail connector RC2, the third rail connector RC3, and the fourth rail connector RC4 are also each coupled to a metal line 179-1 (e.g., a first metal line included in the distal metal layer 173-M). In this configuration, the metal pad 106 is connected in parallel with the metal line 179-1, forming a first conductive path CP1 including the first rail connector RC1 and the second rail connector RC2, and a second conductive path CP2 including the third rail connector RC3 and the fourth rail connector RC4. The metal line 179-1 is disposed within the second interconnect stack 172 and is configured to deliver power (e.g., from the supply voltage 118 connected to the metal pad 106 formed in the first semiconductor substrate 102) to components (e.g., the circuitry 156) formed in or on the second semiconductor substrate 152. The metal pad 106 and the metal line 179-1 provide first and second conductive paths, respectively, that each extend from different rail connectors (e.g., laterally from the first rail connector to the fourth rail connector). In other words, the second die 151 includes circuitry 156 disposed in or on the second semiconductor substrate 152, and the metal pad 106 is coupled to the circuitry 156 through the first rail connector to provide the supply voltage 118 to the circuitry 156.

[0031] In some embodiments, the components included in the circuitry 156 include any one or combination of pixel transistors such as reset transistors, source follower transistors, row select transistors, switchable conversion gain transistors, and the like, readout circuitry, analog-to-digital circuitry, row driver circuitry, control circuitry, signal processing circuitry, application specific integrated circuitry, microprocessors, or other circuitry associated with operation of the stacked semiconductor device 100 (e.g., to facilitate imaging and corresponding processing of an external scene with a pixel cell array when the stacked semiconductor device 100 is configured as an image sensor).

[0032] As previously discussed, the metal pad 106 provides a reduced resistance path for current to traverse (e.g., laterally along the xy-plane of the coordinate system 199) to mitigate IR drops that can occur in other paths having more restricted (e.g., in terms of width and / or depth) critical dimensions. In the illustrated embodiment, the metal pad 106 is coupled to a first rail connector RC1 formed by the bond pads 145-1 and 155-1, a second rail connector RC2 formed by the bond pads 145-2 and 155-2, a third rail connector RC3 formed by the bond pads 145-3 and 155-3, and a fourth rail connector RC4 formed by the bond pads 145-4 and 155-4. The first rail connector RC1, the second rail connector RC2, the third rail connector RC3, and the fourth rail connector RC4 are also each coupled to a metal line 179-1 (e.g., a first metal line included in the distal metal layer 173-M). In this configuration, the metal pad 106 is connected in parallel with the metal line 179-1, forming a first conductive path CP1 including the first rail connector RC1 and the second rail connector RC2, and a second conductive path CP2 including the third rail connector RC3 and the fourth rail connector RC4. The metal line 179-1 is disposed within the second interconnect stack 172 and is configured to deliver power (e.g., from the supply voltage 118 connected to the metal pad 106 formed in the first semiconductor substrate 102) to components (e.g., the circuitry 156) formed in or on the second semiconductor substrate 152. The metal pad 106 and the metal line 179-1 provide first and second conductive paths, respectively, that each extend from different rail connectors (e.g., laterally from the first rail connector to the fourth rail connector). In other words, the second die 151 includes circuitry 156 disposed in or on the second semiconductor substrate 152, and the metal pad 106 is coupled to the circuitry 156 through the first rail connector to provide the supply voltage 118 to the circuitry 156. Figure 1AAs illustrated in the middle, the first interconnect stack 122 includes a proximal metal layer 123-1 and a distal metal layer 123-N. The proximal metal layer 123-1 is closer to the first side 103 of the first semiconductor substrate 102 than any other metal layer included in the plurality of metal layers 123, while the distal metal layer 123-N is disposed closer to the bonding interface 150 than any other metal layer included in the plurality of metal layers 123. Similarly, the second interconnect stack 172 includes a distal metal layer 173-M that is closer to the bonding interface 150 than any other metal layer included in the plurality of metal layers 173. It should be appreciated that the plurality of metal layers 123, 173 each provide lateral routing (e.g., x or y direction of coordinate system 199), while the plurality of vias 124, 184 provide vertical routing (e.g., z direction of coordinate system 199). The distal metal layer 173-M is formed from metal lines 179 (e.g., 179-1 and 179-2). As previously discussed, the metal pad 106 and the metal line 179-1 provide a first conductive path and a second conductive path, respectively, that are coupled in parallel to distribute power (e.g., operating voltage AVDD or DVDD) across the stacked semiconductor device 100.

[0033] It should be appreciated that the first conductive path CP1 and the second conductive path CP2 are arranged to provide a parallel connection between the supply voltage 118 and the circuitry 156 via the metal pad 106 and the metal line 179-1, respectively, to reduce IR drop current flow paths (e.g., from A to B as illustrated in the middle). Figure 1A In other words, the first conductive path CP1 can extend primarily laterally (e.g., along the xy-plane of coordinate system 199) through the metal pad 106 and vertically through the metal line 129-1 and the corresponding bonding pad. The second conductive path CP2 can extend vertically (e.g., along the z-direction of coordinate system 199) through the metal line 129-2 and the corresponding bonding pad and primarily laterally (e.g., along the xy-plane of coordinate system 199) through the metal line 179-1. As such, two equivalent or parallel paths from point A to point B can be achieved, and the IR drop between points A and B is reduced. It should be appreciated that points A and B are illustrated as one possible example to show the IR drop reduction achieved by parallel circuit connections (e.g., between the supply voltage 118 and the circuitry 156) having embodiments in accordance with the present disclosure.

[0034] The first and second conductive paths CP1, CP2 also extend through metal lines included in the proximal metal layer 123-1 (e.g., metal lines 125-2 and 125-3) and metal lines included in the distal metal layer 123-N (e.g., metal lines 129-1 and 129-2) to traverse the z-direction of the coordinate system 199 (a direction normal to the surface of the first side 103 of the first semiconductor substrate 102). However, it should be appreciated that due to the metal pads 106 and isolation trenches 105 extending from the second side 104 of the first semiconductor substrate 102 to the first side 103 of the first semiconductor substrate 102, some embodiments can have restrictions on the placement of metal lines included in the proximal metal layer 123-1 (e.g., to increase the spatial utilization of the first interconnect stack 122). Specifically, in some embodiments, metal lines included in the proximal metal layer 123-1 do not overlap or otherwise align with respective boundaries 107, 113, 109, 115 (e.g., outer boundaries defining a perimeter) of the metal pads 106 and / or isolation trenches 105, e.g., in regions CR1 and CR2, as etch damage to metal lines included in the proximal metal layer 123-1 within regions CR1 and CR2 can occur near respective boundaries 107, 113, 109, 115 during formation of the metal pads 106. Thus, in some embodiments, the proximal metal layer 123-1 includes proximal lines that are adjacent (e.g., a first pair of adjacent proximal lines corresponding to metal lines 125-1 and 125-2 and / or a second pair of adjacent proximal lines corresponding to metal lines 125-3 and 125-4) without any intervening metal lines included in the proximal metal layer 123-1 disposed therebetween. For example, metal line 125-1 is separated from metal line 125-2 by a separation region 126 within the first interconnect stack 122, where no intervening metal lines included in the proximal metal layer 123-1 are disposed within the separation region 126 and respective boundaries 113, 115 of the metal pads 106 and isolation trenches 105 overlap the separation region 126. In another example, metal line 125-3 is separated from metal line 125-4 by a separation region 127 within the first interconnect stack 122, where no intervening metal lines included in the proximal metal layer 123-1 are disposed within the separation region 127 and respective boundaries 107, 109 of the metal pads 106 and isolation trenches 105 overlap the separation region 127. In other words, respective boundaries 107, 113, 109, 115 of the metal pads 106 and / or isolation trenches 105 do not overlap any metal lines included in the proximal metal layer 123-1.

[0035] Figure 1B FIG. 1 illustrates a plan view of a stacked semiconductor device 100 having metal pads 106, in accordance with embodiments of the present disclosure. Figure 1A It should be appreciated that, Figure 1AThe cross-sectional view 100-A of the stacked semiconductor device 100 illustrated in the middle is along a cutline CI - CI'that extends along either the x or y direction of the coordinate system 199, and thus shows horizontally overlapping features (e.g., with respect to the x or y direction of the coordinate system 199) of the stacked semiconductor device 100. Figure 1B The plan view 100-B illustrated in the middle provides a view of the xy plane and thus shows vertically overlapping features (e.g., with respect to the z direction of the coordinate system 199) of the stacked semiconductor device 100. For example, the metal lines 129-1 and 129-2 are disposed between the metal pads 106 and the plurality of bond connections 190 with respect to the z direction of the coordinate system 199.

[0036] The plurality of bond connections 190 (e.g., 190-1, 190-2, 190-3, 190-4, 19-4, 190-5, 190-6, 190-7, 190-8, 190-9, 190-10) are shown where each individual bond connection corresponds to Figure 1A The pairs of bond pads coupled directly together at the bond interface 150 included in the plurality of first bond pads 145 and the plurality of second bond pads 155 illustrated in the middle. For example, Figure 1B The bond connection 190-1 illustrated in the middle corresponds to Figure 1A The pair of bond pads 145-1 and 155-1 illustrated in the middle, Figure 1B The bond connection 190-2 illustrated in the middle corresponds to Figure 1A The pair of bond pads 145-2 and 155-2 illustrated in the middle, Figure 1B The bond connection 190-3 illustrated in the middle corresponds to Figure 1A The pair of bond pads 145-3 and 155-3 illustrated in the middle, Figure 1B The bond connection 190-4 illustrated in the middle corresponds to Figure 1A The pair of bond pads 145-4 and 155-4 illustrated in the middle, Figure 1B The bond connection 190-5 illustrated in the middle corresponds to Figure 1A The pair of bond pads 145-5 and 155-5 illustrated in the middle, Figure 1B The bond connection 190-6 illustrated in the middle corresponds to Figure 1AThe illustrated pairs of bonding pads 145-6 and 155-6, etc., are shown in the figure. As previously discussed, some of the multiple bonding connections 190 correspond to track connections, indicated by "X", and facilitate power distribution across the stacked semiconductor device 100. As illustrated, the track connections overlap perpendicularly with the metal pads 106 and the metal lines 179-1 and 179-3 to provide multiple conductive paths. In some embodiments, the metal pads 106 and the metal lines 179-1 and 179-3 are arranged such that, when viewed from plan view 100-B, the metal pad 106 at least partially covers the metal lines 179-1 and 179-3. In other words, the metal pad 106 extends over the metal lines 179-1 and 179-3.

[0037] Figure 1A The plan view 100-B illustrated herein shows at least three conductive paths for distributing power across multiple dies of a stacked semiconductor device 100. The three conductive paths include a first conductive path provided by a metal pad 106, a second conductive path provided by metal wire 179-1, and a third conductive path provided by metal wire 179-3. Specifically, the metal pad 106 is configured to receive input power (e.g., via...). Figure 1A The supply voltage 118 is illustrated in the figure. Metal pads 106 are coupled at one or more locations (e.g., via bonding connections 190-1, 190-2, 190-3, 190-4, or other bonding connections indicated by "X" or otherwise referred to as track connections) to one or more metal lines (e.g., metal lines 179-1 and 179-3) located within the distal metal layer 173-M included in the second interconnect stack to increase the number of conductive paths for power wiring while reducing IR drop and maintaining or increasing interconnect density. As illustrated, metal line 179-1 is coupled to bonding connections 190-2 and 190-3 to provide a second conductive path extending from bonding connections 190-2 and 190-3, while metal line 179-3 is coupled to bonding connections 190-4 and 190-9 to provide a third conductive path extending from bonding connections 190-4 to 190-9.

[0038] Metal lines 179-1 and 179-3 are included in the distal metal layer 173-M of the second interconnect stack 172 (see, for example, Figure 1A) and disposed between one or more pairs of bond connections (e.g., bond connections 190-5 and 190-10) included in the plurality of bond connections 190. The metal lines 179-1 and 179-3 can be spatially confined due to the plurality of bond connections 190 (e.g., the metal lines 179-1 and 179-3 can be confined in width as the density of the plurality of bond connections 190 increases), which can result in an increase in IR drop due to an increase in electrical resistance. In contrast, the metal pad 106 does not have the same lateral confinement. The metal pad 106 extends laterally between a first pair of bond connections (e.g., 190-5 and 190-10) in the plurality of bond connections 190 when the stacked semiconductor device 100 is viewed from the plan view 100-B. In some embodiments, the first pair of bond connections in the plurality of bond connections corresponds to a signal connection (e.g., for signal or data transfer). The metal pad 106 extends between a first pair of track connections (e.g., 190-2 and 190-3) when the stacked semiconductor device 100 is viewed from the plan view 100-B. The metal pad 106 extends between a second pair of track connections (e.g., 190-4 and 190-9) when the stacked semiconductor device 100 is viewed from the plan view 100-B.

[0039] In some embodiments, the metal pad 106 defines a larger area than a metal line disposed in a distal metal layer (e.g., the metal line 179-1) and disposed between one or more pairs of bond connections (e.g., the bond connections 190-5 and 190-10) included in the plurality of bond connections 190. In some embodiments, the metal pad 106 defines a larger area than a metal line disposed in a distal metal layer (e.g., the metal line 179-1) and disposed between a first pair of track connections (e.g., the track connections 190-2 and 190-3) included in the plurality of track connections 190. Figures 3A to 3CThe combined lateral area of underlying metal lines (e.g., metal lines 179-1 and 179-3) within the lateral area of 123-N and / or 173-M illustrated in the middle. Metal line 179-1 extends (e.g., along length 134) between a first pair of track connections (e.g., bonding connections 190-2 and 190-3) included in the plurality of bonding connections 190, while metal line 179-3 extends between a second pair of track connections (e.g., bonding connections 190-4 and 190-9) included in the plurality of bonding connections 190. In some embodiments, metal line 179-3 extends side-by-side (e.g., parallel) and adjacent to metal line 179-1 and has substantially the same dimensions. It should be appreciated that when viewing stacked semiconductor device 100 from plan view 100-B, both metal lines 179-1 and 179-3 are disposed between the first pair of bonding connections (e.g., 190-5 and 190-10) and are further at least partially covered by metal pad 106. As illustrated, first width 131 of metal pad 106 is greater than second width 133 of metal line 179-1, which mitigates IR drop that would otherwise affect stacked semiconductor device 100 in the absence of metal pad 106. It should be appreciated that a corresponding width of metal line 179-3 can be the same or different than second width 133 of metal line 179-1. In some embodiments, a first conductive path (e.g., defined by metal pad 106), a second conductive path (e.g., defined by metal line 179-1), and a third conductive path (e.g., defined by metal line 179-3) extend a distance (e.g., defined by length 134) along a first direction from respective track connections (e.g., 190-2, 190-3, 190-4, 190-9, etc.). When viewed from plan view, individual bonding connections included in the first pair of bonding connections (e.g., 190-5 and 190-10) in the plurality of bonding connections 190 are separated by a second distance (e.g., separation distance 132) that extends along a second direction that is perpendicular to the first direction. For example, length 134 extends along an x-direction of coordinate system 199, while separation distance 132 extends along a y-direction of coordinate system 199.

[0040] In some embodiments, the plurality of bonding connections 190 includes a first plurality of bonding pads 145 and a second plurality of bonding pads 155 (e.g., as Figure 2AThe associated metal-metal bonds. In the same or other embodiments, individual bond pads included in the plurality of first bond pads 145 and the plurality of second bond pads 155 are arranged in rows and columns to form an array of bond connections that collectively correspond to the plurality of bond connections 190 or otherwise include bond connections in the plurality of bond connections. For example, a first pair of bond connections (e.g., 190-5 and 190-10) are located in the same column included in the columns but in different rows included in the rows, and where the metal pads extend between the different rows when viewed from a plan view.

[0041] As previously discussed, the“metal lines” included in the plurality of metal layers 123, 173 can otherwise be described as traces, lines, pads, etc. that extend along the x / y directions and / or serve as contact pads that connect adjacent vias included in the plurality of vias 124, 184. For example, metal lines 179-1 and 179-3 extend longitudinally to provide respective conductive paths along a lateral distance (e.g., length 134), while metal lines 129-1, 129-2, 129-3, 129-4, 129-5, and 120-6 represent contact pads or metal interconnects that are coupled to respective groups of bond connections included in the plurality of bond connections 190. In the illustrated embodiment, metal lines 129-1, 129-2, 129-3, and 129-4 each directly couple to respective groups of four connection pads included in the plurality of connection pads included in the plurality of bond connections 190, which can improve coupling between respective dies of the stacked semiconductor device 100. For example, metal line 129-2 directly couples to bond connections 190-3, 190-4, 190-7, and 190-8. In the illustrated embodiment, there are multiple metal lines (e.g., metal lines 179-1 and 179-3) disposed between adjacent bond connections (e.g., 190-5 and 190-10). However, in other embodiments (see, e.g., Figure 2A ) there can be only one metal line disposed between adjacent bond connections included in the plurality of bond connections 190 when the stacked semiconductor device 100 is viewed from plan view 100-B.

[0042] It will be appreciated that metal lines 129-3 and 129-4, and the respective groups of bond connections included in the plurality of bond connections 190 coupled thereto, are electrically isolated from the metal pads 106. In the illustrated embodiment, metal lines 129-5 and 129-6 are arranged vertically between the metal pads 106 and the second semiconductor substrate 152 of the second die 151. In some embodiments, metal lines 129-5 and 129-6 are configured to provide other signal connections (e.g., not power lines, such as data signal lines) and thus can be further configured to be electrically isolated from the metal pads 106.

[0043] Figure 2B and 2B Cross-sectional view 200-A and plan view 200-B respectively illustrate a stacked semiconductor device 200 according to an embodiment of the present disclosure, having a metal pad 206 for reducing voltage drop. It should be understood that... Figures 2A to 2B The cross-sectional view 200-A of the stacked semiconductor device 200 illustrated in the figure is along the section line C2-C2′, which extends along the x or y direction of coordinate system 299. Figures 1A to 1B The plan view 200-B illustrated in the figure provides a view of the xy plane and thus shows the vertically overlapping features of the stacked semiconductor devices 200 (e.g., in the z direction relative to coordinate system 299). Figures 1A to 1B The stacked semiconductor device 200 is similar in many ways to Figures 2A to 2B The stacked semiconductor device 100 includes many of the same or similar features. Therefore, there are many elements with similar designations or otherwise included in the stacked semiconductor device 200, having corresponding counterparts included in the stacked semiconductor device 100. In other words, the stacked semiconductor device 200 has metal pads for reducing IR drop. Figures 2A to 2B The diagram illustrates one possible variation of the stacked semiconductor device 100. However, it should be understood that not all elements of the stacked semiconductor device 200 may be labeled, illustrated, or otherwise shown. Figures 1A to 1B Or throughout other figures in this disclosure.

[0044] exist Figures 1A to 1B In the illustrated embodiment, the stacked semiconductor device 200 is different from... Figure 2B The stacked semiconductor device 100 is at least partly due to the different arrangements, positions, sizes, or other configurations of the plurality of metal layers 223, 273 (e.g., relative to the plurality of metal layers 123, 173), the plurality of first bonding pads 245 (e.g., relative to the plurality of first bonding pads 145), the plurality of second bonding pads 255 (e.g., relative to the plurality of second bonding pads 155), and the metal pads 206. Specifically, the metal pads 206 embedded in the first semiconductor substrate 102 are of sufficient size (e.g., in terms of their lateral dimensions along the xy plane of coordinate system 299) to have sufficiently low resistance so that long metal wire interconnects disposed in the second interconnect stack 172 can be omitted. In this embodiment, the second and third conductive paths (e.g., Figure 1AThe first conductive path provided by the metal pad 206 is omitted and provides the supply voltage 118 to the circuitry 156 included in or on the second semiconductor substrate 152. Thus, the first and second bond pads 245-1, 245-2, 255-1, 255-2 correspond to rail connections coupling the metal pad 206 to the circuitry 156, while the first and second bond pads 245-3, 255-3 can correspond to rail or signal connections. In other words, when viewed from the plan view 200-B illustrated in FIG. 1, the first and second bond pads 245-1, 245-2, 255-1, 255-2 can be considered to be in the same plane as the metal pad 206, while the first and second bond pads 245-3, 255-3 can be considered to be in a different plane than the metal pad 206. Figures 1A to 1B When viewed from the plan view 200-B illustrated in FIG. 1, additional bond connections extending through the bond interface 150 can be formed under the metal pad 206. This configuration can also enable the signal and power routing provided by the plurality of metal layers 223, 273 to take advantage of the additional space under the metal pad 206, which enables routing flexibility. For example, the metal lines 225-1 included in the proximal metal layer 223-1, the metal lines 229-1 included in the distal metal layer 223-N, the metal lines 279-1 included in the distal metal layer 273-M, and the metal lines included in the proximal metal layer 273-1 can each be vertically overlaid with one another to be in the same plane as the metal pad 206, while the metal lines 229-2 and 279-2 disposed under the metal pad 206 (e.g., the bond connections 290-3 illustrated in FIG. 1) can be used for power or signal routing. Figure 2B The metal pad 206 is coupled to the circuitry 156 in a similar manner as the stacked semiconductor device 100 illustrated in FIG. 1. However, when the previous space can be limited (e.g., by the metal lines 179-1 illustrated in FIG. 1), the metal lines 229-2 and 279-2 disposed under the metal pad 206 (e.g., the bond connections 290-3 illustrated in FIG. 1) can be used for power or signal routing. Figure 2B The metal pad 206 is coupled to the circuitry 156 in a similar manner as the stacked semiconductor device 100 illustrated in FIG. 1. However, when the previous space can be limited (e.g., by the metal lines 179-1 illustrated in FIG. 1), the metal lines 229-2 and 279-2 disposed under the metal pad 206 (e.g., the bond connections 290-3 illustrated in FIG. 1) can be used for power or signal routing. Figures 3A to 3C The metal pad 206 is coupled to the circuitry 156 in a similar manner as the stacked semiconductor device 100 illustrated in FIG. 1. However, when the previous space can be limited (e.g., by the metal lines 179-1 illustrated in FIG. 1), the metal lines 229-2 and 279-2 disposed under the metal pad 206 (e.g., the bond connections 290-3 illustrated in FIG. 1) can be used for power or signal routing. Figures 3A to 3C The plan view 200-B illustrated in FIG. 1 shows that the plurality of bond connections 290-1 and 290-2 correspond to rail connections coupling the metal pad 206 to the circuitry 156, while the bond connection 290-3 disposed under the metal pad 206 can provide power or signal routing.

[0045] Figures 3A to 3B Expanded plan views of stacked semiconductor devices 300-1, 300-2, and 300-3 including different configurations of metal pads 306 for reduced IR drop in accordance with embodiments of the present disclosure are shown. It should be appreciated that the expanded plan views of Figures 1A to 1B The expanded plan views of provide a view of the xy-plane of the coordinate system 399 and thus show vertically overlaid features (e.g., with respect to the z-direction of the coordinate system 399) of the stacked semiconductor devices 300-1, 300-2, and 300-3. Figures 2A to 2B The stacked semiconductor devices 300-1, 300-2, and 300-3 of are similar in many respects to the stacked semiconductor device 100 of Figures 1A to 1B The stacked semiconductor devices 300-1, 300-2, and 300-3 of and / or Figures 2A to 2Band can include many identical or similar features. Thus, there are many elements that are similarly numbered or otherwise included in stacked semiconductor devices 300-1, 300-2, and 300-3 that have corresponding counterparts included in stacked semiconductor device 100 and / or stacked semiconductor device 200. In other words, stacked semiconductor devices 300-1, 300-2, and 300-3 are Figures 3A to 3C stacked semiconductor device 100 illustrated in FIGS. 1A-1C and / or Figure 3A stacked semiconductor device 200 illustrated in FIGS. 2A-2C. However, it should be appreciated that not all elements of stacked semiconductor devices 300-1, 300-2, and / or 300-3 can be numbered, illustrated, or otherwise shown in Figures 1A to 2B or throughout other figures of the present disclosure.

[0046] Figures 3A to 3C illustrates a plan view of stacked semiconductor device 300-1 having a metal pad 306-1 that includes a plurality of finger portions 386 extending from a body portion 385, in accordance with an embodiment of the present disclosure. Body portion 385 defines a contact window 310 to receive input power (e.g., a supply voltage, which can correspond to voltage AVDD or DVDD), for example, via a wire bonding operation. The plurality of finger portions 386 each define a respective conductive path embedded in a semiconductor substrate (e.g., first semiconductor substrate 102 of Figures 1A to 2B stacked semiconductor device 200) for reduced IR drop. As illustrated, metal pad 306 is coupled to rail connections (e.g., bonding connections 390-R and 390-L, which include 390-1 and 390-4) included in a plurality of bonding connections 390. It should be appreciated that rail connections included in the plurality of bonding connections 390 are denoted by an “X” in Figure 3B and throughout other figures of the present disclosure, while other connections included in the plurality of bonding connections 390 that can be rail connections or signal connections (e.g., 390-2 and 390-3) do not have an “X” notation. Each of the plurality of finger portions 386 defines a conductive path that extends a length along an x-direction of a coordinate system 399 from bonding connection 390-L to bonding connection 390-R. Bonding connections 390-L and 390-R are each separated from one another and positioned proximate to opposite ends of the plurality of finger portions 386. Each of the plurality of finger portions 386 is also aligned to vertically cover at least two metal lines (e.g., 379-1 and 379-2) that define a metal interconnect stack (e.g., Figure 3BThe respective conductive paths within the second interconnect stack 172 included in the second die 151 illustrated in the middle. Each of the plurality of finger portions 386 is also aligned to vertically cover at least one row of the plurality of bond connections 390. In some embodiments, the rows of the plurality of bond connections 390 are alternately covered and uncovered by a corresponding one of the plurality of finger portions 386.

[0047] Figure 3A A plan view of a stacked semiconductor device 300-2 having a metal pad 306-2 including an extended portion 387 extending from a body portion 385 is illustrated in accordance with an embodiment of the present disclosure. Figure 3C The metal pad 306-2 illustrated in the middle is similar in many respects to the metal pad 306-2 illustrated in Figure 3C The metal pad 306-1 illustrated in the middle. One difference is that the extended portion 387 does not form separate fingers that each define a respective conductive path. Thus, relative to the metal pad 306-1, the extended portion 387 of the metal pad 306-2 covers two or more adjacent rows of bond connections of the plurality of bond connections to define a wider conductive path that can have a reduced resistance.

[0048] Figure 3B A plan view of a stacked semiconductor device 300-3 having a metal pad 306-3 including an extended portion 388 extending from a body portion 385 is illustrated in accordance with an embodiment of the present disclosure. Figure 4 The metal pad 306-3 illustrated in the middle is similar in many respects to the metal pad 306-2 illustrated in Figures 1A to 3C The metal pad 306-2 illustrated in the middle. One difference is that the metal pad 306-3 provides sufficient width (e.g., reduced resistance) such that the plurality of bond connections 390-L can be omitted. In the illustrated embodiment, a single column of bond connections (e.g., bond connections 390-R) electrically couple the metal pad 306-3 to an underlying die (e.g., the second die 151).

[0049] Figure 4 A plan view of an image sensor 400 having a plurality of contact pads 489 for reduced IR drop is illustrated in accordance with an embodiment of the present disclosure. The image sensor 400 is Figure 4 One possible implementation of the stacked semiconductor devices 100, 200, 300-A, 300-B, and / or 300-C illustrated in the middle and can include the same or similar features. However, it should be appreciated that not all elements of the image sensor 400 can be numbered, illustrated, or otherwise shown in Figure 1A or throughout other figures of the present disclosure. The image sensor 400 includes at least two interconnect dies (e.g., the first die 101 and the second die 151). As illustrated in the middle, the first die 101 includes a plurality of bond connections 390-1 and the second die 151 includes a plurality of bond connections 390-2.Figure 5 As illustrated in the middle, the first die corresponds to a pixel die and includes a plurality of photodiodes 448 disposed in rows and columns (e.g., R1, R2, RY, and C1, C2, and CX) within a first semiconductor substrate (e.g., the first semiconductor substrate 102) to form a pixel cell array 449. Each pixel cell included in the pixel cell array 449 can include one or more photodiodes included in the plurality of photodiodes 448. In the illustrated embodiment, the pixel cell 449-1 includes a 2x2 arrangement of four photodiodes included in the plurality of photodiodes. However, in other embodiments, each pixel cell can include any number of photodiodes, such as 1, 2, 4, 8, or more photodiodes per pixel cell.

[0050] The first die further includes a plurality of contact pads 489 (e.g., 489-1, 489-2, 489-3, and 489-4) that surround the pixel cell array 449 when viewed from a plan view. The plurality of contact pads 489 each include a respective metal pad 406 (e.g., 406-1 for contact pad 489-1) having an opening that defines a contact window 410 (e.g., contact window 410-1 for contact pad 489-1) for physically coupling the plurality of contact pads 489 to external connections. The plurality of contact pads 489 can correspond to power / ground pads (e.g., to receive input or reference voltages) and non-power pads, such as contact pad 489-4 (e.g., functional I / O pads, general purpose I / O, clock, data I / O, etc.). Each of the plurality of contact pads 489 can optionally include one or more contact trenches 417 (e.g., 417-1) in the respective contact window 410 (e.g., contact window 410-1) that extend to a proximal metal layer (e.g., metal layer 406-1) of an underlying interconnect stack, such as the metal layer 406-1 of the first interconnect stack 406. Figures 1A to 4proximal metal layer 123-1). It should be appreciated that both the plurality of photodiodes 448 and the metal pads 406 (e.g., 406-1 included in contact pad 489-1) laterally surrounding the plurality of photodiodes 448 are disposed or otherwise embedded within the first semiconductor substrate (e.g., between the first side 103 and the second side 104). The metal pads 406 included in each of the plurality of contact pads 489 corresponding to the power pad structures are coupled to one or more of the plurality of bond connections 490 (e.g., track connections) denoted by “X”. For example, contact pads 489-1, 489-2, and 489-3 each correspond to a power pad structure (e.g., to deliver input power to various components of the first and / or second dies included in the image sensor 400), and bond connections 490-1 and 490-2 correspond to track connections, while bond connection 490-3 can be a track connection or a signal connection. In some embodiments, the metal pads 406 included for power or ground pads can have a larger size than the metal pads included for non-power pads.

[0051] It should be appreciated that, in accordance with embodiments of the present disclosure, the metal pads 406 included in each of the plurality of contact pads 489 for track connections (e.g., power or ground wiring) can have different configurations. In one embodiment, the metal pads 406 cover or overlap the plurality of bond connections 490 (e.g., as shown by contact pad 489-3 electrically isolated from all other non-“X” denoted bond connections and a single coupled bond connection “X”, and contact pad 489-1 and two coupled bond connections “X”). In another embodiment, the metal pads 406 are disposed between the plurality of bond connections 490 (when viewed from a top view) (e.g., as shown by contact pad 489-2 between two groups of bond pads included in the bond connection array), except for the coupled bond connections denoted by “X” (e.g., the metal pads 406 are electrically isolated from all bond connections except for bond connections 490-1, 490-2 denoted by “X”).

[0052] Figures 1A to 4 is a functional block diagram of an imaging system 500 (e.g., an image sensor) in accordance with embodiments of the present disclosure, including a first die 505 having a plurality of photodiodes 448 and a plurality of metal pads 406 (e.g., metal pads 106, 206, 306-1, 306-2, 306-3, and / or 406) described in exemplary embodiments for reduced voltage drop. The imaging system 500 is Figure 5 a first die 505 having a plurality of photodiodes 448 and a plurality of metal pads 406 (e.g., metal pads 106, 206, 306-1, 306-2, 306-3, and / or 406) described in exemplary embodiments for reduced voltage drop. The imaging system 500 is Figures 1A to 1BThe stacked semiconductor devices 100, 200, 300-A, 300-B, 300-C and / or 400 illustrated herein may be one possible embodiment and may include the same or similar features. However, it should be understood that not all elements of the imaging system 500 may be labeled, illustrated or otherwise shown. Figure 1A Or throughout other figures of this disclosure. Imaging system 500 includes at least two interconnect dies (e.g., a first die 505 corresponding to a first die 101 and a second die corresponding to a second die 151). First die 505 includes an embedded portion in a first semiconductor substrate (e.g., for reducing voltage drop according to embodiments of this disclosure) for reducing voltage drop. Figure 5 The first semiconductor substrate 102 (illustrated in the figure) contains one or more metal pads. The imaging system 500 includes a first die 505 for generating an electrical or image signal in response to incident light 596 and an objective lens 598 having adjustable optical power to focus on one or more points of interest within an external scene 591. The imaging system 500 further includes a controller 572 for controlling the operation of, in particular, the image sensor 505 and the objective lens 598. It should be understood that the components of the controller 572 may be distributed between at least two interconnected dies of the imaging system 500 or may be individually contained within a die separate from the first die 505. The first die 505 is a simplified schematic diagram showing the first semiconductor substrate 502, a plurality of color filters 519, and a plurality of microlenses 535, wherein a plurality of photodiodes 548 are disposed within corresponding portions of the semiconductor substrate 502. The controller 572 includes one or more processors 574, a memory 576, a control circuit system 578, a readout circuit system 580, and functional logic 582.

[0053] The controller 572 includes logic and / or circuitry to control the operation of various components of the imaging system 500 (e.g., during, before, after, and in situ stages of image and / or video acquisition). The controller 572 can be implemented as hardware logic (e.g., an application specific integrated circuit, a field programmable gate array, a system on a chip, etc.), software / firmware logic executing on a general purpose microcontroller or microprocessor, or a combination of both hardware and software / firmware logic. In one embodiment, the controller 572 includes a processor 574 coupled to a memory 576 storing instructions for execution by the controller 572, the processor 574, and / or one or more other components of the imaging system 500. The instructions, when executed, can cause the imaging system 500 to perform operations associated with various functional modules, logic blocks, or circuitry of the imaging system 500 including any one or combination of the control circuitry 578, the readout circuitry 580, the functional logic 582, the image sensor 505, the objective lens 598, and any other elements (illustrated or otherwise) of the imaging system 500. The memory is a non-transitory computer readable medium, which can include, but is not limited to, a volatile (e.g., RAM) or non-volatile (e.g., ROM) storage system readable by the controller 572. It should be further appreciated that the controller 572 can be a monolithic integrated circuit that can be formed on one or more substrates coupled together, one or more discrete interconnecting electrical components, or a combination thereof. Additionally, in some embodiments, one or more electrical components can be coupled together to collectively function as the controller 572 for coordinating the operation of the imaging system 500.

[0054] The control circuitry 578 can control operational characteristics of the array formed by the plurality of photodiodes 548 (e.g., exposure duration, when to capture a digital image or video, etc.). The readout circuitry 580 reads or otherwise samples analog signals from individual photodiodes (e.g., reads out electrical signals generated by each of the plurality of photodiodes 548 in response to incident light to generate image signals for capturing an image frame, etc.), and can include amplification circuitry, analog-to-digital conversion (ADC) circuitry, image buffers, or others. In the illustrated embodiment, the readout circuitry 580 is included in the controller 572, but in other embodiments, the readout circuitry 580 can be separate from the controller 572. The functional logic 582 is coupled to the readout circuitry 580 to receive image data to demosaic the image data and generate one or more image frames. In some embodiments, electrical signals and / or image data can be manipulated or otherwise processed by the functional logic 582 (e.g., apply post-image effects such as cropping, rotation, red-eye removal, adjusting brightness, adjusting contrast, or otherwise). In some embodiments, all or portions of the controller 572 can be disposed on a die separate from the first semiconductor substrate 502 (e.g., such as a system on a chip (SoC) die, a microcontroller die, a microprocessor die, etc.). ​The second die or different subsequent die in a stacked semiconductor device (e.g., the second die 151 illustrated in FIG. 1, or a different subsequent die in a stacked semiconductor device) can be configured to provide electrical power to the first semiconductor substrate 502. In the same or other embodiments, the metal pads embedded in the first semiconductor substrate 502 (e.g., portions of the first die such as the first die 101) can facilitate power distribution from the first semiconductor substrate 502 to components of one or more underlying dies included in the imaging system 500.

[0055] Reference throughout this specification to "one example" or "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0056] It should be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. Unless otherwise indicated, these terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element discussed below could be termed a second element without departing from the teachings of the disclosure.

[0057] Spatially relative terms, such as "beneath", "below", "lower", "above", "upper", "top", "bottom", "left", "right", "center", "intermediate", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, it will be understood that, when an element is referred to as being "between" two other elements, it can be the only element between the two other elements or one or more other elements can also be between the two other elements.

[0058] Throughout the present specification, several technical terms are used. These terms will take their ordinary meaning in the art to which they belong unless specifically defined herein or the context of their use clearly dictates otherwise. It is noted that in this document, element names and symbols can be used interchangeably (e.g., Si and silicon); however, both have the same meaning.

[0059] The processes explained above can employ software and / or hardware. The described techniques can constitute machine-executable instructions embodied within machine- readable storage medium used in operation of a machine, such as a computer. Such machine- executable instructions can manifest the form of program code (which can include ​ be stored in a tangible machine-readable storage medium or transmitted from a website, server, or other remote source using a transitory medium. Alternatively, the machine- executable instructions can manifest the form of loadable or unloadable modules that can be loaded by a machine, such as a computer, to implement the techniques described herein. Additionally, the processes can be embodied within hardware, such as an application- specific integrated circuit ("ASIC"), field-programmable gate array ("FPGA"), or other.

[0060] A tangible machine-readable storage medium includes any mechanism that provides (i.e., stores) information in a non-transitory form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, a machine-readable storage medium includes recordable / non-recordable media (e.g., read only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.).

[0061] The above specification, which includes the description of the illustrated embodiments of the invention, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific examples of the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention as those skilled in the relevant art will recognize.

[0062] These modifications can be made in light of the above detailed description of the invention. The terms used in the following claims should not be construed to limit the invention to the specific examples disclosed in the specification and the drawings. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be interpreted in accordance with established doctrines of claim interpretation.

Claims

1. A stacked semiconductor device comprising: a first die including a first semiconductor substrate and a first interconnect stack; a second die including a second semiconductor substrate and a second interconnect stack, wherein the first interconnect stack and the second interconnect stack are disposed between the first semiconductor substrate and the second semiconductor substrate; a plurality of first bonding pads disposed within the first interconnect stack and a plurality of second bonding pads disposed within the second interconnect stack, wherein the plurality of first bonding pads contact the plurality of second bonding pads at a bonding interface to form a plurality of bonding connections, the plurality of bonding connections including track connections and signal connections; and a metal pad embedded in the first semiconductor substrate, wherein the metal pad is coupled to a first track connection included in the track connections, and wherein the metal pad extends laterally between a first pair of bonding connections in the plurality of bonding connections when the stacked semiconductor device is viewed from a plan view.

2. The stacked semiconductor device of claim 1, further comprising: a second track connection included in the track connections, the second track connection coupled to the metal pad; and a first metal line coupled to the first track connection and the second track connection, wherein the first metal line is disposed within the second interconnect stack, wherein the metal pad and the first metal line provide first and second conductive paths coupled in parallel through the first and second track connections, respectively, wherein the first metal line and the metal pad each extend laterally from the first track connection to the second track connection.

3. The stacked semiconductor device of claim 2, wherein the first metal line extends laterally between the first pair of bonding connections in the plurality of bonding connections when viewed from the plan view, wherein the metal pad has a first width and the first metal line has a second width, wherein the first width is greater than the second width.

4. The stacked semiconductor device of claim 2, wherein the metal pad and the first metal line are arranged such that the metal pad at least partially covers the first metal line when viewed from the plan view, and wherein the first pair of bonding connections in the plurality of bonding connections are included in the signal connections.

5. The stacked semiconductor device of claim 2, further comprising: a second metal line coupled to a third track connection and a fourth track connection included in the track connections, wherein the first metal line and the second metal line extend side-by-side between the first pair of bonding connections in the plurality of bonding connections, wherein the second metal line is coupled to the metal pad to provide a third conductive path extending from the third track connection to the fourth track connection. ​ 6. The stacked semiconductor device of claim 5, wherein the metal pad extends over both the first metal line and the second metal line, and wherein one or more of the plurality of bond connections are disposed between the first metal line and the second metal line when viewed from the plan view.

7. The stacked semiconductor device of claim 2, wherein the second interconnect stack includes a plurality of metal layers including a distal metal layer disposed closer to the bond interface than any other metal layer included in the plurality of metal layers, and wherein the first metal line is included in the distal metal layer.

8. The stacked semiconductor device of claim 2, wherein the first and second conductive paths extend a first distance along a first direction from the first rail connection to the second rail connection, and wherein individual bond connections included in the first pair of the plurality of bond connections are separated by a second distance extending along a second direction perpendicular to the first direction when viewed from the plan view.

9. The stacked semiconductor device of claim 1, further comprising an isolation trench formed within the first semiconductor substrate, wherein the metal pad is disposed within the isolation trench, and wherein the isolation trench is filled with an isolation material that surrounds the metal pad to electrically isolate the metal pad from a substrate material of the first semiconductor substrate.

10. The stacked semiconductor device of claim 9, wherein the isolation trench includes an opening extending through the isolation material to expose a surface of the metal pad, and wherein the opening defines a contact window for the metal pad to enable external connection to the metal pad.

11. The stacked semiconductor device of claim 9, wherein the first interconnect stack includes a plurality of metal layers including a proximal metal layer disposed closer to the first semiconductor substrate than any other metal layer included in the plurality of metal layers, wherein the proximal metal layer includes a plurality of metal lines including a first proximal line and a second proximal line adjacent to the first proximal line, no intervening metal line included in the proximal metal layer is disposed between the first proximal line and the second proximal line, wherein the first proximal line is separated from the second proximal line by a separation region within the first interconnect stack, and wherein respective boundaries of the metal pad and the isolation trench overlap the separation region.

12. The stacked semiconductor device of claim 1, wherein the first die includes a plurality of photodiodes disposed within the first semiconductor substrate and arranged in rows and columns to form an array of pixel cells, wherein the first die further includes a plurality of contact pads laterally surrounding the array of pixel cells when viewed from the plan view, and wherein the plurality of contact pads includes the metal pad.

13. The stacked semiconductor device of claim 1, wherein the second die includes circuitry disposed in or on the second semiconductor substrate, and wherein the metal pad is coupled to the circuitry through the first rail connection to provide a supply voltage to the circuitry.

14. The stacked semiconductor device of claim 1, wherein the plurality of bond connections includes metal-metal bonds associated with contact of the plurality of first bond pads and the plurality of second bond pads, wherein individual bond pads included in the plurality of first bond pads and the plurality of second bond pads are arranged in rows and columns to form a bond connection array that collectively corresponds to the plurality of bond connections, wherein the first pair of bond connections are located in a same column included in the columns, wherein the first pair of bond connections are located in different rows included in the rows, and wherein the metal pad extends between the different rows when viewed from the plan view.

15. An image sensor, comprising: a first die including a first interconnect stack and a plurality of photodiodes disposed within a first semiconductor substrate to form an array of pixel cells; a second die including a second interconnect stack and a second semiconductor substrate having integrated circuitry, wherein the first interconnect stack and the second interconnect stack are disposed between the first semiconductor substrate and the second semiconductor substrate; a plurality of first bond pads disposed within the first interconnect stack and a plurality of second bond pads disposed within the second interconnect stack, wherein the plurality of first bond pads contact the plurality of second bond pads at a bond interface to form a plurality of bond connections, the plurality of bond connections including rail connections and signal connections; and a metal pad embedded in the first semiconductor substrate, wherein the metal pad is coupled to a first rail connection included in the rail connections, and wherein the metal pad extends laterally between a first pair of bond connections in the plurality of bond connections when the image sensor is viewed from a plan view.

16. The image sensor of claim 15, further comprising a plurality of contact pads laterally surrounding the array of pixel cells when viewed from the plan view, and wherein the plurality of contact pads includes the metal pad.

17. The image sensor of claim 15, further comprising: a second rail connection included in the rail connections, the second rail connection coupled to the metal pad; and a first metal line coupled to the first rail connection and the second rail connection, wherein the first metal line is disposed within the second interconnect stack, wherein the metal pad and the first metal line respectively provide first and second conductive paths that are coupled in parallel, each extending from the first rail connection to the second rail connection.

18. The image sensor of claim 17, further comprising: ​ a second metal line coupled to a third rail connector and a fourth rail connector included in the rail connectors, wherein the first metal line and the second metal line extend side-by-side between the first pair of bond connectors, wherein the second metal line is coupled to the metal pad to provide a third conductive path extending from the third rail connector to the fourth rail connector.

19. The image sensor of claim 17, wherein the first conductive path and the second conductive path extending from the first rail connector to the second rail connector are along a first direction, and wherein individual bond connectors included in the first pair of bond connectors of the plurality of bond connectors are separated by a distance extending along a second direction perpendicular to the first direction when viewed from the plan view.

20. The image sensor of claim 15, further comprising an isolation trench disposed within the first semiconductor substrate, wherein the metal pad is disposed within the isolation trench, wherein the isolation trench is filled with an isolation material surrounding the metal pad to electrically isolate the metal pad from the first semiconductor substrate, wherein the isolation trench includes an opening extending through the isolation material to expose a surface of the metal pad, and wherein the opening defines a contact window for the metal pad to enable external connection to the metal pad. ​

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