Manufacturing method of flip LED chip

Abstract

The invention relates to the technical field of semiconductor light-emitting device manufacturing, in particular to a method for manufacturing a flip LED chip, which comprises the following steps of: 1, manufacturing an epitaxial layer including N-GaN, a quantum well and P-GaN on a patterned sapphire substrate; 2, manufacturing an MESA, etching an N-type region, and determining the size and a channel of a chip; step 3, manufacturing ISO to etch the middle part of the cutting channel to the patterned sapphire substrate; 4, manufacturing a transparent conductive layer; step 5, manufacturing a non-metal reflecting layer; step 6, manufacturing a metal conductive reflecting layer; step 7, manufacturing a non-metal passivation layer I; 8, manufacturing a metal series electrode I; step 9, manufacturing a non-metal passivation layer II; and 10, manufacturing a metal electrode II. By optimizing ICP process parameters, a traditional DBR-ICP etching and SiO2 wet etching two-step process is integrated into one-step dry etching, and the process flow is simplified.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor light-emitting device manufacturing, in particular to a flip LED chip manufacturing method, and especially to a flip LED chip manufacturing method for improving ODR reflection area by optimizing dry etching process. BACKGROUND

[0002] With the rapid development of LED technology, flip LED chips are widely used in display, lighting and other fields due to their excellent heat dissipation performance and light extraction efficiency. In the prior art, in order to improve reflectivity, an ODR reflection structure of thin layer DBR (3-5 pairs) combined with Ag is usually used. However, the existing manufacturing process has the following technical problems:

[0003] 1. When DBR is etched by dry etching (ICP), in order to avoid damaging the epitaxial layer, the etching amount needs to be controlled to reserve part of SiO2, and then the remaining SiO2 is removed by wet etching;

[0004] 2. Due to the overlay window and wet etching stability problems, part of the area changes from DBR+Ag ODR reflection to SiO2+Ag reflection, which reduces the product brightness;

[0005] 3. The traditional process steps are complicated, and the etching precision is difficult to accurately control. SUMMARY

[0006] The purpose of the present application is to provide a flip LED chip manufacturing method, which maximizes the ODR reflection area by adjusting the ICP parameters, combining with the OES endpoint detection system, unifying DBR-ICP etching and SiO2 wet etching into one-step dry etching, and improving the LED brightness and light efficiency to solve the problems raised in the background technology.

[0007] To achieve the above purpose, the present application provides the following technical scheme: a flip LED chip manufacturing method, comprising the following steps:

[0008] Step one, making an epitaxial layer on a patterned sapphire substrate, including N-GaN, quantum well, P-GaN;

[0009] Step two, making MESA to etch out N-type area and determine chip size and channel;

[0010] Step three, making ISO to etch the middle part of the cutting path to the patterned sapphire substrate;

[0011] Step four, making a transparent conductive layer;

[0012] Step five, making a non-metallic reflection layer;

[0013] Step six, making a metal conductive reflection layer;

[0014] Step seven, making non-metallic passivation layer one;

[0015] Step eight, making metal series electrode one;

[0016] Step nine, making non-metallic passivation layer two;

[0017] Step ten, making metal electrode two.

[0018] Preferably, in the step five, the adjusted ICP process parameters are used: upper power 700-1200W, lower power 100-400W, and CF4 gas is used;

[0019] The DBR etching rate is controlled within The ITO etching rate is controlled within

[0020] After the In element is detected by the OES endpoint detection system, the etching is continued for 50s;

[0021] The overall ITO over-etching amount is controlled within .

[0022] Preferably, in the step four, the transparent conductive layer is made of ITO or ZnO material, and the thickness is 10-60nm.

[0023] Preferably, in the step six, the metal conductive reflection layer is made of Ag material, and the thickness is greater than 80nm, and a metal adhesion layer with a thickness less than 10nm is arranged below the Ag.

[0024] Compared with the prior art, the beneficial effects of the present application are:

[0025] 1. By optimizing the ICP process parameters, the traditional two-step process of DBR-ICP etching and SiO2 wet etching is integrated into one-step dry etching, which simplifies the process flow;

[0026] 2. The OES endpoint detection system is used to accurately control the etching endpoint, avoiding damage to the epitaxial layer;

[0027] 3. By reducing the etching rate of DBR and ITO, the etching uniformity is improved, and the maximum ODR reflection area is maximized;

[0028] 4. The overall process stability is good, which can significantly improve the brightness and light efficiency of the LED chip. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or the prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0030] Fig. 1 The existing structure diagram of the LED chip;

[0031] Fig. 2 The structure view of the LED chip of the present application. EMBODIMENT

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0033] Please refer to Figs. 1-2 The present application provides a technical solution:

[0034] A manufacturing method of a flip LED chip, comprising the following steps:

[0035] Step one, growing an epitaxial layer on a patterned sapphire substrate by MOCVD method, in sequence of N-GaN layer, multi-quantum well layer and P-GaN layer;

[0036] Step two, manufacturing MESA structure by photolithography and ICP etching process, etching out N-type contact area and determining chip size;

[0037] Step three, manufacturing ISO structure, etching the middle part of the cutting path to the patterned sapphire substrate;

[0038] Step four, manufacturing ITO transparent conductive layer by sputtering method, with thickness of 30nm, and performing annealing treatment;

[0039] Step five, manufacturing DBR reflection layer:

[0040] Depositing SiO2 / SiNx multi-layer structure by PECVD, with total thickness of about 2000nm;

[0041] Using optimized ICP etching process:

[0042] Upper power 900W, lower power 200W

[0043] CF4 gas is used, flow rate 50sccm

[0044] Chamber pressure 5mTorr

[0045] DBR etching rate is controlled at

[0046] ITO etching rate is controlled at

[0047] OES endpoint detection system is used to monitor the etching process, and etching is continued for 50s after In signal is detected;

[0048] Step six, Ag reflective layer is made, thickness 150nm, 5nm Ti adhesion layer is arranged below;

[0049] Step seven, SiNx passivation layer is deposited by PECVD, thickness 800nm;

[0050] Step eight, metal series electrode is made, Ti / Al / Ti / Au multilayer structure is used;

[0051] Step nine, second passivation layer is deposited, SiO2 / SiNx alternating structure is used;

[0052] Step ten, P, N electrode is made, Cr / AuSn alloy is used.

[0053] Through testing, compared with the conventional process, the flip LED chip made by the method of the present application has:

[0054] ODR reflective area is increased by about 15%;

[0055] Chip brightness is increased by 8-12%;

[0056] Process stability is improved, and yield is increased by 5%.

[0057] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for fabricating a flip-chip LED, characterized in that: The method comprises the following steps: Step 1: making an epitaxial layer on a patterned sapphire substrate, including N-GaN, quantum well, P-GaN; Step 2: making MESA to etch N-type region and determine chip size and channel; Step 3: making ISO to etch the middle part of the cutting path to the patterned sapphire substrate; Step 4: making a transparent conductive layer; Step 5: making a non-metallic reflective layer; Step 6: making a metal conductive reflective layer; Step 7: making a non-metallic passivation layer 1; Step 8: making a metal series electrode 1; Step 9: making a non-metallic passivation layer 2; Step 10: making a metal electrode 2.

2. The method for making the flip LED chip according to claim 1, characterized in that: In step 5, the adjusted ICP process parameters are used: upper power 700-1200W, lower power 100-400W, and CF4 gas is used; The DBR etch rate is controlled to be The ITO etch rate is controlled to be An OES endpoint detection system is used, and etching is continued for 50s after In element is detected; The overall ITO overetch amount is controlled to be within 0.5 nm.

3. The method of claim 1, wherein: In step 4, ITO or ZnO material is used to make the transparent conductive layer, and the thickness is 10-60nm.

4. The method of claim 1, wherein: In step 6, the metal conductive reflective layer uses Ag material, and the thickness is greater than 80nm, and a metal adhesion layer with a thickness less than 10nm is arranged below the Ag.

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