Magnetoresistive random access memory and manufacturing method thereof

Abstract

The invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof, and the manufacturing method of the magnetoresistive random access memory (MRAM) mainly comprises the following steps: firstly, forming a spin-orbit torque (SOT) layer on a substrate, then forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first covering layer beside the MTJ, forming a second covering layer beside the MTJ, and forming a third covering layer beside the MTJ. An ion implantation process is then performed to form a first doped region in the SOT layer and on one side of the MTJ and a second doped region in the SOT layer and on the other side of the MTJ, wherein the first doped region and the second doped region form a ring around the MTJ in a plan view.

Description

TECHNICAL FIELD

[0001] The present application relates to a magnetoresistive random access memory (MRAM) element and a method for fabricating the same. BACKGROUND

[0002] It is known that the magnetoresistance (MR) effect is an effect in which the resistance of a material changes with an applied magnetic field. The physical quantity is defined as the difference in resistance with and without a magnetic field divided by the original resistance, and is used to represent the resistance change rate. At present, the magnetoresistance effect has been successfully applied in the production of hard disks, and has important commercial application value. In addition, using the characteristic that the giant magnetoresistance material has different resistance values in different magnetization states, a magnetic random access memory (MRAM) can also be made, which has the advantage of being able to continue to retain stored data without power.

[0003] The above-mentioned magnetoresistance effect is also applied in the field of magnetic field sensors, for example, an electronic compass component for mobile phones matched with a global positioning system (GPS) to provide the user with information about the direction of movement. At present, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art usually include: occupying a large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity, and being easily affected by temperature changes, etc., and it is necessary to further improve. SUMMARY

[0004] One embodiment of the present application discloses a method for fabricating a magnetoresistive random access memory (MRAM) element, which mainly forms a spin orbit torque (SOT) layer on a substrate, then forms a magnetic tunneling junction (MTJ) on the SOT layer, forms a first cover layer beside the MTJ, and then performs an ion implantation fabrication process to form a first doped region in the SOT layer and on one side of the MTJ and a second doped region in the SOT layer and on the other side of the MTJ, wherein the first doped region and the second doped region form a ring shape around the MTJ in a top view.

[0005] Another embodiment of the present application discloses a magnetic random access memory (MRAM) element, which mainly comprises a spin-orbit torque (SOT) layer disposed on a substrate, a magnetic tunnel junction (MTJ) disposed on the SOT layer, a first doped region disposed in the SOT layer and on one side of the MTJ, and a second doped region disposed in the SOT layer and on another side of the MTJ.

[0006] Another embodiment of the present application discloses a magnetic random access memory (MRAM) element, which mainly comprises a spin-orbit torque (SOT) layer disposed on a substrate, a magnetic tunnel junction (MTJ) disposed on the SOT layer, and a doped region disposed in the SOT layer and surrounding the MTJ, wherein the doped region comprises a first recess in a top view. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figures 1 to 7 A schematic diagram of a method for manufacturing an MRAM cell according to a Y direction for an embodiment of the present application;

[0008] Figures 8 to 14 A schematic diagram of a method for manufacturing an MRAM cell according to an X direction for an embodiment of the present application;

[0009] Figure 15 A top view of an MRAM element for different embodiments of the present application.

[0010] LIST OF SYMBOLS

[0011] 12: substrate

[0012] 14: MRAM region

[0013] 40: logic region

[0014] 16: interlayer dielectric layer

[0015] 18: metal interconnect structure

[0016] 20: metal interconnect structure

[0017] 22: intermetal dielectric layer

[0018] 24: metal interconnect

[0019] 26: stop layer

[0020] 28: intermetal dielectric layer

[0021] 30: metal interconnect

[0022] 32: metal interconnect

[0023] 34: barrier layer

[0024] 36: metal layer

[0025] 40: logic region

[0026] 44: SOT layer

[0027] 46: free layer

[0028] 48: barrier layer

[0029] 50: pinned layer

[0030] 60: capping layer

[0031] 62: upper electrode

[0032] 64: dielectric layer

[0033] 66: MTJ stack

[0034] 70: MTJ

[0035] 72: first capping layer

[0036] 76: bottom antireflective layer

[0037] 78: patterned mask

[0038] 80: second capping layer

[0039] 84: intermetal dielectric layer

[0040] 86: metal interconnect

[0041] 88: stop layer

[0042] 90: intermetal dielectric layer

[0043] 92: metal interconnect

[0044] 94: stop layer

[0045] 96: ion implantation fabrication process

[0046] 98: doped region

[0047] 102: short side

[0048] 104: short side

[0049] 106: long side

[0050] 108: long side

[0051] 112: first portion

[0052] 114: second portion

[0053] 116: third portion

[0054] 118: recess

[0055] 120: recess DETAILED DESCRIPTION

[0056] Referring to Figures 1 to 14 , Figures 1 to 14 A method for fabricating an MRAM cell according to an embodiment of the present application is shown in FIG. 1 1 1, in which a substrate 1 12 is provided, such as a substrate 1 12 composed of a semiconductor material selected from a group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc. The substrate 1 12 is preferably defined with an MRAM region 1 14 and a logic region 140. Figures 1 to 7 A method for fabricating an MRAM cell according to an embodiment of the present application is shown in FIG. 1 1 1, in which a substrate 1 12 is provided, such as a substrate 1 12 composed of a semiconductor material selected from a group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc. The substrate 1 12 is preferably defined with an MRAM region 1 14 and a logic region 140. Figures 8 to 14 A method for fabricating an MRAM cell according to an embodiment of the present application is shown in FIG. 1 1 1, in which a substrate 1 12 is provided, such as a substrate 1 12 composed of a semiconductor material selected from a group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc. The substrate 1 12 is preferably defined with an MRAM region 1 14 and a logic region 140. Figure 1 and Figure 8 As shown in FIG. 1, a substrate 12, such as a substrate 12 composed of a semiconductor material selected from a group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., is provided. The substrate 12 is preferably defined with an MRAM region 14 and a logic region 40.

[0057] The substrate 12 can include active (e.g., metal-oxide semiconductor (MOS) transistors), passive elements, conductive layers, and dielectric layers (e.g., interlayer dielectric (ILD) 16) formed thereon. More specifically, the substrate 12 can include planar or non-planar (e.g., fin-type transistors) MOS transistor elements, which can include gate structures (e.g., metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, etc. The ILD 16 can be formed on the substrate 12 and cover the MOS transistors, and can have contact plugs electrically connected to the gate and / or source / drain regions of the MOS transistors. The fabrication of planar or non-planar transistors and ILDs are well known in the art and will not be described in detail herein.

[0058] Then, a metal interconnect structure 18, 20 is formed on the ILD 16 of the MRAM region 14, which is electrically connected to the contact plug as described above. The metal interconnect structure 18 includes an ILD 22 and a metal interconnect 24 embedded in the ILD 22, and the metal interconnect structure 20 includes a stop layer 26, an ILD 28 and a plurality of metal interconnects 30, 32 embedded in the stop layer 26 and the ILD 28. It is noted that, compared to the MRAM region 14 which has the metal interconnects 24, 30, 32 at the same time, the logic region 40 has only the metal interconnect 24 embedded in the ILD 22 at this stage, but no metal interconnect in the ILD 28. In addition, although the metal interconnects 24, 30, 32 are shown as having the same shape in the present embodiment, the metal interconnects 24, 30, 32 can have different shapes, such as a line shape, a via shape, a trench shape, or a combination thereof. Figure 1 As can be seen along the Y direction, the metal interconnects 30, 32 are embedded in the ILD 28, Figure 8 As can be seen along the X direction, there is no metal interconnect in the ILD 28.

[0059] In the present embodiment, each metal interconnect 24 in the metal interconnect structure 18 preferably includes a trench conductor, and each metal interconnect 30, 32 in the metal interconnect structure 20 preferably includes a via conductor. In addition, each metal interconnect 24, 30, 32 in each metal interconnect structure 18, 20 can be embedded in the ILD 22, 28 and / or the stop layer 26 according to a single damascene process or a dual damascene process and electrically connected to each other. For example, each metal interconnect 24, 30, 32 can further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from a group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), and the metal layer 36 can be selected from a group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), etc., but not limited thereto. Since the single damascene or dual damascene process is well known in the art, no further description is given herein. In addition, in the present embodiment, the metal layer 36 in the metal interconnect 24 preferably includes copper, the metal layer 36 in the metal interconnect 30, 32 preferably includes tungsten, the ILD 22, 28 preferably includes silicon oxide or ultra low dielectric constant dielectric layer, and the stop layer 26 includes a nitrogen doped carbide (NDC) layer, silicon nitride or silicon carbon nitride (SiCN), but not limited thereto.

[0060] A selective lower electrode (not shown), a spin orbit torque (SOT) layer 44, an MTJ stack 66, a capping layer 60, and a patterned upper electrode 62 are then formed on the metal interconnect structure 20. In the present embodiment, the MTJ stack 66 is formed by sequentially forming a free layer 46, a barrier layer 48, a reference layer (not shown), a spacer (not shown), and a pinned layer 50 on the SOT layer 44. The free layer 46 can be formed of a ferromagnetic material such as iron, cobalt, nickel, or an alloy thereof such as cobalt-iron-boron (CoFeB), but is not limited thereto, and the magnetization direction of the free layer 46 is changed "freely" by an external magnetic field. The barrier layer 48 can be formed of an insulating material containing an oxide such as aluminum oxide (AlO x ) or magnesium oxide (MgO), but is not limited thereto.

[0061] The reference layer is preferably disposed between the barrier layer 48 and the spacer layer, and can be formed of a ferromagnetic material such as iron, cobalt, nickel, or an alloy thereof such as cobalt-iron-boron (CoFeB), but is not limited thereto. The spacer layer includes a non-magnetic layer formed of a non-magnetic material, such as ruthenium, iridium, and rhodium.

[0062] The fixed layer 50 can comprise a ferromagnetic material such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), cobalt (Co), and the like. Alternatively, the fixed layer 50 can also be composed of an antiferromagnetic (AFM) material such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), and the like, to fix or pin the direction of the magnetic moment of the adjacent layer. In detail, the fixed layer 50 can comprise a lower synthetic antiferromagnetic (SAF) layer, a coupling layer, and an upper synthetic antiferromagnetic layer, wherein the lower and upper synthetic antiferromagnetic layers can comprise the same or different materials and both can comprise a ferromagnetic material such as cobalt (Co), nickel (Ni), platinum (Pt), palladium (Pd), or a combination thereof, and the coupling layer can preferably comprise a material such as ruthenium (Ru), tantalum (Ta), gadolinium (Gd), platinum (Pt), hafnium (Hf), or a combination thereof to provide mechanical and / or lattice support to the lower and upper synthetic antiferromagnetic layers.

[0063] In addition, in the present embodiment, the selective lower electrode preferably comprises an electrically conductive material such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), and the like, the SOT layer 44 is preferably a channel of a spin orbit torque (SOT) MRAM and thus the material thereof can comprise tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (BiSe), or a combination thereof, the capping layer 60 preferably comprises a metal such as ruthenium, and the upper electrode 62 can comprise an electrically conductive or dielectric material such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or a combination thereof. x Se 1-x In addition, in the present embodiment, the SOT layer 44 can be formed by a method such as, but not limited to, sputtering, evaporation, or a combination thereof, and the SOT layer 44 can be formed by a method such as, but not limited to, sputtering, evaporation, or a combination thereof.

[0064] In addition, in the present embodiment, the patterned upper electrode 62 can be formed by forming a dielectric layer 64 composed of silicon oxide on the unpatterned upper electrode 62, using a patterned mask (not shown) such as a patterned photoresist as a mask to remove portions of the dielectric layer 64 and the upper electrode 62 by a method such as reactive ion etching (RIE) to form a patterned dielectric layer 64 and a patterned upper electrode 62, and then selectively removing the dielectric layer 64 composed of silicon oxide.

[0065] As Figure 2 and Figure 9As shown, portions of the capping layer 60, portions of the MTJ stack 66, and even portions of the SOT layer 44 of the MRAM region 14 can then be removed using the patterned dielectric layer 64 or the patterned upper electrode 62 as a mask to form the MTJ 70, and a first capping layer 72 is then formed on the MTJ 70. In this embodiment, the first capping layer 72 preferably comprises silicon nitride. It is noted that the SOT layer 44 can be selectively removed when patterning the MTJ stack 66 to form the MTJ 70 using the patterned upper electrode 62, so that the top surface of the SOT layer 44 remaining on both sides of the MTJ 70 is slightly lower than the top surface of the SOT layer 44 directly below the MTJ 70. According to another embodiment of the present application, if no SOT layer 44 is removed when forming the MTJ 70, then the top surface of the SOT layer 44 remaining on both sides of the MTJ 70 is preferably cut flush with the top surface of the SOT layer 44 directly below the MTJ 70. Furthermore, the first capping layer 72 formed at this stage is preferably formed on both the MRAM region 14 and the logic region 40.

[0066] As shown, a bottom anti-reflective coating (BARC) 76 is then formed on the first capping layer 72, and a patterning mask 78, such as a patterned photoresist, is then used as a mask to perform an etching process, such as another RIE process, to remove portions of the BARC 76, portions of the first capping layer 72 of the MRAM region 14, and all of the BARC 76 and the first capping layer 72 of the logic region 40 and expose the underlying SOT layer 44, so that the remaining first capping layer 72 is only provided on the MRAM region 14, but the underlying SOT layer 44 is still provided on both the MRAM region 14 and the logic region 40. Figure 3 Figure 10 As shown, a bottom anti-reflective coating (BARC) 76 is then formed on the first capping layer 72, and a patterning mask 78, such as a patterned photoresist, is then used as a mask to perform an etching process, such as another RIE process, to remove portions of the BARC 76, portions of the first capping layer 72 of the MRAM region 14, and all of the BARC 76 and the first capping layer 72 of the logic region 40 and expose the underlying SOT layer 44, so that the remaining first capping layer 72 is only provided on the MRAM region 14, but the underlying SOT layer 44 is still provided on both the MRAM region 14 and the logic region 40.

[0067] Subsequently, an ion implantation process 96 is performed to implant dopants into the SOT layer 44 on both sides of the MTJ 70. In this embodiment, the ion implantation process 96 performed at this stage is preferably an oblique angle ion implantation process, and the angle a between the ion and the sidewall of the first capping layer 72 or the sidewall of the BARC 76 is preferably between 65-85 degrees or most preferably less than 70 degrees when implanting the ion into the SOT layer 44. Since the ion is implanted into the SOT layer 44 on both sides of the MTJ 70 at an oblique angle, the ion not only penetrates into the SOT layer 44 on both sides of the first capping layer 72, but also penetrates into the portion of the SOT layer 44 directly below the first capping layer 72, and thus forms a doped region 98 in the SOT layer 44 on both sides of the MTJ 70. It is noted that the doped region 98 formed at this stage is respectively provided on both sides of the MTJ 70 in the cross-sectional view, but preferably appears as a ring surrounding the entire MTJ 70 in the top view.

[0068] ​Furthermore, since logic region 40 is not covered by a mask, when ions are implanted into the SOT layer 44 of MRAM region 14 to form doped region 98, all SOT layers 44 of logic region 40 are preferably also implanted with ions to form doped regions 98. In this embodiment, the implanted ions are preferably nitrogen (N2) ions. Therefore, if the original SOT layer 44 is composed of tungsten, the doped region 98 formed in the SOT layer 44 after ion implantation preferably contains a metal nitride such as tungsten nitride (WN). x ).

[0069] Subsequently, as Figure 4 and Figure 11 As shown, the patterned mask 78 and the bottom anti-reflective layer 76 are first removed. Then, an etching process can be performed without forming an additional patterned mask. For example, an ion beam etching (IBE) process different from the one described above can be used to remove part of the first masking layer 72, part of the SOT layer 44, and even part of the intermetallic dielectric layer 28 of the MRAM region 14, as well as all the SOT layers 44 and part of the intermetallic dielectric layer 28 of the logic region 40. This makes the left and right sidewalls of the first masking layer 72, the SOT layer 44, and even part of the intermetallic dielectric layer 28 of the MRAM region 14 slightly recessed and can be approximately aligned with the sidewalls of the metal interconnect 32. The top surface of the remaining intermetallic dielectric layer 28 of the logic region 40 can be selectively slightly lower than the top surface of the intermetallic dielectric layer 28 of the MRAM region 14.

[0070] A second masking layer 80 is then formed on the first masking layer 72 and the intermetallic dielectric layer 28, wherein the second masking layer 80 preferably covers the top surface of the first masking layer 72, the sidewalls of the first masking layer 72, the sidewalls of the SOT layer 44 containing the doped region 98, and the top surface of the intermetallic dielectric layer 28. In this embodiment, the first masking layer 72 and the second masking layer 80 preferably contain the same material, for example, both preferably contain silicon nitride. Since the portion of the intermetallic dielectric layer 28 next to the metal interconnects 30 and 32 is simultaneously removed by the aforementioned IBE fabrication process, the bottom surface of the formed second masking layer 80 is preferably slightly lower than the bottom surface of the first masking layer 72.

[0071] Then as Figure 5 and Figure 12 As shown, an etching process can be performed without forming a patterned mask to remove part of the second masking layer 80 of the MRAM region 14 and all of the second masking layer 80 of the logic region 40, exposing the top surface of the intermetallic dielectric layer 28.

[0072] Subsequently, as Figure 6 and Figure 13As shown, another inter-metal dielectric layer 84 is first formed over the MRAM region 14 and the logic region 40. A planarization process such as a chemical mechanical polishing (CMP) process is then performed to remove portions of the inter-metal dielectric layer 84, portions of the second cap layer 80 and portions of the first cap layer 72 so that the top surface of the remaining inter-metal dielectric layer 84 is flush with the top surface of the hard mask 62. A pattern transfer process is then performed to remove portions of the inter-metal dielectric layer 84, portions of the inter-metal dielectric layer 28 and portions of the stop layer 26 in the logic region 40 to form contact holes (not shown) and expose the underlying metal interconnects 24. The contact holes are then filled with a desired conductive material such as a barrier layer including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and the like and a low resistance metal layer selected from tungsten (W), copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) and the like or a combination thereof. A planarization process such as a chemical mechanical polishing process is then performed to remove portions of the conductive material to form metal interconnects 86 in the contact holes to electrically connect the metal interconnects 24. A stop layer 88 is then formed over the hard mask 62 and the metal interconnects 86. In this embodiment, the inter-metal dielectric layer 84 can include silicon oxide and the stop layer 88 can include silicon dioxide, silicon nitride, or silicon carbon nitride (SiCN) and is preferably silicon carbon nitride, but is not limited thereto.

[0073] Thereafter, as shown in FIG. 2B, a first cap layer 72 is formed over the hard mask 62 and the stop layer 88. A second cap layer 80 is then formed over the first cap layer 72. A planarization process such as a chemical mechanical polishing (CMP) process is then performed to remove portions of the second cap layer 80 and portions of the first cap layer 72 so that the top surface of the remaining second cap layer 80 is flush with the top surface of the hard mask 62. A pattern transfer process is then performed to remove portions of the second cap layer 80 and portions of the first cap layer 72 in the MRAM region 14 to form contact holes (not shown) and expose the underlying metal interconnects 24. The contact holes are then filled with a desired conductive material such as a barrier layer including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and the like and a low resistance metal layer selected from tungsten (W), copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) and the like or a combination thereof. A planarization process such as a chemical mechanical polishing process is then performed to remove portions of the conductive material to form metal interconnects 86 in the contact holes to electrically connect the metal interconnects 24. A stop layer 88 is then formed over the hard mask 62 and the metal interconnects 86. In this embodiment, the inter-metal dielectric layer 84 can include silicon oxide and the stop layer 88 can include silicon dioxide, silicon nitride, or silicon carbon nitride (SiCN) and is preferably silicon carbon nitride, but is not limited thereto. Figure 7 and Figure 14As shown, an inter-metal dielectric layer 90 is first formed on the stop layer 88 of the MRAM region 14 and the logic region 40, and then a pattern transfer fabrication process is performed to remove portions of the inter-metal dielectric layer 90 and portions of the stop layer 88 to form contact holes (not shown) and expose the underlying hard mask 62 and metal interconnects 86 using a patterned mask (not shown). Then, a desired conductive material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. and a low resistance metal layer selected from tungsten (W), copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), etc. or a combination thereof, is filled into the contact holes. Then, a planarization fabrication process, such as a chemical mechanical polishing fabrication process, is performed to remove portions of the metal material to form contact plugs or metal interconnects 92 within the contact holes to electrically connect the hard mask 62 and the metal interconnects 86, and then a stop layer 94 is selectively formed on the metal interconnects 92. In this embodiment, the inter-metal dielectric layer 90 preferably includes an ultra low dielectric constant dielectric layer, such as a porous dielectric material including, but not limited to, silicon oxycarbide (SiOC) or silicon oxycarbide hydrogen (SiOCH).

[0074] Referring to Figure 7 or Figure 14 , Figure 7 or Figure 14 , respectively, show a schematic structural view of an MRAM element according to an embodiment of the present application. As shown in Figure 7 or Figure 14 , the MRAM element mainly includes a SOT layer 44 disposed on a substrate 12, an MTJ 70 disposed on the SOT layer 44, a doped region 98 disposed in the SOT layer 44 on one side, such as the left side, of the MTJ 70, and another doped region 98 disposed in the SOT layer 44 on the other side of the MTJ 70, wherein the edges of the doped regions 98 are preferably cut flush with the sidewalls of the first capping layer 72 above, the second capping layer 80 contacts the sidewalls of the first capping layer 72 and the doped regions 98, and the doped regions 98 preferably form a ring shape surrounding the MTJ 70 in a top view. According to an embodiment of the present application, the doped regions 98 preferably include a metal nitride, such as tungsten nitride (WN x ).

[0075] Referring to Figure 15 , Figure 15 , respectively, show a top view of an MRAM element according to different embodiments of the present application. As shown in Figure 15As shown, the MRAM device, according to the aforementioned fabrication process, preferably includes a spin-orbit torque (SOT) layer 44 disposed on the substrate 12, a magnetic tunnel junction (MTJ) 70 disposed on the SOT layer 44, and a doped region 98 disposed within the SOT layer 44 and surrounding the MTJ 70. The MTJ 70 has short sides 102 and 104 extending along the X direction and long sides 106 and 108 extending along the Y direction, and the short sides 102 and 104 can be optionally aligned with or not aligned with the edge of the SOT layer 44.

[0076] Firstly, as Figure 15 As shown in the left-hand embodiment, according to one embodiment of the present invention, the SOT layer 44 may be rectangular and extend along the X direction on the substrate 12, the MTJ 70 may extend along the Y direction on the SOT layer 44, and the doped region 98 surrounds the entire MTJ 70 along the edge of the SOT layer 44. Since the SOT layer 44 is rectangular when viewed from above, the inner and outer sidewalls of the doped region 98 are also rectangular.

[0077] In this embodiment, the doped region 98 has a length L1 extending along the X direction between its inner and outer sidewalls, another length L2 extending along the X direction between its outer sidewalls, a width W1 extending along the Y direction between its inner and outer sidewalls, and another width W2 extending along the Y direction between its outer sidewalls. In this embodiment, the ratio of length L1 to length L2, or L1 / L2, is preferably between 0.1 and 0.3, and the ratio of width W1 to width W2, or W1 / W2, is preferably between 0.05 and 0.15.

[0078] Then as Figure 15 As shown in the intermediate embodiment, according to one embodiment of the present invention, the SOT layer 44 can also be presented in an H shape on the substrate 12, and the MTJ 70 also extends along the Y direction on the SOT layer 44. In detail, the H shape of the SOT layer 44 has a first portion 112 and a second portion 114 extending along the Y direction, and a third portion 116 extending along the X direction and connecting the first portion 112 and the second portion 114, wherein the MTJ 70 preferably extends along the Y direction in the middle region of the third portion 116.

[0079] In this embodiment, the SOT layer 44 includes a groove 118 facing the short side 102 of the MTJ 70 and another groove 120 facing the other short side 104 of the MTJ 70. Each groove 118, 120 has a length L1 extending along the X direction; the entire H-shape of the SOT layer 44, from the edge of the first portion 112 to the edge of the second portion 114, has another length L2 extending along the X direction; each groove 118, 120 has a width W1 extending along the Y direction; and the first portion 112 or the second portion 114 of the SOT layer 44 has another width W2 extending along the Y direction. In this embodiment, the ratio of length L1 to length L2, or L1 / L2, is preferably between 0.2 and 0.6, while the ratio of width W1 to width W2, or W1 / W2, is preferably between 0.2 and 0.5.

[0080] Then as Figure 15 As shown in the embodiment on the right, according to one embodiment of the present invention, the aforementioned doped region 98 can be incorporated into the H-shaped SOT layer 44. That is, the doped region 98 can surround the MTJ 70 along the edge of the H-shaped SOT layer 44, and the doped region 98 can include the short side 102 of the aforementioned groove 118 facing the MTJ 70 and another groove 120 facing the other short side 104 of the MTJ 70. The doped region 98 has a length L1 extending along the X direction, the entire H-shape of the SOT layer 44 from the edge of the first portion 112 to the edge of the second portion 114 has another length L2 extending along the X direction, the doped region 98 has a width W1 extending along the Y direction, and the first portion 112 or the second portion 114 of the SOT layer 44 has another width W2 extending along the Y direction. In this embodiment, the ratio of length L1 to length L2, or L1 / L2, is preferably between 0.025 and 0.1, while the ratio of width W1 to width W2, or W1 / W2, is preferably between 0.025 and 0.075.

[0081] In summary, this invention primarily discloses a method and related structure for fabricating MRAM devices. Preferably, an MTJ (Metal-to-Jet) is first formed on a SOT (Surface-on-Title) layer, and a patterned first masking layer 72 is then applied to the surfaces of the MTJ and the SOT layer. Next, using a patterned mask as a mask, nitrogen-based dopants are implanted into the SOT layer on both sides of the first masking layer, and even partially beneath the first masking layer, via oblique ion implantation to form doped regions 98. Preferably, the doped regions 98, viewed from a top-down angle, surround the MTJ along the edge of the SOT layer and can be rectangular or H-shaped depending on the shape of the SOT layer. According to the preferred embodiment of this invention, using oblique ion implantation to implant nitrogen into the SOT layer on both sides of the MTJ to form doped regions can effectively improve the overall efficiency of the SOT layer.

[0082] The above merely describes the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall fall within the scope of the present application.

Claims

1. A method of fabricating a magnetoresistive random access memory element, comprising: Comprising: forming a spin orbit torque layer on a substrate; forming a magnetic tunneling junction on the spin orbit torque layer; forming a first capping layer next to the magnetic tunneling junction; and performing an ion implantation fabrication process to form a first doped region within the spin orbit torque layer.

2. The method of claim 1, further comprising: forming a first intermetallic dielectric layer on the substrate; forming the spin orbit torque layer on the first intermetallic dielectric layer; forming the first capping layer on the magnetic tunneling junction and the spin orbit torque layer; performing the ion implantation fabrication process to form the first doped region within the spin orbit torque layer on a side of the magnetic tunneling junction; forming a second capping layer on the first capping layer; and forming a second intermetallic dielectric layer on the second capping layer.

3. The method of claim 2, wherein a bottom surface of the second capping layer is lower than a bottom surface of the first capping layer.

4. The method of claim 2, further comprising performing the ion implantation fabrication process to form a second doped region within the spin orbit torque layer on another side of the magnetic tunneling junction.

5. The method of claim 4, wherein a sidewall of the second doped region is trimmed to a sidewall of the first capping layer.

6. The method of claim 4, wherein the first doped region and the second doped region form a ring shape around the magnetic tunneling junction in a top view.

7. The method of claim 1, wherein a sidewall of the first doped region is trimmed to a sidewall of the first capping layer.

8. The method of claim 1, wherein the ion implantation fabrication process comprises an oblique angle ion implantation fabrication process. Comprising:

9. A Magnetoresistive Random Access Memory (MRAM) element comprising: a spin orbit torque layer disposed on a substrate; a magnetic tunneling junction disposed on the spin orbit torque layer; a first doped region disposed within the spin orbit torque layer on a side of the magnetic tunneling junction; and a second doped region disposed within the spin orbit torque layer on another side of the magnetic tunneling junction.

10. The magnetoresistive random access memory element of claim 9, further comprising: a first intermetallic dielectric layer disposed on the substrate; the spin orbit torque layer disposed on the first intermetallic dielectric layer; a first capping layer disposed next to the magnetic tunneling junction and the spin orbit torque layer; a second capping layer disposed on the first capping layer; and a second intermetallic dielectric layer disposed on the second capping layer.

11. The magnetoresistive random access memory element of claim 10, wherein a sidewall of the first doped region is trimmed to a sidewall of the first capping layer.

12. The magnetoresistive random access memory element of claim 10, wherein a sidewall of the second doped region is trimmed to a sidewall of the first capping layer.

13. The magnetoresistive random access memory element of claim 10, wherein a bottom surface of the second capping layer is lower than a bottom surface of the first capping layer.

14. The magnetoresistive random access memory element of claim 9, wherein the first doped region and the second doped region form a ring shape around the magnetic tunneling junction in a top view. Comprising: ​ ​ 15. A Magnetoresistive Random Access Memory (MRAM) element comprising: ​ A spin orbit torque (SOT) layer disposed on a substrate; A magnetic tunneling junction (MTJ) disposed on the spin orbit torque layer; and A doped region disposed within the spin orbit torque layer and surrounding the magnetic tunneling junction, wherein the doped region comprises a first recess when viewed from a top angle.

16. The magnetoresistive random access memory element of claim 15, wherein the magnetic tunneling junction comprises: a first short side; a second short side; a first long side; and a second long side.

17. The magnetoresistive random access memory element of claim 16, wherein the first recess faces the first short side.

18. The magnetoresistive random access memory element of claim 15, wherein the doped region comprises a second recess when viewed from a top angle.

19. The magnetoresistive random access memory element of claim 18, wherein the second recess faces the second short side.

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