N-path fault-tolerant processing system

Abstract

A processor [102] includes two or more core dies [104], each core die including one or more processor cores [106, 108]. A first core die of a processor is associated with a first operating system [112], and a processor core of the first core die executes an instruction set according to the first operating system to produce a first result. A second core of the processor is associated with a second operating system [112], and a processor core of the second core of the second core die executes the instruction set according to the second operating system to produce a second result. The first core die and the second core die provide the first result and the second result to a voting circuit [338] that generates an output based on the first result and the second result.

Description

BACKGROUND

[0001] The processing system runs one or more operating systems configured to manage and allocate hardware and software resources of the processing system to support the execution of applications. Additionally, the processing system includes one or more processors (e.g., central processing units) each having an architecture defined by one or more instruction set architectures (ISAs) to execute instructions for the applications. However, certain operating systems for managing applications, certain ISAs of the processors configured to execute instructions for the applications, or both, can introduce errors or security vulnerabilities into the processing system when executing the applications. For example, certain ISAs increase the risk of transient execution attacks and sampling microarchitectural data into the processing system, thereby reducing the security and reliability of the processing system. As another example, an operating system controlled by a malicious entity can remap memory addresses or replace function calls, thereby increasing the risk of exposing data in the processing system to one or more malicious entities and increasing the risk of one or more errors occurring when executing instructions for the applications. BRIEF DESCRIPTION OF DRAWINGS

[0002] The present disclosure can be better understood, and its numerous features and advantages can become more apparent, by reference to the following drawings. Like reference numerals are used throughout the drawings to refer to like or similar items. In this Specification, when a document, act, or product is referred to, it is understood that the reference is made to the document, act, or product as it existed on or before the date of the particular reference.

[0003] Figure 1 is a block diagram of a processing system 100 implementing N-way fault tolerance according to some implementations.

[0004] Figure 2 is a block diagram of a central processing unit (CPU) implementing an N-way redundancy framework according to some implementations.

[0005] Figure 3 is a block diagram of an exemplary CPU implementing an N-way operating system redundancy framework according to some implementations.

[0006] Figure 4 is a block diagram of an exemplary CPU implementing an N-way hardware redundancy framework according to some implementations.

[0007] Figure 5 is a block diagram of an exemplary CPU implementing an N-way hardware redundancy framework according to some implementations.

[0008] Figure 6 is a flow diagram illustrating an exemplary method for implementing N-way fault tolerance according to some implementations. DETAILED DESCRIPTION

[0009] To support the processing system’s execution of applications, the processing system runs one or more operating systems configured to manage (e.g., allocate, configure) resources (e.g., hardware resources, software resources) of the processing system to execute instructions, workloads, and operations for the applications. However, certain operating systems running on the processing system can introduce errors and security vulnerabilities into the processing system. As an example, when a processor executes instructions for an application, the interaction between the operating system and the application (e.g., how resources are allocated to the application) can introduce one or more errors (e.g., incorrect values), thereby reducing the reliability of the processing system. As another example, an operating system controlled by a malicious entity introduces security vulnerabilities by remapping memory addresses (e.g., page tables), altering memory requests (e.g., direct memory access (DMA) requests, memory-mapped I / O (MMIO) requests), replacing function calls, and the like. For example, these security vulnerabilities increase the risk of data in the processing system being exposed to one or more malicious entities, thereby reducing the security of the processing system.

[0010] Additionally, to support the execution of one or more applications, the processing system includes one or more processors each including one or more processor cores configured to execute instructions, workloads, and operations for the applications and configured to store data resulting from the execution of the instructions, workloads, and operations in, for example, a memory of the processing system. The architecture of these processors (e.g., the architecture of the processor cores of the processors) is defined by an instruction set architecture (ISA) that indicates: instructions, data types, registers, memory management, memory consistency, addressing modes, virtual memory, input / output models, or any combination thereof, supported by the architecture of the processors; how machine code is represented on the architecture of the processors; or both. However, executing instructions for some applications on processors defined by certain ISAs can introduce errors and security vulnerabilities (e.g., transient execution attacks, microarchitectural data sampling) into the processing system due to the architecture (e.g., the processor architecture) of the ISA, thereby reducing the security and reliability of the processing system.

[0011] To this end, the systems and techniques disclosed herein relate to processing systems that implement N-way fault tolerance. To this end, a processing system includes a central processing unit (CPU) that includes one or more core dies (e.g., corelet dies). For example, each core die includes one or more processor cores that are each configured to execute instructions, workloads, operations, or any combination thereof for an application executed by the processing system. To support N-way fault tolerance, one or more core dies of the CPU are each associated with a respective operating system, a respective ISA, or both, that is different from the operating system, the ISA, or both associated with one or more other core dies of the CPU. For example, in a particular implementation, the CPU includes a first core die that is associated with a first operating system and a second core die that is associated with a second operating system that is different from the first operating system. As another example, the CPU includes a first core die that is associated with a first ISA (e.g., has processor cores defined by the first ISA) and a second core die that is associated with a second ISA that is different from the first ISA.

[0012] According to a particular implementation, each core die (e.g., processor core of each core die) of the CPU is configured to concurrently execute the same instruction set, workload, operation, or any combination thereof for the application. For example, each core die is configured to execute the same instruction set, workload, operation, or any combination thereof for the application such that results (e.g., data resulting from execution of the instructions, workloads, or operations) are produced based on the respective operating system and ISA associated with the core die. Because one or more core dies of the CPU are each associated with a respective operating system, a respective ISA, or both, that is different from the operating system, the ISA, or both associated with one or more other core dies of the CPU, the core dies together generate multiple results, each based on the respective operating system, the ISA, or both (e.g., the operating system and ISA of the core die that generated the result). In this way, results are produced based on different operating systems, ISAs, or both. For example, a first result is produced based on a first operating system, a first ISA, or both, and a second result is produced based on a second operating system, a second ISA, or both, where the first operating system and the second operating system are different from one another, and where the first ISA and the second ISA are different from one another.

[0013] After generating the results, each core die is configured to provide the results to a voting circuit that is included in or otherwise connected to the CPU and configured to determine an output of the CPU based on the results received from the two or more core dies. In response to receiving the results from the two or more core dies, the voting circuit determines the output of the CPU based on, for example, the received results. For example, to determine the output, the voting circuit is configured to determine a majority result (e.g., the result that occurs most frequently or is the mode in the received results), a minority result (e.g., the result that occurs least frequently in the received results), or both, from the received results. In this way, the processing system implements N-way fault tolerance to help minimize errors, security vulnerabilities, or both, introduced by certain operating systems, ISAs, or both, into the processing system. As an example, in a particular implementation, three or more core dies of a CPU are each associated with a respective operating system, ISA, or both, that is different from the operating system, ISA, or both, associated with one or more other core dies of the CPU. The core dies each execute the same instruction set and provide results to the voting circuit, which then determines a majority result to determine the output of the CPU. In this way, if one of the core dies provides an incorrect result due to one or more errors, security vulnerabilities, or both, introduced by the certain operating system, ISA, or both, associated with that core die, the voting circuit still determines the correct output by determining the majority result and ignoring the incorrect result. Because the incorrect result is discarded, the security and reliability of the processing system is improved.

[0014] Figure 1is a block diagram of a processing system 100 that implements N-way fault tolerance according to some implementations. As an example, the processing system 100 includes a server system (e.g., one or more physical servers, virtual servers) configured to execute one or more applications (e.g., machine learning applications, artificial intelligence (AI) applications, deep learning applications, shader applications, high performance computing (HPC) applications, data center applications, cloud computing applications). To support execution of such applications, the processing system 100 includes or can access a memory 118 or other storage component implemented using a non-transitory computer-readable medium (e.g., dynamic random access memory (DRAM)). However, in implementations, the memory 118 is implemented using other types of memory including, for example, static random access memory (SRAM), double data rate SDRAM (DDR SRAM), non-volatile RAM, etc. According to implementations, the memory 118 includes an external memory implemented external to processing units implemented in the processing system 100. The processing system 100 also includes a bus 101 to support communication between entities implemented in the processing system 100 such as the memory 118, an accelerated processing unit (APU) 114, a central processing unit (CPU) 102, input / output (I / O) devices 120, or any combination thereof.

[0015] In implementations, the memory 118 is configured to store one or more operating systems 112 to support execution of one or more applications. Such operating systems 112 include, for example, data (e.g., program code) indicative of one or more operations, instructions, or both, to support execution of applications by the processing system 100. These operations and instructions include, for example, scheduling tasks (e.g., workloads, instructions) of one or more applications, allocating resources (e.g., registers, local data shares, temporary memory) to tasks of one or more applications, providing interfaces to I / O devices 120 (e.g., hard disks, network interface controllers, modems) of one or more applications, or any combination thereof. Although Figure 1 The example implementation illustrated in FIG. 1 A presents the memory 118 as storing two operating systems (112-1, 112-P) representative of P operating systems 112, but in other implementations, the memory 118 can store any number of operating systems 112.

[0016] Further, to support execution of one or more applications, processing system 100 includes CPU 102. CPU 102 includes, for example, one of various parallel processors, vector processors, co-processors non- scalar processors, highly parallel processors, artificial intelligence (AI) processors, inference engines, machine learning processors, other multithreaded processing units, scalar processors, serial processors, or any combination thereof. As an example, CPU 102 includes one or more dies (e.g., core dies 104, corelet dies) each including one or more parallel processors, vector processors, co-processors, non-scalar processors, highly parallel processors, AI processors, inference engines, machine learning processors, other multithreaded processing units, scalar processors, serial processors, or any combination thereof. In implementations, CPU 102 is configured to receive and execute one or more instructions for one or more applications executed by processing system 100.

[0017] In implementations, memory 118 includes program code 110 for one or more applications executed by processing system 100. Such program code 110 includes, for example, data indicative of one or more workloads, instructions, operations, or any combination thereof to be performed for one or more applications. As an example, program code 110 includes data indicative of one or more instructions to be executed by processing system 100 for an AI application, a machine learning application, an HPC application, or any combination thereof. Depending on the implementation, CPU 102 is configured to receive one or more instructions from program code 110 and, using a plurality of processor cores (e.g., processor cores 106, 108), is configured to perform one or more operations of the instructions (e.g., one or more operations indicated in the instructions). To this end, CPU 102 includes two or more core dies 104 (e.g., corelet dies) each including one or more processor cores (e.g., one or more integrated circuits (ICs) each including one or more processor cores). As an example, Figure 1 The implementation illustrated in FIG. 1 presents CPU 102 having two core dies (104-1, 104-N) representative of N core dies 104, where first core die 0 104-1 includes three processor cores (106-1, 106-2, 106-M) representative of M processor cores 106 and second core die N 104-N includes three processor cores (108-1, 108-2, 108-K) representative of K processor cores 108. Although Figure 1 While the example implementation in FIG. 1 presents CPU 102 having two core dies (104-1, 104-N) representative of N core dies 104, in other implementations, CPU 102 can include any number of core dies 104. Additionally, whileFigure 1 Exemplary implementations in which each core die 104 is presented as having three processor cores (106-1, 106-2, 106-M, 108-1, 108-2, 108-K) representing M and K processor cores 106, 108, respectively, but in other implementations, each core die 104 can include any number of processor cores. For example, in implementations, a first core die 104 has the same number of processor cores as one or more other core dies 104, a first core die 104 has a different number of processor cores than one or more other core dies 104, or both.

[0018] According to implementations, to perform one or more operations on one or more instructions of an application executed by the processing system 100, one or more processor cores 106, 108 of one or more core dies 104 of the CPU 102 each operate as a compute unit. These compute units each include one or more single instruction multiple data (SIMD) units that perform the same operation on different sets of data to produce one or more results. For example, such results include data produced by one or more processor cores 106, 108 performing one or more operations. After producing one or more results, the compute units are then configured to store the results in a cache within the compute unit (e.g., the processor core 106, 108 operating as the compute unit), the memory 118, or both, or otherwise coupled to the compute unit, the memory, or both. Additionally, in implementations, to execute one or more instructions of an application executed by the processing system 100, execute one or more instructions of an application executed by the processing system, or both, one or more processor cores 106, 108 of the core die 104 are configured to support one or more instruction set architectures (ISAs). Such ISAs include, for example, a model that indicates instructions, data types, registers, memory management, virtual memory management, I / O models, or any combination thereof, supported by one or more processors (e.g., by one or more processor cores 106, 108 of the core die 104). That is, one or more processor cores 106, 108 of the core die 104 include an architecture configured to support instruction sets defined by one or more ISAs. As an example, one or more processor cores 106, 108 of one or more core dies 104 include an architecture that supports instruction sets defined by a complex instruction set (CISC) ISA (e.g., x86). As another example, one or more processor cores 106, 108 of one or more core dies 104 include an architecture that supports instruction sets defined by a reduced instruction set (RISC) ISA (e.g., Advanced RISC Machines (ARM)).

[0019] In this manner, one or more processor cores 106, 108 of one or more core dies 104 of CPU 102 are configured to execute instructions, perform workloads, perform execution operations, or any combination thereof for one or more applications executed by processing system 100. However, due to the architecture associated with the ISA (e.g., processor architecture), the manner in which instruction sets (e.g., kernel code) are executed according to the ISA, or both, executing instructions for some applications on processor cores 106, 108 associated with certain ISAs (e.g., x86, ARM) can introduce errors and security vulnerabilities (e.g., transient execution attacks, microarchitectural data sampling) into processing system 100. Additionally, certain operating systems 112 that support execution of instructions for one or more applications can also introduce errors and security vulnerabilities into processing system 100. For example, operating systems 112 controlled by malicious entities introduce security vulnerabilities by remapping memory addresses (e.g., page tables), altering memory requests (e.g., direct memory access (DMA) requests, memory-mapped I / O (MMIO) requests), replacing function calls, and the like.

[0020] To help reduce the likelihood of such errors and security vulnerabilities in processing system 100, CPU 102 is configured to implement N-way fault tolerance. To implement N-way fault tolerance, one or more core dies 104 of CPU 102 each include processor cores 106, 108 associated with a respective ISA, a respective operating system 112, or both, that is different from the ISA, operating system 112, or both, associated with one or more other core dies 104 of CPU 102. For example, in some implementations, a first core die 104-1 of CPU 102 includes a processor core 106 having an architecture associated with a first ISA (e.g., x86), and a second core die 104-N of CPU 102 includes a processor core 108 having an architecture associated with a second ISA (e.g., ARM). As another example, a first core die 104-1 of CPU 102 includes a processor core 106 configured to execute instructions for a first operating system 112-1 (e.g., execute instructions managed by first operating system 112-1), and a second core die 104-N of CPU 102 includes a processor core 108 configured to execute instructions for a second operating system 112-P that is different from first operating system 112-1. As yet another example, a first core die 104-1 of CPU 102 includes a processor core 106 having an architecture associated with a first ISA (e.g., x86) and configured to execute instructions for a first operating system 112-1, and a second core die 104-N of CPU 102 includes a processor core 108 having an architecture associated with a second ISA (e.g., ARM) and configured to execute instructions for a second operating system 112-P that is different from first operating system 112-1.

[0021] To execute different operating systems 112 on different core dies 104 of the CPU 102, the processing system 100 is configured to execute two or more virtual machines (VMs) that are each associated with a respective operating system 112. That is, the processing system 100 executes two or more VMs, each of which runs a respective operating system 112. For example, the processing system 100 executes a first VM that runs a first operating system 112-1 and a second VM that runs a second operating system 112-P, where the first operating system 112-1 is different than the second operating system 112-P. To help support the VMs, in implementations, one or more core dies 104 of the CPU 102 are configured to function as a hypervisor (e.g., a system manager). For example, such a hypervisor includes hardware-based circuitry, software-based circuitry, or both, that are configured to create and manage the VMs executed by the processing system 100. For example, the core dies 104 include one or more processor cores 104, 106 that are configured to execute instructions, commands, operations, or any combination thereof to create and manage the VMs executed by the processing system 100.

[0022] In implementations, the one or more processor cores 104, 106 of the core dies 104 functioning as the hypervisor are configured to allocate the core dies 104 of the CPU 102 to the VMs executed by the processing system 100. For example, the one or more processor cores 104, 106 of the core dies 104 functioning as the hypervisor are configured to allocate the first core die 0 104-1 to the first VM that runs the first operating system 112-1. After the core dies 104 are allocated to the VMs, the one or more processor cores 104, 106 of the core dies 104 are configured to execute one or more instructions, workloads, operations, or any combination thereof for one or more applications (machine learning applications, AI applications, deep learning applications, shader applications, HPC applications, data center applications, cloud computing applications) executed by the VMs, the processing system 100, or both based on the operating systems 112 running on the VMs (e.g., as managed thereby). As an example, after the core die 0 104-1 is allocated to the first VM that runs the first operating system 112-1, the one or more processor cores of the core die 0 104-1 are configured to execute one or more instructions, workloads, operations, or any combination thereof for an application based on the first operating system 112-1. Because each core die 104 of the CPU 102 is allocated to a respective VM that runs a respective operating system 112, the core dies 104 of the CPU 102 are configured to execute instructions, workloads, and operations concurrently based on two or more different operating systems 112.

[0023] Additionally, in some implementations, to implement N-way fault tolerance, one or more core dies 104 of CPU 102 have programmable hardware configured to execute one or more instructions, workloads, operations, or any combination thereof for one or more applications executed by processing system 100. Such programmable hardware includes one or more programmable logic devices, e.g., simple programmable logic devices (SPLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), etc. For example, in implementations, one or more core dies 104 of CPU 102 include one or more FPGAs configured to execute one or more instructions, workloads, operations, or any combination thereof for one or more applications executed by processing system 100. In response to executing one or more instructions, workloads, or operations, the one or more programmable logic devices are configured to store results (e.g., data resulting from execution of the instructions, workloads, or operations) in, e.g., memory 118. In some implementations, CPU 102 includes one or more core dies 104 each associated with a respective ISA and operating system 112 (e.g., core dies 104 have processor cores 104, 106 associated with a respective ISA) and one or more core dies 104 each including one or more programmable logic devices (e.g., FPGAs).

[0024] In particular implementations, to implement N-way fault tolerance, two or more core dies 104 of CPU 102 are configured to execute the same workloads, instructions, operations, or any combination thereof for one or more applications in parallel. That is, processor cores 106, 108 of each core die 104 are configured to concurrently execute the same workloads, instructions, operations, or any combination thereof for the same application. As such, within the N-way redundancy framework, instructions, workloads, and operations for an application are executed on two or more core dies 104, each core die associated with a respective operating system 112 (e.g., each core die is assigned to a respective VM running a respective operating system 112 that executes the application), ISA, or both. In other words, instructions, workloads, and operations for an application are concurrently executed on two or more core dies 104 such that the instructions, workloads, and operations are executed according to two or more operating systems 112 (e.g., operating systems 112 assigned to VMs running on respective core dies 104), two or more ISAs (e.g., ISAs associated with respective core dies 104), or both. As an example, processor core 106 of first core die 104-1 is configured to execute instructions for an application executed by a first VM running a first operating system 112-1, and processor core 108 of second core die 104-2 is configured to execute the same instructions for an application executed by a second VM running a second operating system 112-P. As another example, processor core 106 of first core die 104-1 having an architecture associated with a first ISA is configured to execute instructions for an application, and processor core 108 of second core die 104-N having an architecture associated with a second ISA is configured to execute the same instructions for the application. Further, in some particular implementations, instructions, workloads, and operations for an application are executed on a core die having one or more programmable logic devices and two or more core dies 104, each core die associated with a respective operating system 112 (e.g., each core die is assigned to a respective VM running a respective operating system 112 that executes the application), ISA, or both. For example, in a particular implementation, CPU 102 includes: a first core die 104 having one or more programmable logic devices (e.g., FPGAs) configured to execute instructions for an application; a second core die 104 having processor cores 106, 108 associated with a first ISA (e.g., x86) configured to execute instructions for the application; and a third core die 104 having processor cores 106, 108 associated with a second ISA (e.g., ARM) configured to execute instructions for the application.

[0025] According to specific implementations, in response to one or more processor cores 106, 108, programmable logic devices, or both of a core die 104 completing execution of one or more instructions, workloads, operations, or any combination thereof, one or more processor cores 106, 108, programmable logic devices, or both of the core die 104 are configured to provide results (e.g., data resulting from execution of one or more instructions, workloads, operations, or any combination thereof) to a voting circuit. Such a voting circuit includes, for example, a hardware-based circuit, a software-based circuit, or both, that is configured to determine an output based on two or more results received from two or more core dies 104. In some implementations, the voting circuit is included in the core die 104 (e.g., one or more processor cores 106, 108 of the core die 104 operate as the voting circuit), while in other implementations, the CPU 102 is otherwise connected to the voting circuit. In response to receiving results from two or more core dies 104 (each resulting from execution of the same instruction, workload, operation, or any combination thereof), the voting circuit is configured to determine an output based on, for example, the received results. For example, to determine the output, the voting circuit (e.g., including a majority logic gate) is configured to determine a majority result (e.g., a result that occurs most frequently or is the mode of the received results) from the received results, determine a minority result (e.g., a result that occurs least frequently of the received results), or both. In this way, the CPU 102 implements N-way fault tolerance to help minimize errors, security vulnerabilities, or both introduced into the processing system 100 by one or more operating systems 112, ISAs, or both. For example, in implementations, three or more core dies 104 of the CPU 102 (each associated with a respective operating system 112, ISA, or both) each execute the same instruction set and provide results to the voting circuit. The voting circuit then determines a majority result (e.g., a result that occurs most frequently or is the mode of the received results) to determine an output of the CPU 102. In this way, if one of the core dies 104 of the CPU 102 provides an incorrect result due to one or more errors, security vulnerabilities, or both introduced by the operating system 112, ISA, or both associated with the core die 104, the voting circuit still determines a correct output by determining a majority result and ignoring the incorrect result. In this way, the security and fault tolerance of the processing system 100 is improved as the voting security helps ensure that errors introduced by certain operating systems 112, ISAs, or both do not affect the output of the CPU 102.

[0026] The processing system 100 also includes an APU 114, which is connected to bus 101 and thus communicates with CPU 102 and memory 118 via bus 101. APU 114 implements multiple processor cores 116-1 to 116-N that execute instructions concurrently or in parallel. In a specific implementation, one or more processor cores in processor core 116 each operate as one or more computational units (e.g., SIMD units) performing the same operation on different datasets. Although in Figure 1 In the illustrated exemplary embodiment, three processor cores (116-1, 116-2, 116-L) representing L cores are presented, but the number of processor cores 116 implemented in APU 114 is a matter of design choice. Thus, in other embodiments, APU 114 may include any number of processor cores 116. The processor cores 116 execute instructions stored in memory 118, such as program code 110 (e.g., a shader program), and APU 114 stores information in memory 118, such as the results of the executed instructions (e.g., instructions from the shader program).

[0027] Now for reference Figure 2 The document presents a CPU 102 implementing an N-way redundancy framework 200. In specific implementations, the CPU 102 implementing the N-way redundancy framework 200 includes, for example, core die 0 104-1, core die 1 104-2, core die 2 104-3, core die N 104-N, input / output (I / O) die 228, or any combination thereof. Although... Figure 2 The illustrated exemplary embodiment presents CPU 102 as having four core dies (104-1, 104-2, 104-3, 104N) representing N core dies 104; however, in other embodiments, CPU 102 may have any number of core dies 104. Depending on the embodiment, one or more core dies 104 each include one or more processor cores similar to or identical to processor cores 106, 108, which are configured to execute one or more instructions, workloads, operations, or any combination thereof for one or more applications executed by processing system 100, VM, or both. As an example, see [reference needed]. Figure 3In the specific implementation illustrated in FIG. 1, CPU 102 includes a first core die 0 104-1 that includes three processor cores (106-1, 106-2, 106-M) representing M processor cores, a second core die 1 104-2 that includes three processor cores (108-1, 108-2, 108-J) representing J processor cores, and a third core die N 104-N that includes three processor cores (232-1, 232-2, 232-L) representing L processor cores. Although Figure 2 The exemplary implementation illustrated in FIG. 1 presents core dies 104-1, 104-2, 104-N as having three processor cores, but in other implementations each core die 104 can have any respective number of processor cores. Additionally, in implementations two or more core dies 104 of CPU 102 have an equal number of processor cores, two or more core dies 104 of CPU 102 have a different number of processor cores, or both. Further, in implementations one or more core dies 104 of CPU 102 include one or more programmable logic devices 230. Such programmable logic devices 230 include, for example, SPLDs, CPLDs, FPGAs, or any combination thereof, to name a few. Although Figure 2 The exemplary implementation illustrated in FIG. 1 presents core die 2 104-3 as having two programmable logic devices (230-1, 230-K) representing K programmable logic devices, but in other implementations a core die 104 can include any number of programmable logic devices 230.

[0028] Depending on the particular implementation, one or more of the core dies 104 are configured to operate as a hypervisor. That is, one or more of the processor cores 106, 108, 232 of the core dies 104 are configured to create and manage one or more VMs executed by the processing system 100, each of which runs a respective operating system 112. To do so, the core die 104 functioning as a hypervisor is configured to allocate one or more of the other core dies 104 of the CPU 102 to one or more VMs, each of which runs a respective operating system 112. After allocation to a VM running a respective operating system 112, the processor cores 106, 108, 232 of the allocated core dies 104 are configured to execute instructions, workloads, operations, or any combination thereof for one or more applications executed by the VM based on the operating system 112 running on the VM (e.g., as managed by the operating system). By allocating VMs running different operating systems to respective core dies 104, two or more of the core dies 104 are each associated with a different operating system 112. That is, the processor cores 106, 108, 232 of two or more of the core dies 104 are each configured to execute instructions, workloads, operations, or any combination thereof for applications managed by different operating systems 112.

[0029] In particular implementations, one or more core dies 104 of the CPU are each associated with a respective operating system 112 (e.g., assigned to a respective VM running the respective operating system 112), associated with a respective ISA (e.g., the processor cores 106, 108, 232 of the core die 104 have an architecture defined by the respective ISA), include one or more programmable logic devices 230, or any combination thereof. For example, in particular implementations, two or more core dies 104 of the CPU are each associated with a respective different operating system 112 (e.g., each core die 104 is assigned to a respective VM running a respective different operating system 112), two or more core dies 104 are each associated with a respective different ISA, one or more core dies 104 include one or more programmable logic devices (e.g., FPGAs), or any combination thereof. In this way, the CPU 102 is configured to concurrently execute the same instruction set, workload, operation, or any combination thereof for one or more applications using one or more operating systems 112, ISAs, programmable devices 230, or any combination thereof. As an example, the CPU 102 is configured to concurrently execute an instruction set for an application on a first core die 0 104-1 including processor cores 106 associated with a first operating system 112-1 (e.g., the processor cores 106 are configured to execute instructions, workloads, and operations managed by the operating system 112-1), a second core die 1 104-2 including processor cores 108 associated with a second operating system 112-P, and a third core die 2 104-2 having one or more programmable logic devices 230, where the first operating system 112-1 and the second operating system 112-P are each different from one another. As another example, the CPU 102 is configured to concurrently execute an instruction set for an application on a first core die 0 104-1 including processor cores 106 associated with a first ISA (e.g., the processor cores 106 have an architecture based on the first ISA) and a second core die 1 104-2 including processor cores 108 associated with a second ISA, where the first ISA and the second ISA are different. As yet another example, the CPU 102 is configured to concurrently execute the same instruction set on a first core die 0 104-1 including processor cores 106 associated with a first operating system 112-1 and a first ISA and a second core die 1 104-2 including processor cores 108 associated with a second operating system 112-P and a second ISA, where the first operating system 112-1 and the second operating system 112-P are different, and where the first ISA and the second ISA are different.

[0030] To help support the execution of instructions, workloads, and operations on the CPU 102, the CPU 102 includes an I / O die 228 connected to each of the core dies 104. The I / O die 228 includes hardware-based circuitry, software-based circuitry, or both, that is configured to provide an interface between the core dies 104 and the memory 118, between the core dies and one or more I / O devices 120, or between the core dies and both the memory and the one or more I / O devices. To this end, the I / O die 228 includes or otherwise connects to a data fabric 224 that includes hardware-based circuitry, software-based circuitry, or both, that provides an interconnect fabric between the core dies 104, the I / O die 228 (e.g., I / O controllers 222, memory controllers 226), the memory 118, the one or more I / O devices 120, the bus 101, or any combination thereof. As an example, the data fabric 224 provides an interconnect fabric between the core dies 104, the memory controllers 226, and the memory 118. As another example, the data fabric 224 provides an interconnect fabric between the core dies 104, the one or more I / O controllers 222, and the one or more I / O devices 120. Additionally, to provide an interface between the core dies 104 and the memory 118, the I / O die 228 includes a memory controller 226. The memory controller 226 includes, for example, hardware-based circuitry, software-based circuitry, or both, that is configured to access, modify, and delete data in the memory 118. For example, the memory controller 226 is configured to access, modify, and delete data in the memory 118 to help manage read operations, write operations, fetch operations, pre-fetch operations, copy operations, or any combination thereof, between the core dies 104 and the memory 118. Further, to provide an interface between the core dies 104 and the one or more I / O devices 120, the I / O die 228 includes one or more I / O controllers 222. Such I / O controllers 222 each include, for example, hardware-based circuitry, software-based circuitry, or both, that is configured to manage data transfers (e.g., memory access requests) between the core dies 104, the memory 118, and the one or more I / O devices 120. For example, the I / O controllers 222 are configured to manage direct memory access (DMA) requests from the I / O devices 120 to access the memory 118. As another example, the I / O controllers 222 are configured to manage memory-mapped input / output (MMIO) requests from the one or more core dies 104 to access memory or registers of the I / O devices 120.

[0031] According to some implementations, one or more core dies 104 of CPU 102 function as a voting circuit, while in other implementations, CPU 102 is connected to such a voting circuit in other ways. The voting circuit, for example, includes a hardware-based circuit, a software-based circuit, or both, that is configured to determine an output of CPU 102 based on two or more received results from two or more core dies 104 (e.g., data resulting from execution of one or more instructions of an application, a workload, an operation, or any combination thereof executed by processing system 100, a VM, or both). As an example, in implementations, one or more core dies 104 each include one or more processor cores 106, 108, 232 that are configured to determine an output based on results received from two or more other core dies 104. To do so, in response to receiving results from two or more core dies 104 (each resulting from execution of the same instruction, workload, operation, or any combination thereof for an application), one or more processor cores 106, 108, 232 of the core die 104 operating as a voting circuit are configured to determine an output of CPU 102 by, for example, determining a majority result from the received results (e.g., a result that occurs most frequently or is the mode of the received results), determining a minority result from the received results (e.g., a result that occurs least frequently), or both. In this way, CPU 102 implements an N-way redundancy framework 200 to help minimize errors, security vulnerabilities, or both introduced into processing system 100 by one or more operating systems 112, ISAs, or both.

[0032] Referring now to Figures 3 to 5 , a CPU 102 implementing an example N-way redundancy framework is presented. In implementations, the example N-way operating system redundancy framework 300 includes CPU 102 having core die 1 104-1, core die 2 104-2, core die 2 104-3, and core die N 104-N. Additionally, to provide an interface between core dies 104 and memory 118, core dies and one or more I / O devices 120, or core dies and both memory and one or more I / O devices, CPU 102 includes I / O die 228. Although Figures 3 to 5 The example implementation presented in FIG. 3 presents CPU 102 as having four core dies (104-1, 104-2, 104-3, 104-N) representative of an N number of core dies 104, in other implementations, CPU 102 can have any number of core dies 104.

[0033] In particular implementations, the processing system 100 is configured to execute one or more VMs. Each VM executed by the processing system 100 is configured to run a respective operating system 112, for example. As an example, one or more VMs executed by the processing system 100 are configured to run an operating system 112 that is different from one or more operating systems 112 run by one or other VMs. Additionally, each VM is configured to execute an application managed by the operating system 112 running on the VM. Depending on the implementation, one or more core dies 104 of the CPU 102 are configured to function as a hypervisor that is configured to create and manage the VMs executed by the processing system 100. That is, the one or more core dies 104 run a hypervisor, a system hypervisor, or both, for the processing system 100. To that end, the core dies 104 (e.g., core dies N 104-N) include hypervisor circuitry 336 that includes hardware-based circuitry, software-based circuitry, or both, configured to create and manage the VMs. For example, the hypervisor circuitry 336 includes one or more processor cores 106, 108, 232 configured to execute instructions, commands, operations, or any combination thereof, to create and manage the VMs. Depending on the implementation, the hypervisor circuitry 336 is configured to allocate one or more core dies 104 to one or more respective VMs executed on the processing system 100. In some implementations, the hypervisor circuitry 336 is configured to allocate an equal number of core dies 104 to each VM executed by the processing system 100, while in other implementations, the hypervisor circuitry 336 is configured to allocate different numbers of core dies 104 to two or more VMs executed by the processing system 100.

[0034] Reference is now made to Figure 3presented. Because each VM runs a respective operating system 112, within the N-way operating system redundancy framework 300, the hypervisor circuitry 336 is configured to allocate core dies 104 to VMs such that two or more core dies 104 are associated with different operating systems 112. That is, the hypervisor circuitry 336 is configured to allocate one or more core dies 104 to a first VM running a first operating system 112 and one or more other core dies 104 to one or more other VMs each running a respective operating system 112 different from the first operating system 112, one or more operating systems 112 run by the other VMs, or both. For example, the hypervisor circuitry 336 is configured to allocate a first core die 0 104-1 to a first VM running a first operating system 0 112-1, a second core die 1 104-2 to a second VM running a second operating system 1 112-2, and a third core die 2 104-3 to a third VM running a third operating system 2 112-3, where the first, second, and third operating systems 112-1, 112-2, 112-3 are each different from one another. After being allocated to a VM running a respective operating system 112, a core die 104 (e.g., a processor core 106, 108, 232 of the core die 104) is configured to execute instructions, workloads, operations, or any combination thereof for an application performed by the VM based on the operating system 112 running on the VM. In implementations, each core die 104 is allocated to a respective VM running the same application. In this way, each core die 104 associated with a respective operating system 112 is configured to concurrently execute the same instructions, workloads, operations, or any combination thereof for the same application. In other words, two or more core dies 104 of the CPU 102 concurrently execute the same instructions, workloads, operations, or any combination thereof for an application according to two or more respective operating systems 112 (e.g., the operating system 112 associated with each core die 104) (e.g., as governed thereby). In this way, the CPU 102 is configured to execute the same instructions, workloads, operations, or any combination thereof for an application according to different operating systems 112.

[0035] In response to executing one or more instructions, workloads, operations, or any combination thereof for an application, each core die 104 is configured to provide results 342 (e.g., data resulting from execution of the instructions, workloads, operations, or any combination thereof) to a voting circuit 338 included in the CPU 102 or otherwise connected to the CPU. That is, the core dies 104 provide results 342 from executing the same instruction set, workload, operation, or any combination thereof in accordance with (e.g., as directed by) two or more operating systems 112 (e.g., the operating system 112 associated with each core die 104 providing the results 342). The voting circuit 338 includes, for example, hardware-based circuitry, software-based circuitry, or both, configured to determine an output 344 of the CPU 102 based on, for example, the received results 342 (e.g., the results 342 received from each core die 104 associated with a respective operating system 112). For example, to determine the output 344, the voting circuit (e.g., including a majority logic gate) is configured to determine a majority result (e.g., the result that occurs most frequently or is the mode in the received results 342) from the received results 342, determine a minority result (e.g., the result that occurs least frequently in the received results 342) from the received results 342, or both. In this way, the CPU 102 implements the N-way operating system redundancy framework 300 to help minimize errors, security vulnerabilities, or both introduced by one or more operating systems 112 into the processing system 100. For example, in a particular implementation, the CPU 102 includes a first core die 0 104-1 associated with a first operating system 0 112, a second core die 1 104-2 associated with a second operating system 1 112-2, and a third core die 2 104-3 associated with a third operating system 2 112-3, each core die configured to execute the same instruction set for an application. In response to executing the instruction set, each core die 104 is configured to provide results (e.g., data resulting from execution of the instruction set) to the voting circuit 338. The voting circuit 336 then determines a majority result (e.g., the result that occurs most frequently or is the mode in the received results 342) to determine the output 344 of the CPU 102. In this way, if one of the core dies 104 of the CPU 102 provides an incorrect result due to one or more errors, security vulnerabilities, or both introduced by the operating system (e.g., operating system 0 112-1, operating system 1 112-2, operating system 2 112-3) associated with the core die 104, the voting circuit still determines the correct output 344 by determining the majority result and ignoring the incorrect result caused by the one or more errors, security vulnerabilities, or both introduced by the operating system 112.

[0036] Reference is now made to Figure 4presented within an N-way hardware redundancy framework 400. Within the N-way hardware redundancy framework 400, the CPU 102 includes one or more core dies 104 associated with one or more ISAs 440 (e.g., one or more cores 104 including processor cores 106, 108, 232 having architectures associated with one or more ISAs 440), one or more core dies 104 each including one or more programmable logic devices 230, or both. For example, the CPU 102 includes a first core die 0 104-1 associated with a first ISA 0 440-1 (e.g., x86), a second core die 1 104-2 associated with a second ISA 1 440-2 (e.g., ARM), and a third core die 2 104-3 including one or more programmable logic devices 230 (e.g., FPGAs). Although Figure 4 The illustrated example implementation presents the core die 2 104-3 as having two programmable logic devices (230-1, 230-K) representative of K programmable logic devices 230, but in other implementations, a core die 104 can include any number of programmable logic devices 230. According to the implementation, the hypervisor circuit 336 is configured to assign each core die 104 to a respective VM such that each core die 104 executes the same instructions, workloads, operations, or any combination thereof for applications executed by each of the VMs. In this way, each core die 104 is configured to concurrently execute the same instructions, workloads, operations, or any combination thereof for the same application. As such, the CPU 102 is configured to execute the same instructions, workloads, operations, or any combination thereof for an application using different hardware (e.g., based on core dies 104). For example, the CPU 102 is configured to execute the same instructions, workloads, operations, or any combination thereof using core dies 104 associated with two or more different ISAs 440 (e.g., x86, ARM). Additionally, the CPU 102 is configured to execute the same instructions, workloads, operations, or any combination thereof for an application using core dies 104 associated with one or more ISAs 440 (e.g., x86, ARM), having one or more programmable logic devices 230, or both.

[0037] In response to executing one or more instructions, workloads, operations, or any combination thereof for an application, each core die 104 is configured to provide results 342 (e.g., data resulting from execution of the instructions, workloads, operations, or any combination thereof) to a voting circuit 338 included in the CPU 102 or otherwise connected to the CPU. That is, the core dies 104 provide results 342 from executing the same instruction set, workload, operation, or any combination thereof based on the hardware (ISA 440, programmable logic device) associated with the core dies 104. To determine an output 344, the voting circuit 338 (e.g., including a majority logic gate) is configured to determine a majority result (e.g., a result that occurs most frequently or is the mode in the received results 342) from the received results 342, determine a minority result (e.g., a result that occurs least frequently in the received results 342) from the received results 342, or both. In this way, the CPU 102 implements the N-way hardware redundancy framework 300 to help minimize errors, security vulnerabilities, or both introduced by one or more ISAs 440 into the processing system 100. For example, in a particular implementation, the CPU 102 includes a first core die 1 104-1 associated with a first ISA 0 440-1 (e.g., x86), a second core die 2 104-2 associated with a second ISA 1 440-2 (e.g., ARM), and a third core die 3 104-3 including one or more programmable logic devices 230 (e.g., FPGAs) each configured to execute the same instruction set for an application. In response to executing the instruction set, each core die 104 is configured to provide results (e.g., data resulting from execution of the instruction set) to the voting circuit 338. The voting circuit 338 then determines a majority result (e.g., a result that occurs most frequently or is the mode in the received results 342) to determine an output 344 of the CPU 102. In this way, if one of the core dies 104 of the CPU 102 provides an incorrect result due to one or more errors, security vulnerabilities, or both introduced by the ISA 440 associated with the core die 104, the voting circuit still determines a correct output 344 by determining the majority result and ignoring the incorrect result caused by the ISA 440 introducing the one or more errors, security vulnerabilities, or both.

[0038] Reference is now made to Figure 5presented in FIG. 1, the CPU 102 includes one or more core dies 104 (e.g., one or more cores 104 including processor cores 106, 108, 232 having architectures associated with one or more ISAs 440) associated with one or more ISAs 440. For example, the CPU 102 includes a first core die 0 104-1 associated with a first ISA 0 440-1 (e.g., x86), a second core die 1 104-2 associated with a second ISA 1 440-2 (e.g., ARM), and a third core die 2 104-3 associated with the second ISA 1 440-2 (e.g., ARM). Depending on the implementation, the hypervisor circuit 336 is configured to assign each core die 104 to a respective VM such that each core die 104 executes the same instructions, workloads, operations, or any combination thereof for applications executed by each of the VMs. In this way, each core die 104 is configured to concurrently execute the same instructions, workloads, operations, or any combination thereof for the same application. As such, the CPU 102 is configured to execute the same instructions, workloads, operations, or any combination thereof for an application using different hardware (e.g., based on the core dies 104). For example, the CPU 102 is configured to execute the same instructions, workloads, operations, or any combination thereof using core dies 104 associated with two or more different ISAs 440 (e.g., x86, ARM).

[0039] To support execution of one or more instructions, workloads, operations, or any combination thereof of an application by the core dies 104, the CPU 102 includes a respective I / O die 544 for one or more core dies 104 of the CPU 102 that is similar or identical to the I / O die 228. For example, the CPU 102 includes a respective I / O die 544 connected to each core die 104 of the CPU 102. In some implementations, each I / O die 544 comprises a separate and distinct die, while in other implementations, each I / O die 544 is formed from a partition of a larger I / O die (e.g., the I / O die 228). Although Figure 5 The example implementation presented in FIG. 1 presents the CPU 102 including four I / O dies (544-1, 544-2, 544-3, 544-N) representing N I / O dies 544, but in other implementations, the CPU 102 can have any number of I / O dies 544. For example, in implementations, the CPU 102 has an I / O die 544 for each core die 104 of the CPU 102.

[0040] Depending on the particular implementation, each I / O die 544 is associated with (e.g., connected to) a respective core die 104. For example, a first I / O die 0 544-1 is associated with a first core die 0 104-1, a second I / O die 1 544-2 is associated with a second core die 1 104-2, a third I / O die 2 544-3 is associated with a third core die 2 104-3, and a fourth I / O die 544-N is associated with a fourth core die N 104-N. Further, each I / O die 544 includes hardware-based circuitry, software-based circuitry, or both, that is configured to provide an interface between a respective core die 104 and the memory 118, between the respective core die and the one or more I / O devices 120, or between the respective core die and both the memory and the one or more I / O devices. For example, each I / O die 544 includes or is otherwise connected to a respective data fabric 224 to provide an interconnect fabric between the respective core die 104, the memory 118, the one or more I / O devices 120, the bus 101, or any combination thereof. Additionally, to provide an interface between the core dies 104 and the memory 118, each I / O die 544 includes a respective memory controller 226 that is configured to access, modify, and delete data in the memory 118. Further, to provide an interface between the respective core dies 104 and the one or more I / O devices 120, each I / O die 544 includes one or more respective I / O controllers 222 that are configured to manage data transfers (e.g., memory access requests) between the respective core dies 104, the memory 118, and the one or more I / O devices 120. Because each core die 104 interfaces with the memory 118 and the I / O devices 120 through a respective I / O die 104, the processing system 100 is able to partition the memory 118 and the I / O devices 120 such that only respective partitions of the memory 118 and the I / O devices 120 are accessible by certain core dies 544. As a result of this partitioning, a level of redundancy in the processing system 100 is improved, which reduces a likelihood that the operating system 112, the ISA, or both, will introduce further errors, security vulnerabilities, or both, into the processing system 100, and improves a reliability of the processing system 100.

[0041] Additionally, in particular implementations, each I / O die 544 is associated with an ISA (e.g., ISA 440). That is, each I / O die 544 has an ISA-based architecture such that the I / O die 544 is configured to perform one or more operations (e.g., memory ordering, interrupt delivery, I / O device control, input-output memory management unit (IOMMU) implementation, root complex interaction, memory interaction) in accordance with the ISA. According to implementations, each I / O die 544 is associated with the same ISA as a core die 104 with which the I / O die 544 is associated. For example, I / O die 0 544-1 is associated with ISA 0 440-1 as is core die 0 104-1. In this way, each I / O die 544 is configured to support each core die 104 when two or more core dies 104 are associated with different ISAs (e.g., x86, ARM).

[0042] Referring now to Figure 6presenting an exemplary method 600 for implementing N-way fault tolerance. In particular implementations, the method 600 includes the CPU 102 having one or more core dies 104 each associated with a respective ISA 440 (e.g., having one or more processor cores 106, 108, 232 associated with a respective ISA 440), associated with one or more core dies 104 having a programmable logic device 230 (e.g., FPGA), or both. Additionally, the CPU 102 includes a core die 104 that includes a hypervisor circuit 336 (e.g., one or more processing cores 106, 108, 232 that execute one or more instructions to create and manage VMs). At step 605, the hypervisor circuit 336 is configured to allocate two or more core dies 104 of the CPU 102 to respective VMs executed by the processing system 100. In particular implementations, each VM executed by the processing system 100 executes the same application and runs a respective operating system 112, where two or more VMs executed by the processing system 100 run different operating systems 112. As an example, the hypervisor circuit 336 is configured to allocate a first core die 104 to a first VM running a first operating system 112, a second core die 104 to a second VM running a second operating system 112, and a third core die 104 to a third VM running a third operating system 112, where the first, second, and third operating systems 112 are each different from one another. As another example, the hypervisor circuit 336 is configured to allocate the same operating system to two or more core dies 104 each associated with a different ISA 440. As yet another example, the hypervisor circuit 336 is configured to allocate a first core die 104 associated with a first ISA 112 to a first VM running a first operating system 112 and a second core die 104 associated with a second ISA 112 to a second VM running a second operating system 440, where the first ISA 440 is different from the second ISA 112, and where the first operating system 440 is different from the second operating system 440.

[0043] At step 610, in response to being assigned to the VM, the core die 104 is configured to execute the instruction set, workload, operation, or any combination thereof for the same application executed by the processing system 100, the respective VM (e.g., the VM to which the core die 104 is assigned), or both. That is, the processor cores 106, 108, 232 of each core die 104 execute the instruction set, workload, operation, or any combination thereof for the same application executed by the processing system 100, the respective VM, or both. In this way, the core die 104 executes the instruction set, workload, operation, or any combination thereof using two or more operating systems 112, two or more ISAs 440, or both. At step 615, after executing the instruction set, workload, operation, or any combination, each core die 104 provides the results 342 (e.g., data resulting from the execution of the instruction, workload, operation, or any combination thereof) to the voting circuit 336. Such results 342, for example, represent the concurrent execution of the same instruction set, workload, operation, or any combination thereof according to two or more operating systems 112, ISAs 440, or both (e.g., according to the operating system 112 and the ISA 440 associated with the core die 104).

[0044] At step 620, in response to receiving the results 342 from the core dies 104, the voting circuit 336 is configured to determine the output 344 of the CPU 102 based on, for example, the received results 342. For example, to determine the output 344 of the CPU 102, the voting circuit (e.g., including a majority logic gate) is configured to determine a majority result (e.g., the result that occurs most frequently or is the mode in the received results) from the received results 342, to determine a minority result (e.g., the result that occurs least frequently in the received results) from the received results 342, or both. In this way, the CPU 102 implements N-way fault tolerance to help minimize errors, security vulnerabilities, or both introduced into the processing system 100 by one or more operating systems 112, ISAs, or both.

[0045] As disclosed herein, in some embodiments, a processor includes: a first core die associated with a first operating system and including one or more processor cores, wherein the one or more processor cores of the first core die are configured to execute instructions to produce a first result; a second core die associated with a second operating system and including one or more processor cores, wherein the one or more processor cores of the second core die are configured to execute instructions to produce a second result, and wherein the second operating system is different from the first operating system; and a voting circuit configured to generate an output based on the first result and the second result. In one aspect, the processor includes: a third core die associated with a third operating system and including one or more processor cores, wherein the one or more processor cores of the third core die are configured to execute instructions to produce a third result. In another aspect, the voting circuit is configured to generate the output based on the first result, the second result, and the third result. In yet another aspect, the one or more processor cores of the first core die are associated with a first instruction set architecture (ISA); the one or more processor cores of the second core die are associated with a second ISA; and the second ISA is different from the first ISA.

[0046] In one aspect, a first input / output (I / O) die is associated with the first ISA and connected to the first core die; and a second I / O die is associated with the second ISA and connected to the second core die. In another aspect, the processor includes: a third core die including one or more programmable logic devices. In yet another aspect, the processor includes: a third core die including one or more processor cores configured to: allocate the first core die to a first virtual machine (VM) running the first operating system; and allocate the second core die to a second VM running the second operating system.

[0047] In some embodiments, a method includes executing instructions on a first core die of a processor to produce a first result, wherein the first core die is associated with a first operating system; executing instructions on a second core die of the processor to produce a second result, wherein the second core die is associated with a second operating system, and wherein the second operating system is different than the first operating system; and generating an output based on the first result and the second result. In one aspect, the instructions are executed concurrently on the first core die and the second core die. In another aspect, the method includes executing instructions on a third core die of the processor to produce a third result, wherein the third core die is associated with a third operating system, and wherein the output is generated based on the first result, the second result, and the third result. In yet another aspect: the first core die includes one or more processor cores associated with a first instruction set architecture (ISA); the second core die includes one or more processor cores associated with a second ISA; and the second ISA is different than the first ISA.

[0048] In one aspect, the method includes assigning the first core die to a first virtual machine (VM) running a first operating system; and assigning the second core die to a second VM running a second operating system. In another aspect, the processor further includes a third core die including one or more programmable logic devices.

[0049] In some embodiments, a processor includes: a first core die including one or more processor cores associated with a first instruction set architecture (ISA), wherein the one or more processor cores of the first core die are configured to execute instructions to produce a first result; a second core die including one or more processor cores associated with a second ISA, wherein the one or more processor cores of the second core die are configured to execute instructions to produce a second result, and wherein the second ISA is different than the first ISA; and a voting circuit configured to generate an output based on the first result and the second result. In one aspect, the first core die is associated with a first operating system; the second core die is associated with a second operating system; and the second operating system is different than the first operating system. In another aspect, the processor includes: a third core die including one or more processor cores configured to: assign the first core die to a first virtual machine (VM) running a first operating system; and assign the second core die to a second VM running a second operating system.

[0050] In one aspect, the processor includes a first input / output (I / O) die associated with the first ISA and connected to the first core die, and a second I / O die associated with the second ISA and connected to the second core die. In another aspect, the processor includes a third core die including one or more programmable logic devices. In yet another aspect, the one or more programmable logic devices include one or more field programmable gate arrays. In still another aspect, the one or more processor cores of the first core die and the one or more processor cores of the second core die are configured to concurrently execute instructions.

[0051] In some implementations, the above-described devices and techniques are implemented in systems including one or more integrated circuit (IC) devices (also referred to as integrated circuit packages or microchips), such as the CPUs described above with reference to Figures 1 to 6 Electronic design automation (EDA) and computer-aided design (CAD) software tools can be used in the design and manufacture of these IC devices. These design tools typically are represented as one or more software programs. The one or more software programs include code executable by a computer system to manipulate the computer system to operate on code representative of circuitry of one or more IC devices so as to perform at least a portion of a process to design or adapt a manufacturing system to manufacture the circuitry. The code can include instructions, data, or a combination of instructions and data. The software instructions representative of the design tool or manufacturing tool typically are stored in a computer-readable storage medium accessible to the computing system. Also, the code representative of one or more phases of the design or manufacture of the IC device can be stored on and accessed from the same computer-readable storage medium or a different computer-readable storage medium.

[0052] The computer-readable storage medium can include any non-transitory storage medium (or combination of non-transitory storage media) readable by a computer system including optical, magnetic, or semiconductor storage. The computer-readable storage medium can also include pentaerythritol, a medium that can be accessed via a wired or wireless communication medium such as the Internet. The computer-readable storage medium can also be embedded in a computer system (e.g., system RAM or ROM), fixed in a computer system (e.g., on a hard disk drive), removable from a computer system (e.g., on a Universal Serial Bus (USB) flash drive), or coupled to a computer system via a wired or wireless network (e.g., network accessible storage).

[0053] In some implementations, certain aspects of the techniques described above can be implemented by one or more processors of a processing system executing software. The software includes one or more sets of executable instructions stored or otherwise tangibly embodied on a non-transitory computer- readable storage medium. The software can include the instructions and certain data that, when executed by the one or more processors, manipulate the one or more processors to perform one or more aspects of the techniques described above. The non-transitory computer-readable storage medium can include, for example, magnetic disks or optical disks, solid-state memory such as Flash memory, cache memory, random access memory (RAM) or other non-volatile storage device, etc. The executable instructions stored on the non-transitory computer-readable storage medium can be in source code, assembly language code, object code, or other instruction format that is interpreted or otherwise executable by one or more processors.

[0054] Note that not all of the activities or elements described above in the general description are required, that a portion of a specific activity or device can not be required, and that one or more further activities can be performed, or elements included, in addition to those described. Still further, the order in which activities are listed are not necessarily the order in which they are performed. Also, the concepts have been described with reference to particular means, materials, and embodiments. A person of ordinary skill in the art understands that variations in these specific details are encompassed by the disclosure. Accordingly, the disclosure is not limited to the specific details described above.

[0055] Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems and any feature(s) that can cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature of any or all the claims. Furthermore, the particular embodiments disclosed above are illustrative only as to a possible implementation and are not intended to limit the claimed subject matter in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the claimed subject matter to those skilled in the art. Other embodiments can be apparent to those of ordinary skill in the art from the disclosure provided herein, which incorporates all such alternatives, modifications and variations in the scope of the present disclosure. Accordingly, it is submitted that that all such alternatives, modifications and variations are meant to be within the scope of the claimed subject matter.

Claims

1. A processor comprising: a first core die associated with a first operating system and comprising one or more processor cores, wherein the one or more processor cores of the first core die are configured to execute an instruction to produce a first result; a second core die associated with a second operating system and comprising one or more processor cores, wherein the one or more processor cores of the second core die are configured to execute the instruction to produce a second result, and wherein the second operating system is different from the first operating system; and a voting circuit configured to generate an output based on the first result and the second result.

2. The processor of claim 1, further comprising: a third core die associated with a third operating system and comprising one or more processor cores, wherein the one or more processor cores of the third core die are configured to execute the instruction to produce a third result. the voting circuit is configured to generate the output based on the first result, the second result, and the third result.

3. The processor of claim 2, wherein, 4. The processor of claim 1, wherein: the one or more processor cores of the first core die are associated with a first instruction set architecture (ISA); the one or more processor cores of the second core die are associated with a second ISA; and the second ISA is different from the first ISA.

5. The processor of claim 4, further comprising: a first input / output (I / O) die associated with the first ISA and connected to the first core die; and a second I / O die associated with the second ISA and connected to the second core die.

6. The processor of claim 1, further comprising: a third core die comprising one or more programmable logic devices.

7. The processor of claim 1, further comprising: a third core die comprising one or more processor cores configured to: allocate the first core die to a first virtual machine (VM) running the first operating system; and allocate the second core die to a second VM running the second operating system.

8. A method comprising: executing an instruction on a first core die of a processor to produce a first result, wherein the first core die is associated with a first operating system; executing the instruction on a second core die of the processor to produce a second result, wherein the second core die is associated with a second operating system, and wherein the second operating system is different from the first operating system; and generating an output based on the first result and the second result. the instruction is executed concurrently on the first core die and the second core die. ​ ​ ​ 9. The method of claim 8, wherein, ​ 10. The method of claim 8, further comprising: executing the instructions on a third core die of the processor to produce a third result, wherein the third core die is associated with a third operating system, and wherein the output is generated based on the first result, the second result, and the third result.

11. The method of claim 8, wherein: the first core die comprises one or more processor cores associated with a first instruction set architecture (ISA); the second core die comprises one or more processor cores associated with a second ISA; and the second ISA is different from the first ISA.

12. The method of claim 8, further comprising: allocating the first core die to a first virtual machine (VM) running the first operating system; and allocating the second core die to a second VM running the second operating system.

13. The method of claim 8, wherein, the processor further comprises a third core die comprising one or more programmable logic devices.

14. A processor, comprising: a first core die comprising one or more processor cores associated with a first instruction set architecture (ISA), wherein the one or more processor cores of the first core die are configured to execute instructions to produce a first result; a second core die comprising one or more processor cores associated with a second ISA, wherein the one or more processor cores of the second core die are configured to execute the instructions to produce a second result, and wherein the second ISA is different from the first ISA; and and voting circuitry configured to generate an output based on the first result and the second result.

15. The processor of claim 14, wherein: the first core die is associated with a first operating system; the second core die is associated with a second operating system; and the second operating system is different from the first operating system.

16. The processor of claim 15, further comprising: a third core die comprising one or more processor cores configured to: allocate the first core die to a first virtual machine (VM) running the first operating system; and allocate the second core die to a second VM running the second operating system.

17. The processor of claim 14, further comprising: a first input / output (I / O) die associated with the first ISA and connected to the first core die; and a second I / O die associated with the second ISA and connected to the second core die.

18. The processor of claim 14, further comprising: a third core die comprising one or more programmable logic devices. ​ 19. The processor of claim 18, wherein, The one or more programmable logic devices include one or more field programmable gate arrays.

20. The processor of claim 14, wherein, The one or more processor cores of the first core die and the one or more processor cores of the second core die are configured to execute the instructions concurrently.

Images