Electronic device with post-molded nickel tungsten and tin dual layer for improved
By employing a double-layer plating process of nickel-tungsten and tin on the conductive leads, the board-level reliability problem caused by tin plating on bare copper leads is solved, improving heat dissipation at high temperatures and reducing costs, while providing an efficient diffusion barrier layer and interface stability.
Patent Information
- Application Number
- CN202380095735.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-04-28
- Filing Date
- 2023-12-29
- Publication Date
- 2025-11-07
AI Technical Summary
Tin plating of bare copper leads may reduce the board-level reliability of electronic systems, especially at high temperatures where heat dissipation and material defects are prominent issues, and existing plating processes are expensive.
A double-layer plating process using nickel-tungsten and tin is adopted. First, a nickel-tungsten layer is formed on the surface of the conductive lead, and then a tin layer is plated on it to form a diffusion barrier layer to prevent copper and tin from diffusing into each other. A matte tin layer is formed through an electroless plating process to reduce the risk of interface cracking.
It improves board-level reliability of electronic devices, extends shelf life, reduces manufacturing costs, and avoids the use of expensive plating alternatives.
Smart Images
Figure CN120917564A_ABST
Abstract
Description
BACKGROUND
[0001] Copper integrated circuit leads can be tinned in order to mitigate degradation of material properties and extend shelf life prior to soldering to a printed circuit board. However, tinning of bare copper leads can impact board level reliability (BLR) of electronic systems due to cracking and material defects at the solder joints of integrated circuit leads and pads of printed circuit boards. Additionally, for compact and more highly integrated systems with smaller features and higher currents, heat dissipation through die attach structures is important for mitigation of degradation and operation enhancement of electronic devices at high temperatures. SUMMARY
[0002] In one aspect, an electronic device includes a semiconductor die, a package structure enclosing the semiconductor die, and a conductive lead having a first surface and a second surface, the first surface having a bilayer exposed outside the package structure along one side of the package structure, and the second surface exposed outside the package structure along another side of the package structure, the bilayer including a first plating layer and a second plating layer, the first plating layer on and contacting the first surface of the conductive lead, the second plating layer on and contacting the first plating layer and exposed outside the package structure along the side of the package structure, the first plating layer including nickel tungsten, and the second plating layer including tin.
[0003] In another aspect, a system includes a circuit board and an electronic device. The electronic device includes a semiconductor die, a package structure enclosing the semiconductor die, and a conductive lead electrically coupled to a circuit of the semiconductor die and a conductive feature of the circuit board. The conductive lead has a first surface and a second surface, the first surface having a bilayer exposed outside the package structure along one side of the package structure, and the second surface exposed outside the package structure along another side of the package structure, the bilayer including a first plating layer and a second plating layer, the first plating layer on and contacting the first surface of the conductive lead, the second plating layer on and contacting the first plating layer and exposed outside the package structure along the side of the package structure, the first plating layer including nickel tungsten, and the second plating layer including tin.
[0004] In another aspect, a method of manufacturing an electronic device includes performing a first plating process that forms a first plating layer on a first surface of a conductive lead exposed along a side of a molded structure in an array of panels of an intended electronic device, the first plating layer including nickel tungsten; performing a second plating process that forms a second plating layer on the first plating layer, the second plating layer including tin; and performing a package singulation process that singulates the electronic device from the array of panels, wherein the conductive lead is exposed along a side of a respective package structure, the package singulation process exposing a second surface of the conductive lead along a first side of the package structure. BRIEF DESCRIPTION OF DRAWINGS
[0005] Figure 1 is a perspective view of an electronic device.
[0006] Figure 1A is a bottom view of the electronic device of Figure 1
[0007] Figure 1B is a partial cross-sectional side elevation view of the electronic device of Figure 1 and 1A
[0008] Figure 2 is a flowchart of a method of manufacturing an electronic device.
[0009] Figures 3 to 8 is a partial cross-sectional side elevation view of the electronic device of Figure 2 undergoing manufacturing processing according to the method of Figures 1 to 1B
[0010] Figure 9 is a system diagram of a system including the electronic device of Figures 1 to 1B DETAILED DESCRIPTION
[0011] In the drawings, like reference numerals refer to like elements throughout, and various features are not necessarily drawn to scale. Also, the term "couple" or "couples" includes either an indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or with a second device, that connection can be through a direct electrical connection or through an indirect electrical connection via one or more intervening devices and connections. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the stated value. Within the scope of the claims, modifications can be made to the described examples, and other embodiments are possible.
[0012] Figures 1 to 1B An electronic device 100 is shown having electrically conductive (e.g., copper) leads that are electroplated with nickel tungsten and tin after molding to improve BLR performance by minimizing defects and larger grain size, providing a diffusion barrier that prevents copper and tin from interdiffusing. Nickel tungsten alloys (e.g., any suitable stoichiometry of Ni x W y The electroplated nanostructure, for example, where x is approximately equal to y, is a prominent diffusion barrier that prevents copper (Cu) from interdiffusing with tin (Sn). Because the solubility of nickel tungsten and copper with each other is very low, the formation of intermetallic compounds (IMCs), such as Cu3Sn and Cu6Sn5, is slowed, resulting in higher BLR performance. In addition, the nickel tungsten tin intermetallics have high fracture toughness and high ductility, resulting in solder voiding at the interface and reducing the probability of cracking at the interface of the nickel tungsten copper IMC and the plated fog tin. The described examples enable electrically conductive (e.g., copper) integrated circuit leads to be tinned in order to mitigate degradation of material properties and extend shelf life prior to soldering to a printed circuit board, while improving BLR of the electronic system once the electronic device is soldered to the host printed circuit board.
[0013] Figures 1 to 1B The electronic device 100 is shown in an example position in a three-dimensional space having a first direction X, a perpendicular (orthogonal) second direction Y Figure 1A , and a third direction Z Figure 1 and 1B that is perpendicular (orthogonal) to the respective first direction X and second direction Y. Structures or features along any two of these directions are orthogonal to each other. As best shown in Figure 1 The electronic device 100 has opposing first and second sides 101 and 102 (e.g., bottom and top sides) that are spaced apart from each other along the third direction Z, respectively. The electronic device 100 has opposing first and second sides 101 and 102 that are spaced apart from each other along the first direction X and extend along the second direction Y. The electronic device 100 also includes third and fourth sides 103 and 104 that are spaced apart from each other along the second direction Y, and a bottom side 105 and a top side 106 that is spaced apart from the bottom side 105 along the third direction Z. The electronic device 100 has a molded package structure 108 that forms the device sides 101-106. In the illustrated example, the respective sides 101-106 are generally planar, and the sides 105 and 106 extend in respective X-Y planes of the first direction X and the second direction Y. In one example, the sides 101-106 have generally planar outer surfaces. In other examples (not shown), one or more of the sides 101-106 have curved, angled features, or other non-planar surface features.
[0014] The electronic device 100 includes electrically conductive leads 110 along the lateral sides 101-104 to form a quad flat no-lead (QFN) package structure. In another implementation, the device has electrically conductive leads on two opposite sides to provide a dual flat no-lead (DFN) package structure (not shown). In one example, the electrically conductive leads 110 are or include copper (Cu). As Figure 1B As best shown in FIG. 1, the individual electrically conductive leads 110 have a first (e.g., bottom) surface 131 and a second surface 132 (e.g., lateral side surface).
[0015] Figure 1B The first surface 131 of the illustrated portion in FIG. 1 has a bilayer 111, 112 exposed outside the package structure 108 along the bottom side 105 of the package structure 108. The second surface 132 is exposed outside the package structure 108 along the first side 101 of the package structure 108. The bilayer includes a first plating layer 111 and a second plating layer 112. The first plating layer 111 is on and contacts the first surface 131 of the electrically conductive lead 110. The first plating layer 111 includes nickel tungsten. In one example, the first layer 111 has a thickness of substantially 0.1 pm or more and substantially 2.0 pm or less along the third direction Z. In this or another example, the first plating layer 111 has a thickness of substantially 0.5 pm or more and substantially 2.0 pm or less along the third direction Z. In these or other examples, the first plating layer 111 has a thickness of substantially 1.0 pm along the third direction Z.
[0016] The second plating layer 112 is on and contacts the first plating layer 111, and the second plating layer 112 is exposed outside the package structure 108 along the bottom side 105 of the package structure 108. In the above or other examples, the second plating layer 112 has a thickness of substantially 3.0 pm or more and substantially 12.0 pm or less along the third direction Z. The second plating layer 112 includes tin formed, for example, by an electroless plating process as further described below in connection with FIG. 2. Figure 2 The second plating layer 112 is on and contacts the first plating layer 111, and the second plating layer 112 is exposed outside the package structure 108 along the bottom side 105 of the package structure 108. In the above or other examples, the second plating layer 112 has a thickness of substantially 3.0 pm or more and substantially 12.0 pm or less along the third direction Z. The second plating layer 112 includes tin formed, for example, by an electroless plating process as further described below in connection with FIG. 2.
[0017] Figure 1B A portion of the example electrically conductive lead 110 along the first side 101 of the electronic device 100 is shown in cross-sectional view. The electrically conductive leads on the other sides 102-104 of the electronic device 100 are similarly constructed and have second surfaces 132 extending along the respective lateral sides of the electronic device 100.
[0018] As Figure 1As shown in FIG. 1, the electronic device 100 also includes a semiconductor die 120 enclosed by the package structure 108. The semiconductor die 120 has conductive bond pads electrically connected to respective lead wires 110 by bond wires 122, and includes one or more circuit components (e.g., transistors, diodes, resistors, etc.) formed on or in a semiconductor layer of the semiconductor die 120.
[0019] The semiconductor die 120 can also include a single-level or multi-level metallization structure having conductive metal interconnects with one or more components of the semiconductor layer, where one or more additional components (e.g., inductors, transformers, resistors, capacitors, etc.) can be formed wholly or partially in the metallization structure. One or more of the conductive lead wires 110 are electrically coupled to the circuitry or components of the semiconductor die 120, e.g., by respective bond wires 122, to provide circuitry for the electronic device 100 with electrical connections to external connections of a host system (e.g., a circuit board) as described further below. Figure 9
[0020] Figure 2 A method 200 of manufacturing an electronic device is shown, and Figures 3 to 8 An electronic device 100 is shown undergoing a manufacturing process according to the method 200. The method 200 includes a die attach process at 202. Figure 3 One example of a die attach process 300 is shown in which the semiconductor die 120 is attached to the die attach pads 114 of a starting leadframe panel array or strip (e.g., copper) that also includes the intended lead wires 110. As shown in FIG. 3, the die attach pads 114 have a lower surface 302, and the lead wires 110 have a lower first surface 131. In one example, the starting leadframe has a plurality of intended device sections or cell areas of the intended electronic device 100 arranged in rows and columns (not shown) in a panel array 301. The die attach process 300 includes placing and attaching a plurality of semiconductor dies 120 to respective die attach pads 114 of the panel array 301 simultaneously or sequentially, e.g., using an epoxy or other suitable die attach adhesive (not shown), and optionally including a thermal, UV, or other suitable curing step. Figure 3
[0021] The method 200 continues to 204, where the formation of electrical connections includes electrically coupling one or more conductive terminals (e.g., bond pads) of the die 120 to respective conductive lead wires 110, as well as any die-to-die connections required for a given electronic device design (e.g., die-to-die connections for a multi-chip module or MCM device, not shown). Figure 4 One example in which the wire bonding process 400 is performed is shown, forming bond wires 122 between respective conductive bond pads of the semiconductor dies 120 and associated ones of the conductive leads 110 of the leadframe of the starting leadframe in the panel array 301.
[0022] The method 200 also includes performing a molding process at 206 that forms a molded package structure 108 that encloses the semiconductor dies 120 and the bond wires 122. Figure 5 One example in which the molding process 500 is performed is shown, forming a molded package structure 108 that encloses the semiconductor dies 120 and the bond wires 122. In the illustrated example, the molding process 500 exposes the lower surfaces 302 of the respective die attach pads 114. In other examples, the molded package structure 108 covers the lower surfaces 302 of the respective die attach pads 114, and the lower die attach pad surfaces 302 are subsequently un-plated.
[0023] The method 200 includes plating to form the dual layers 111, 112 described above in connection with Figures 1 to 1B In one embodiment, the method 200 includes an optional activation step at 207 after the molding at 106 in Figure 2 In one example, an activation process is performed on the leadframe panel array 301 with the bottom surfaces 131 of the leads 110 and the lower surfaces 302 of the respective die attach pads 114 exposed outside of the molded package structure 108. In one embodiment, the activation process for the first surfaces 131 of the conductive leads 110 and the lower surfaces 302 of the respective die attach pads 114 uses water containing approximately 10% by volume methanesulfonic acid. In other embodiments of the method 200, the activation step at 207 can be omitted.
[0024] At 208, the method 200 includes performing a first plating process to plate the first surfaces 131 of the conductive leads 110 with a first plated layer 111 including nickel tungsten. Figure 6 One example in which the first plating process 600 is performed is shown, forming the first plated layer 111 on the first surfaces 131 of the conductive leads 110 exposed along the bottom side 105 of the molded structure 108 in the panel array 301 of the intended electronic device 100. In the illustrated example, the first plating process 600 simultaneously forms the first plated layer 111 on the lower surfaces 302 of the respective die attach pads 114 exposed along the bottom side 105 of the molded structure 108 in the panel array 301.
[0025] In one example, the first plating process 600 is an electroplating process that forms a first plated layer 111 on the exposed first surface 131 of the conductive lead 110 having a thickness of substantially 0.1 μιη or more and substantially 2.0 μιη or less, where the first plated layer 111 includes nickel tungsten. In one implementation, in one example, the first plating process 600 is an electroplating process that forms the first plated layer 111 having a thickness of substantially 0.5 μιη or more and substantially 2.0 μιη or less along the third direction Z. In these or other examples, the first plating process 600 forms the first plated layer 111 having a thickness of substantially 1.0 μιη along the third direction Z.
[0026] The method 200 continues with the tin fog plating at 210. Figure 7 One example is shown in which a second plating process 700 is performed that forms a second plated layer 112 on the first plated layer 111, where the second plated layer 112 includes tin. In one example, the second plating process 700 is an electroless plating process that forms the second plated layer 112 on the first plated layer 111. The second plated layer 112 is on and contacts the first plated layer 111, and the second plated layer 112 is exposed outside of the package structure 108 along the bottom side 105 of the package structure 108. In the illustrated example, the plating at 208 and 210 forms a bilayer 111, 112 on the lower surface 302 of the respective die land 114 exposed along the bottom side 105 of the molded structure 108 in the panel array 301. In the above or other examples, the second plating process 700 forms the second plated layer 112 having a thickness of substantially 3.0 μιη or more and substantially 12.0 μιη or less along the third direction Z. The second plated layer 112 includes tin, such as matte tin, formed by the electroless plating process at 210.
[0027] The method 200 continues with the package singulation at 212. Figure 2 The method 200 continues with the package singulation at 212. Figure 8 One example is shown in which a package singulation process 800 is performed that separates the electronic device 100 from the panel array 301, such as by sawing, laser cutting, or other suitable process along the line 802. The singulation process 800 separates the individual semiconductor device 100 from the plated nickel tungsten and tin surface 131 of the conductive lead 110 exposed along the bottom side 105 of the respective package structure 108. The package singulation process 800 exposes the second surface 132 of the conductive lead 110 along the sides 101-104 of the package structure 108.
[0028] Figure 9 One example is shown in which a package singulation process 800 is performed that separates the electronic device 100 from the panel array 301, such as by sawing, laser cutting, or other suitable process along the line 802. The singulation process 800 separates the individual semiconductor device 100 from the plated nickel tungsten and tin surface 131 of the conductive lead 110 exposed along the bottom side 105 of the respective package structure 108. The package singulation process 800 exposes the second surface 132 of the conductive lead 110 along the sides 101-104 of the package structure 108. Figures 1 to 1Bof the electronic device 100, where one or more of the double layer plated conductive leads 110 are electrically coupled to circuitry of the semiconductor die 110 and conductive features 142 of the circuit board 140. In the illustrated example, the conductive leads 110 are individually soldered to corresponding pads or other conductive features 142 on a top side of the circuit board 140 using solder (not shown), in another implementation, the electronic device is mounted in a socket (not shown) of the circuit board 140. The molding post-plating of the exposed first surfaces 131 of the conductive leads 110 with the underlayer 111 including nickel tungsten at 208 Figure 2 ) improves board level reliability (BLR) performance of the device 100 mounted on the circuit board 140 of the system 900 by reducing defects and including a larger grain size that provides a diffusion barrier that prevents interdiffusion of copper and tin in the subsequent tin plating at 210.
[0029] The presence of nickel tungsten in the first plated layer 111 slows the formation of intermetallic compounds (IMCs) (e.g., Cu3Sn and Cu6Sn5) in the double layer that are susceptible to cracking when soldered to the circuit board 140, resulting in higher BLR performance because nickel tungsten and copper have very low solubility in each other. In addition, the nickel tungsten tin intermetallics have high fracture toughness and high ductility, resulting in solder voiding at the interface and reducing the probability of cracking of the nickel tungsten copper IMCs at the plated fog tin interface. The described examples enable copper integrated circuit leads to be tinned in order to mitigate degradation of material properties and extend shelf life prior to soldering to a printed circuit board, while improving BLR of the electronic system once the electronic device is soldered to the host printed circuit board. The described examples provide improved reliability over direct plating of fog tin on bare copper post-molding and provide a solution with low manufacturing cost without using expensive plating alternatives such as electroless plated nickel phosphorous and gold (e.g., NiP and Au).
[0030] The foregoing examples merely illustrate several possible implementations of various aspects of the present disclosure, wherein equivalents of the forms and details of the foregoing examples will suggest themselves to persons of ordinary skill and creativity in the art, and are considered within the scope of the present disclosure.
Claims
1. An electronic device comprising: a semiconductor die; a package structure enclosing the semiconductor die; and a conductive lead having a first surface and a second surface, the first surface having a bilayer exposed outside the package structure along one side of the package structure, and the second surface exposed outside the package structure along another side of the package structure, the bilayer including a first plating layer and a second plating layer, the first plating layer being on and contacting the first surface of the conductive lead, the second plating layer being on and contacting the first plating layer and exposed outside the package structure along the side of the package structure, the first plating layer including nickel tungsten, and the second plating layer including tin.
2. The electronic device of claim 1, wherein the first plating layer has a thickness of substantially 0.1 μm or more and substantially 2.0 μm or less.
3. The electronic device of claim 2, wherein the second plating layer has a thickness of substantially 3.0 μm or more and substantially 12.0 μm or less.
4. The electronic device of claim 3, wherein the first plating layer has a thickness of substantially 0.5 μm or more and substantially 2.0 μm or less.
5. The electronic device of claim 3, wherein the first plating layer has a thickness of substantially 1.0 μm.
6. The electronic device of claim 1, wherein the first plating layer has a thickness of substantially 0.5 μm or more and substantially 2.0 μm or less.
7. The electronic device of claim 1, wherein the first plating layer has a thickness of substantially 1.0 μm.
8. The electronic device of claim 1, wherein the second plating layer has a thickness of substantially 3.0 μm or more and substantially 12.0 μm or less.
9. A system comprising: a circuit board; and an electronic device comprising: a semiconductor die; a package structure enclosing the semiconductor die; and a conductive lead electrically coupled to a circuit of the semiconductor die and a conductive feature of the circuit board, the conductive lead having a first surface and a second surface, the first surface having a bilayer exposed outside the package structure along one side of the package structure, and the second surface exposed outside the package structure along another side of the package structure, the bilayer including a first plating layer and a second plating layer, the first plating layer being on and contacting the first surface of the conductive lead, the second plating layer being on and contacting the first plating layer and exposed outside the package structure along the side of the package structure, the first plating layer including nickel tungsten, and the second plating layer including tin.
10. The system of claim 9, wherein the first plating layer has a thickness of substantially 0.1 μm or more and substantially 2.0 μm or less.
11. The system of claim 9, wherein the second plating layer has a thickness of substantially 3.0 μm or more and substantially 12.0 μm or less. 12. The system of claim 9, wherein the first plating layer has a thickness of substantially 0.5 pm or greater and substantially 2.0 pm or less.
13. The system of claim 9, wherein the first plating layer has a thickness of substantially 1.0 pm.
14. A method of manufacturing electronic devices, the method comprising: performing a first plating process that forms a first plating layer on a first surface of a conductive lead exposed along a side of a molded structure in an array of panels of an intended electronic device, the first plating layer including nickel tungsten; performing a second plating process that forms a second plating layer on the first plating layer, the second plating layer including tin; and performing a package singulation process that separates an electronic device from the array of panels with the conductive lead exposed along a side of a respective package structure, the package singulation process exposing a second surface of the conductive lead along a first side of the package structure.
15. The method of claim 14, further comprising: prior to performing the first plating process, performing an activation process on the first surface of the conductive lead using water including substantially 10 volume percent methanesulfonic acid.
16. The method of claim 15, wherein the first plating process is an electroplating process that forms the first plating layer on the first surface of the conductive lead having a thickness of substantially 0.1 pm or greater and substantially 2.0 pm or less.
17. The method of claim 14, wherein the second plating process is an electroless plating process that forms the second plating layer on the first plating layer having a thickness of substantially 3.0 pm or greater and substantially 12.0 pm or less.
18. The method of claim 14, wherein the first plating process is an electroplating process that forms the first plating layer on the first surface of the conductive lead having a thickness of substantially 0.1 pm or greater and substantially 2.0 pm or less.
19. The method of claim 14, wherein the first plating process is an electroplating process that forms the first plating layer on the first surface of the conductive lead having a thickness of substantially 0.5 pm or greater and substantially 2.0 pm or less.
20. The method of claim 14, wherein the first plating process is an electroplating process that forms the first plating layer on the first surface of the conductive lead having a thickness of substantially 1.0 pm.