Memory device and method of manufacturing the same

Abstract

A memory device and a method of manufacturing the same are disclosed. The disclosed manufacturing method of the memory device may include the steps of: forming a structure, the structure includes an epitaxial material plug extending in a vertical direction on a substrate, an epitaxial channel material layer extending in a horizontal direction from a side surface of the epitaxial material plug, and a gate insulating material layer formed at least on a surface portion of the epitaxial channel material layer. The manufacturing method of the memory device can also comprise the following step of forming a filling insulating layer for filling the peripheral space of the epitaxial material plug and the epitaxial channel material layer on the gate insulating material layer. The manufacturing method of the memory device can also comprise the following steps of: forming a transistor comprising the epitaxial channel material layer; and forming a capacitor electrically connected to the transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor / electronic device and a manufacturing method thereof, and more particularly, to a memory device and a manufacturing method thereof. BACKGROUND

[0002] Currently, there is an increasing demand for improving the performance of semiconductor devices and the integration of semiconductor devices. The integration of semiconductor devices has reached a limit in terms of improving the integration by two-dimensionally, i.e., planarly, arranging unit cells of semiconductor devices. Therefore, a technology of greatly improving the integration of semiconductor devices by three-dimensionally integrating a plurality of unit cells of semiconductor devices is being attempted. As a result, the integration of memory devices such as a flash (NAND) device or a dynamic random access memory (DRAM) device is being attempted in various ways. Meanwhile, research and development for improving the performance and operating characteristics of memory devices are continuously being conducted.

[0003] In the process of manufacturing a three-dimensional memory, for example, a stacked structure in which a silicon (Si) / silicon germanium (SiGe) structure is repeatedly stacked several hundreds of times has been used in the past, and such a method has problems of extremely low productivity, high production cost, and great difficulty in process. In particular, there is a disadvantage that an epitaxial process takes a long time and is difficult in the process of forming the stacked structure. Also, the existing method can have difficulty in securing uniformity of a channel thickness, and depending on the case, when a silicon germanium (SiGe) layer is removed, there can be a problem that a silicon (Si) layer is structurally difficult to withstand. SUMMARY

[0004] TECHNICAL PROBLEM

[0005] The technical problem to be solved by the present application is to provide a memory device and a manufacturing method thereof, which can improve the integration, secure excellent performance, and at the same time, can simplify the process and reduce the manufacturing cost.

[0006] Also, the technical problem to be solved by the present application is to provide a memory device and a manufacturing method thereof, which can improve the performance such as mobility, improve the uniformity of a channel thickness, and improve the on-current characteristics by using a single-crystal channel material.

[0007] The technical problem to be solved by the present application is not limited to the above-mentioned problems, and other problems not mentioned can be clearly understood by those skilled in the art to which the present application pertains from the following description.

[0008] TECHNICAL SOLUTION

[0009] According to an embodiment of the present application, there is provided a method of manufacturing a memory device, including the steps of: forming a stack including a first insulating layer, a first sacrificial layer, and a second insulating layer, which are sequentially stacked on a substrate; forming a patterned stack having at least one pattern portion having a first sacrificial layer pattern obtained from the first sacrificial layer by patterning the stack, the pattern portion having a form extending in a first direction, and having blank spaces provided on both sides of the pattern portion in a second direction perpendicular to the first direction; forming a structure including the patterned stack and an insulating material by filling the insulating material in the blank spaces on both sides of the at least one pattern portion; forming a first vertical hole penetrating the first sacrificial layer pattern of the pattern portion in the structure; forming an epitaxial material plug filling the first vertical hole from the substrate by an epitaxial growth method; forming a first etching portion separated from the epitaxial material plug in the structure; forming a horizontal hole extending in the first direction by removing the first sacrificial layer pattern exposed through the first etching portion; forming an epitaxial channel material layer filling the horizontal hole from a side surface of the epitaxial material plug by an epitaxial growth method; forming a blank region around the epitaxial material plug and the epitaxial channel material layer by removing the first insulating layer, the second insulating layer, and the insulating material from the structure; forming a gate insulating material layer on a surface portion of the epitaxial material plug and the epitaxial channel material layer; forming a filling insulating layer filling the blank region on the gate insulating material layer; forming a second vertical hole in a region corresponding to the first vertical hole in the structure in which the gate insulating material layer and the filling insulating layer are formed; exposing the gate insulating material layer by removing the filling insulating layer from a transistor formation region around the second vertical hole of the structure; defining a transistor including a word line by forming the word line around a portion of the exposed gate insulating material layer in the transistor formation region; forming a bit line connected to one end of the epitaxial channel material layer in the transistor formation region in a region corresponding to the second vertical hole; and forming a capacitor connected to the other end of the epitaxial channel material layer of the transistor by removing the epitaxial channel material layer and the gate insulating material layer from a capacitor formation region adjacent to the transistor formation region of the structure.

[0010] The first insulating layer, the second insulating layer, and the insulating material can include silicon nitride, and the first sacrificial layer can include silicon oxide.

[0011] The epitaxial material plug and the epitaxial channel material layer can include a single-crystal semiconductor.

[0012] The epitaxial material plug and the epitaxial channel material layer can include one of single-crystal silicon (Si), single-crystal germanium (Ge), and single-crystal silicon germanium (SiGe).

[0013] The step of defining the transistor by forming the word line can include a step of forming a word line material layer surrounding the exposed gate insulating material layer portion in the transistor formation region; forming a through-hole by etching a region of the word line material layer corresponding to the second vertical hole; recessing a portion of the word line material layer exposed through the through-hole so that the one end of the epitaxial channel material layer protrudes more to the through-hole side than the word line material layer; and forming a bulk insulating layer filling the through-hole.

[0014] The step of defining the transistor by forming the word line can include a step of forming a word line material layer surrounding the exposed gate insulating material layer portion in the transistor formation region; forming a through-hole by etching a region of the word line material layer corresponding to the second vertical hole; recessing a portion of the word line material layer exposed through the through-hole so that the one end of the epitaxial channel material layer protrudes more to the through-hole side than the word line material layer; and forming a bulk insulating layer filling the through-hole.

[0015] The step of forming the bit line can include a step of forming a third vertical hole in a region corresponding to the second vertical hole of the bulk insulating layer; and forming the bit line in the third vertical hole.

[0016] The step of forming the bit line can include a step of forming a third vertical hole in a region corresponding to the second vertical hole of the bulk insulating layer; and forming the bit line in the third vertical hole.

[0017] The step of forming the bit line can include a step of forming a third vertical hole in a region corresponding to the second vertical hole of the bulk insulating layer; and forming the bit line in the third vertical hole.

[0018] The step of forming the capacitor can include a step of forming an electrode member connected to the other end of the epitaxial channel material layer on an inner side surface of the second recessed portion; forming a dielectric layer on the electrode member; and forming a plate electrode on the dielectric layer.

[0019] It can further include the steps of, after forming the electrode member, exposing an outer side surface of the electrode member by etching the mold insulating layer, and sequentially forming the dielectric layer and the plate electrode after etching the mold insulating layer.

[0020] The laminate can further include a second sacrificial layer and a third insulating layer sequentially stacked on the second insulating layer, and can have a structure symmetric with respect to the second insulating layer.

[0021] The second insulating layer can have a thickness greater than each of the first insulating layer, the third insulating layer, the first sacrificial layer, and the second sacrificial layer.

[0022] The transistor can be a first transistor, the capacitor can be a first capacitor, and the memory device can be formed to further include a second transistor disposed on the first transistor and a second capacitor disposed on the first capacitor.

[0023] According to another embodiment of the present application, there is provided a method of manufacturing a memory device, including the steps of forming a structure including an epitaxial material plug extending in a vertical direction on a substrate, an epitaxial channel material layer extending in a horizontal direction from a side surface of the epitaxial material plug, a gate insulating material layer formed at least at a surface portion of the epitaxial channel material layer, and a filling insulating layer formed on the gate insulating material layer and filling a surrounding space of the epitaxial material plug and the epitaxial channel material layer; forming a vertical hole (hereinafter, referred to as a second vertical hole) by removing the epitaxial material plug from the structure; exposing the gate insulating material layer by removing the filling insulating layer from a transistor formation region around the second vertical hole of the structure; defining a transistor including a word line by forming the word line around a portion of the exposed gate insulating material layer in the transistor formation region; forming a bit line connected to one end of the epitaxial channel material layer in a region corresponding to the second vertical hole in the transistor formation region; and removing the epitaxial channel material layer and the gate insulating material layer from a capacitor formation region adjacent to the transistor formation region of the structure, forming a capacitor connected to the other end of the epitaxial channel material layer of the transistor.

[0024] According to another embodiment of the present application, a memory device is provided, including a plurality of memory cells stacked in a vertical direction, each of the plurality of memory cells including a transistor and a capacitor electrically connected to the transistor in a lateral direction of the transistor, the transistor including an epitaxial channel material layer, a word line surrounding the epitaxial channel material layer, and a gate insulating layer disposed between the epitaxial channel material layer and the word line, the capacitor including an electrode part electrically connected to the transistor, a dielectric layer disposed on a surface of the electrode part, and a plate electrode disposed on a surface of the dielectric layer, a bit line electrically connected to a plurality of transistors of the plurality of memory cells and extending in the vertical direction, the transistor having a gate-all-around (GAA) structure.

[0025] The epitaxial channel material layer may, for example, include one of single-crystal silicon (Si), single-crystal germanium (Ge), and single-crystal silicon germanium (SiGe).

[0026] A body insulating layer surrounding at least a portion of an outer surface of the bit line between the bit line and the word line can be further provided, and a gap filling insulating layer, which is a material layer separate from the body insulating layer, can be provided between two adjacent word lines of the plurality of transistors.

[0027] The body insulating layer can have a structure in which a plurality of annular-shaped unit bodies are connected in a row when viewed from above, and the bit line can be disposed in an inner portion of each of the plurality of annular-shaped unit bodies.

[0028] An insertion insulating layer can be further provided, the insertion insulating layer extending in a manner of surrounding a portion of the gate insulating layer adjacent to the electrode part and covering a lateral surface of the word line, and the insertion insulating layer can be a material layer separate from the body insulating layer and the gap filling insulating layer.

[0029] The body insulating layer can be in contact with a first lateral surface of the gap filling insulating layer, and the insertion insulating layer can be in contact with a second lateral surface of the gap filling insulating layer.

[0030] According to another embodiment of the present application, there is provided a method of manufacturing a memory device, comprising the steps of: forming a stack including a first insulating layer, a first sacrificial layer, and a second insulating layer sequentially stacked on a substrate; forming a first etched portion penetrating a region including at least one bit line preformation region in the stack; forming an epitaxial material plug filling the first etched portion from the substrate using an epitaxial growth method; forming a second etched portion spaced apart from the epitaxial material plug in the stack; removing the first sacrificial layer exposed by the second etched portion to form a horizontal space portion; forming an epitaxial channel material layer filling the horizontal space portion from a side surface of the epitaxial material plug using an epitaxial growth method; forming a patterned stack having at least one pattern portion having an epitaxial channel pattern obtained from the epitaxial channel material layer by patterning the stack formed with the epitaxial channel material layer and an epitaxial plug pattern obtained from the epitaxial material plug; removing the first and second insulating layers from the patterned stack; forming a gate insulating material layer on a surface portion of the epitaxial plug pattern and the epitaxial channel pattern; forming a structure including the epitaxial plug pattern, the epitaxial channel pattern, the gate insulating material layer, and a filling insulating layer by filling a surrounding space of the epitaxial plug pattern and the epitaxial channel pattern on the gate insulating material layer; forming a first vertical hole exposing the epitaxial channel pattern in a region corresponding to the bit line preformation region of the structure; exposing the gate insulating material layer by removing the filling insulating layer from a transistor formation region around the first vertical hole of the structure; defining a transistor including a word line by forming the word line around a portion of the exposed gate insulating material layer in the transistor formation region; forming a bit line connected to one end of the epitaxial channel pattern in a region corresponding to the first vertical hole in the transistor formation region; and forming a capacitor connected to the other end of the epitaxial channel pattern of the transistor by removing the epitaxial channel pattern and the gate insulating material layer from a capacitor formation region adjacent to the transistor formation region of the structure.

[0031] The first and second insulating layers can include silicon nitride, and the first sacrificial layer can include silicon oxide.

[0032] The first etched portion can have a trench shape penetrating a plurality of the bit line preformation regions in common.

[0033] The epitaxial material plug and the epitaxial channel material layer can include a single-crystal semiconductor.

[0034] The epitaxial material plug and the epitaxial channel material layer can include one of single-crystal silicon (Si), single-crystal germanium (Ge), and single-crystal silicon germanium (SiGe).

[0035] The step of defining the transistor by forming the word line can include a step of forming a word line material layer surrounding the exposed gate insulating material layer portion in the transistor formation region; forming a through hole by etching a region of the word line material layer corresponding to the first vertical hole; recessing a portion of the word line material layer exposed through the through hole so that the one end of the epitaxial channel pattern protrudes more to the through hole side than the word line material layer; and forming a bulk insulating layer filling the through hole.

[0036] The step of defining the transistor by forming the word line can include a step of forming a word line material layer surrounding the exposed gate insulating material layer portion in the transistor formation region; forming a through hole by etching a region of the word line material layer corresponding to the first vertical hole; recessing a portion of the word line material layer exposed through the through hole so that the one end of the epitaxial channel pattern protrudes more to the through hole side than the word line material layer; and forming a bulk insulating layer filling the through hole.

[0037] The step of forming the bit line can include a step of forming a second vertical hole in a region corresponding to the first vertical hole of the bulk insulating layer; and forming the bit line in the second vertical hole.

[0038] The step of forming the bit line can include a step of forming a second vertical hole in a region corresponding to the first vertical hole of the bulk insulating layer; and forming the bit line in the second vertical hole.

[0039] The step of forming the bit line can include a step of forming a second vertical hole in a region corresponding to the first vertical hole of the bulk insulating layer; and forming the bit line in the second vertical hole.

[0040] The step of forming the capacitor can include a step of forming an electrode member connected to the other end of the epitaxial channel pattern on an inner side of the second recessed portion; forming a dielectric layer on the electrode member; and forming a plate electrode on the dielectric layer.

[0041] The manufacturing method can further include, after forming the electrode member, exposing an outer side surface of the electrode member by etching the mold insulating layer, and the dielectric layer and the plate electrode can be formed in this order after etching the mold insulating layer.

[0042] The laminate can further include a second sacrificial layer and a third insulating layer which are laminated in this order on the second insulating layer, and the laminate can have a structure which is symmetrical with respect to the second insulating layer.

[0043] The second insulating layer can have a thickness which is greater than each of the first insulating layer, the third insulating layer, the first sacrificial layer, and the second sacrificial layer.

[0044] The transistor can be a first transistor, the capacitor can be a first capacitor, and the memory device can be formed to further include a second transistor disposed on the first transistor and a second capacitor disposed on the first capacitor.

[0045] According to another embodiment of the present application, there is provided a manufacturing method of a memory device, including the steps of forming a structure including an epitaxial plug pattern extending in a vertical direction on a substrate, an epitaxial trench pattern extending in a horizontal direction from a side surface of the epitaxial plug pattern, a gate insulating material layer formed at least at a surface portion of the epitaxial trench pattern, and a filling insulating layer formed on the gate insulating material layer and filling a surrounding space of the epitaxial plug pattern and the epitaxial trench pattern; removing the epitaxial plug pattern by etching a bit line preformation region in the structure, forming a first vertical hole exposing the epitaxial trench pattern; exposing the gate insulating material layer by removing the filling insulating layer from a transistor formation region around the first vertical hole of the structure; defining a transistor including a word line by forming the word line around a portion of the exposed gate insulating material layer in the transistor formation region; forming a bit line connected to one end of the epitaxial trench pattern in the transistor formation region in a region corresponding to the first vertical hole; and removing the epitaxial trench pattern and the gate insulating material layer from a capacitor formation region adjacent to the transistor formation region of the structure, forming a capacitor connected to the other end of the epitaxial trench pattern of the transistor.

[0046] In the structure, the epitaxial plug pattern and the epitaxial trench pattern can have the same width.

[0047] According to another embodiment of the present application, there is provided a memory device including a plurality of memory cells stacked in a vertical direction, each of the plurality of memory cells including a transistor and a capacitor electrically connected to the transistor in a lateral direction of the transistor, the transistor including an epitaxial channel material layer, a word line surrounding the epitaxial channel material layer, and a gate insulating layer disposed between the epitaxial channel material layer and the word line, the capacitor including an electrode part electrically connected to the transistor, a dielectric layer disposed on a surface of the electrode part, and a plate electrode disposed on a surface of the dielectric layer, a bit line electrically connected to a plurality of transistors of the plurality of memory cells and extending in the vertical direction, the transistor having a gate-all-around (GAA) structure.

[0048] The epitaxial channel material layer may, for example, include one of single-crystal silicon (Si), single-crystal germanium (Ge), and single-crystal silicon germanium (SiGe).

[0049] A body insulating layer surrounding at least a portion of an outer surface of the bit line between the bit line and the word line can be provided, and a gap filling insulating layer, which is a material layer separate from the body insulating layer, can be provided between two adjacent word lines of the plurality of transistors.

[0050] The body insulating layer can have a structure in which a plurality of annular-shaped unit bodies are connected in a row when viewed from above, and the bit line can be disposed in an inner portion of each of the plurality of annular-shaped unit bodies.

[0051] An interposed insulating layer can also be provided, which extends in a manner surrounding a portion of the gate insulating layer adjacent to the electrode part and covering a lateral surface of the word line, and the interposed insulating layer can be a material layer separate from the body insulating layer and the gap filling insulating layer.

[0052] The body insulating layer can be in contact with a first lateral surface of the gap filling insulating layer, and the interposed insulating layer can be in contact with a second lateral surface of the gap filling insulating layer.

[0053] Effects of the Invention

[0054] According to embodiments of the present application, a memory device (stacked memory device) and a manufacturing method thereof can be implemented in which integration can be improved, excellent performance can be ensured, a process can be simple, and manufacturing costs can be reduced. Also, according to embodiments of the present application, a memory device (stacked memory device) and a manufacturing method thereof can be implemented in which, by using a single-crystal channel material, performance such as mobility can be improved, uniformity of a channel thickness can be improved, and on-current characteristics can be improved.

[0055] According to an embodiment of the present application, an epitaxial channel layer is formed by a selective epitaxial growth (SEG) method using a stack of an insulating layer and a sacrificial layer, so that compared with a conventional method using a silicon (Si) / silicon germanium (SiGe) stack structure, process difficulty can be reduced, manufacturing cost can be reduced, and a memory device with improved performance can be manufactured.

[0056] According to an embodiment of the present application, an epitaxial channel layer is formed by a selective epitaxial growth (SEG) method using a stack of an insulating layer and a sacrificial layer, so that compared with a conventional method using a silicon (Si) / silicon germanium (SiGe) stack structure, process difficulty can be reduced, manufacturing cost can be reduced, and a memory device with improved performance can be manufactured. According to an embodiment, when a memory device is manufactured, after a stack of an insulating layer and a sacrificial layer is formed, an epitaxial material plug is formed by a selective epitaxial growth (SEG) method through a trench-shaped etching part, an epitaxial channel material layer is formed from the epitaxial material plug by a selective epitaxial growth method in a space where the sacrificial layer has been removed, cell patterning is performed, and a process of forming a word line and a capacitor can be performed. In this case, process difficulty can be reduced, and a stack-type memory device with excellent performance can be manufactured. In particular, when an epitaxial material plug is formed by a selective epitaxial growth method through a trench-shaped etching part, process difficulty of epitaxial growth can be reduced compared with a case where epitaxial growth is performed through a narrow hole.

[0057] According to an example, the memory device can be configured to include a horizontal stack-type dynamic random access memory (DRAM) device.

[0058] However, the effects of the present application are not limited to the effects described above, and can be expanded in various ways without departing from the technical idea and scope of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0059] Figure 1a 、 Figure 2a 、 Figure 3a 、 Figure 4a 、 Figure 5a 、 Figure 6a 、 Figure 7a 、 Figure 8a 、 Figure 9a 、 Figure 10a 、 Figure 11a 、 Figure 12a 、 Figure 13a、 Figure 14a 、 Figure 15a 、 Figure 16a 、 Figure 17a 、 Figure 18a 、 Figure 19a 、 Figure 20a 、 Figure 21a 、 Figure 22a 、 Figure 23a 、 Figure 24a 、 Figure 25a 、 Figure 26a 、 Figure 27a 、 Figure 28a 、 Figure 29a 、 Figure 30a 、 Figure 31a and Figure 32a are cross-sectional views of a manufacturing method of a memory device for illustrating an embodiment of the present application.

[0060] Figure 1b 、 Figure 2b 、 Figure 3b 、 Figure 4b 、 Figure 5b 、 Figure 6b 、 Figure 7b 、 Figure 8b 、 Figure 9b 、 Figure 10b 、 Figure 11b 、 Figure 12b 、 Figure 13b 、 Figure 14b 、 Figure 15b 、 Figure 16b 、 Figure 17b 、 Figure 18b 、 Figure 19b 、 Figure 20b 、 Figure 21b 、 Figure 22b 、 Figure 23b 、 Figure 24b 、 Figure 25b 、 Figure 26b 、 Figure 27b 、 Figure 28b 、 Figure 29b 、 Figure 30b 、 Figure 31b and Figure 32b are diagrams of a manufacturing method of a memory device for illustrating an embodiment of the present application.

[0061] Figure 1c 、 Figure 2c 、 Figure 3c 、 Figure 4c and Figure 5c are cross-sectional views of a manufacturing method of a memory device for illustrating an embodiment of the present application.

[0062] Figure 32a and Figure 32b are diagrams of a memory device for illustrating an embodiment of the present application.

[0063] Figure 33a 、 Figure 34a 、 Figure 35a 、 Figure 36a 、 Figure 37a 、 Figure 38a 、 Figure 39a 、 Figure 40a 、 Figure 41a 、 Figure 42a 、 Figure 43a 、 Figure 44a 、 Figure 45a 、 Figure 46a 、 Figure 47a 、 Figure 48a 、 Figure 49a 、 Figure 50a 、 Figure 51a 、 Figure 52a 、 Figure 53a 、 Figure 54a 、 Figure 55a 、 Figure 56a 、 Figure 57a 、 Figure 58a 、 Figure 59a 、 Figure 60a 、 Figure 61a 、 Figure 62a and Figure 63a are cross-sectional views for illustrating a manufacturing method of a memory device according to an embodiment of the present application.

[0064] Figure 33b 、 Figure 34b 、 Figure 35b 、 Figure 36b 、 Figure 37b 、 Figure 38b 、 Figure 39b 、 Figure 40b 、 Figure 41b 、 Figure 42b 、 Figure 43b 、 Figure 44b 、 Figure 45b 、 Figure 46b 、 Figure 47b 、 Figure 48b 、 Figure 49b 、 Figure 50b 、 Figure 51b 、 Figure 52b 、 Figure 53b 、 Figure 54b 、 Figure 55b 、 Figure 56b 、 Figure 57b 、 Figure 58b 、 Figure 59b 、 Figure 60b 、 Figure 61b 、 Figure 62b and Figure 63b are diagrams for illustrating a manufacturing method of a memory device according to an embodiment of the present application.

[0065] Figure 33c , Figure 34c , Figure 35c , Figure 36c , Figure 37c , Figure 38c , Figure 39c , Figure 40c , Figure 41c , Figure 42c , Figure 43c and Figure 44c This is a cross-sectional view illustrating a method for manufacturing a memory device according to an embodiment of the present invention.

[0066] Figure 63a and Figure 63b This is a diagram illustrating a memory device according to an embodiment of the present invention. Detailed Implementation

[0067] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0068] The embodiments of the present invention described below are provided to more clearly illustrate the present invention to those skilled in the art. The scope of the present invention is not limited to the following embodiments, and the following embodiments can be modified into many other forms.

[0069] The terminology used in this specification is for describing specific embodiments and is not intended to limit the invention. Unless otherwise expressly indicated in the context, the singular form of the term used in this specification may also include the plural form. Furthermore, the terms "comprise" and / or "comprising" as used in this specification specifically refer to the presence of shapes, steps, numbers, actions, components, elements, and / or combinations thereof, and do not exclude the presence or additional possibilities of more than one other shape, step, number, action, component, element, and / or combination thereof. Moreover, the concept of terms such as "connected" as used in this specification not only refers to the situation where some components are directly connected, but also includes the situation where other components are indirectly connected between multiple components.

[0070] Furthermore, in the specification, terms such as "first" and "second," "upper" and "lower" are used to distinguish components, not to limit the components themselves or indicate a specific order. They indicate relative positional relationships, not specific cases where the component is in direct contact with another component or where other components are introduced at the interface between them. The same interpretation can be applied to other descriptions of the relationships between structural elements.

[0071] Also, in the present specification, when a component is referred to as being "on" another component, it can be directly on the other component or an intervening component can also be present. The term "and / or" used in the present specification encompasses all combinations of one and more of the corresponding listed items. Also, the term "about", "substantially" and the like in the present specification are used as terms of approximation and do not exclude the existence of slight errors or variations that occur in the process of manufacturing and materials, and are used in the meaning of the value or range of the value or close thereto, and are used to provide accurate or absolute values in order to prevent an infringer from unfairly using the disclosed content.

[0072] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings. The size or thickness of regions or portions shown in the drawings can be exaggerated for clarity and convenience of explanation. Throughout the detailed description, like reference numerals refer to like structures.

[0073] Figures 1a to 32b A diagram for illustrating a manufacturing method of a memory device (stacked memory device) of an embodiment of the present application.

[0074] In Figures 1a to 32b the same reference numerals (e.g., 101 in FIG. 1) represent the same steps. Figure 1a , Figure 1b , Figure 1c Figure 1a , Figure 2a , Figure 3a , Figure 4a , Figure 5a , Figure 6a , Figure 7a , Figure 8a , Figure 9a , Figure 10a , Figure 11a , Figure 12a , Figure 13a , Figure 14a , Figure 15a , Figure 16a , Figure 17a , Figure 18a , Figure 19a , Figure 20a , Figure 21a , Figure 22a , Figure 23a , Figure 24a , Figure 25a , Figure 26a , Figure 27a , Figure 28a , Figure 29a , Figure 30a , Figure 31a , Figure 32a is a cross-sectional view taken along the XZ plane. Figure 1b ,​Figure 2b 、 Figure 3b 、 Figure 4b 、 Figure 5b 、 Figure 6b 、 Figure 7b 、 Figure 8b 、 Figure 9b 、 Figure 10b 、 Figure 11b 、 Figure 12b 、 Figure 13b 、 Figure 14b 、 Figure 15b 、 Figure 16b 、 Figure 17b 、 Figure 18b 、 Figure 19b 、 Figure 20b 、 Figure 21b 、 Figure 22b 、 Figure 23b 、 Figure 24b 、 Figure 25b 、 Figure 26b 、 Figure 27b 、 Figure 28b 、 Figure 29b 、 Figure 30b 、 Figure 31b 、 Figure 32b is a top-view or a Z-cut view. Figure 1c 、 Figure 2c 、 Figure 3c 、 Figure 4c 、 Figure 5c is a ZY-cut view.

[0075] Referring to Figures 1a to 1c The stack S10 can be formed on a prescribed substrate (not shown). The substrate can be made of a variety of materials. The substrate can include a semiconductor material. The substrate can include a semiconductor wafer. The substrate can include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate formed by an epitaxial growth process. The substrate can include a single-crystal semiconductor material. For example, the substrate can include one of a single-crystal silicon (Si), a single-crystal germanium (Ge), and a single-crystal silicon-germanium (SiGe).

[0076] A laminate S10 can be formed on the substrate. The laminate S10 may include a first insulating layer NL10 and a first sacrificial layer SL10 and a second insulating layer NL20 sequentially formed on the first insulating layer NL10. As a non-limiting example, the first insulating layer NL10 and the second insulating layer NL20 may contain silicon nitride (e.g., SiN). x ) or made of silicon nitride (ex, SiN) x The first insulating layer NL10 and the first sacrificial layer SL10 may be formed by comprising or being formed of silicon oxide (ex, SiO2). The first insulating layer NL10 and the first sacrificial layer SL10 may have an etch selectivity ratio, and similarly, the second insulating layer NL20 and the first sacrificial layer SL10 may have an etch selectivity ratio. The first insulating layer NL10, the first sacrificial layer SL10, and the second insulating layer NL20 may be formed by a deposition process.

[0077] Furthermore, according to one embodiment, the laminate S10 may further include a second sacrificial layer SL20 and a third insulating layer NL30 sequentially laminated on the second insulating layer NL20. In this case, the laminate S10 may have a structure that is vertically symmetrical with respect to the second insulating layer NL20. The second sacrificial layer SL20 may be formed of the same material as the first sacrificial layer SL10, and the third insulating layer NL30 may be formed of the same material as the first insulating layer NL10 and / or the second insulating layer NL20. The second sacrificial layer SL20 and the third insulating layer NL30 may be formed by a deposition process.

[0078] The thickness of the second insulating layer NL20 can be greater than the thicknesses of the first insulating layer NL10, the third insulating layer NL30, the first sacrificial layer SL10, and the second sacrificial layer SL20. For example, the thickness of the second insulating layer NL20 can be approximately 1.5 to 2.5 times the thickness of each of the first insulating layer NL10, the third insulating layer NL30, the first sacrificial layer SL10, and the second sacrificial layer SL20. By forming a relatively thick second insulating layer NL20, the gap between the subsequently formed upper and lower cells can be ensured. The first insulating layer NL10 and the third insulating layer NL30 can have the same thickness or be practically the same thickness. The first sacrificial layer SL10 and the second sacrificial layer SL20 can have the same thickness or be practically the same thickness.

[0079] Reference Figures 2a to 2c This can be achieved by modifying the laminate ( Figure 1aIn step S10), patterning is performed to form a patterned laminate S11 having at least one patterned portion SP1. The patterned portion SP1 may have a shape extending along a first direction, such as the X-axis direction, and blank spaces may be present on both sides of the patterned portion SP1 along a second direction perpendicular to the first direction, such as the Y-axis direction. Multiple patterned portions SP1 may be spaced apart along the Y-axis direction and arranged side by side with each other along the X-axis direction. In this step, the remaining area, except for the area extending from the subsequently formed channel area, can be removed by patterning.

[0080] The patterned section SP1 may include a patterned first insulating layer NL11, a patterned first sacrificial layer SL11, a patterned second insulating layer NL21, a patterned second sacrificial layer SL21, and a patterned third insulating layer NL31. The patterned first sacrificial layer SL11 may be referred to as the first sacrificial layer (…). Figure 1a The first sacrificial layer pattern SL11 is obtained from the second sacrificial layer (SL10). Furthermore, the patterned second sacrificial layer SL21 can be referred to as the pattern obtained from the second sacrificial layer (SL10). Figure 1a The second sacrificial layer pattern SL21 is obtained by SL20. Multiple first sacrificial layer patterns SL11 can be spaced apart along the Y-axis and extend side-by-side along the X-axis; similarly, multiple second sacrificial layer patterns SL21 can be spaced apart along the Y-axis and extend side-by-side along the X-axis. Both the multiple first sacrificial layer patterns SL11 and the multiple second sacrificial layer patterns SL21 can be line-shaped.

[0081] In order to conduct Figures 2a to 2c Patterning techniques can be used to set patterns on the stacked body ( Figure 1a The first mask pattern M10 is applied to the S10. The first mask pattern M10 may have a defined pattern structure. The first mask pattern M10 may be, for example, a photoresist pattern. After the patterning process, the first mask pattern M10 may be removed.

[0082] Reference Figures 3a to 3c The patterned laminate can be formed by filling the blank spaces on both sides of at least one patterned portion SP1 with insulating material NM1. Figure 2a The structure S20 consists of S11 and the insulating material NM1. Figure 3b It can be along Figure 3a (A) sectional view of wire cutting.

[0083] The insulating material NM1, which may be referred to as an "insulating material layer" or "insulating material layer pattern," may have the same (or practically the same) height as the patterned portion SP1. The insulating material NM1 may be formed from the same material as the first insulating layer NL11, the second insulating layer NL21, and the third insulating layer NL31. For example, the insulating material NM1 may contain silicon nitride (e.g., SiN). x ) or made of silicon nitride (ex, SiN) x Therefore, a plurality of first sacrificial layer patterns SL11 and a plurality of second sacrificial layer patterns SL21 formed of a second material having an etch selectivity ratio therewith are disposed within a matrix material layer formed of the first material.

[0084] Reference Figures 4a to 4c A first vertical hole H10 can be formed in the structure S20 to penetrate the first sacrificial layer pattern SL11 of the patterned portion SP1. The first vertical hole H10 can be formed to penetrate the second sacrificial layer pattern SL21 and the first sacrificial layer pattern SL11. The first vertical hole H10 can be formed to penetrate from the third insulating layer NL31 of the patterned portion SP1 to the first insulating layer NL11 in a defined area of ​​the structure S20. The first vertical hole H10 can correspond to the area where bit lines are subsequently formed. The first vertical hole H10 can be formed in the area of ​​the structure S20 where a transistor is to be formed, that is, the transistor forming area (transistor pre-forming area). Multiple first vertical holes H10 can be formed spaced apart from each other along the Y-axis direction. With the formation of the first vertical hole H10, the sides of the first sacrificial layer pattern SL11 and the second sacrificial layer pattern SL21 can be exposed.

[0085] To form the first vertical aperture H10, a second mask pattern M20 can be used. The second mask pattern M20 may have a defined opening pattern. The second mask pattern M20 may, for example, be a photoresist pattern. After the first vertical aperture H10 is formed, the second mask pattern M20 can be removed.

[0086] Reference Figures 5a to 5c An epitaxial growth method can be used to form an epitaxial material plug EP1 filling the first vertical hole H10 from the substrate (not shown). Using the epitaxial growth process, the epitaxial material plug EP1 filling the first vertical hole H10 can be formed from the upper surface portion of the substrate exposed by the first vertical hole H10. Therefore, this epitaxial growth method can be called selective epitaxial growth (SEG).

[0087] The epitaxial material plug EP1 may comprise a single-crystal semiconductor. For example, the epitaxial material plug EP1 may comprise single-crystal silicon. The epitaxial material plug EP1 may be composed of single-crystal silicon. However, the material of the epitaxial material plug EP1 is not limited to single-crystal silicon. Depending on the circumstances, the epitaxial material plug EP1 may comprise or be composed of other materials such as single-crystal germanium or single-crystal silicon-germanium.

[0088] Reference Figure 6a and Figure 6b A first etched portion T10, separated from the epitaxial material plug EP1, can be formed in the structure S20. The first etched portion T10 can be formed in the capacitor forming region adjacent to the transistor forming region in the structure S20. The first etched portion T10 can have a trench shape. Therefore, the first etched portion T10 can be referred to as a first trench. The first etched portion T10 can be formed to extend from the third insulating layer NL31 to the first insulating layer NL11, and can have a shape extending along the Y-axis direction. The first etched portion T10 can have a line pattern shape.

[0089] To form the first etched portion T10, a third mask pattern M30 can be used. The third mask pattern M30 may have a defined opening area. The third mask pattern M30 may, for example, be a photoresist pattern. After the first etched portion T10 is formed, the third mask pattern M30 can be removed.

[0090] Reference Figure 7a and Figure 7b The pattern of the first sacrificial layer exposed by the first etched portion T10 can be removed. Figure 6a SL11) and the second sacrificial layer pattern ( Figure 6a SL21) is used to form a horizontal hole H15 extending along the first direction, such as the X-axis direction. This can be achieved using the pattern of the first sacrificial layer (SL21). Figure 6a SL11) and the second sacrificial layer pattern ( Figure 6a SL21) has an etch-selective wet etchant and selectively removes the first sacrificial layer pattern via a wet etching process. Figure 6a SL11) and the second sacrificial layer pattern ( Figure 6a SL21). By removing the pattern of the first sacrificial layer ( Figure 6a The horizontal hole H15 formed by (SL11) can be referred to as the first horizontal hole, which is formed by removing the second sacrificial layer pattern ( Figure 6a The horizontal hole H15 formed by SL21 can be called the second horizontal hole. The horizontal hole H15 can have a linear shape extending along the X-axis direction.

[0091] According to one embodiment, in the step of forming the horizontal hole H15, the entire first sacrificial layer pattern can be removed.Figure 6a SL11). Also, in the step of forming the horizontal hole H15, the entire second sacrificial layer pattern (SL21) can be removed. Figure 6a SL11) and the entire second sacrificial layer pattern (SL21). Thus, the horizontal hole H15 can be formed to extend not only to the region where the transistor is to be formed (i.e., the transistor formation region), but also to the region where the capacitor is to be formed (i.e., the capacitor formation region). In this step, when the entire first sacrificial layer pattern (SL11) and the entire second sacrificial layer pattern (SL21) are removed, the horizontal hole H15 can be formed to extend to the region where the capacitor is to be formed. Figure 6a SL11) and the entire second sacrificial layer pattern (SL21). Thus, the horizontal hole H15 can be formed to extend not only to the region where the transistor is to be formed (i.e., the transistor formation region), but also to the region where the capacitor is to be formed (i.e., the capacitor formation region). In this step, when the entire first sacrificial layer pattern (SL11) and the entire second sacrificial layer pattern (SL21) are removed, the horizontal hole H15 can be formed to extend to the region where the capacitor is to be formed. Figure 6a SL11) and the entire second sacrificial layer pattern (SL21). Thus, the horizontal hole H15 can be formed to extend not only to the region where the transistor is to be formed (i.e., the transistor formation region), but also to the region where the capacitor is to be formed (i.e., the capacitor formation region). In this step, when the entire first sacrificial layer pattern (SL11) and the entire second sacrificial layer pattern (SL21) are removed, the horizontal hole H15 can be formed to extend to the region where the capacitor is to be formed.

[0092] Referring to Figure 8a and Figure 8b , the epitaxial channel material layer EC1 can be formed by an epitaxial growth method from the side surface of the epitaxial material plug EP1. The epitaxial channel material layer EC1 can be formed by an epitaxial growth process from the side surface portion of the epitaxial material plug EP1 exposed by the horizontal hole H15. Thus, the epitaxial growth method can be referred to as a selective epitaxial growth (SEG) method.

[0093] The epitaxial channel material layer EC1 can include a single-crystal semiconductor. For example, the epitaxial channel material layer EC1 can include single-crystal silicon. The epitaxial channel material layer EC1 can consist of single-crystal silicon. However, the material of the epitaxial channel material layer EC1 is not limited to single-crystal silicon. Depending on the case, the epitaxial channel material layer EC1 can include or consist of other materials such as single-crystal germanium or single-crystal silicon germanium. Since the epitaxial channel material layer EC1 can consist of a single-crystal material, the transistor formed using the epitaxial channel material layer EC1 can have excellent performance such as high mobility. Also, as described in the embodiments of the present application, the epitaxial channel material layer EC1 can have excellent thickness uniformity when formed.

[0094] Referring to Figure 9a and Figure 9b , a blank region can be formed around the epitaxial material plug EP1 and the epitaxial channel material layer EC1 by removing the first to third insulating layers (NL11, NL21, NL31) and the insulating material (NM1) from the structure S20. Since the first to third insulating layers (NL11, NL21, NL31) and the insulating material (NM1) can be the same material, they can be easily removed using an etching method having etching selectivity. Figure 8a Figure 8b Since the first to third insulating layers (NL11, NL21, NL31) and the insulating material (NM1) can be the same material, they can be easily removed using an etching method having etching selectivity. Figure 8a Figure 8b Since the first to third insulating layers (NL11, NL21, NL31) and the insulating material (NM1) can be the same material, they can be easily removed using an etching method having etching selectivity. ​​

[0095] Reference Figure 10a and Figure 10b A gate insulating material layer GN1 can be formed on the surface portion of the epitaxial material plug EP1 and the epitaxial channel material layer EC1. According to one embodiment, the gate insulating material layer GN1 can be formed using a thermal oxidation process targeting the surface portion of the epitaxial material plug EP1 and the epitaxial channel material layer EC1. In this case, the gate insulating material layer GN1 can be an oxide layer. For example, the gate insulating material layer GN1 can be a silicon oxide layer.

[0096] However, the method for forming the gate insulating material layer GN1 and its constituent materials are not limited to those described above and can be varied in various ways. For example, the gate insulating material layer GN1 can also be formed using an atomic layer deposition (ALD) process. In this case, the gate insulating material layer GN1 can be formed to include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material. The high-k material can be a material with a dielectric constant higher than that of silicon nitride.

[0097] Reference Figure 11a and Figure 11b A filling insulation layer NF1 can be formed on the gate insulating material layer GN1 to fill the blank area. That is, a filling insulation layer NF1 can be formed on the gate insulating material layer GN1 to fill the blank area surrounding the epitaxial material plug EP1 and the epitaxial channel material layer EC1. As a non-limiting example, the filling insulation layer NF1 may contain silicon nitride (e.g., SiN). x ) or made of silicon nitride (ex, SiN) x The filling insulating layer NF1 can also be formed from materials other than silicon nitride. When forming the filling insulating layer NF1, after depositing the insulator for the filling insulating layer NF1, a planarization process can be further performed on its upper surface and surrounding area.

[0098] In this step, the structure S20 can include the epitaxial material plug EP1, the epitaxial channel material layer EC1, the gate insulating material layer GN1, and the filling insulating layer NF1. The structure S20 can include the epitaxial material plug EP1 extending in a vertical direction on the substrate (not shown), the epitaxial channel material layer EC1 extending in a horizontal direction from a side surface of the epitaxial material plug EP1, the gate insulating material layer GN1 formed at least on a surface portion of the epitaxial channel material layer EC1, and the filling insulating layer NF1 formed on the gate insulating material layer GN1 and filling a surrounding space of the epitaxial material plug EP1 and the epitaxial channel material layer EC1. Here, the gate insulating material layer GN1 can be formed on the surface portion of the epitaxial material plug EP1 and the epitaxial channel material layer EC1.

[0099] As shown in the structure S20 shown in Figure 11a and Figure 11b , the setting method of the structure S20 can be varied in various ways. In other words, the process described with reference to Figures 1a to 11b can be deformed in various ways.

[0100] With reference to Figure 12a and Figure 12b , in the structure S20 in which the gate insulating material layer GN1 and the filling insulating layer NF1 are formed, a second vertical hole H20 can be formed in a region corresponding to the first vertical hole H10 of the first vertical hole H10. The second vertical hole H20 can be formed to penetrate the filling insulating layer NF1 in the up-down direction. For reference, the expression "corresponding" in the present specification can mean the same, but can be a concept that covers substantially the same or similar. This can be equally applied in the present specification. Figure 4a

[0101] In order to form the second vertical hole H20, a fourth mask pattern M40 can be used. The fourth mask pattern M40 can have a prescribed opening pattern. The fourth mask pattern M40 can be, for example, a photoresist pattern. After the second vertical hole H20 is formed, the fourth mask pattern M40 can be removed.

[0102] With reference to Figure 13a and Figure 13b , the gate insulating material layer GN1 can be exposed by removing the filling insulating layer NF1 from a transistor formation region (transistor pre-formation region) around the second vertical hole H20 of the structure S20. In this case, a fifth mask pattern M50 can be formed on a capacitor formation region (capacitor pre-formation region) adjacent to the transistor formation region (transistor pre-formation region), and the fifth mask pattern M50 can be formed to expose the transistor formation region. The filling insulating layer NF1 in the transistor formation region can be etched and removed using the fifth mask pattern M50 as an etching mask. Then, the fifth mask pattern M50 can be removed.

[0103] ​Then, using, for example Figures 14a to 23b The illustrated method forms word lines surrounding the exposed gate insulating material layer GN1 portion in the transistor formation region. Figure 23a The WL1 is used to define the transistor that includes the word line.

[0104] Reference Figure 14a and Figure 14b A word line material layer WM1 can be formed around the exposed gate insulating material layer GN1 portion in the transistor formation region. The word line material layer WM1 can be formed substantially conformally along the shape of the exposed surface region in the transistor formation region. The word line material layer WM1 can be formed, for example, by an atomic layer deposition process. In this case, such as... Figure 14a As shown, the gap along the Z-axis between the lower and upper epitaxial channel material layers EC1 can be greater than approximately twice the thickness of the word line material layer WM1. Furthermore, the gap along the Z-axis between the lower and upper gate insulating material layers GN1 can be greater than approximately twice the thickness of the word line material layer WM1. On the other hand, as... Figure 14b As shown, the gap along the Y-axis between the two epitaxial channel material layers EC1 separated along the Y-axis can be less than approximately twice the thickness of the word line material layer WM1. Furthermore, the gap along the Y-axis between the two gate insulating material layers GN1 separated along the Y-axis can be less than approximately twice the thickness of the word line material layer WM1.

[0105] The word line material layer WM1 can be formed as a material layer EC1 surrounding each epitaxial channel in the transistor formation region. Furthermore, the word line material layer WM1 can have a line shape extending along the Y-axis direction.

[0106] Reference Figure 15a and Figure 15b This can form a gap-fill insulation layer NG1, which fills the blank space in the bend (bend) of the filler word line material layer WM1. The gap-fill insulation layer NG1 can be formed of insulating oxide or other insulating materials.

[0107] Reference Figure 16a and Figure 16b The letter lines are etched using material layer WM1 and the second vertical hole ( Figure 12a The via H25 is formed in the area corresponding to H20. The via H25 can be a vertical hole. To form the via H25, a sixth mask pattern M60 can be used. The sixth mask pattern M60 can have a defined opening pattern. The sixth mask pattern M60 can, for example, be a photoresist pattern. After forming the via H25, the sixth mask pattern M60 can be removed.

[0108] Referring to Figure 17a and Figure 17b A portion of the word line material layer WM1 exposed through the through hole H25 can be recessed so that one end of the epitaxial channel material layer EC1 protrudes more to the through hole H25 side than the word line material layer WM1. Thus, a portion of the word line material layer WM1 can be etched around the through hole H25, and a plurality of etched regions (a plurality of recessed regions) can be connected in the Y-axis direction.

[0109] Referring to Figure 18a and Figure 18b A bulk insulating layer BN1 can be formed to fill the through hole H25 and the plurality of etched regions (a plurality of recessed regions) around the same. The bulk insulating layer BN1 can be formed of insulating oxide or other insulating material. The bulk insulating layer BN1 can be formed of the same material as the gap filling insulating layer NG1, or can be formed of other material.

[0110] Referring to Figure 19a and Figure 19b A third vertical hole H30 can be formed in a region corresponding to the second vertical hole (H20) of the bulk insulating layer BN1. To form the third vertical hole H30, a seventh mask pattern M70 can be used. The seventh mask pattern M70 can have a prescribed opening pattern. The seventh mask pattern M70 can be, for example, a photoresist pattern. After the third vertical hole H30 is formed, the seventh mask pattern M70 can be removed. Figure 12a Referring to

[0111] and Figure 20a A bit line BL1 can be formed within the third vertical hole H30. The bit line BL1 can be connected (contacted) to one end of the epitaxial channel material layer EC1. Thus, the bit line BL1 can be formed to be connected (contacted) to one end of the epitaxial channel material layer EC1 in a region of the transistor formation region corresponding to the second vertical hole (H20) of the bulk insulating layer BN1. The bit line BL1 can have a columnar shape that penetrates the structure S20 in the vertical direction. The bit line BL1 can be electrically connected to one end of the epitaxial channel material layer EC1 in the lateral direction. A plurality of bit lines BL1 connected to a plurality of epitaxial channel material layers EC1 can be formed. Figure 20b Figure 12a Although not shown, if a conductive material of the bit line BL1 is deposited on the upper side of the third vertical hole H30, it can be removed by, for example, an etchback process.

[0112] Referring to and

[0113] A bit line BL1 can be formed within the third vertical hole H30. The bit line BL1 can be connected (contacted) to one end of the epitaxial channel material layer EC1. Thus, the bit line BL1 can be formed to be connected (contacted) to one end of the epitaxial channel material layer EC1 in a region of the transistor formation region corresponding to the second vertical hole (H20) of the bulk insulating layer BN1. The bit line BL1 can have a columnar shape that penetrates the structure S20 in the vertical direction. The bit line BL1 can be electrically connected to one end of the epitaxial channel material layer EC1 in the lateral direction. A plurality of bit lines BL1 connected to a plurality of epitaxial channel material layers EC1 can be formed. Figure 21a Figure 21b ​A second etching portion T20 can be formed in the capacitor formation region of the structure S20, which is spaced apart from the bit line BL1. The second etching portion T20 can have a trench shape. Thus, the second etching portion T20 can be referred to as a second trench. The second etching portion T20 can be formed to be through the filling insulating layer NF1, and can have a shape extending in the Y-axis direction. The second etching portion T20 can have a line pattern shape. The second etching portion T20 can be formed in a region corresponding to the first etching portion (T10) of the structure S10. Figure 6a

[0114] According to an embodiment, the second etching portion T20 can be formed by etching a portion of the filling insulating layer NF1 and a portion of the gate insulating material layer GN1. An end portion of the gate insulating material layer GN1 and an end portion of the epitaxial channel material layer EC1 can be exposed toward the second etching portion T20 side.

[0115] To form the second etching portion T20, an eighth mask pattern M80 can be used. The eighth mask pattern M80 can have a prescribed opening region. The eighth mask pattern M80 can be, for example, a photoresist pattern.

[0116] Referring to Figure 22a and Figure 22b , a first recessed portion R1 exposing the gate insulating material layer GN1 and the word line material layer WM1 can be formed by removing (etching) the filling insulating layer (NF1) exposed by the second etching portion T20 from the capacitor formation region. Figure 21a

[0117] Referring to Figure 23a and Figure 23b , after the first recessed portion R1 is formed in the capacitor formation region, a portion of the word line material layer (WM1) exposed by the first recessed portion R1 can be recessed. In other words, a portion of the word line material layer (WM1) exposed toward the capacitor formation region side can be recessed. As a result, the word line material layer portion surrounding the lower epitaxial channel material layer EC1 and the word line material layer portion surrounding the upper epitaxial channel material layer EC1 can be separated from each other. Among them, the separated word line material layer portions can be referred to as word lines WL1. Then, the eighth mask pattern M80 can be removed. However, the removal timing point of the eighth mask pattern M80 can vary. Figure 22a Figure 22a The word line WL1 can have a structure surrounding the gate insulating material layer GN1. Thus, a transistor including the word line WL1 can have a gate-all-around (GAA) structure. Thereby, the transistor can have excellent gate control and high on-current characteristics.

[0118] The word line WL1 can have a structure surrounding the gate insulating material layer GN1. Thus, a transistor including the word line WL1 can have a gate-all-around (GAA) structure. Thereby, the transistor can have excellent gate control and high on-current characteristics. ​​​

[0119] Although the present application is described with reference to Figures 14a to 23b The method of forming the word line WL1 and the like is specifically described, but this is merely exemplary, and the method of forming the word line WL1 and the like can be changed in various ways according to the situation.

[0120] Referring to Figure 24a and Figure 24b After the first recessed portion R1 is formed in the capacitor formation region, an insertion insulating layer NN1 can be formed which surrounds the exposed gate insulating material layer GN1 portion in the capacitor formation region. The insertion insulating layer NN1 can be formed conformally on the surface region exposed to the first recessed portion R1. The insertion insulating layer NN1 can be formed to cover the surfaces of the gate insulating material layer GN1, the epitaxial channel material layer EC1, and the word line WL1 and the like exposed to the capacitor formation region. The insertion insulating layer NN1 can be formed, for example, by an atomic layer deposition process. The thickness of the insertion insulating layer NN1 can be as thin as several tens of nm or less. The insertion insulating layer NN1 can be formed of an insulating oxide or of another insulating material.

[0121] Referring to Figure 25a and Figure 25b A mold insulating layer MN1 can be formed which fills the first recessed portion R1. The mold insulating layer MN1 can be formed on the insertion insulating layer NN1 to fill the first recessed portion R1 and the second etched portion T20. The mold insulating layer MN1 can contain, for example, silicon nitride (ex, SiN x ) or be formed of silicon nitride (ex, SiN x ). When the mold insulating layer MN1 is formed, after the deposition of the mold insulating layer MN1 with an insulator, a planarization process is further performed on the upper surface and the surrounding region thereof.

[0122] Referring to Figure 26a and Figure 26b A third etched portion T30 can be formed in the mold insulating layer MN1 corresponding to the T20 of the second etched portion ( Figure 21a ). The third etched portion T30 can be formed by etching a portion of the mold insulating layer MN1 and a portion of the insertion insulating layer NN1. Thus, the end portion of the gate insulating material layer GN1 and the end portion of the epitaxial channel material layer EC1 can be exposed toward the third etched portion T30 side. The third etched portion T30 can have a linear shape extending in the Y-axis direction. The third etched portion T30 can be referred to as a third trench.

[0123] To form the third etched portion T30, a ninth mask pattern M90 can be used. The ninth mask pattern M90 can have a prescribed opening region. The ninth mask pattern M90 can be, for example, a photoresist pattern. After the third etched portion T30 is formed, the ninth mask pattern M90 can be removed.

[0124] Referring to Figure 27a and Figure 27b The second recessed portion R2 can be formed by etching the epitaxial channel material layer EC1, the gate insulating material layer GN1, and the intervening insulating layer NN1 exposed by the third etching portion T30. The epitaxial channel material layer EC1, the gate insulating material layer GN1, and the intervening insulating layer NN1 can be etched by introducing a prescribed wet etchant, i.e., a wet etching solution, through the third etching portion T30. In this case, one or more wet etchants can be used. The second recessed portion R2 can be formed to a region slightly spaced apart from the word line WL1. The etching range of the epitaxial channel material layer EC1, the gate insulating material layer GN1, and the intervening insulating layer NN1 can be controlled by adjusting the conditions of the etching process.

[0125] When the intervening insulating layer NN1 is first formed in the step of the above Figure 24a and then removed in the step of the above Figure 27a , the second recessed portion R2 can be formed to have a width greater than the width of the remaining gate insulating material layer GN1. Thus, the width of the second recessed portion R2 in the Z-axis direction can be greater than the width of the remaining gate insulating material layer GN1 in the Z-axis direction. Also, the width of the second recessed portion R2 in the Y-axis direction can be greater than the width of the remaining gate insulating material layer GN1 in the Y-axis direction. Finally, in subsequent processes, the process margin for forming the capacitor can increase. In order to secure the process margin or the like, it can be preferable to form the intervening insulating layer NN1. However, the formation of the intervening insulating layer NN1 can be optional and can be omitted, as appropriate.

[0126] On the other hand, in the step of the above Figure 27a , the epitaxial channel material layer EC1 can be etched and removed in the capacitor formation region using a wet etching process, and thus such wet etching can hardly cause etching damage to the epitaxial channel material layer EC1.

[0127] Referring to Figure 28a and Figure 28b , an electrode member EL1 connected to the other end of the epitaxial channel material layer EC1 can be formed on the inner side surface of the second recessed portion R2 of the above Figure 27a . The electrode member EL1 can be connected to the other end of the epitaxial channel material layer EC1 of the transistor. The electrode member EL1 can be referred to as a capacitor electrode layer (first electrode layer). The electrode member EL1 can be formed conformally along the surface shape of the mold insulating layer MN1. The electrode member EL1 can be formed by, for example, an atomic layer deposition process.

[0128] Referring to Figure 29a and Figure 29bIt can be located in the capacitor forming region and the third etched portion ( Figure 26a The fourth etched portion T40 is formed in the area corresponding to T30. The fourth etched portion T40 can be formed by etching a portion of the electrode component EL1. The fourth etched portion T40 can have a line shape extending along the Y-axis direction. The fourth etched portion T40 can be referred to as the fourth trench. Through this process, the electrode component EL1 can be separated into individual capacitor regions. In other words, the electrode component EL1 can be separated into unit cell regions.

[0129] To form the fourth etched portion T40, a tenth mask pattern M100 can be used. The tenth mask pattern M100 may have a defined opening area. The tenth mask pattern M100 may, for example, be a photoresist pattern. After forming the fourth etched portion T40, the tenth mask pattern M100 can be removed.

[0130] Reference Figure 30a and Figure 30b After forming the electrode component EL1, the mold insulating layer can be etched ( Figure 29a The outer surface of the electrode component EL1 is exposed by removing the entire mold insulation layer (MN1). Figure 29a The MN1 is used to expose the insertion insulating layer NN1. However, the mold insulating layer (MN1) can be appropriately adjusted as needed. Figure 29a The etching range of MN1). As a method of adjusting the etching range, the tenth mask pattern ( Figure 29a At least a portion of the M100 can be used, or a separate hard mask (not shown) can also be used. If necessary, the mold insulation layer adjacent to the insertion insulation layer NN1 can also be retained. Figure 29a A portion of MN1, without etching.

[0131] Reference Figure 31a and Figure 31b A dielectric layer DL1 can be formed on the electrode component EL1 in the capacitor forming region. The dielectric layer DL1 can be a dielectric layer for a capacitor. The dielectric layer DL1 can be formed conformally along the surface shape of the electrode component EL1. The dielectric layer DL1 can be formed (deposited) by, for example, an atomic layer deposition process. The dielectric layer DL1 can be formed to contain at least one of a variety of dielectric materials. For example, the dielectric layer DL1 can contain a high-k material with a dielectric constant higher than that of silicon nitride. The specific material of the dielectric layer DL1 can vary in various ways.

[0132] Reference Figure 32a and Figure 32bA plate electrode PL1 can be formed on the dielectric layer DL1 in the capacitor formation region. The plate electrode PL1 can be referred to as a capacitor electrode layer (second electrode layer). The plate electrode PL1 can be formed to fill the space between the fourth etching portion (T40) of the capacitor formation region and the inside of the electrode member EL1 and between the plurality of electrode members EL1. The plate electrode PL1 can be formed to contain one or more of a plurality of electrode materials used in a semiconductor device process. The plate electrode PL1 can have a linear shape. Thus, the plate electrode PL1 can be referred to as a plate electrode line. The electrode member EL1, the dielectric layer DL1, and the plate electrode PL1 can constitute a capacitor. Figure 29a

[0133] Figures 28a to 32b The method of forming the capacitor is exemplarily shown and explained in the above, but the method of forming the capacitor and the detailed structure of the capacitor can be changed in various ways depending on the situation.

[0134] In the device structure shown in the above, Figure 32a The lower epitaxial channel material layer EC1, the word line WL1 surrounding the same, and the gate insulating material layer GN1 therebetween can be regarded as constituting a first transistor TR1. Also, the lower electrode member EL1 electrically connected to the first transistor TR1 along the side of the first transistor TR1, and the dielectric layer DL1 and the plate electrode PL1 in contact with the same can be regarded as constituting a first capacitor CP1. Also, the first transistor TR1 and the first capacitor CP1 can be regarded as constituting one memory cell (lower memory cell). The first transistor TR1 and the first capacitor CP1 can be arranged in the horizontal direction.

[0135] Also, the upper epitaxial channel material layer EC1, the word line WL1 surrounding the same, and the gate insulating material layer GN1 therebetween, etc. can be regarded as constituting a second transistor TR2. Also, the upper electrode member EL1 electrically connected to the second transistor TR2 along the side of the second transistor TR2, and the dielectric layer DL1 and the plate electrode PL1 in contact with the same can be regarded as constituting a second capacitor CP2. Also, the second transistor TR2 and the second capacitor CP2 can be regarded as constituting one memory cell (upper memory cell). The second transistor TR2 and the second capacitor CP2 can be arranged in the horizontal direction. The second transistor TR2 can be provided on the first transistor TR1, and the second capacitor CP2 can be provided on the first capacitor CP1.

[0136] Although not shown, as Figure 32a and Figure 32b ​The device structure shown can be repeatedly arranged in the Z-axis direction, can be repeatedly arranged in the X-axis direction, or can be repeatedly arranged in the Y-axis direction. According to this embodiment of the present application, a memory device having a high degree of integration and excellent performance and operating characteristics can be realized. The memory device can be a stacked memory device of a gate-all-around (GAA) type having a horizontal arrangement and a stacked structure. Furthermore, the memory device of this embodiment of the present application can be a vertical dynamic random access memory (DRAM) device or a three-dimensional DRAM device.

[0137] Hereinafter, a memory device of an embodiment of the present application will be described with reference to Figure 32a and Figure 32b A memory device of an embodiment of the present application will be further described.

[0138] With reference to Figure 32a and Figure 32b , a memory device of an embodiment of the present application can include a plurality of memory cells stacked in a vertical direction. The plurality of memory cells can each include a transistor and a capacitor electrically connected to the transistor in a lateral direction of the transistor. The transistor can correspond to TR1 and TR2, and the capacitor can correspond to CP1 and CP2. The transistor can include an epitaxial channel material layer EC1, a word line WL1 surrounding the epitaxial channel material layer EC1, and a gate insulating layer GN1 provided therebetween. The capacitor can include an electrode member EL1 electrically connected to the transistor, a dielectric layer DL1 provided on a surface of the electrode member EL1, and a plate electrode PL1 provided on a surface of the dielectric layer DL1.

[0139] Furthermore, the memory device can include a bit line BL1 connected to a plurality of transistors of the plurality of memory cells. The bit line BL1 can extend in the vertical direction. A bulk insulating layer BN1 surrounding at least a portion of an outer surface of the bit line BL1 can be provided between the bit line BL1 and the word line WL1. A gap filling insulating layer NG1, which is a material layer separate from the bulk insulating layer BN1, can be provided between two adjacent word lines WL1 of the plurality of transistors.

[0140] The epitaxial channel material layer EC1 can include a single-crystal semiconductor. For example, the epitaxial channel material layer EC1 can include one of a single-crystal silicon, a single-crystal germanium, and a single-crystal silicon germanium. The transistor including the epitaxial channel material layer EC1 can have excellent performance.

[0141] When viewed from above, the bulk insulating layer BN1 can have a structure in which a plurality of annular-shaped unit bodies are connected in a row (see FIG. 1A). Figure 32bThe plurality of circular ring-shaped unit bodies can each have a ring-shaped cross-sectional structure. For example, the plurality of circular ring-shaped unit bodies can each have a ring-shaped or substantially circular ring-shaped cross-sectional structure. Also, the bulk insulating layer BN1 can have a shape extending in the same direction as the word lines WL1 when viewed from above. Within the bulk insulating layer BN1, the plurality of bit lines BL1 can be provided apart from each other in the horizontal direction, that is, the horizontal direction in which the word lines WL1 extend.

[0142] In an embodiment of the present application, the transistor can have a gate-all-around (GAA) structure. Thereby, the transistor and the memory device including the same can have excellent characteristics.

[0143] Further, the memory device can further include an interposed insulating layer NN1 extending in a manner surrounding a portion (end portion) of the gate insulating layer GN1 adjacent to the electrode member EL1 and covering a side surface of the word line WL1. The interposed insulating layer NN1 can be a material layer separate from the bulk insulating layer BN1 and the gap filling insulating layer NG1. The interposed insulating layer NN1 can be, for example, an atomic layer deposition (ALD) material layer.

[0144] According to an embodiment, the bulk insulating layer BN1 can be in contact with a first side surface (first end portion) of the gap filling insulating layer NG1, and the interposed insulating layer NN1 can be in contact with a second side surface (second end portion) of the gap filling insulating layer NG1. A portion of the interposed insulating layer NN1 can be in contact with the electrode member EL1.

[0145] Also, according to an embodiment, a side surface of the interposed insulating layer NN1 can be in contact with a side surface of the dielectric layer DL1. The word line WL1 can be in contact with a first side surface of the interposed insulating layer NN1, and the dielectric layer DL1 can be in contact with a second side surface of the interposed insulating layer NN1. However, this result is not limited, and can be modified.

[0146] The memory device of an embodiment of the present application can have structural features as shown in Figure 32a and Figure 32b For example, the memory device can have a stacked structure including an epitaxial channel material layer EC1, and have structural features of the bulk insulating layer BN1, the gap filling insulating layer NG1, the interposed insulating layer NN1, and their peripheral portions, and the transistor and the capacitor.

[0147] According to the above-described embodiments of the present application, a memory device (stacked memory device) and a manufacturing method thereof can be implemented, in which integration can be improved, excellent performance can be ensured, a process can be simple, and manufacturing costs can be reduced. Also, according to the embodiments of the present application, a memory device (stacked memory device) and a manufacturing method thereof can be implemented, in which by using a single-crystal channel material, performance such as mobility can be improved, uniformity of a channel thickness can be improved, and on-current characteristics can be improved. In particular, according to an embodiment of the present application, by using a stack of an insulating layer and a sacrificial layer, an epitaxial channel layer is formed by a selective epitaxial growth (SEG) method, so that compared to a conventional method using a silicon (Si) / silicon germanium (SiGe) stack structure, process difficulty can be reduced, manufacturing costs can be reduced, and a memory device having improved performance can be manufactured. In the embodiments of the present application, since a selective epitaxial process for a single material is used, compared to a conventional method in which an epitaxial process is repeatedly performed for a plurality of materials (e.g., Si and SiGe), a process can be greatly simplified.

[0148] Figures 33a to 63b FIG. 1 is a flowchart illustrating a manufacturing method of a memory device (stacked memory device) according to an embodiment of the present application.

[0149] In Figures 33a to 63b , the same reference numerals (e.g., 100 in FIG. 1) denote the same steps. Figure 33a , Figure 33b , Figure 33c Figure 33a , Figure 34a , Figure 35a , Figure 36a , Figure 37a , Figure 38a , Figure 39a , Figure 40a , Figure 41a , Figure 42a , Figure 43a , Figure 44a , Figure 45a , Figure 46a , Figure 47a , Figure 48a , Figure 49a , Figure 50a , Figure 51a , Figure 52a , Figure 53a , Figure 54a , Figure 55a , Figure 56a , Figure 57a , Figure 58a , Figure 59a , Figure 60a , Figure 61a ,​Figure 62a 、 Figure 63a is a cross-sectional view taken along the XZ plane. Figure 33b 、 Figure 34b 、 Figure 35b 、 Figure 36b 、 Figure 37b 、 Figure 38b 、 Figure 39b 、 Figure 40b 、 Figure 41b 、 Figure 42b 、 Figure 43b 、 Figure 44b 、 Figure 45b 、 Figure 46b 、 Figure 47b 、 Figure 48b 、 Figure 49b 、 Figure 50b 、 Figure 51b 、 Figure 52b 、 Figure 53b 、 Figure 54b 、 Figure 55b 、 Figure 56b 、 Figure 57b 、 Figure 58b 、 Figure 59b 、 Figure 60b 、 Figure 61b 、 Figure 62b 、 Figure 63b is a top-view or a Z-cut view taken along the XY plane. Figure 33c 、 Figure 34c 、 Figure 35c 、 Figure 36c 、 Figure 37c 、 Figure 38c 、 Figure 39c 、 Figure 40c 、 Figure 41c 、 Figure 42c 、 Figure 43c 、 Figure 44c is a cross-sectional view taken along the YZ plane.

[0150] Referring to Figures 33a to 33cA laminate S10 can be formed on a specified substrate (not shown). The material of the substrate can be selected from a variety of materials. The substrate can contain semiconductor materials. The substrate can contain semiconductor wafers. The substrate can include bulk silicon substrates, silicon-on-insulator (SOI) substrates, germanium substrates, germanium-on-insulator (GOI) substrates, silicon-germanium substrates, or substrates formed by epitaxial growth processes. The substrate can contain single-crystal semiconductor materials. For example, the substrate can contain one of single-crystal silicon (Si), single-crystal germanium (Ge), and single-crystal silicon-germanium (SiGe).

[0151] A laminate S10 can be formed on the substrate. The laminate S10 may include a first insulating layer NL10 and a first sacrificial layer SL10 and a second insulating layer NL20 sequentially formed on the first insulating layer NL10. As a non-limiting example, the first insulating layer NL10 and the second insulating layer NL20 may contain silicon nitride (e.g., SiN). x ) or made of silicon nitride (ex, SiN) x The first insulating layer NL10 and the first sacrificial layer SL10 may be formed by comprising or being formed of silicon oxide (ex, SiO2). The first insulating layer NL10 and the first sacrificial layer SL10 may have an etch selectivity ratio, and similarly, the second insulating layer NL20 and the first sacrificial layer SL10 may have an etch selectivity ratio. The first insulating layer NL10, the first sacrificial layer SL10, and the second insulating layer NL20 may be formed by a deposition process.

[0152] Furthermore, according to one embodiment, the laminate S10 may further include a second sacrificial layer SL20 and a third insulating layer NL30 sequentially laminated on the second insulating layer NL20. In this case, the laminate S10 may have a structure that is vertically symmetrical with respect to the second insulating layer NL20. The second sacrificial layer SL20 may be formed of the same material as the first sacrificial layer SL10, and the third insulating layer NL30 may be formed of the same material as the first insulating layer NL10 and / or the second insulating layer NL20. The second sacrificial layer SL20 and the third insulating layer NL30 may be formed by a deposition process.

[0153] The thickness of the second insulating layer NL20 can be greater than the thickness of each of the first insulating layer NL10, the third insulating layer NL30, the first sacrificial layer SL10, and the second sacrificial layer SL20. For example, the thickness of the second insulating layer NL20 can be about 1.5 to 2.5 times the thickness of each of the first insulating layer NL10, the third insulating layer NL30, the first sacrificial layer SL10, and the second sacrificial layer SL20. By forming the relatively thick second insulating layer NL20, a gap between upper and lower cells to be formed later can be ensured. The first insulating layer NL10 and the third insulating layer NL30 can have the same thickness or substantially the same thickness. The first sacrificial layer SL10 and the second sacrificial layer SL20 can have the same thickness or substantially the same thickness. The first insulating layer NL10, the third insulating layer NL30, the first sacrificial layer SL10, and the second sacrificial layer SL20 can have the same thickness or substantially the same thickness.

[0154] Referring to Figures 34a to 34c A first etching portion T10 can be formed through a region including at least one bit line preformation region in the laminate S10. The first etching portion T10 can be formed through the at least one bit line preformation region and a region adjacent thereto. The first etching portion T10 can be formed through a plurality of the bit line preformation regions in common. The first etching portion T10 can have a trench shape through the plurality of the bit line preformation regions in common. Thus, the first etching portion T10 can be referred to as a first trench. The first etching portion T10 can be formed through from the third insulating layer NL30 to the first insulating layer NL10, for example, can have a shape extending in the Y-axis direction. The first etching portion T10 can have a line pattern shape. The first etching portion T10 can be formed in a region where a transistor is to be formed, i.e., a transistor formation region (a transistor preformation region). Among them, Figure 34c may be a cross-sectional view taken along Figure 34a (A) line.

[0155] To form the first etching portion T10, a first mask pattern M10 can be used. The first mask pattern M10 can have a prescribed opening region. The first mask pattern M10 can be, for example, a photoresist pattern. After the first etching portion T10 is formed, the first mask pattern M10 can be removed.

[0156] Referring to Figures 35a to 35c, an epitaxial material plug EP10 filling the first etching portion T10 can be formed from the substrate (not shown) by an epitaxial growth method. The epitaxial material plug EP10 filling the first etching portion T10 can be formed from the upper surface portion of the substrate exposed by the first etching portion T10 by an epitaxial growth process. Thus, the epitaxial growth method can be referred to as a selective epitaxial growth (SEG) method. In this case, Figure 35b may be a cross-sectional view taken along the (B) line of Figure 35a .

[0157] The epitaxial material plug EP10 can include a single-crystal semiconductor. For example, the epitaxial material plug EP10 can include single-crystal silicon. The epitaxial material plug EP10 can consist of single-crystal silicon. However, the material of the epitaxial material plug EP10 is not limited to single-crystal silicon. Depending on the case, the epitaxial material plug EP10 can include or consist of single-crystal germanium or single-crystal silicon germanium or other materials. The epitaxial material plug EP10 can have, for example, a vertical plate shape extending in the Y-axis direction.

[0158] Referring to Figures 36a to 36c , a second etching portion T20 spaced apart from the epitaxial material plug EP10 can be formed in the laminate S10. The second etching portion T20 can be formed in a capacitor formation region (capacitor pre-formation region) of the laminate S10 adjacent to the transistor formation region. The second etching portion T20 can have a trench shape. Thus, the second etching portion T20 can be referred to as a second trench. The second etching portion T20 can be formed to penetrate through the first insulating layer NL10 from the third insulating layer NL30, for example, can have a shape extending in the Y-axis direction. The second etching portion T20 can have a line pattern shape.

[0159] To form the second etching portion T20, a second mask pattern M20 can be used. The second mask pattern M20 can have a prescribed opening region. The second mask pattern M20 can be, for example, a photoresist pattern. The second mask pattern M20 can be removed after the second etching portion T20 is formed.

[0160] Referring to Figures 37a to 37c , a horizontal space portion H5 can be formed by removing the first sacrificial layer (SL10 of Figure 36a ) and the second sacrificial layer (SL20 of Figure 36a ) exposed by the second etching portion T20. The horizontal space portion H5 can extend parallel to the XY plane. The first sacrificial layer (SL10 of Figure 36a ) and the second sacrificial layer (SL20 of Figure 36aSL20) is an etch-selective wet etchant that selectively removes the first sacrificial layer via a wet etching process. Figure 36a SL10) and the second sacrificial layer ( Figure 36a SL20). By removing the first sacrificial layer ( Figure 36a The horizontal space portion H5 formed by removing the second sacrificial layer (SL10) can be referred to as the first horizontal space portion. Figure 36a The horizontal space H5 formed by SL20 can be called the second horizontal space.

[0161] According to one embodiment, in the step of forming the horizontal space portion H5, the entire first sacrificial layer can be removed. Figure 36a SL10). Furthermore, in the step of forming the horizontal space H5, the entire second sacrificial layer can be removed ( Figure 36a SL20). Therefore, the horizontal space portion H5 can be formed to extend not only to the region where a transistor is to be formed (i.e., the transistor forming region) but also to the region where a capacitor is to be formed (i.e., the capacitor forming region). In this step, when the entire first sacrificial layer is removed ( Figure 36a SL10) and the entire second sacrificial layer ( Figure 38a to 38c When using SL20, the process can be simplified.

[0162] Reference Figures 39a to 39c Using an epitaxial growth method, an epitaxial channel material layer EC10 filling the horizontal space H5 can be formed from the side of the epitaxial material impregnating EP10. Using an epitaxial growth process, an epitaxial channel material layer EC10 filling the horizontal space H5 can be formed from the exposed epitaxial material impregnating the side of EP10. Therefore, this epitaxial growth method can be called selective epitaxial growth (SEG). The epitaxial channel material layer EC10 can have a plate (horizontal plate) shape parallel to the XY plane.

[0163] The epitaxial channel material layer EC10 can comprise a single-crystal semiconductor. For example, the epitaxial channel material layer EC10 can comprise single-crystal silicon. The epitaxial channel material layer EC10 can be composed of single-crystal silicon. However, the material of the epitaxial channel material layer EC10 is not limited to single-crystal silicon. Depending on the circumstances, the epitaxial channel material layer EC10 can comprise or be composed of other materials such as single-crystal germanium or single-crystal silicon germanium. Since the epitaxial channel material layer EC10 can be composed of single-crystal materials, transistors formed using the epitaxial channel material layer EC10 can have excellent performance such as high mobility. Furthermore, as described in the embodiments of the present invention, when the epitaxial channel material layer EC10 is formed, the epitaxial channel material layer EC10 can have excellent thickness uniformity.

[0164] Reference Figure 38a This can be achieved by processing the epitaxial channel material layer ( Figure 38a The laminate of EC10) Figure 38a The patterned laminate S11 is formed by patterning the epitaxial channel material layer (S10) to form a patterned laminate S11 having at least one patterned portion SP1, wherein the at least one patterned portion SP1 has a patterned portion originating from the epitaxial channel material layer (S10). Figure 38a The epitaxial channel pattern EC1 obtained from EC10 and the epitaxial material plug ( Figures 39a to 39c The epitaxial embolization pattern EP1 obtained from EP10. The epitaxial channel pattern EC1 can be referred to as the "epitaxical channel pattern section", and the epitaxial embolization pattern EP1 can be referred to as the "epitaxical embolization pattern section".

[0165] Referring to the pattern portion SP1, it can have a shape extending along a first direction, such as the X-axis, and blank spaces can be provided on both sides of the pattern portion SP1 along a second direction perpendicular to the first direction, such as the Y-axis. Multiple pattern portions SP1 can be spaced apart along the Y-axis and arranged side-by-side along the X-axis. In each pattern portion SP1, the epitaxial channel pattern EC1 and the epitaxial plug pattern EP1 can have the same width (width along the Y-axis). The epitaxial channel pattern EC1 can be line-shaped and can have a shape broken (disconnected) by the second etching portion T20. In this step, the epitaxial channel pattern EC1, including the channel region that will subsequently be used as the actual channel, can be defined. Therefore, this step can be considered a cell patterning step.

[0166] for Figure 38a Patterning techniques can be used to set patterns on the stacked body ( Figures 40a to 40c The third mask pattern M30 is applied to the S10. The third mask pattern M30 may have a defined pattern structure. The third mask pattern M30 may be, for example, a photoresist pattern. The third mask pattern M30 may be removed after the patterning process.

[0167] Reference Figure 39a This can be achieved by removing the first insulating layer to the third insulating layer from the patterned laminate S11. Figure 39a NL10, NL20, and NL30 are used to form blank areas around the epitaxial plug pattern EP1 and the epitaxial channel pattern EC1. Due to the first insulating layer to the third insulating layer (… Figures 41a to 41c NL10, NL20, and NL30 can be made of the same material, so they can be easily removed using an etching method with etching selectivity.

[0168] Reference Figures 42a to 42c A gate insulating material layer GN1 can be formed on the surface of the epitaxial plug pattern EP1 and the epitaxial channel pattern EC1. According to one embodiment, the gate insulating material layer GN1 can be formed using a thermal oxidation process targeting the surface of the epitaxial plug pattern EP1 and the epitaxial channel pattern EC1. In this case, the gate insulating material layer GN1 can be an oxide layer. For example, the gate insulating material layer GN1 can be a silicon oxide layer.

[0169] However, the method for forming the gate insulating material layer GN1 and its constituent materials are not limited to those described above and can be varied in various ways. For example, the gate insulating material layer GN1 can also be formed using an atomic layer deposition (ALD) process. In this case, the gate insulating material layer GN1 can be formed to include at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material. The high-k material can be a material with a dielectric constant higher than that of silicon nitride.

[0170] Reference Figures 42a to 42c The structure S20, comprising the epitaxial plug pattern EP1, the epitaxial channel pattern EC1, the gate insulating material layer GN1, and the filling insulating layer NF1, can be formed by forming a filling insulating layer NF1 on the gate insulating material layer GN1 to fill the space surrounding the epitaxial plug pattern EP1 and the epitaxial channel pattern EC1 (i.e., the blank area). As a non-limiting example, the filling insulating layer NF1 may comprise silicon nitride (e.g., SiN). x ) or made of silicon nitride (ex, SiN) x The filling insulating layer NF1 can also be formed from materials other than silicon nitride. When forming the filling insulating layer NF1, after depositing the insulator for the filling insulating layer NF1, a planarization process can be further performed on its upper surface and surrounding area.

[0171] In this step, the structure S20 can include an epitaxial plug pattern EP1 extending in a vertical direction on the substrate (not shown), an epitaxial channel pattern EC1 extending in a horizontal direction from a side surface of the epitaxial plug pattern EP1, a gate insulating material layer GN1 formed at least on a surface portion of the epitaxial channel pattern EC1, and a filling insulating layer NF1 formed on the gate insulating material layer GN1 and filling a surrounding space of the epitaxial plug pattern EP1 and the epitaxial channel pattern EC1. The gate insulating material layer GN1 can be formed on the surface portion of the epitaxial plug pattern EP1 and the epitaxial channel pattern EC1. In the structure S20, the epitaxial plug pattern EP1 and the epitaxial channel pattern EC1 can have the same width.

[0172] As shown in the structure S20, the gate insulating material layer GN1 can be formed on the surface portion of the epitaxial plug pattern EP1 and the epitaxial channel pattern EC1. In the structure S20, the epitaxial plug pattern EP1 and the epitaxial channel pattern EC1 can have the same width. Figures 33a to 42c The setting method of the structure S20 can be varied in various ways. In other words, the process described with reference to Figures 43a to 43c the structure S20 can be deformed in various ways.

[0173] With reference to Figures 44a to 44c , a first vertical hole H10 exposing the epitaxial channel pattern EC1 can be formed in a region corresponding to the bit line preformation region of the structure S20. In other words, the epitaxial plug pattern EP1 can be removed and the first vertical hole H10 exposing the epitaxial channel pattern EC1 can be formed by etching the bit line preformation region in the structure S20. The first vertical hole H10 can be formed to penetrate the structure S20 in the up-down direction. The first vertical hole H10 can correspond to a region in which a bit line is to be formed later. The first vertical hole H10 can be formed in a region of the structure S20 in which a transistor is to be formed, i.e., a transistor formation region (transistor preformation region). A plurality of first vertical holes H10 can be formed spaced apart from each other in the Y-axis direction. For reference, the expression "corresponding" in the present specification can mean the same, but can encompass the concept of substantially the same or similar. This can be equally applied in the present specification.

[0174] To form the first vertical hole H10, a fourth mask pattern M40 can be used. The fourth mask pattern M40 can have a prescribed opening pattern. The fourth mask pattern M40 can be, for example, a photoresist pattern. After the first vertical hole H10 is formed, the fourth mask pattern M40 can be removed.

[0175] With reference to Figure 43a , the gate insulating material layer GN1 can be exposed by removing the filling insulating layer NF1 from a transistor formation region (transistor preformation region) around the first vertical hole H10 of the structure S20. In this case, a mask pattern (not shown) exposing the transistor formation region can be provided on the structure S20, and the filling insulating layer NF1 in the transistor formation region can be etched and removed using the mask pattern as an etching mask. Then, the mask pattern can be removed. The mask pattern can be, for example, a photoresist pattern.Figures 45a to 54b The remaining portion of the fourth mask pattern M40, or the newly deposited hard mask pattern.

[0176] Then, it can be used Figure 54a The illustrated method forms word lines surrounding the exposed gate insulating material layer GN1 portion in the transistor formation region. Figure 45a The WL1 is used to define the transistor that includes the word line.

[0177] Reference Figure 45b and Figure 45a A word line material layer WM1 can be formed around the exposed gate insulating material layer GN1 portion in the transistor formation region. The word line material layer WM1 can be formed substantially conformally along the shape of the exposed surface region in the transistor formation region. The word line material layer WM1 can be formed, for example, by an atomic layer deposition process. In this case, such as... Figure 45b As shown, the gap along the Z-axis between the lower and upper epitaxial channel patterns EC1 can be greater than approximately twice the thickness of the word line material layer WM1. Furthermore, the gap along the Z-axis between the lower and upper gate insulating material layers GN1 can be greater than approximately twice the thickness of the word line material layer WM1. On the other hand, as... Figure 46a As shown, the gap along the Y-axis between two epitaxial channel patterns EC1 separated along the Y-axis can be less than approximately twice the thickness of the word line material layer WM1. Furthermore, the gap along the Y-axis between two gate insulating material layers GN1 separated along the Y-axis can be less than approximately twice the thickness of the word line material layer WM1.

[0178] The word line material layer WM1 can be formed as a pattern EC1 surrounding each epitaxial channel in the transistor formation region. Furthermore, the word line material layer WM1 can have a line shape extending along the Y-axis direction.

[0179] Reference Figure 46b and Figure 47a This can form a gap-fill insulation layer NG1, which fills the blank space in the bend (bend) of the filler word line material layer WM1. The gap-fill insulation layer NG1 can be formed of insulating oxide or other insulating materials.

[0180] Reference Figure 47b and Figure 43a The letter lines can be etched using material layer WM1 with the first vertical hole ( Figure 48aThe via H15 is formed in the area corresponding to H10. The via H15 can be a vertical hole. To form the via H15, a fifth mask pattern M50 can be used. The fifth mask pattern M50 can have a defined opening pattern. The fifth mask pattern M50 can be, for example, a photoresist pattern. After forming the via H15, the fifth mask pattern M50 can be removed.

[0181] Reference Figure 48b and Figure 49a This allows a portion of the word line material layer WM1 exposed through the through-hole H15 to be recessed, causing one end of the epitaxial channel pattern EC1 to protrude further toward the through-hole H15 than the word line material layer WM1. Therefore, a portion of the word line material layer WM1 can be etched around the through-hole H15, and multiple etched areas (multiple recessed areas) can be connected along the Y-axis.

[0182] Reference Figure 49b and Figure 50a A body insulating layer BN1 can be formed to fill the through-hole H15 and the surrounding plurality of etched areas (plural recessed areas). The body insulating layer BN1 can be formed of an insulating oxide or of other insulating materials. The body insulating layer BN1 can be formed of the same material as the gap-filling insulating layer NG1, or it can be formed of other materials.

[0183] Reference Figure 50b and Figure 43a It can be connected to the first vertical hole of the body insulating layer BN1 ( Figure 51a A second vertical aperture H20 is formed in the region corresponding to H10. To form the second vertical aperture H20, a sixth mask pattern M60 can be used. The sixth mask pattern M60 can have a defined opening pattern. The sixth mask pattern M60 can, for example, be a photoresist pattern. After forming the second vertical aperture H20, the sixth mask pattern M60 can be removed.

[0184] Reference Figure 51b and Figure 43a Bit line BL1 can be formed within the second vertical hole H20. Bit line BL1 can be connected to (contact with) one end of the epitaxial channel pattern EC1. Therefore, bit line BL1 can be formed to connect to (contact with) the transistor formation region and the first vertical hole ( Figure 52a One end of the epitaxial channel pattern EC1 in the region corresponding to H10. The bit line BL1 may have a columnar shape that extends vertically through the structure S20. The bit line BL1 may be electrically connected to one end of the epitaxial channel pattern EC1 in the lateral direction. Multiple bit lines BL1 may be formed that are connected to multiple epitaxial channel patterns EC1.

[0185] Although not shown, if there is a conductive material of the bit line BL1 deposited on the upper side of the second vertical hole H20, it can be removed by, for example, an etchback process.

[0186] Referring to Figure 52b and Figure 36a , a third etching portion T30 can be formed in the capacitor formation region of the structure S20, which is separated from the bit line BL1. The third etching portion T30 can have a trench shape. Therefore, the third etching portion T30 can be referred to as a third trench. The third etching portion T30 can be formed to be through-filling the insulating layer NF1, and can have a shape extending in the Y-axis direction. The third etching portion T30 can have a line pattern shape. The third etching portion T30 can be formed in a region corresponding to the second etching portion (T20) of the structure S20. Figure 53a

[0187] According to an embodiment, the third etching portion T30 can be formed by etching a portion of the filling insulating layer NF1 and a portion of the gate insulating material layer GN1. The end portion of the gate insulating material layer GN1 and the end portion of the epitaxial channel pattern EC1 can be exposed toward the third etching portion T30 side.

[0188] In order to form the third etching portion T30, a seventh mask pattern M70 can be used. The seventh mask pattern M70 can have a prescribed opening region. The seventh mask pattern M70 can be, for example, a photoresist pattern.

[0189] Referring to ​ and Figure 53b , a first recessed portion R1 exposing the gate insulating material layer GN1 and the material layer WM1 for word line can be formed by removing (etching) the filling insulating layer (NF1) exposed by the third etching portion T30 from the capacitor formation region. Figure 52a

[0190] Referring to Figure 54a and Figure 54b , after the first recessed portion R1 is formed in the capacitor formation region, a portion of the material layer (WM1) for word line exposed by the first recessed portion R1 can be recessed. In other words, a portion of the material layer (WM1) for word line exposed toward the capacitor formation region side can be recessed. As a result, the material layer portion for word line surrounding the lower epitaxial channel pattern EC1 and the material layer portion for word line surrounding the upper epitaxial channel pattern EC1 can be separated from each other. Among them, the separated material layer portion for word line can be referred to as a word line WL1. Then, the seventh mask pattern M70 can be removed. However, the removal timing point of the seventh mask pattern M70 can vary. Figure 53a Figure 53a

[0191] ​​​​The word line WL1 can have a structure surrounding the gate insulating material layer GN1. Thus, a transistor including the word line WL1 can have a gate-all-around (GAA) structure. Due to this, the transistor can have excellent gate control and high on-current characteristics.

[0192] Although reference is made to Figures 45a to 54b The method of forming the word line WL1 and the like is specifically described, but this is merely exemplary, and the method of forming the word line WL1 and the like can be changed in various ways according to the situation.

[0193] Reference is made to Figure 55a and Figure 55b After the first recessed portion R1 is formed in the capacitor formation region, an insertion insulating layer NN1 can be formed so as to surround the exposed gate insulating material layer GN1 portion in the capacitor formation region. The insertion insulating layer NN1 can be formed conformally on the surface region exposed to the first recessed portion R1. The insertion insulating layer NN1 can be formed so as to cover the surfaces of the gate insulating material layer GN1, the epitaxial channel pattern EC1, and the word line WL1, and the like exposed to the capacitor formation region. The insertion insulating layer NN1 can be formed, for example, by an atomic layer deposition process. The thickness of the insertion insulating layer NN1 can be as thin as several tens of nm or less. The insertion insulating layer NN1 can be formed of an insulating oxide or of another insulating material.

[0194] Reference is made to Figure 56a and Figure 56b A mold insulating layer MN1 can be formed so as to fill the first recessed portion R1. The mold insulating layer MN1 can be formed on the insertion insulating layer NN1 so as to fill the first recessed portion R1 and the third etched portion T30. The mold insulating layer MN1 can contain, for example, silicon nitride (ex, SiN x ) or be formed of silicon nitride (ex, SiN x ). When the mold insulating layer MN1 is formed, after the deposition of the mold insulating layer MN1 with an insulator, a planarization process is further performed on the upper surface and the surrounding region thereof.

[0195] Reference is made to Figure 57a and Figure 57b A fourth etched portion T40 can be formed in a region of the mold insulating layer MN1 corresponding to the T30 of the third etched portion Figure 52a . The fourth etched portion T40 can be formed by etching a portion of the mold insulating layer MN1 and a portion of the insertion insulating layer NN1. Thus, the end portion of the gate insulating material layer GN1 and the end portion of the epitaxial channel pattern EC1 can be exposed toward the fourth etched portion T40 side. The fourth etched portion T40 can have a linear shape extending in the Y-axis direction. The fourth etched portion T40 can be referred to as a fourth trench.

[0196] To form the fourth etching portion T40, an eighth mask pattern M80 can be used. The eighth mask pattern M80 can have a prescribed opening region. The eighth mask pattern M80 can be, for example, a photoresist pattern. After the fourth etching portion T40 is formed, the eighth mask pattern M80 can be removed.

[0197] Referring to Figure 58a and Figure 58b The second recessed portion R2 can be formed by etching the epitaxial channel pattern EC1, the gate insulating material layer GN1, and the intervening insulating layer NN1 exposed by the fourth etching portion T40. The epitaxial channel pattern EC1, the gate insulating material layer GN1, and the intervening insulating layer NN1 can be etched by introducing a prescribed wet etchant, i.e., a wet etching solution, through the fourth etching portion T40. In this case, one or more wet etchants can be used. The second recessed portion R2 can be formed to a region slightly spaced apart from the word line WL1. The etching range of the epitaxial channel pattern EC1, the gate insulating material layer GN1, and the intervening insulating layer NN1 can be controlled by adjusting the conditions of the etching process.

[0198] When the intervening insulating layer NN1 is formed first in the step of Figure 55a and then removed in the step of Figure 58a , the second recessed portion R2 can be formed to have a width greater than the remaining gate insulating material layer GN1. Thus, the width of the second recessed portion R2 in the Z-axis direction can be greater than the width of the remaining gate insulating material layer GN1 in the Z-axis direction. Also, the width of the second recessed portion R2 in the Y-axis direction can be greater than the width of the remaining gate insulating material layer GN1 in the Y-axis direction. Ultimately, in subsequent processes, the process margin for forming the capacitor can increase. To ensure the process margin and the like, it can be preferable to form the intervening insulating layer NN1. However, the formation of the intervening insulating layer NN1 can be optional and can be omitted, as appropriate.

[0199] On the other hand, in the step of Figure 58a , the epitaxial channel pattern EC1 can be etched and removed in the capacitor formation region using a wet etching process, and thus such wet etching can hardly cause etching damage to the epitaxial channel pattern EC1.

[0200] Referring to Figure 59a and Figure 59b , the second recessed portion (R2) can be formed to have a prescribed width in the Y-axis direction. Figure 58aThe inner side surface of the electrode member EL1 of R2) forms an electrode part EL1 connected to the other end of the epitaxial channel pattern EC1. The electrode part EL1 can be connected to the other end of the epitaxial channel pattern EC1 of the transistor. The electrode part EL1 can be referred to as a capacitor electrode layer (first electrode layer). The electrode part EL1 can be formed conformally along the surface shape of the mold insulating layer MN1. The electrode part EL1 can be formed by, for example, an atomic layer deposition process.

[0201] Referring to Figure 60a and Figure 60b , a fifth etching part T50 can be formed in a region corresponding to the fourth etching part (T40) in the capacitor formation region. The fifth etching part T50 can be formed by etching a part of the electrode member EL1. The fifth etching part T50 can have a linear shape extending in the Y-axis direction. The fifth etching part T50 can be referred to as a fifth trench. Through the process of this step, the electrode member EL1 can be separated into individual capacitor regions. In other words, the electrode member EL1 can be separated into unit cell regions. Figure 57a

[0202] To form the fifth etching part T50, a ninth mask pattern M90 can be used. The ninth mask pattern M90 can have a prescribed opening region. The ninth mask pattern M90 can be, for example, a photoresist pattern. After the fifth etching part T50 is formed, the ninth mask pattern M90 can be removed.

[0203] Referring to Figure 61a and Figure 61b , after the electrode member EL1 is formed, the outer side surface of the electrode member EL1 can be exposed by etching the mold insulating layer (MN1) of R1). In this step, the interposed insulating layer NN1 can be exposed by removing the entire mold insulating layer (MN1) of R1). However, as necessary, the etching range of the mold insulating layer (MN1) of R1) can be adjusted as appropriate. As a method of adjusting the etching range, at least a part of the ninth mask pattern (M90) of R3) can be temporarily left, or a separate hard mask (not shown) or the like can be used. As necessary, a part of the mold insulating layer (MN1) of R1) adjacent to the interposed insulating layer NN1 can also be left without being etched. Figure 60a Figure 60a Figure 60a Figure 60a Figure 60a

[0204] Referring to Figure 62a and Figure 62b ​​​​​​A dielectric layer DL1 can be formed on the electrode part EL1 in the capacitor formation region. The dielectric layer DL1 can be a capacitor dielectric layer. The dielectric layer DL1 can be formed conformally along the surface shape of the electrode part EL1. The dielectric layer DL1 can be formed (deposited) by, for example, an atomic layer deposition process. The dielectric layer DL1 can be formed to contain at least one of a plurality of dielectric materials. For example, the dielectric layer DL1 can contain a high-k material having a dielectric constant higher than that of silicon nitride. The specific material of the dielectric layer DL1 can vary in various ways.

[0205] Referring to Figure 63a and Figure 63b A plate electrode PL1 can be formed on the dielectric layer DL1 in the capacitor formation region. The plate electrode PL1 can be referred to as a capacitor electrode layer (second electrode layer). The plate electrode PL1 can be formed to fill the space between the fifth etching part (T50) and the electrode part EL1 and the inside of the electrode part EL1. The plate electrode PL1 can be formed to contain one or more of a plurality of electrode materials used in a semiconductor device process. The plate electrode PL1 can have one line shape. Thus, the plate electrode PL1 can be referred to as a plate electrode line. The electrode part EL1, the dielectric layer DL1, and the plate electrode PL1 can constitute a capacitor. Figure 60a

[0206] Figures 59a to 63b The method of forming the capacitor is exemplarily shown and explained in the above, but the method of forming the capacitor and the specific structure of the capacitor can vary in various ways depending on the situation.

[0207] In Figure 63a the device structure, the lower epitaxial channel pattern EC1, the word line WL1 surrounding it, and the gate insulating material layer GN1 therebetween, etc. can be regarded as constituting a first transistor TR1. Also, the lower electrode part EL1 electrically connected to the first transistor TR1 along the side of the first transistor TR1, and the dielectric layer DL1 and the plate electrode PL1 in contact therewith can be regarded as constituting a first capacitor CP1. Also, the first transistor TR1 and the first capacitor CP1 can be regarded as constituting one memory cell (lower memory cell). The first transistor TR1 and the first capacitor CP1 can be arranged in the horizontal direction.

[0208] ​And, the upper epitaxial channel pattern EC1, the word line WL1 surrounding it, and the gate insulating material layer GN1 therebetween, etc. can be regarded as constituting the second transistor TR2. And, the upper electrode member EL1 electrically connected to the second transistor TR2 along the side of the second transistor TR2 and the dielectric layer DL1 and the plate electrode PL1 in contact therewith can be regarded as constituting the second capacitor CP2. And, the second transistor TR2 and the second capacitor CP2 can be regarded as constituting one memory cell (upper memory cell). The second transistor TR2 and the second capacitor CP2 can be arranged in the horizontal direction. The second transistor TR2 can be provided on the first transistor TR1, and the second capacitor CP2 can be provided on the first capacitor CP1.

[0209] Although not shown, as Figure 63a and Figure 63b described above, the device structure can be repeatedly provided in the Z-axis direction, can be repeatedly provided in the X-axis direction, or can be repeatedly provided in the Y-axis direction. According to this embodiment of the present application, a memory device having a greatly improved integration degree while having excellent performance and operating characteristics can be realized. The memory device can be a stacked memory device of a gate-all-around (GAA) type having a horizontal arrangement and a stacked structure. And, the memory device of an embodiment of the present application can be a vertical dynamic random access memory (DRAM) device or a three-dimensional dynamic random access memory (DRAM) device.

[0210] Hereinafter, the memory device of an embodiment of the present application will be further described with reference to Figure 63a and Figure 63b .

[0211] With reference to Figure 63a and Figure 63b , the memory device of an embodiment of the present application can include a plurality of memory cells stacked in the vertical direction. The plurality of memory cells can each include a transistor and a capacitor electrically connected to the transistor along the side of the transistor. The transistor can correspond to TR1 and TR2, and the capacitor can correspond to CP1 and CP2. The transistor can include an epitaxial channel pattern EC1, a word line WL1 surrounding it, and a gate insulating layer GN1 provided therebetween. The capacitor can include an electrode member EL1 electrically connected to the transistor, a dielectric layer DL1 provided on the surface of the electrode member EL1, and a plate electrode PL1 provided on the surface of the dielectric layer DL1.

[0212] Further, the memory device can include a bit line BL1 connected to the plurality of transistors of the plurality of memory cells. The bit line BL1 can extend in a vertical direction. A bulk insulating layer BN1 can be provided between the bit line BL1 and the word line WL1, the bulk insulating layer BN1 surrounding at least a portion of an outer side surface of the bit line BL1. A gap filling insulating layer NG1 can be provided between two adjacent word lines WL1 of the plurality of transistors, the gap filling insulating layer NG1 being a material layer separate from the bulk insulating layer BN1.

[0213] The epitaxial channel pattern EC1 can include a single crystal semiconductor. For example, the epitaxial channel pattern EC1 can include one of single crystal silicon (Si), single crystal germanium (Ge), and single crystal silicon germanium (SiGe). The transistor including the epitaxial channel pattern EC1 can have excellent performance. The epitaxial channel pattern EC1 can be referred to as an epitaxial channel material layer.

[0214] The bulk insulating layer BN1 can have a structure in which a plurality of annular-shaped unit bodies are connected in a row when viewed from above (see FIG. 1A). Figure 63b The plurality of annular-shaped unit bodies can each have an inner portion in which the bit line BL1 is provided. The plurality of annular-shaped unit bodies can each have an annular cross-sectional structure. For example, the plurality of annular-shaped unit bodies can each have an annular or substantially annular cross-sectional structure. Further, the bulk insulating layer BN1 can have a shape extending in the same direction as the word line WL1 when viewed from above. The plurality of bit lines BL1 can be provided to be spaced apart from each other in a horizontal direction within the bulk insulating layer BN1, i.e., in the horizontal direction in which the word line WL1 extends.

[0215] In an embodiment of the present application, the transistor can have a gate-all-around (GAA) structure. Thereby, the transistor and the memory device including the same can have excellent characteristics.

[0216] Further, the memory device can further include an insertion insulating layer NN1 extending in a manner surrounding a portion (end portion) of the gate insulating layer GN1 adjacent to the electrode member EL1 and covering a side surface of the word line WL1. The insertion insulating layer NN1 can be a material layer separate from the bulk insulating layer BN1 and the gap filling insulating layer NG1. The insertion insulating layer NN1 can be, for example, an atomic layer deposition (ALD) material layer.

[0217] According to an embodiment, the bulk insulating layer BN1 can be in contact with a first side surface (first end portion) of the gap filling insulating layer NG1, and the insertion insulating layer NN1 can be in contact with a second side surface (second end portion) of the gap filling insulating layer NG1. A portion of the insertion insulating layer NN1 can be in contact with the electrode member EL1.

[0218] Also, according to an embodiment, a side surface of the interposed insulating layer NN1 can be in contact with a side surface of the dielectric layer DL1. The word line WL1 can be in contact with a first side surface of the interposed insulating layer NN1, and the dielectric layer DL1 can be in contact with a second side surface of the interposed insulating layer NN1. However, it is not limited to this result, and can be modified.

[0219] The memory device of an embodiment of the present application can have structural features as shown in Figure 63a and Figure 63b For example, the memory device can have a stacked structure including an epitaxial channel pattern EC1, and have structural features of a bulk insulating layer BN1, a gap fill insulating layer NG1, an interposed insulating layer NN1, and their peripheral portions, and a transistor and a capacitor.

[0220] According to the above-described embodiments of the present application, a memory device (stacked memory device) and a manufacturing method thereof can be implemented, in which integration can be improved, excellent performance can be ensured, a process can be simple, and manufacturing costs can be reduced. Also, according to the embodiments of the present application, a memory device (stacked memory device) and a manufacturing method thereof can be implemented, in which by using a single-crystal channel material, performance such as mobility can be improved, uniformity of a channel thickness can be improved, and on-current characteristics can be improved. In particular, according to an embodiment of the present application, by using a stack of an insulating layer and a sacrificial layer, an epitaxial channel layer is formed by a selective epitaxial growth (SEG) method, so that compared to a conventional method using a silicon (Si) / silicon germanium (SiGe) stack structure, process difficulty can be reduced, manufacturing costs can be reduced, and a memory device with improved performance can be manufactured. In the embodiments of the present application, since a selective epitaxial process for a single material is used, compared to a conventional method in which an epitaxial process is repeatedly performed for a plurality of materials (ex, Si and SiGe), a process can be greatly simplified.

[0221] According to an embodiment, when manufacturing a memory device, after forming a stack of an insulating layer and a sacrificial layer, an epitaxial material plug is formed by selective epitaxial growth (SEG) through a trench-shaped etching portion, and an epitaxial channel material layer is formed from the epitaxial material plug by selective epitaxial growth in a space where the sacrificial layer has been removed, and then cell patterning is performed, and a process of forming a word line and a capacitor can be performed. In this case, it is possible to advantageously reduce process difficulty and manufacture a stacked memory device with excellent performance. In particular, when an epitaxial material plug is formed by selective epitaxial growth through a trench-shaped etching portion, it is possible to reduce epitaxial process difficulty compared to the case of epitaxial growth through a narrow hole.

[0222] According to an example, the memory device of the embodiment of the present application can include a horizontal stacked dynamic random access memory device (DRAM). However, at least a part of the device structure and the manufacturing method of the embodiment of the present application can also be applied to the technical field of a dynamic random access memory device (DRAM) and other memory devices (for example, (phase change memory) (PRAM), (resistive random access memory) (RRAM), (static random access memory) (SRAM), flash memory, (magnetic random access memory) (MRAM), (ferroelectric random access memory) (FRAM), etc.) or a logic device integrated with a logic circuit, etc.

[0223] In the present specification, preferred embodiments of the present application are disclosed, although specific terms are used, which are only general meanings for facilitating explanation of technical contents of the present application and helping understanding of the application, and do not limit the scope of the present application. In addition to the embodiments disclosed herein, other modifications based on the technical idea of the present application can be implemented, which is obvious to those skilled in the art to which the present application pertains. Those skilled in the art to which the present application pertains can understand that the memory device and the manufacturing method thereof explained with reference to the embodiments can be replaced, changed, and modified in various ways without departing from the scope of the technical idea of the present application. Figures 1a to 32b and Figures 33a to 63b The memory device and the manufacturing method thereof explained with reference to the embodiments can be replaced, changed, and modified in various ways without departing from the scope of the technical idea of the present application. Therefore, the scope of the application should not be defined by the embodiments, but by the technical idea recited in the scope of the claims.

[0224] Industrial applicability

[0225] Embodiments of the present application can be applied to semiconductor / electronic devices and manufacturing methods thereof. For example, embodiments of the present application can be applied to memory devices and manufacturing methods thereof.

Claims

1. A method of manufacturing a memory device, characterized by, comprises the following steps: forming a laminate including a first insulating layer, a first sacrificial layer, and a second insulating layer, which are sequentially layered on a substrate; forming a patterned laminate having at least one pattern portion having a first sacrificial layer pattern obtained from the first sacrificial layer by patterning the laminate, the pattern portion having a form extending in a first direction, blank spaces being provided on both sides of the pattern portion in a second direction perpendicular to the first direction; forming a structure including the patterned laminate and an insulating material by filling the insulating material in the blank spaces on both sides of the at least one pattern portion; forming a first vertical hole penetrating the first sacrificial layer pattern of the pattern portion in the structure; forming an epitaxial material plug filling the first vertical hole from the substrate by an epitaxial growth method; forming a first etching portion separated from the epitaxial material plug in the structure; forming a horizontal hole extending in the first direction by removing the first sacrificial layer pattern exposed by the first etching portion; forming an epitaxial channel material layer filling the horizontal hole from a side surface of the epitaxial material plug by an epitaxial growth method; forming a blank region around the epitaxial material plug and the epitaxial channel material layer by removing the first insulating layer, the second insulating layer, and the insulating material from the structure; forming a gate insulating material layer on a surface portion of the epitaxial material plug and the epitaxial channel material layer; forming a filling insulating layer filling the blank region on the gate insulating material layer; forming a second vertical hole in a region corresponding to the first vertical hole in the structure in which the gate insulating material layer and the filling insulating layer are formed; exposing the gate insulating material layer by removing the filling insulating layer from a transistor formation region around the second vertical hole of the structure; defining a transistor including a word line by forming the word line around a portion of the exposed gate insulating material layer in the transistor formation region; forming a bit line connected to one end of the epitaxial channel material layer in the transistor formation region in a region corresponding to the second vertical hole; and removing the epitaxial channel material layer and the gate insulating material layer from a capacitor formation region adjacent to the transistor formation region of the structure to form a capacitor connected to the other end of the epitaxial channel material layer of the transistor.

2. The method of manufacturing a memory device according to claim 1, wherein the first insulating layer, the second insulating layer, and the insulating material contain silicon nitride, the first sacrificial layer contains silicon oxide. the epitaxial material plug and the epitaxial channel material layer contain a single-crystal semiconductor.

3. The method of manufacturing a memory device according to claim 1, wherein, the epitaxial material plug and the epitaxial channel material layer contain one of a single-crystal silicon, a single-crystal germanium, and a single-crystal silicon germanium.

4. The method of manufacturing a memory device according to claim 3, wherein, the step of defining the transistor by forming the word line includes the following steps:

5. The method of manufacturing a memory device according to claim 1, wherein, forming a word line material layer around the portion of the exposed gate insulating material layer in the transistor formation region; ​ forming a through-hole by etching a region of the word line material layer corresponding to the second vertical hole; recessing a portion of the word line material layer exposed through the through-hole so that the one end of the epitaxial channel material layer protrudes more to the through-hole side than the word line material layer; and forming a bulk insulating layer filling the through-hole.

6. The method of manufacturing a memory device according to claim 5, wherein, Further comprising the steps of: forming a first recessed portion exposing the word line material layer by removing the filling insulating layer from the capacitor formation region; and recessing a portion of the word line material layer exposed by the first recessed portion.

7. The method of manufacturing a memory device according to claim 5, wherein, The step of forming the bit line includes the steps of: forming a third vertical hole in a region corresponding to the second vertical hole of the bulk insulating layer; and forming the bit line in the third vertical hole.

8. The method of manufacturing a memory device according to claim 1, wherein, Further comprising the steps of: forming a second etching portion spaced apart from the bit line in the capacitor formation region; and forming a first recessed portion exposing the gate insulating material layer by removing the filling insulating layer exposed by the second etching portion from the capacitor formation region.

9. The method of manufacturing a memory device according to claim 8, wherein, Further comprising the steps of: forming an interposed insulating layer surrounding the exposed portion of the gate insulating material layer in the capacitor formation region; forming a mold insulating layer filling the first recessed portion and the second etching portion on the interposed insulating layer; forming a third etching portion in the mold insulating layer in a region corresponding to the second etching portion; and etching the epitaxial channel material layer, the gate insulating material layer, and the interposed insulating layer exposed by the third etching portion to form a second recessed portion. The step of forming the capacitor includes the steps of:

10. The method of manufacturing a memory device according to claim 9, wherein, forming an electrode member connected to the other end of the epitaxial channel material layer on an inner side of the second recessed portion; forming a dielectric layer on the electrode member; and forming a plate electrode on the dielectric layer.

11. The manufacturing method of a memory device according to claim 10, further comprising the step of: forming an outer side surface of the electrode member by etching the mold insulating layer after the electrode member is formed, the dielectric layer and the plate electrode are formed in this order after the mold insulating layer is etched.

12. The manufacturing method of a memory device according to claim 1, wherein: the laminate further includes a second sacrificial layer and a third insulating layer laminated in this order on the second insulating layer, the laminate has a structure symmetric with respect to the second insulating layer. the thickness of the second insulating layer is greater than the thickness of each of the first insulating layer, the third insulating layer, the first sacrificial layer, and the second sacrificial layer.

13. The method of manufacturing a memory device according to claim 12, wherein, 14. The manufacturing method of a memory device according to claim 12, wherein: the transistor is a first transistor, the capacitor is a first capacitor, the memory device is formed to further include a second transistor provided on the first transistor and a second capacitor provided on the first capacitor. comprising the steps of:

15. A method of manufacturing a memory device, characterized by, ​ forming a structure including an epitaxial-material plug extending in a vertical direction on a substrate, an epitaxial-channel-material layer extending in a horizontal direction from a side surface of the epitaxial-material plug, a gate-insulating-material layer formed at least on a surface portion of the epitaxial-channel-material layer, and a filled-insulating layer formed on the gate-insulating-material layer and filling a surrounding space of the epitaxial-material plug and the epitaxial-channel-material layer; forming a vertical hole, hereinafter referred to as a second vertical hole, by removing the epitaxial-material plug from the structure; exposing the gate-insulating-material layer by removing the filled-insulating layer from a transistor formation region around the second vertical hole of the structure; defining a transistor including a word line by forming the word line around a portion of the gate-insulating-material layer exposed in the transistor formation region; forming a bit line connected to one end of the epitaxial-channel-material layer in a region corresponding to the second vertical hole in the transistor formation region; and removing the epitaxial-channel-material layer and the gate-insulating-material layer from a capacitor formation region adjacent to the transistor formation region of the structure to form a capacitor connected to the other end of the epitaxial-channel-material layer of the transistor. including the steps of:

16. A method of manufacturing a memory device, characterized by, forming a stack including a first insulating layer, a first sacrificial layer, and a second insulating layer sequentially stacked on a substrate; forming a first etched portion penetrating a region including at least one bit line pre-formation region in the stack; forming an epitaxial-material plug filling the first etched portion from the substrate using an epitaxial growth method; forming a second etched portion separated from the epitaxial-material plug in the stack; forming a horizontal space portion by removing the first sacrificial layer exposed by the second etched portion; forming an epitaxial-channel-material layer filling the horizontal space portion from a side surface of the epitaxial-material plug using an epitaxial growth method; forming a patterned stack having at least one pattern portion having an epitaxial-channel pattern obtained from the epitaxial-channel-material layer and an epitaxial-plug pattern obtained from the epitaxial-material plug by patterning the stack formed with the epitaxial-channel-material layer; removing the first insulating layer and the second insulating layer from the patterned stack; forming a gate-insulating-material layer on surface portions of the epitaxial-plug pattern and the epitaxial-channel pattern; forming a structure including the epitaxial-plug pattern, the epitaxial-channel pattern, the gate-insulating-material layer, and a filled-insulating layer by filling a surrounding space of the epitaxial-plug pattern and the epitaxial-channel pattern with the filled-insulating layer on the gate-insulating-material layer; forming a first vertical hole exposing the epitaxial-channel pattern in a region corresponding to the bit line pre-formation region of the structure; exposing the gate-insulating-material layer by removing the filled-insulating layer from a transistor formation region around the first vertical hole of the structure; defining a transistor including a word line by forming the word line around a portion of the gate-insulating-material layer exposed in the transistor formation region; ​ In the transistor formation region, a bit line connected to one end of the epitaxial channel pattern is formed in a region corresponding to the first vertical hole; and From a capacitor formation region adjacent to the transistor formation region of the structure, the epitaxial channel pattern and the gate insulating material layer are removed to form a capacitor connected to the other end of the epitaxial channel pattern of the transistor.

17. The manufacturing method of a memory device according to claim 16, wherein the first insulating layer and the second insulating layer include silicon nitride, the first sacrificial layer includes silicon oxide.

18. The method of manufacturing a memory device according to claim 16, wherein, The first etching portion has a trench shape that penetrates through a plurality of the bit line pre-formation regions.

19. The method of manufacturing a memory device according to claim 16, wherein, The epitaxial material plug and the epitaxial channel material layer include a single-crystal semiconductor.

20. The method of manufacturing a memory device according to claim 19, wherein, The epitaxial material plug and the epitaxial channel material layer include one of single-crystal silicon, single-crystal germanium, and single-crystal silicon germanium.

21. The method of manufacturing a memory device according to claim 16, wherein, The step of defining the transistor by forming the word line includes the steps of: forming a word line material layer surrounding the exposed portion of the gate insulating material layer in the transistor formation region; forming a through hole by etching a region of the word line material layer corresponding to the first vertical hole; recessing a portion of the word line material layer exposed through the through hole so that the one end of the epitaxial channel pattern protrudes more to the through hole side than the word line material layer; and and forming a bulk insulating layer filling the through hole.

22. The method of manufacturing a memory device according to claim 21, wherein, Further including the steps of: forming a first recessed portion exposing the word line material layer by removing the filling insulating layer from the capacitor formation region; and recessing a portion of the word line material layer exposed by the first recessed portion.

23. The method of manufacturing a memory device according to claim 21, wherein, The step of forming the bit line includes the steps of: forming a second vertical hole in a region corresponding to the first vertical hole of the bulk insulating layer; and forming the bit line in the second vertical hole.

24. The method of manufacturing a memory device according to claim 16, wherein, After the step of forming the bit line, further including the steps of: forming a third etching portion in the capacitor formation region separated from the bit line; and forming a first recessed portion exposing the gate insulating material layer by removing the filling insulating layer exposed by the third etching portion from the capacitor formation region.

25. The method of manufacturing a memory device according to claim 24, wherein, After the step of forming the first recessed portion in the capacitor formation region, further including the steps of: forming an interposed insulating layer surrounding the exposed portion of the gate insulating material layer in the capacitor formation region; forming a mold insulating layer filling the first recessed portion and the third etching portion on the interposed insulating layer; forming a fourth etching portion in a region of the mold insulating layer corresponding to the third etching portion; and and etching the epitaxial channel pattern, the gate insulating material layer, and the interposed insulating layer exposed by the fourth etching portion to form a second recessed portion.

26. The method of manufacturing a memory device according to claim 25, wherein, The step of forming the capacitor includes the steps of: forming an electrode member connected to the other end of the epitaxial channel pattern on an inner side of the second recessed portion; forming a dielectric layer on the electrode member; and forming a plate electrode on the dielectric layer.

27. The method according to claim 26, wherein the method further comprises a step of exposing an outer side surface of the electrode member by etching the mold insulating layer after the electrode member is formed, the dielectric layer and the plate electrode are formed in this order after the mold insulating layer is etched.

28. The method according to claim 16, wherein the laminate further comprises a second sacrificial layer and a third insulating layer which are laminated in this order on the second insulating layer, the laminate has a structure which is symmetric with respect to the second insulating layer in the up-down direction.

29. The method of manufacturing a memory device according to claim 28, wherein, the second insulating layer has a thickness which is greater than each of the thicknesses of the first insulating layer, the third insulating layer, the first sacrificial layer, and the second sacrificial layer.

30. The method according to claim 28, wherein the transistor is a first transistor, the capacitor is a first capacitor, the memory device is formed to further include a second transistor provided on the first transistor and a second capacitor provided on the first capacitor.

31. A method of manufacturing a memory device, comprising: comprises the steps of: forming a structure including an epitaxial plug pattern extending in a vertical direction on a substrate, an epitaxial trench pattern extending in a horizontal direction from a side surface of the epitaxial plug pattern, a gate insulating material layer formed at least on a surface portion of the epitaxial trench pattern, and a filling insulating layer formed on the gate insulating material layer and filling a surrounding space of the epitaxial plug pattern and the epitaxial trench pattern; removing the epitaxial plug pattern by etching a bit line preformation region in the structure to form a first vertical hole exposing the epitaxial trench pattern; exposing the gate insulating material layer by removing the filling insulating layer from a transistor formation region around the first vertical hole of the structure; defining a transistor including a word line by forming the word line around a portion of the gate insulating material layer exposed in the transistor formation region; in the transistor formation region, forming a bit line connected to one end of the epitaxial trench pattern in a region corresponding to the first vertical hole; and from a capacitor formation region adjacent to the transistor formation region of the structure, removing the epitaxial trench pattern and the gate insulating material layer to form a capacitor connected to the other end of the epitaxial trench pattern of the transistor. In the structure, the epitaxial plug pattern and the epitaxial trench pattern have the same width.

32. The method of manufacturing a memory device according to claim 31, wherein, 33. A memory device, comprising: a plurality of memory cells laminated in a vertical direction, the plurality of memory cells each including a transistor and a capacitor electrically connected to the transistor in a side direction of the transistor, the transistor including an epitaxial channel material layer, a word line surrounding the epitaxial channel material layer, and a gate insulating layer provided between the epitaxial channel material layer and the word line, the capacitor including an electrode member electrically connected to the transistor, a dielectric layer provided on a surface of the electrode member, and a plate electrode provided on a surface of the dielectric layer, ​ a plurality of transistors connected to the plurality of memory cells and extending in a vertical direction, the transistors have a ring gate structure.

34. The memory device of claim 33, wherein, the epitaxial channel material layer includes one of single crystal silicon, single crystal germanium, and single crystal silicon germanium.

35. The memory device of claim 33, wherein a body insulating layer is provided, the body insulating layer surrounding at least a portion of an outer side surface of the bit line between the bit line and the word line, a gap filling insulating layer is provided between two adjacent word lines of the plurality of transistors, the gap filling insulating layer being a material layer separate from the body insulating layer.

36. The memory device of claim 35, wherein when viewed from above, the body insulating layer has a structure in which a plurality of ring-shaped unit bodies are connected in a row, the bit line is provided inside each of the plurality of ring-shaped unit bodies.

37. The memory device of claim 35, further comprising an interposed insulating layer, the interposed insulating layer extending in a manner surrounding a portion of the gate insulating layer adjacent to the electrode member and covering a side surface of the word line, the interposed insulating layer being a material layer separate from the body insulating layer and the gap filling insulating layer.

38. The memory device of claim 37, wherein the body insulating layer is in contact with a first side surface of the gap filling insulating layer, the interposed insulating layer is in contact with a second side surface of the gap filling insulating layer. ​

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