Semiconductor device

Abstract

The present invention is easy to manufacture, suppresses an increase in the on-resistance of a MOSFET, and reduces a recovery current. A semiconductor device (1) is provided with: a drain region (11) of a first conductivity type; a drift region (10) of the first conductivity type, which is disposed above the drain region (11), and which has a lower impurity concentration than the drain region (11); a second conductivity-type body region (9) disposed above the drift region (10); a source region (3) of the first conductivity type disposed above the body region (9); a channel region (5) of a second conductivity type in contact with the body region (9) and the source region (3); a gate insulating film (6) in contact with the channel region (5); a gate electrode (7) in contact with the gate insulating film (6); a JFET region (8) of a first conductivity type disposed between two adjacent body regions (9); and a first conductivity-type low-lifetime region (4) that does not overlap the JFET region (8), is disposed between the body region (9) and the drift region (10), and contains a second conductivity-type impurity in a range of 6 * 1011 cm <-2 > to 1 * 1013 cm <-2 >.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. BACKGROUND

[0002] A MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is one of semiconductor devices is a switching element, and has a diode built therein. The diode changes from a state in which it is turned on from forward bias to a state in which it is reverse-biased, and a recovery current flows in the reverse direction due to carriers accumulated at the time of turn-on.

[0003] As a technique for reducing this recovery current, for example, there is Patent Literature 1. In the abstract and the like of Patent Literature 1, it is stated that "A semiconductor device has an N-type silicon carbide layer (2), a P-type region (3), an N-type source region (4), a P-type contact region (5), a gate insulating film (6), a gate electrode (7), and a source electrode (8) on the front surface side of an N-type silicon carbide substrate (1). The semiconductor device has a drain electrode (9) on the back surface of the N-type silicon carbide substrate (1). The semiconductor device has a lifetime control body-introduced region (10) in which a lifetime control body is injected at least in the entirety of the boundary between the N-type silicon carbide layer (2) and the bottom surface of the P-type region (3). The lifetime control body is introduced in the entirety of the boundary between the N-type silicon carbide layer (2) and the bottom surface of the P-type region (3) from the back surface side of the N-type silicon carbide substrate (1) after the surface structure of the element is made on the front surface side of the N-type silicon carbide substrate (1) and before the drain electrode (9) is provided. Thus, it is possible to reduce the reverse recovery loss of the PN diode built in the semiconductor device." Figure 1 In addition, in paragraph 0007 of Patent Literature 1, it is stated that "The lifetime control body which becomes a recombination center for minority carriers is introduced in the entirety of the boundary between the first-conductivity-type silicon carbide layer and the second-conductivity-type region, and thus the elimination of the minority carriers is accelerated at the time of turn-off of the built-in PN diode."

[0004] Further, in FIG. 10 and paragraph 0079 of Patent Literature 1, it is stated that "As shown in FIG. 10, the semiconductor device of Embodiment 3 has a lifetime control body introduced in the entirety of the Jfet region between the adjacent P-type regions 3 and the P-type region 3 in the semiconductor device of Embodiment 1. That is, the lifetime control body-introduced region 10 is provided in the entirety of the region at the same depth as the boundary between the N-type silicon carbide layer 2 and the bottom surface of the P-type region 3."

[0005] Figure 1 In addition, in paragraph 0007 of Patent Literature 1, it is stated that "The lifetime control body which becomes a recombination center for minority carriers is introduced in the entirety of the boundary between the first-conductivity-type silicon carbide layer and the second-conductivity-type region, and thus the elimination of the minority carriers is accelerated at the time of turn-off of the built-in PN diode."

[0006] PRIOR ART DOCUMENTS

[0007] PATENT LITERATURE

[0008] ​Patent Document 1: International Publication No. 2016 / 039071 Summary of the Invention

[0009] The problem that the invention aims to solve

[0010] However, in Patent Document 1, a lifetime control body for reducing recovery current is formed by creating lattice defects through helium or proton injection; therefore, as in Patent Document 1... Figure 1 As shown, a mask is required to partially form the lifetime control device introduction region (10), which presents problems such as difficulty in manufacturing and difficulty in manufacturing with high precision. In addition, when the lifetime control device introduction region (10) is formed over the entire surface as in Figure 10 of Patent Document 1, including the current path during MOSFET operation, there is also a problem that the on-resistance of the MOSFET increases due to the decrease in the amount of charge carriers in the semiconductor during the current path during MOSFET operation.

[0011] The problem to be solved by the present invention is to provide a semiconductor device that is easy to manufacture and can reduce recovery current while suppressing the increase of the on-resistance of the MOSFET.

[0012] Methods for solving problems

[0013] To address the aforementioned issues, the semiconductor device of the present invention comprises: a drain region of a first conductivity type; a drift region of the first conductivity type disposed above the drain region, having a lower impurity concentration than the drain region; a body region of a second conductivity type disposed above the drift region; a source region of the first conductivity type disposed above the body region; a channel region of the second conductivity type connected to the body region and the source region; a gate insulating film connected to the channel region; a gate electrode connected to the gate insulating film; a drain electrode electrically connected to the drain region; a source electrode electrically connected to the source region; a JFET region of the first conductivity type disposed between two adjacent body regions above the drift region; and a low lifetime region of the first conductivity type disposed between the body region and the drift region, with a spacing of 6 × 10 11 cm -2 Above and 1×10 13 cm -2 The following range includes impurities of the second conductivity type, and the low lifetime region is not disposed between the JFET region and the drift region.

[0014] Invention Effects

[0015] The semiconductor device according to the present invention is easy to manufacture by using a low-lifetime region of a first conductivity type containing impurities of a second conductivity type, and can reduce recovery current while suppressing the increase in the on-resistance of the MOSFET. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view of a semiconductor device according to Embodiment 1.

[0017] Figure 2 It is the semiconductor device in Example 1 that is relative to Figure 1 The impurity concentration distribution curve at depth in the Z1-Z1' direction.

[0018] Figure 3 This is a cross-sectional view of the semiconductor device according to Embodiment 2.

[0019] Figure 4 This is a perspective view of the semiconductor device in Example 3.

[0020] Figure 5 It is the semiconductor device in Example 3 Figure 4 The X1-X1' sectional view.

[0021] Figure 6 It is the semiconductor device in Example 3 Figure 4 The X2-X2' sectional view.

[0022] Figure 7 It is the semiconductor device in Example 3 Figure 4 Y1-Y1' sectional view.

[0023] Figure 8 This is a cross-sectional view of the semiconductor device according to Embodiment 4. Detailed Implementation

[0024] Hereinafter, embodiments of the present invention will be described using the accompanying drawings. In the various figures and embodiments, the same or similar constituent elements are labeled with the same reference numerals, and repeated descriptions are omitted.

[0025] Example 1

[0026] Figure 1 This is a cross-sectional view of the semiconductor device of Example 1.

[0027] The semiconductor device 1 of Embodiment 1 has a drain region 11 of the first conductivity type; a drift region 10 of the first conductivity type, which is disposed above the drain region 11 and has a lower impurity concentration than the drain region 11; a body region 9 of the second conductivity type, which is disposed above the drift region 10; a source region 3 of the first conductivity type, which is disposed above the body region 9; and a channel region 5 of the second conductivity type, which is in contact with the body region 9 and the source region 3.

[0028] In addition, in Embodiment 1, a case where the first conductivity type is n-type and the second conductivity type is p-type is described as an example, but the present embodiment is not limited to this. The first conductivity type can be p-type and the second conductivity type can be n-type.

[0029] In addition, the semiconductor device 1 of Embodiment 1 has a gate insulating film 6 in contact with the channel region 5, a gate electrode 7 in contact with the gate insulating film 6, a drain electrode 13 electrically connected to the drain region 11, and a source electrode 12 electrically connected to the source region 3.

[0030] Here, the semiconductor device 1 of Embodiment 1 is a planar type MOSFET, and the gate insulating film 6 and the gate electrode 7 are disposed above the channel region 5.

[0031] The semiconductor device 1 of Embodiment 1 has a JFET region 8 of the first conductivity type, which is disposed above the drift region 10 and between two body regions 9 adjacent to each other. The impurity concentration of the JFET region 8 is preferably higher than that of the drift region 10, but the present embodiment is not limited to this. The impurity concentration of the JFET region 8 can be the same as that of the drift region 10.

[0032] In addition, the semiconductor device 1 of Embodiment 1 has an interlayer insulating film 14, but the present embodiment is not limited to this.

[0033] The configuration up to this point is a general configuration of a MOSFET, and the configuration of the detailed part is not limited to Figure 1 the configuration shown in the drawing. The semiconductor device 1 of Embodiment 1 can be formed of an n+ type SiC substrate, for example, but the present embodiment is not limited to this. In addition, the n+ type drain region 11 can be formed by an n+ type SiC substrate, and the n- type drift region 10 and the like can be formed by a general semiconductor device manufacturing method such as epitaxial growth, so a detailed description is omitted.

[0034] Here, in order to reduce the recovery current of the built-in diode of the MOSFET, the semiconductor device 1 of Embodiment 1 is configured to have a low-lifetime region 4 of the first conductivity type, which is disposed between the body region 9 and the drift region 10, has an impurity concentration of 6 x 10 11 cm -2 or less, and has a lifetime of 1 x 10 13 cm -2The following range contains impurities of the second conductivity type. Furthermore, the JFET region 8 and the drift region 10 become a current path at the time of MOSFET operation, so in order to avoid an increase in on-resistance, a low-lifetime region 4 is not provided here. That is, the low-lifetime region 4 is formed so as not to overlap the JFET region 8, which becomes a current path at the time of MOSFET operation. In addition, in the case where the second conductivity type is p-type, it is preferable that the low-lifetime region 4 has aluminum as an impurity of the second conductivity type. Impurities of p-type are known to include aluminum and boron, but aluminum is particularly effective in reducing the lifetime of holes, and thus is effective in reducing the recovery current.

[0035] An example in which the second conductivity type is p-type will be described. In order to reduce the recovery current, it is effective to make the holes, which are carriers, have low lifetimes. Here, if a low-lifetime region 4 of n-type is formed only between the body region 9 and the drift region 10, the effect of low lifetime is small. If the impurity concentration of n-type is increased, the effect of low lifetime becomes greater, but if the impurity concentration of n-type is excessively increased, there is a problem in that the withstand voltage decreases.

[0036] Therefore, in the semiconductor device 1 of Embodiment 1, by including impurities of p-type in the low-lifetime region 4 of n-type, it is achieved that the substantial total amount of impurities obtained by subtracting the impurity concentration of p-type from the impurity concentration of n-type becomes low, and the holes, which are carriers, have low lifetimes. In addition, there are impurities of p-type in the body region 9 as well, but there are many holes in the body region 9 as well, so the impurities of p-type in the body region 9 do not contribute to the reduction of the recovery current. Therefore, it is effective to include impurities of p-type in the low-lifetime region 4 of n-type in order to reduce the recovery current.

[0037] In addition, in a method in which low lifetimes are achieved by lattice defects formed by implanting helium or protons as in the past, there is a problem in that it is difficult to locally form a low-lifetime region, and in the case where a low-lifetime region is formed over the entire surface of a wafer, there is a problem in that the on-resistance at the time of MOSFET operation increases because the current path at the time of MOSFET operation is included, but if it is the low-lifetime region 4 of the first conductivity type including impurities of the second conductivity type of Embodiment 1, it is easy to form the low-lifetime region 4 so as not to be included in the current path at the time of MOSFET operation with high precision compared to local implantation of helium or protons, and thus it is possible to suppress an increase in on-resistance due to the addition of the low-lifetime region 4.

[0038] The low lifetime region 4 of the first conductivity type containing the impurities of the second conductivity type can be produced by the return of the impurities. The difference between the impurity concentration of the first conductivity type and the impurity concentration of the second conductivity type becomes the concentration of the low lifetime region 4. There is no particular limitation on the order of the return, and either of the impurities of the first conductivity type and the impurities of the second conductivity type can be used first. In addition, the formation process of the JFET region 8 of the first conductivity type can also serve as the return.

[0039] The low lifetime region 4 is preferably such that the substantial total amount of impurities obtained by subtracting the impurity concentration of the second conductivity type from the impurity concentration of the first conductivity type is 15% or less of the total amount of impurities in the drift region 10. In order to increase the amount of the impurities of the second conductivity type in the low lifetime region 4, it is necessary to increase the dose of the returned impurities of the first conductivity type, but when the dose is increased, the net total amount of impurities increases, and the withstand voltage decreases. If the substantial total amount of impurities of the low lifetime region 4 is greater than 15% of the total amount of impurities in the drift region 10, significant degradation of the withstand voltage can occur, and thus it is preferable to suppress the amount to 15% or less.

[0040] In addition, in order to increase the effect of reducing the recovery current, the low lifetime region 4 is preferably such that the dose of the impurities of the second conductivity type is 6 x 10 11 cm -2 above, but in order to suppress the amount of the returned impurities of the first conductivity type, it is preferable to set the dose to 1 x 10 13 cm -2 or less.

[0041] Since the path of the recovery current passes between the body region 9 and the drift region 10, it is preferable that the low lifetime region 4 be formed on the entire lower surface of the body region 9.

[0042] Figure 2 is the impurity concentration distribution curve with respect to the depth in the Z1-Z1' direction of the semiconductor device of Example 1. In Figure 1 , the vertical axis indicates the impurity concentration IC on a log scale, and the horizontal axis is the depth DP. Figure 2 The n and p of Figure 2 respectively indicate the distribution curves of the impurity concentrations of the n type (first conductivity type) and the p type (second conductivity type).

[0043] As shown in Figure 2 , it is preferable that the low lifetime region 4 of the first conductivity type containing the impurities of the second conductivity type have a region in which the distribution curve of the impurity concentration of the second conductivity type (p of Figure 2 ) is flat in the depth direction. Thereby, it is possible to form the low lifetime region 4 of the first conductivity type containing the impurities of the second conductivity type deeper (thicker). The distribution curve having such a flat region can be formed, for example, by channeling effect implantation in which the crystal axis of the semiconductor substrate is aligned with the direction of ion implantation. In Figure 2In the present embodiment, an example is shown in which the implantation of impurities of the second conductivity type is performed twice, and the implantation of impurities of the second conductivity type for forming the body region 9 is performed by ordinary ion implantation, and the implantation of impurities of the second conductivity type having a flat region for forming the low-lifetime region 4 is performed by channeling implantation.

[0044] Further, in Embodiment 1, as an example, the JFET region 8 is illustrated as n-type, the body region 9 is illustrated as p-type, the drift region 10 and the low-lifetime region 4 are illustrated as low-concentration n-type, and the source region 3 and the drain region 11 are illustrated as high-concentration n+-type, but is not limited thereto as long as the intended operation in Embodiment 1 is achieved. For example, the JFET region 8 can also be low-concentration n-type.

[0045] Further, an example of each constituent element in Embodiment 1 is shown below, but is not limited thereto as long as the intended operation in Embodiment 1 is achieved.

[0046] The drain region 11 is a SiC wafer, and contains n-type impurities (nitrogen) at 1 x 10 18 cm -3 or less. The thickness is in the range of 50 to 500 um, and in a representative example, is about 150 um.

[0047] The drift region 10 is an epitaxial layer of SiC formed on a SiC wafer, and contains n-type impurities (nitrogen) in the range of 1 x 10 14 cm -3 to 1 x 10 17 cm -3 or less. The thickness is in the range of 5 to 100 um. In a representative example, the concentration is 1 x 10 16 cm -3 or less, and the thickness is 10 um. The withstand voltage in the off state is determined by the drift region 10. A representative example is a specification of 1200 V withstand voltage.

[0048] The body region 9 is formed in a plurality of stripes, and is formed by ion implantation of p-type impurities (aluminum). The depth is about 1 um, and the concentration is about 1 x 10 18 cm -3 or less.

[0049] The source region 3 is formed inside the body region 9, and has a depth (thickness) of about 0.4 um, and a concentration of about 1 x 10 20 cm -3 or less.

[0050] The channel region 5 is formed on the surface of the body region 9, and is formed by ion implantation of p-type impurities (aluminum). The depth is about 0.2 um, and the concentration is about 1 x 10 17 cm -3The channel region 5 can also be provided with the same concentration as the body region 9. In this case, a part of the body region 9 functions as the channel region 5.

[0051] The gate insulating film 6 is a film having SiO2as a main component, and has a thickness of about 50 nm. In the vicinity of the boundary between SiC and SiO2, nitrogen is introduced to improve the boundary characteristics.

[0052] The gate electrode 7 is polycrystal silicon containing n-type impurities at a high concentration.

[0053] The low-lifetime region 4 is formed on the entire lower surface of the body region 9, and is formed by implanting n-type impurities into the bottom of the body region 9. The concentration of the n-type impurities contained in the low-lifetime region 4 is 6 x 1015cm-3or more. 11 cm -2 The above aluminum is a p-type impurity.

[0054] The source electrode 12 and the drain electrode 13 are formed of a metal such as aluminum.

[0055] Embodiment 2

[0056] Embodiment 2 is a modification of Embodiment 1, and is an embodiment applied to a trench MOSFET.

[0057] Figure 3 A sectional view of the semiconductor device of Embodiment 2.

[0058] The semiconductor device 1 of Embodiment 2 has a trench 2 formed to a position deeper than the source region 3 and the channel region 5, and the gate insulating film 6 and the gate electrode 7 are disposed inside the trench 2.

[0059] In addition, the structure of the detailed portion is not limited to Figure 3 the structure shown in the drawing. For example, the trench 2 can be disposed between two body regions 9 as shown in Figure 3 , the side surfaces of the trench 2 can be in contact with the channel region 5 on both sides, or the side surfaces of the trench 2 can be in contact with the channel region 5 on one side.

[0060] The MOSFET having the trench structure can be used at a large current density because the channel resistance is low. At this time, the hole current flowing through the built-in diode also becomes large, and thus the recovery current becomes large. Therefore, the necessity of reducing the recovery current is high, and the effect of reducing the recovery current by the low-lifetime region 4 becomes large.

[0061] Embodiment 3

[0062] Embodiment 3 is a modification of Embodiment 1, and is an embodiment applied to a trench MOSFET having a longitudinal channel fin structure.

[0063] Figure 4 is a perspective view of the semiconductor device of Embodiment 3.Figure 5 The semiconductor device of Example 3 Figure 4 X1-X1' sectional view, Figure 6 The semiconductor device of Example 3 Figure 4 X2-X2' sectional view, Figure 7 The semiconductor device of Example 3 Figure 4 The Y1-Y1' sectional view. Furthermore, in Figure 4 The diagrams of gate electrode 7, gate insulating film 6, interlayer insulating film 14, source electrode 12, and drain electrode 13 are omitted. Additionally, Figure 4 and Figure 5 The groove 2 shown by the dashed line in the cross section is a hypothetical groove that corresponds to the position of the groove 2 in order to illustrate the positional relationship between the other constituent elements and the groove 2.

[0064] The semiconductor device 1 of Embodiment 3 has a plurality of trenches 2 formed at a depth greater than that of the source region 3 and the channel region 5. The source region 3 and the channel region 5 have regions that are fin structures divided by the plurality of trenches 2. The gate insulating film 6 and the gate electrode 7 are disposed inside the plurality of trenches 2. In addition, the structure of the details is not limited to... Figures 4 to 7 The structure shown.

[0065] The trench MOSFET with longitudinal channel fin structure also has a trench structure. Similar to Embodiment 2, it has a low channel resistance, thus enabling it to be used with a high current density. Therefore, similar to Embodiment 2, the recovery current is larger, thus increasing the need to reduce the recovery current. The effect of reducing the recovery current through the low-lifetime region 4 is greater.

[0066] The following shows one example of the constituent elements in Embodiment 3, but it is not limited thereto as long as the actions intended in Embodiment 3 can be achieved.

[0067] Channel region 5 is formed directly below source region 3, sandwiched between two main regions 9. It is formed through ion implantation of p-type impurities (aluminum). The depth is approximately 0.6 μm, and the concentration is 1 × 10⁻⁶. 17 cm -3 Left and right. The distance from the bottom of source region 3 to the bottom of channel region 5 is called the channel length.

[0068] The short side of the trench 2 is about 0.5 μm, the long side is about 1.5 μm, and the distance between the trenches 2 is about 0.5 μm. Multiple trenches are formed in a manner that spans the main body region 9, and the sidewall of the trench 2 on the long side becomes the channel surface.

[0069] like Figure 4 as well as Figure 5As shown, the semiconductor device 1 of Embodiment 3 has a plurality of trenches 2 having a lengthwise direction in a first direction and a short side direction in a second direction and arranged in the second direction in plan view. The source region 3 has a region that becomes a fin structure divided by the plurality of trenches 2. The channel region 5 has a fin structure divided by the plurality of trenches 2, with a lower surface of the region of the source region 3 that becomes the fin structure.

[0070] As shown, the gate electrodes 7 disposed inside the trenches 2 are connected to each other outside the trenches 2. An interlayer insulating film 14 is formed between the connected portions of the gate electrodes 7 and the source region 3. The interlayer insulating film 14 is formed to cover the upper and side portions of the connected portions of the gate electrodes 7. The gate electrodes 7 can be formed of polysilicon, for example. Figures 5 to 7 As shown, the trenches 2 are formed so that the length in the lengthwise direction overlaps the body region 9 on both sides of the JFET region 8. The depth of the trenches 2 is shallower than the body region 9 and deeper than the channel region 5.

[0071] Figure 5 As shown, the trenches 2 are formed so that the length in the lengthwise direction overlaps the body region 9 on both sides of the JFET region 8. The depth of the trenches 2 is shallower than the body region 9 and deeper than the channel region 5.

[0072] The semiconductor device 1 of Embodiment 3 is controlled by inputting a gate drive signal to the gate electrodes 7 inside the trenches 2, so that a channel current flows in the longitudinal direction in the channel region 5 of the fin structure. That is, a trench MOSFET that is a longitudinal channel fin structure. Therefore, by reducing the trench pitch and increasing the density of the trenches 2, the channel density can be increased, the channel resistance can be reduced, and the on-resistance can be reduced.

[0073] Embodiment 4

[0074] Embodiment 4 is a modification of Embodiment 1 and is an embodiment combined with a technique of irradiating protons or helium.

[0075] Figure 8 A cross-sectional view of the semiconductor device of Embodiment 4.

[0076] The semiconductor device 1 of Embodiment 3 has a lattice defect region 15 containing protons or helium and formed with lattice defects in a portion of the drift region 10 on the basis of the structure of Embodiment 1.

[0077] ​By combining the low-lifetime region 4 of the first conductivity type containing impurities of the second conductivity type and the lattice defect region 15 of the first conductivity type of Example 1, it is possible to further reduce the recovery current. In addition, since the low-lifetime region 4 is provided, it is possible to reduce the dosage of the lattice defect region 15 compared to the case where the lattice defect region 15 is provided alone. Furthermore, it is possible to form the lattice defect region 15 at a position away from the body region 9. In the case where the lattice defect region 15 is provided over the entire surface, there is a disadvantage that the on-resistance during MOSFET operation increases due to the current path during MOSFET operation, but in Example 4, it is possible to reduce the dosage of the lattice defect region 15, and thus it is possible to reduce the increase in the on-resistance during MOSFET operation.

[0078] One example of each constituent element in Example 4 is shown below, but is not limited thereto as long as the intended operation in Example 4 can be achieved.

[0079] The lattice defect region 15 is a region where lattice defects are formed by irradiation of protons or helium. By the lattice defect region 15, it is possible to reduce the lifetime. For example, as the depth direction, irradiation is performed to the vicinity of the center of the depth direction of the drift region 10, and the dosage is preferably in the range of 1 x 10 10 cm -2 to 1 x 10 12 cm -2 , and is typically around 5 x 10 10 cm -2 .

[0080] The above describes Examples of the present application, but the present application is not limited to the structure described in the Examples, and various changes can be made within the scope of the technical idea of the present application. In addition, it is also possible to combine and apply part or all of the structures described in each of the Examples. For example, it is also possible to apply Example 4 to Example 2 or Example 3.

[0081] Symbol explanation

[0082] 1: semiconductor device, 2: trench, 3: source region, 4: low-lifetime region, 5: channel region, 6: gate insulating film, 7: gate electrode, 8: JFET region, 9: body region, 10: drift region, 11: drain region, 12: source electrode, 13: drain electrode, 14: interlayer insulating film, 15: lattice defect region, IC: impurity concentration, DP: depth.

Claims

1. A semiconductor device, characterized by comprising: has: a drain region of a first conductivity type; a drift region of the first conductivity type provided above the drain region with a lower impurity concentration than the drain region; a body region of a second conductivity type provided above the drift region; a source region of the first conductivity type provided above the body region; a channel region of the second conductivity type in contact with the body region and the source region; a gate insulating film in contact with the channel region; a gate electrode in contact with the gate insulating film; a drain electrode electrically connected to the drain region; a source electrode electrically connected to the source region; a JFET region of the first conductivity type provided above the drift region and between two body regions adjacent to each other; and the low lifetime region is not provided between the JFET region and the drift region. a low lifetime region of the first conductivity type disposed between the body region and the drift region and having a concentration of 6 x 1014 11 cm -2 - 1 x 1015 13 cm -2 the following ranges contain impurities of the second conductivity type, 2. The semiconductor device according to claim 1, wherein in the low lifetime region, a substantial total amount of impurities obtained by subtracting an impurity concentration of the second conductivity type from an impurity concentration of the first conductivity type is 15% or less of a total amount of impurities of the drift region.

3. The semiconductor device according to claim 1, wherein the low lifetime region has a region in which a distribution curve of the impurity concentration of the second conductivity type is flat in a depth direction.

4. The semiconductor device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

5. The semiconductor device according to claim 4, wherein the low lifetime region has aluminum as the impurity of the second conductivity type.

6. The semiconductor device according to claim 1, wherein a part of the drift region has a lattice defect region containing protons or helium and formed with lattice defects.

7. The semiconductor device according to claim 1, wherein the JFET region has a higher impurity concentration than the drift region.

8. The semiconductor device according to claim 1, wherein the gate insulating film and the gate electrode are provided above the channel region.

9. The semiconductor device according to claim 1, wherein a trench is formed to a position deeper than the source region and the channel region, the gate insulating film and the gate electrode are provided inside the trench. has:

10. The semiconductor device according to claim 1, wherein a plurality of trenches formed to a position deeper than the source region and the channel region, the source region and the channel region have regions that become fin structures divided by the plurality of trenches, the gate insulating film and the gate electrode are provided inside the plurality of trenches. ​

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