Isolation module formation for backside power applications

Abstract

Semiconductor elements and methods of manufacturing the same are described. The method includes combining the selective recess of the sacrificial layer and the isotropic etching of the silicon layer to form a protective cap that will allow the silicon layer of the substrate to be etched without affecting the sacrificial layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure generally relate to semiconductor elements. More specifically, embodiments of the present disclosure relate to gate-all-around (GAA) elements, FinFET elements, and CFET elements including a dielectric material instead of a silicon substrate to form isolated modules in backside power delivery applications. BACKGROUND

[0002] Transistors are a key component of most integrated circuits. Because the drive current of a transistor and its speed are proportional to the gate width of the transistor, faster transistors generally require larger gate widths. Thus, there is a tradeoff between transistor size and speed, and “fin field-effect transistors” (finFETs) have been developed to address the conflicting goals of a transistor with maximum drive current and minimum size. FinFETs feature a fin-shaped channel region that greatly increases the size of the transistor without significantly increasing the footprint of the transistor, and are now being applied in many integrated circuits. However, finFETs have their own drawbacks.

[0003] As transistor elements continue to shrink in feature size to achieve greater circuit density and higher performance, transistor element structures need to be improved to improve electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage current. Examples of transistor element structures include planar structures, fin field-effect transistors (FinFET) structures, and gate-all-around (GAA) structures. GAA element structures include several lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. GAA structures provide good electrostatic control and can be widely adopted in complementary metal oxide semiconductor (CMOS) wafer fabrication.

[0004] In backside power delivery (BSPDN) architectures, silicon (Si) substrates need to be replaced with a dielectric material so that there is no shorting mechanism between adjacent contacts. However, because direct backside contact requires silicon germanium (SiGe) as a placeholder, it is extremely difficult to selectively remove silicon (Si) relative to silicon germanium (SiGe). Thus, improved semiconductor elements and fabrication methods are needed. SUMMARY

[0005] One or more implementations of the present disclosure relate to methods of forming a semiconductor element. In one or more implementations, a method of forming a semiconductor element includes recessing a sacrificial layer relative to a silicon layer of a substrate formed on a channel including a superlattice structure formed on a shallow trench isolation on the substrate and the channel on a gate, etching the silicon layer isotropically to form a first opening, depositing a cap layer in the first opening, removing the silicon layer to form a second opening, depositing a flowable layer in the second opening, removing the cap layer and the sacrificial layer to form a third opening, and forming a backside contact metallization in the third opening.

[0006] Additional implementations of the present disclosure relate to methods of forming a semiconductor element. In one or more implementations, a method of forming a semiconductor element includes recessing a sacrificial layer relative to a silicon layer of a substrate formed on a channel including a superlattice structure formed on a shallow trench isolation on the substrate and the channel on a gate, etching the silicon layer isotropically to form a first opening, depositing a cap layer in the first opening, partially removing the silicon layer to form a second opening, oxidizing the remaining silicon layer to form a silicon oxide layer, optionally depositing a conformal liner in the second opening, depositing a flowable layer on the second opening on the silicon oxide layer or on the optional conformal liner, removing the cap layer and the sacrificial layer to form a third opening, and forming a backside contact metallization in the third opening.

[0007] Still another implementation of the present disclosure relates to a semiconductor element. In one or more implementations, a semiconductor element includes a recessed sacrificial layer of a substrate formed on a channel including a superlattice structure formed on a shallow trench isolation on the substrate and the channel on a gate, a cap layer on the recessed sacrificial layer, and a flowable layer adjacent to the recessed sacrificial layer. BRIEF DESCRIPTION OF DRAWINGS

[0008] For a more complete understanding of the above-described features of the present disclosure, reference is made to the detailed description of the embodiments in connection with the accompanying drawings, in which:

[0009] Figure 1 Process flow diagrams for methods according to one or more implementations;

[0010] Figure 2 Cross-sectional views of semiconductor elements according to one or more implementations are shown;

[0011] Figure 3Cross-sectional views of semiconductor elements according to one or more embodiments are shown;

[0012] Figure 4 Cross-sectional views of semiconductor elements according to one or more embodiments are shown;

[0013] Figure 5 Cross-sectional views of semiconductor elements according to one or more embodiments are shown;

[0014] Figure 6 Cross-sectional views of semiconductor elements according to one or more embodiments are shown;

[0015] Figure 7 Cross-sectional views of semiconductor elements according to one or more embodiments are shown;

[0016] Figure 8 Cross-sectional views of semiconductor elements according to one or more embodiments are shown;

[0017] Figure 9 Cross-sectional views of semiconductor elements according to one or more embodiments are shown;

[0018] Figure 10 Cross-sectional views of semiconductor elements according to one or more embodiments are shown;

[0019] Figure 11 Cross-sectional views of semiconductor elements according to one or more embodiments are shown; and

[0020] Figure 12 A cluster tool according to one or more embodiments is shown.

[0021] For ease of understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment can be beneficially incorporated into other embodiments without further recitation. DETAILED DESCRIPTION

[0022] Before several exemplary embodiments of the disclosure are described, it is to be understood that the disclosure is not limited to the details of construction or process steps set forth in the following description. The disclosure is capable of other embodiments and of being practiced or being carried out in various ways.

[0023] As used in this specification and the appended claims, the term "substrate" refers to a surface upon or to portions of a surface upon which process acts are performed. One skilled in the art will further appreciate that a reference to a substrate can also refer to a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, reference to depositing on a substrate can mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0024] As used herein, "substrate" refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material layer or layers that are to be processed. Substrates include, without limitation, semiconductor wafers. Substrates can be exposed to pre-processing before processing to polish, etch, reduce, oxidize, hydroxylate (or otherwise create or graft a desired chemical moiety to impart a chemical functionality), anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed can also be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayer as the context indicates. Thus, for example, where a film / layer or partial film / layer has been deposited onto a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface. What a given substrate surface comprises will depend on the film to be deposited and the particular chemistry used.

[0025] As used in the present specification and in the appended claims, the terms "precursor", "reactant", "reactive gas", and the like are used interchangeably to represent any gaseous species that can react with a substrate surface.

[0026] "Epitaxy" is a process that deposits a film in highly crystalline alignment with a substrate. Epitaxial growth is broadly defined as the condensation of a gas precursor to form a film on a substrate. Liquid precursors can also be used. Vapor precursors can be obtained by chemical vapor deposition (CVD) and laser ablation. Several epitaxy techniques are now available, such as molecular beam epitaxy (MBE), epitaxial CVD, or atomic layer epitaxy (ALE).

[0027] A transistor is an electrical circuit component or element often formed on a semiconductor element. Depending on the circuit design, transistors are formed on semiconductor elements in addition to capacitors, inductors, resistors, diodes, wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of a substrate and exhibit a doping profile suitable for a particular application. The gate is positioned over a channel region and includes a gate dielectric between the gate electrode and the channel region in the substrate.

[0028] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the element. Enhancement mode field effect transistors typically show very high input impedance at low temperatures. The conductance between the drain terminal and the source terminal is controlled by the electric field in the element, which is generated by the voltage difference between the body of the element and the gate. The three terminals of a FET are the source, through which the carriers enter the channel; the drain, through which the carriers leave the channel; and the gate, which is the terminal for controlling the conductance of the channel. Conventionally, the current entering the channel at the source (S) is designated as I S , and the current entering the channel at the drain (D) is designated as I D . The voltage from drain to source is designated as V DS . By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ) can be controlled.

[0029] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field effect transistor. It has an insulated gate, the voltage of which determines the conductance of the element. This ability to vary conductance with the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of charge density by a metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode above the body, insulated from all other element regions by a gate dielectric layer. In contrast to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to an individual highly doped region separated by a body region. These regions can be p-type or n-type, but they are both of the same type and opposite to that of the body region. The source and drain (unlike the body) are highly doped, indicated by a "+" following the doping type.

[0030] If the MOSFET is an n-channel or nMOSFET, the source and drain are n+ regions and the body is a p region. If the MOSFET is a p-channel or pMOSFET, the source and drain are p+ regions and the body is an n region. The source is so named because it is the source of the charge carriers (electrons for n-channel, holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers leave the channel.

[0031] As used herein, the term "fin field-effect transistor (FinFET)" refers to a MOSFET transistor built on a substrate in which a gate is placed on two or three sides of a channel, forming a dual-gate or tri-gate structure. FinFET elements are given the generic name FinFET because the channel region forms a "fin" on the substrate. FinFET elements have fast switching times and high current densities.

[0032] As used herein, the term "gate-all-around (GAA)" is used to represent an electronic element, such as a transistor, in which gate material surrounds a channel region on all sides. The channel region of a GAA transistor can include nanowires or nanosheets or nanoplates, strip channels, or other suitable channel configurations known to those of skill in the art. In one or more embodiments, the channel region of a GAA element has a plurality of horizontal nanowires or horizontal strips spaced vertically, such that the GAA transistor is a horizontal gate-all-around (hGAA) transistor.

[0033] One example of a gate-all-around (GAA) technology is a complementary field-effect transistor (CFET). As used herein, the term "complementary field-effect transistor (CFET)" refers to a transistor that includes an NMOS FET element and a PMOS FET element stacked on one another. Each of the NMOS FET element and the PMOS FET element forming the CFET is a GAA transistor or a hGAA transistor. CFET transistors have increased on-chip element density and reduced area consumption compared to GAA transistors.

[0034] As used herein, the term "nanowire" refers to a nanostructure having a diameter on the order of a nanometer (10 -9 Alternatively, a nanowire can be defined as a structure having a thickness or diameter that is confined to tens of nanometers or less and an unconfined length. Nanowires are used in transistors and some laser applications, and in one or more embodiments, nanowires are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, as well as volatile (e.g., DRAM) and non-volatile elements (e.g., NAND). As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness scale in the range of about 0.1 nm to about 1000 nm.

[0035] Embodiments of the disclosure are described with the aid of the accompanying drawings, which illustrate elements (e.g., transistors) and processes for forming transistors according to one or more embodiments of the disclosure. The processes shown are merely illustrative of possible uses of the disclosed processes, and one of skill in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0036] One or more embodiments of the disclosure are described with reference to the accompanying drawings. In the methods of one or more embodiments, transistors, such as all-around gate transistors, FinFETs, CFETs, and the like, are fabricated. One or more embodiments advantageously combine selective recessing of a sacrificial layer and isotropic etching of a silicon layer to form a protective cap that will allow etching of the silicon layer of the substrate without affecting the sacrificial layer. In one or more embodiments, formation of the protective cap is essential.

[0037] Figure 1 A process flow diagram of a method 10 for forming a semiconductor element according to some embodiments of the disclosure is shown. Figures 2 to 11 Stages of fabrication of a semiconductor structure according to a process flow of Figure 1 are depicted.

[0038] The method 10 of forming a semiconductor element is described below with Figures 2 to 11 reference to Figures 2 to 11 a cross-sectional view of a semiconductor element (e.g., a GAA) according to one or more embodiments. Figure 1 The method 10 can be part of a multi-step fabrication process of a semiconductor element. Thus, Figure 1 The method 10 can be performed in any suitable process chamber coupled to a cluster tool. The cluster tool can include process chambers for fabricating semiconductor elements, such as chambers configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, epitaxy, or any other suitable chamber for fabricating semiconductor elements.

[0039] Reference is made to Figure 1The method 10 of forming a semiconductor device 100 begins at operation 12 by planarizing a silicon layer of a substrate as shallow trench isolation (STI). At operation 14, a sacrificial layer is recessed relative to the silicon layer of the substrate and the STI. At operation 16, the silicon substrate is isotropically etched. At operation 18, a cap is formed. At operation 20, the silicon layer of the substrate is etched to form an opening. At operation 22, optionally, the remaining silicon layer is oxidized. At operation 24, a liner layer is optionally deposited in the opening. At operation 26, the opening is filled with a flowable material. At operation 28, the flowable material is densified using a high-density plasma (HDP) process. At operation 30, the cap and the sacrificial layer are removed to form a cavity. At operation 32, the cavity is filled with a backside contact metallization.

[0040] Referring to Figures 2 to 11 In one or more embodiments, at least one superlattice structure 101 is formed on a substrate 102. The superlattice structure 101 includes a plurality of semiconductor material layers and a corresponding plurality of horizontal channel layers alternately arranged in a plurality of stack pairs 116. In some embodiments, such groups of stacked layers include silicon (Si) and silicon germanium (SiGe) groups. In some embodiments, such semiconductor material layers include silicon germanium (SiGe) and such horizontal channel layers include silicon (Si). In other embodiments, such horizontal channel layers include silicon germanium (SiGe) and such semiconductor material layers include silicon (Si).

[0041] In some embodiments, such semiconductor material layers and corresponding such horizontal channel layers can include any number of pairs of lattice-matched materials suitable for forming a superlattice structure 101. In some embodiments, such semiconductor material layers and corresponding such horizontal channel layers include from about 2 to about 50 pairs of lattice-matched materials.

[0042] In one or more embodiments, the thickness of such semiconductor material layers and such horizontal channel layers is in a range from about 2 nm to about 50 nm, in a range from about 3 nm to about 20 nm, or in a range from about 2 nm to about 15 nm.

[0043] Referring to Figure 1 and Figure 2 A shallow trench isolation (STI) 104 is formed adjacent to the substrate including the silicon layer 102 and the sacrificial layer 106. As used herein, the term "shallow trench isolation (STI)" refers to an integrated circuit feature that prevents current leakage. In one or more embodiments, the STI is created by depositing one or more dielectric materials, such as silicon dioxide, to fill trenches or openings, and removing excess dielectric using techniques such as chemical mechanical planarization.

[0044] Referring toFigures 2 to 11 In some embodiments, a dummy gate structure 113 is formed adjacent to the superlattice structure 101. The dummy gate structure 113 defines a channel region of the transistor element. The dummy gate structure 113 can be formed using any suitable conventional deposition and patterning processes known in the art.

[0045] In one or more embodiments, the dummy gate structure 113 includes one or more of a gate material 114 and a polysilicon layer 112. In one or more embodiments, the gate material 114 can include any suitable material known to those skilled in the art. In one or more embodiments, the gate material 114 includes one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and n-type doped polysilicon. In some embodiments, the dummy gate structure 113 can also include a dielectric layer between the superlattice structure and the polysilicon layer 112.

[0046] Referring to Figures 2 to 11 In one or more embodiments, the source / drain 110 regions are formed adjacent to (i.e., on either side of) the superlattice structure 101. In some embodiments, the source 110 region is formed adjacent to a first end of the superlattice structure 101, and the drain 110 region is formed adjacent to a second, opposite end of the superlattice structure 101. In some embodiments, the source / drain 110 regions are formed from any suitable semiconductor material, such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon phosphorous (SiP), silicon arsenic (SiAs), or the like. In some embodiments, the source / drain 110 regions can be formed using any suitable deposition process, such as an epitaxial deposition process. In some embodiments, the source / drain 110 regions are independently doped with one or more of phosphorous (P), arsenic (As), boron (B), and gallium (Ga).

[0047] Referring to Figure 1 and Figure 2 At operation 12, the substrate 102 is planarized to the shallow trench isolation 104. The planarization can be any suitable planarization process known to those skilled in the art, including, but not limited to, chemical mechanical planarization (CMP).

[0048] In some implementations, the substrate 102 can be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate in which the entire substrate is composed of a semiconductor material. The bulk semiconductor substrate can include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer can include one or more materials such as crystalline silicon (e.g., Si<100> or Si<111>), strained silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, or other suitable semiconductor materials. In some implementations, the semiconductor material is silicon (Si). Although some examples of materials that can form a substrate are described herein, any material that can be used as a foundation upon which passive and active electronic elements (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic elements, or any other electronic elements) can be constructed falls within the spirit and scope of the present disclosure.

[0049] In some implementations, the semiconductor substrate 102 material can be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some implementations, the substrate can be doped using any suitable process such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor that is produced by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of the electron. In an n-type semiconductor, electrons are the majority carriers, and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of holes (or electron holes). In contrast to n-type semiconductors, p-type semiconductors have a greater concentration of holes than electrons. In a p-type semiconductor, holes are the majority carriers, and electrons are the minority carriers. In one or more implementations, the dopant is one or more selected from boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof.

[0050] In one or more implementations, the sacrificial layer 106 is adjacent to the semiconductor substrate 102 material. The sacrificial layer 106 can include any suitable material known to those of skill in the art. In some implementations, the sacrificial layer includes one or more of silicon germanium (SiGe), metal, amorphous carbon, and the like. In a particular implementation, the sacrificial layer includes silicon germanium (SiGe).

[0051] Referring to Figure 1 and Figure 3At operation 14, the sacrificial layer 106 is recessed relative to the silicon layer 102 of the substrate to form a recessed region 122. In one or more embodiments, the recessed region 122 has a depth in a range of 2 nm to 50 nm, or in a range of 2 nm to 40 nm, or in a range of 2 nm to 30 nm, or in a range of 2 nm to 20 nm, or in a range of 2 nm to 15 nm, or in a range of 2 nm to 10 nm, or in a range of 2 nm to 7 nm, or in a range of 2 nm to 5 nm.

[0052] Referring to Figure 1 and Figure 4 At operation 16, the silicon layer 102 is isotropically etched to form an opening 124 that includes the recessed region 122 and an etched portion of the silicon layer 102. In one or more embodiments, the opening 124 has a critical dimension (CD) in a range of 2 nm to 60 nm, including in a range of 2 nm to 50 nm, including in a range of 2 nm to 40 nm, including in a range of 2 nm to 30 nm, including in a range of 2 nm to 25 nm, including in a range of 2 nm to 20 nm, including in a range of 2 nm to 15 nm, including in a range of 2 nm to 10 nm, and including in a range of 2 nm to 5 nm.

[0053] Referring to Figure 1 and Figure 5 At operation 18, a cap layer 126 is deposited in the opening 124. The cap layer can include any suitable material known to those of skill in the art. In one or more embodiments, the cap layer includes one or more of silicon nitride (SiN), amorphous carbon, silicon oxynitride (SiON), aluminum oxide (AlOx), and the like.

[0054] Referring to Figure 1 and Figure 6 At operation 20, the silicon layer 102 is etched to form an opening 128. In some embodiments, the silicon layer 102 is completely removed by an SRP etch to form the opening 128. In other embodiments, as shown in FIG. 1C, the silicon layer 102 is anisotropically etched such that portions of the silicon layer 102 remain. Any suitable thickness of the silicon oxide layer 102 can remain. In one or more embodiments, the portions of the remaining silicon oxide layer 102 have a thickness in a range of 3 nm to 5 nm. Figure 6

[0055] The opening 128 can be formed by any suitable means known to those of skill in the art. In some embodiments, the etching process of operation 20 includes one or more of a wet etching process or a dry etching process. The etching process can be a directional etch. ​

[0056] In some embodiments, the dry etch process can include a conventional plasma etch or a remote plasma assisted dry etch process. In a remote plasma assisted dry etch process according to one or more embodiments, the element is exposed to H2, NF3, and / or NH3 plasma species, such as plasma excited hydrogen and fluorine species. For example, in some embodiments, the element can be simultaneously exposed to H2, NF3, and NH3 plasma. The remote plasma assisted dry etch process can be performed in a pre-clean chamber, which can be integrated into one of a variety of multi-processing platforms known to those skilled in the art. The wet etch process can include a hydrofluoric acid (HF) last process, a so-called "HF last" process, in which the surface is etched with HF to hydrogen-terminate the surface. Alternatively, any other liquid-based pre-epitaxy pre-clean process can be employed. In some embodiments, the process includes sublimation etching for removal of native oxides. The etching process can be plasma-based or thermal-based. The plasma process can be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0057] Referring to Figure 1 and Figure 7 At operation 22, the remaining portion of the silicon layer 102 can be oxidized to form an oxide layer 130. The remaining portion of the silicon layer 102 can be oxidized by any suitable method known to those skilled in the art. In one or more embodiments, the remaining silicon layer 102 can be oxidized using a rapid thermal oxidation (RTO) process at a temperature greater than 400 °C.

[0058] Referring to Figure 1 At operation 24, a conformal liner (not shown) is optionally deposited in the opening 128 on the oxide layer 130. The conformal liner can include any suitable material known to those skilled in the art. In one or more embodiments, the conformal liner includes one or more of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), and the like. The conformal liner can have any suitable thickness. In one or more embodiments, the conformal liner has a thickness in a range from 1 nm to 20 nm.

[0059] Referring to Figure 1 and Figure 8At operation 26, flowable material 132 is deposited in openings 128. In embodiments where a conformal liner is first deposited at operation 24, flowable material 132 is deposited in openings 128 on the conformal liner. Flowable material 132 can include any suitable flowable material known to those skilled in the art. In one or more embodiments, flowable material 132 includes one or more of silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxycarbide nitride (SiOCN), and the like. In one or more specific embodiments, flowable material 132 includes silicon oxide (SiOx).

[0060] In one or more embodiments not shown, at operation 28, flowable material 132 is densified using a high-density plasma (HDP) process and then planarized, such as chemical mechanical polishing (CMP), to form a top surface that is flush with STI layer 104. Figure 1

[0061] Referring to FIG. 1, at operation 30, cap layer 126 is removed to form openings 134. Openings 134 expose a top surface of sacrificial layer 106. Figure 1 Figure 9 As shown in FIG. 1, at operation 30, sacrificial layer 106 is removed to form cavities 136. Cavities 136 can be shaped and processed as desired.

[0062] As shown in FIG. 1, at operation 30, sacrificial layer 106 is removed to form cavities 136. Cavities 136 can be shaped and processed as desired. Figure 1 Figure 10 Referring to FIG. 1, at operation 32, backside contact metallization is then performed, in which one or more of metal liner 138 and metal fill 140 can be deposited. Backside contact metallization can include any suitable material known to those skilled in the art. In one or more embodiments, backside contact metallization, such as metal liner 138 and metal fill 140, can include one or more of tungsten (W), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), and copper (Cu).

[0063] In one or more embodiments, at operation 32, backside contact metallization is performed, in which one or more of metal liner 138 and metal fill 140 can be deposited. Backside contact metallization can include any suitable material known to those skilled in the art. In one or more embodiments, backside contact metallization, such as metal liner 138 and metal fill 140, can include one or more of tungsten (W), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), and copper (Cu). Figure 1 Figure 11 In one or more embodiments, at operation 32, backside contact metallization is performed, in which one or more of metal liner 138 and metal fill 140 can be deposited. Backside contact metallization can include any suitable material known to those skilled in the art. In one or more embodiments, backside contact metallization, such as metal liner 138 and metal fill 140, can include one or more of tungsten (W), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), and copper (Cu).

[0064] In one or more embodiments, at operation 32, backside contact metallization is performed, in which one or more of metal liner 138 and metal fill 140 can be deposited. Backside contact metallization can include any suitable material known to those skilled in the art. In one or more embodiments, backside contact metallization, such as metal liner 138 and metal fill 140, can include one or more of tungsten (W), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), and copper (Cu). Figure 1 ​​​​The method 10 of FIG. 1 produces a fully wrapped gate (GAA device). The intermediate device includes a recessed sacrificial layer 106 of a substrate. The substrate is formed on a channel including a superlattice structure 101 on a shallow trench isolation 104 on the substrate and the channel on a gate 113. In one or more embodiments, a cap layer 126 is on the recessed sacrificial layer 106. A flowable layer 132 is adjacent to the recessed sacrificial layer 106. After the cap layer 126 and the recessed sacrificial layer 106 are removed, backside contact metallization 138, 140 is formed.

[0065] Additional embodiments of the present disclosure relate to a processing tool 300 for the described forming GAA devices and methods, as shown in FIG. 2. Various multiprocessing platforms known to those skilled in the art can be utilized. The cluster tool 300 includes at least one central transfer station 314 having multiple sides. A robot 316 is positioned within the central transfer station 314 and is configured to move robot blades and wafers to each of the sides. Figure 12

[0066] The cluster tool 300 includes a plurality of processing chambers 308, 310, and 312, also referred to as process stations, connected to the central transfer station. The various processing chambers provide separate processing areas isolated from adjacent process stations. The processing chambers can be any suitable chamber, including but not limited to, a preclean chamber, a deposition chamber, an anneal chamber, an etch chamber, and the like. The specific arrangement of process chambers and components can vary depending on the cluster tool and should not be considered limiting to the scope of the present disclosure.

[0067] In the embodiment shown in FIG. 2, a factory interface 318 is connected to the front of the cluster tool 300. The factory interface 318 includes a chamber 302 for loading and unloading on the front 319 of the factory interface 318. Figure 12

[0068] The size and shape of the load and unload chambers 302 can vary depending on, for example, the substrate being processed in the cluster tool 300. In the embodiment shown, the size of the load and unload chambers 302 are set to accommodate a wafer cassette in which a plurality of wafers are positioned within the cassette.

[0069] A robot 304 is within the factory interface 318 and can move between the load and unload chambers 302. The robot 304 is capable of transferring wafers from a cassette in the load chamber 302 through the factory interface 318 to a load lock chamber 320. The robot 304 is also capable of transferring wafers from the load lock chamber 320 through the factory interface 318 to a cassette in the unload chamber 302.

[0070] ​​Robots 316 of some embodiments are multi-arm robots capable of moving more than one wafer independently at a time. Robots 316 are configured to move wafers between chambers around transfer chamber 314. Individual wafers are carried on wafer transport blades located at the distal end of the first robot mechanism.

[0071] System controller 357 is in communication with robots 316 and multiple processing chambers 308, 310, and 312. System controller 357 can be any suitable component capable of controlling the processing chambers and robots. For example, system controller 357 can be a computer including a central processing unit (CPU) 392, memory 394, input / output 396, suitable circuitry 398, and storage.

[0072] The processes can generally be stored as software routines in the memory of system controller 357 which, when executed by the processor, cause the process chamber to carry out the processes of the present disclosure. The software routines can also be stored and / or executed by a second processor (not shown) that is remotely located from the hardware being controlled. Some or all of the methods of the present disclosure can also be implemented in hardware. Accordingly, the processes can be implemented in software and executed using a computer system, in hardware as, e.g., a special- purpose application specific integrated circuit, or other type of hardware implementation, or as a combination of software and hardware. When executed by the processor, the software routine converts a general purpose computer into a specific purpose computer (controller) that controls the chamber operations to perform the processes.

[0073] In some embodiments, system controller 357 has a configuration that controls a rapid thermal processing chamber to crystallize a template material.

[0074] In one or more embodiments, a processing tool includes a central transfer station including a robot configured to move wafers, a plurality of process stations each connected to the central transfer station and providing a processing area separate from the processing area of an adjacent process station, the process stations including a recess chamber, an etch chamber, a deposition chamber, and a controller connected to the central transfer station and the process stations, the controller configured to activate the robot to move wafers between the process stations and to control processes occurring in each of the process stations.

[0075] The use of the terms "a" and "an" and "the" and similar referents in the context of describing the materials and methods discussed herein (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. Recitation of a range of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated in the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate materials and methods and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0076] In this specification, references to "one implementation," "some implementations," "one or more implementations," or "an implementation" mean that a particular feature, structure, material, or characteristic is included in at least one implementation of the disclosure. Thus, the appearances of phrases such as "in one or more implementations," "in some implementations," "in one implementation," or "in an implementation" in various places in the specification are not necessarily referring to the same implementation of the disclosure. Furthermore, in one or more implementations, a particular feature, structure, material, or characteristic can be combined in any suitable manner.

[0077] While the disclosure herein has been described with reference to particular embodiments, it is to be understood that the embodiments described are merely illustrative of the principles and applications of the present disclosure. It will thus be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatuses of the disclosure without departing from the spirit and scope of the disclosure. Such modifications and variations are intended to fall within the scope of the present disclosure, which is to be interpreted in the broadest sense possible.

Claims

1. A method of forming a semiconductor device, the method comprising: recessing a sacrificial layer relative to a silicon layer of a substrate to form a recessed region, the substrate formed on a channel comprising a superlattice structure, the superlattice structure on a shallow trench isolation on the substrate, and the channel on a gate; isotropically etching the silicon layer to form a first opening; depositing a cap layer in the first opening; removing at least a portion of the silicon layer to form a second opening; depositing a flowable layer in the second opening; removing the cap layer and the sacrificial layer to form a third opening; and forming a backside contact metallization in the third opening.

2. The method of claim 1, wherein the silicon layer is removed entirely.

3. The method of claim 1, further comprising depositing a conformal liner prior to depositing the flowable layer, the conformal liner comprising one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, the conformal liner having a thickness in a range from 1 nm to 20 nm.

4. The method of claim 1, wherein only a portion of the silicon layer is removed, and a remaining portion of silicon layer remains.

5. The method of claim 4, further comprising oxidizing the remaining silicon layer.

6. The method of claim 1, wherein the superlattice structure comprises a plurality of horizontal channel layers and a corresponding plurality of semiconductor material layers arranged in a plurality of stack pairs.

7. The method of claim 1, wherein the sacrificial layer comprises one or more of silicon germanium (SiGe), metal, amorphous carbon, and the like.

8. The method of claim 1, wherein the cap layer comprises one or more of silicon nitride (SiN), amorphous carbon, silicon oxynitride (SiON), aluminum oxide (AlOx), and the like.

9. The method of claim 1, wherein the recessed region has a depth in a range from 2 nm to 30 nm, and wherein the first opening has a critical dimension in a range from 2 nm to 60 nm.

10. The method of claim 1, wherein the gate comprises one or more of tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum (TiAl), and n-type doped polysilicon, and wherein the flowable layer comprises one or more of silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), and the like.

11. The method of claim 1, wherein the method is performed in a processing chamber without breaking vacuum.

12. The method of claim 1, wherein the backside contact metallization comprises one or more of tungsten (W), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), and copper (Cu).

13. The method of claim 1, wherein the semiconductor device comprises one or more of a fully surrounding gate, a FinFET, and a CFET. ​ 14. A method of forming a semiconductor element, the method comprising: recessing a sacrificial layer relative to a silicon layer of a substrate formed on a passageway comprising a superlattice structure on a shallow trench isolation on the substrate and the passageway on a gate; isotropically etching the silicon layer to form a first opening; depositing a cap layer in the first opening; partially removing the silicon layer to form a second opening; oxidizing a remaining silicon layer to form a silicon oxide layer; optionally depositing a conformal liner in the second opening; depositing a flowable layer on the second opening on the silicon oxide layer; removing the cap layer and the sacrificial layer to form a third opening; and forming a backside contact metallization in the third opening.

15. The method of claim 14, wherein the recessed region has a depth in a range of 2 nm to 30 nm.

16. The method of claim 15, wherein the first opening has a critical dimension in a range of 2 nm to 60 nm.

17. The method of claim 14, wherein the sacrificial layer comprises one or more of silicon germanium (SiGe), metal, amorphous carbon, and the like, wherein the cap layer comprises one or more of silicon nitride (SiN), amorphous carbon, silicon oxynitride (SiON), aluminum oxide (AlOx), and the like, wherein the flowable layer comprises one or more of silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), and the like, and wherein the backside contact metallization comprises one or more of tungsten (W), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), ruthenium (Ru), and copper (Cu).

18. A semiconductor element, the element comprising: a recessed sacrificial layer of a substrate formed on a passageway comprising a superlattice structure on a shallow trench isolation on the substrate and the passageway on a gate, the sacrificial layer comprising one or more of silicon germanium (SiGe), metal, amorphous carbon, and the like; a cap layer on the recessed sacrificial layer, the cap layer comprising one or more of silicon nitride (SiN), amorphous carbon, silicon oxynitride (SiON), aluminum oxide (AlOx), and the like; and a flowable layer adjacent to the recessed sacrificial layer, the flowable layer comprising one or more of silicon oxide (SiOx), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon nitride (SiN), silicon oxycarbonitride (SiOCN), and the like.

19. The element of claim 18, further comprising a conformal liner adjacent to the flowable layer, the conformal liner comprising one or more of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride (SiOCN), and wherein the conformal liner has a thickness in a range of 1 nm to 20 nm. ​ 20. The element of claim 18, wherein the semiconductor element includes one or more of a fully wrapped gate, a FinFET, and a CFET.

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