Semiconductor device

Abstract

The semiconductor device includes first, second, and third power supply lines formed below a substrate in which a through hole is formed and extending in a first direction, and a power switch circuit having first and second transistors formed above the substrate. The first transistor is disposed between the first power supply line and the second power supply line, and a source of the first transistor is connected to a via connected to the first power supply line. The second transistor is disposed at a position overlapping the second power supply line, and a source of the second transistor is connected to a source of the first transistor via a wiring formed over the substrate. As a result, in the power switch circuit, the source of the transistor, which does not overlap the power supply line below the semiconductor substrate in plan view, can be connected to the power supply line below the semiconductor substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device. BACKGROUND

[0002] A technique is known in which a power switch circuit for switching supply and cutoff of power supply to a transistor is provided in a semiconductor device such as a standard cell. A BS-PDN (Backside Power Delivery Network) technique is known in which a power supply line is provided on the back surface of a semiconductor substrate, and power supply is supplied to a transistor provided on the surface of the semiconductor substrate via a TSV (Through Silicon Via). A technique is known in which a via is connected directly from the back surface of a semiconductor substrate to a source and a drain of a transistor provided on the surface of the semiconductor substrate.

[0003] Patent Document 1: U.S. Patent Application Publication No. 2022 / 0344263 Specification

[0004] Patent Document 2: U.S. Patent Application Publication No. 2022 / 0208757 Specification

[0005] Patent Document 3: U.S. Patent Application Publication No. 2021 / 0272903 Specification

[0006] Patent Document 4: U.S. Patent Application Publication No. 2019 / 0305773 Specification

[0007] Patent Document 5: International Publication No. 2020 / 065916

[0008] Patent Document 6: International Publication No. 2022 / 066797

[0009] Patent Document 7: U.S. Patent No. 11552069 Specification SUMMARY

[0010] <Problem to be Solved by the Invention>

[0011] No specific research has been conducted on how to configure and connect wiring and vias and the like in a case where a power supply line formed below a semiconductor substrate is directly connected with a source and a drain of a power switch circuit formed above the semiconductor substrate using a via formed on the semiconductor substrate. For example, no research has been conducted on how to electrically connect a source of a transistor to a power supply line below a semiconductor substrate in a case where the transistor above the semiconductor substrate is not configured at a position overlapping the power supply line below the semiconductor substrate in a plan view.

[0012] The present application has been made in view of the above circumstances, and aims at electrically connecting a source of a transistor not arranged in a position overlapping a first power supply line under a substrate in a plan view to the first power supply line in a power supply switching circuit.

[0013] <Means for solving the problem>

[0014] According to one aspect of the present application, a semiconductor device includes a substrate on which a first via is formed; a first power supply line, a second power supply line, and a third power supply line formed under the substrate, the first power supply line being supplied with a first potential, the second power supply line being supplied with a second potential, and the third power supply line being supplied with a third potential; and a power supply switching circuit having a first transistor and a second transistor, the first transistor being formed over the substrate and electrically connected between the first power supply line and the second power supply line, and the second transistor being formed over the substrate, wherein the first power supply line, the second power supply line, and the third power supply line respectively extend in a first direction in a plan view, the first transistor has a first source and a first drain, the first transistor is arranged in a position overlapping the first power supply line in the plan view, the first source is connected to the first via connected to the first power supply line, the second transistor has a second source and a second drain, the second transistor is arranged in a position overlapping the second power supply line in the plan view, and the second source is electrically connected to the first source via a wiring formed over the substrate.

[0015] <Effects of the Invention>

[0016] According to the disclosed technology, it is possible to electrically connect a source of a transistor not overlapping a power supply line under a semiconductor substrate in a plan view to the power supply line under the semiconductor substrate in a power supply switching circuit. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a plan view showing an example of a layout of a semiconductor device in the first embodiment.

[0018] Figure 2 is a plan view showing an example of a layout of a semiconductor device in the first embodiment. Figure 1 is a cross-sectional view showing an example of a cross-sectional structure of the semiconductor device of

[0019] Figure 3 is a circuit diagram showing an example of a circuit arranged in a standard cell block of Figure 1

[0020] Figure 4 is a plan view showing an example of a layout of a semiconductor device in the first embodiment. Figure 3 ​FIG. 1 is a plan view showing an example of a layout of a power supply switching circuit in a semiconductor device according to a first embodiment of the present application.

[0021] Figure 5 FIG. 2 is a plan view showing an example of a layout of a power supply switching circuit in the semiconductor device according to the first embodiment of the present application. Figure 3 and Figure 4 FIG. 3 is a plan view showing an example of a layout of a power supply switching circuit in the semiconductor device according to the first embodiment of the present application.

[0022] Figure 6 FIG. 4 is a sectional view showing an example of a section along the X1-X2 line of the semiconductor device according to the first embodiment of the present application. Figure 5 FIG. 5 is a sectional view showing another example of a section along the X1-X2 line of the semiconductor device according to the first embodiment of the present application.

[0023] Figure 7 FIG. 6 is a sectional view showing another example of a section along the X1-X2 line of the semiconductor device according to the first embodiment of the present application. Figure 5 FIG. 7 is a sectional view showing another example of a section along the X1-X2 line of the semiconductor device according to the first embodiment of the present application.

[0024] Figure 8 FIG. 8 is a sectional view showing another example of a section along the X1-X2 line of the semiconductor device according to the first embodiment of the present application. Figure 5 FIG. 9 is a plan view showing a first modification example of a layout of a power supply switching circuit in the semiconductor device according to the first embodiment of the present application.

[0025] Figure 9 FIG. 10 is a plan view showing a second modification example of a layout of a power supply switching circuit in the semiconductor device according to the first embodiment of the present application. Figure 3 FIG. 11 is a plan view showing a third modification example of a layout of a power supply switching circuit in the semiconductor device according to the first embodiment of the present application.

[0026] Figure 10 FIG. 12 is a plan view showing a fourth modification example of a layout of a power supply switching circuit in the semiconductor device according to the first embodiment of the present application. Figure 3 FIG. 13 is a plan view showing a fifth modification example of a layout of a power supply switching circuit in the semiconductor device according to the first embodiment of the present application.

[0027] Figure 11 FIG. 14 is a plan view showing an example of a layout of a power supply line arranged on the back surface side of a semiconductor substrate in a semiconductor device according to a second embodiment of the present application. Figure 3 FIG. 15 is a plan view showing an example of a layout of a power supply switching circuit in the semiconductor device according to the second embodiment of the present application.

[0028] Figure 12 FIG. 16 is a plan view showing a modification example of a layout of a power supply switching circuit in the semiconductor device according to the second embodiment of the present application. Figure 3 FIG. 17 is a plan view showing a first modification example of a layout of a power supply switching circuit in the semiconductor device according to the second embodiment of the present application.

[0029] Figure 13 FIG. 18 is a plan view showing a second modification example of a layout of a power supply switching circuit in the semiconductor device according to the second embodiment of the present application. Figure 3 FIG. 19 is a plan view showing a third modification example of a layout of a power supply switching circuit in the semiconductor device according to the second embodiment of the present application.

[0030] Figure 14 FIG. 20 is a plan view showing an example of a layout of a power supply line arranged on the back surface side of a semiconductor substrate in a semiconductor device according to a third embodiment of the present application.

[0031] Figure 15 FIG. 21 is a plan view showing an example of a layout of a power supply switching circuit in the semiconductor device according to the third embodiment of the present application. Figure 14 FIG. 22 is a plan view showing a modification example of a layout of a power supply switching circuit in the semiconductor device according to the third embodiment of the present application.

[0032] Figure 16 FIG. 23 is a plan view showing a modification example of a layout of a power supply switching circuit in the semiconductor device according to the third embodiment of the present application. Figure 14 FIG. 24 is a plan view showing a first modification example of a layout of a power supply switching circuit in the semiconductor device according to the third embodiment of the present application. DETAILED DESCRIPTION

[0033] Hereinafter, an embodiment will be described with reference to the drawings. Hereinafter, a symbol indicating a signal is also used as a symbol indicating a signal line or a signal terminal. A symbol indicating a power supply potential is also used as a symbol indicating a power supply line or a power supply terminal to which a power supply potential is supplied.

[0034] (First Embodiment)

[0035] Figure 1 An example of a layout of a semiconductor device in the first embodiment is shown. For example, Figure 1 The semiconductor device 100 shown can be a SoC (System on Chip), a single FPGA (Field-Programmable Gate Array), or the like.

[0036] The semiconductor device 100 includes a plurality of I / O units IOC, IOCP, and an internal circuit region INTR. The I / O unit IOC is an interface circuit for a signal SIG such as an input signal, an output signal, or an input / output signal. The I / O unit IOCP is an interface circuit for a power supply potential or a ground potential.

[0037] Each of the I / O units IOC, IOCP, and the internal circuit region INTR is connected. For example, the internal circuit region INTR has one or a plurality of standard cell blocks SCB in which standard cells are arranged. Note that a logic circuit other than the standard cells can be mounted in the internal circuit region INTR, and a memory can be mounted. The memory can be mounted in the standard cell block SCB. For example, a transistor mounted in the semiconductor device 100 can be a fin FET (Field Effect Transistor), a nanosheet FET, or a CFET (Complementary FET).

[0038] Figure 2 An example of a cross-sectional structure of the semiconductor device 100 of Figure 1 The semiconductor device 100 includes a substrate SUB, a wiring layer WL1 formed on a surface FS side of the substrate SUB, and a wiring layer WL2 formed on a back surface BS side of the substrate SUB. The surface FS of the substrate SUB is an example of an upper side of the substrate SUB, and the back surface BS of the substrate SUB is an example of a lower side of the substrate SUB. On the surface of the substrate SUB, a fin portion FIN that is a part of a transistor is formed. The fin portion FIN has a source, a drain, and a channel. On a surface (back surface) on the opposite side of the substrate SUB of the wiring layer WL2, a pad PAD that is an external connection terminal is formed.

[0039] The wiring layer WL2 has a plurality of wiring layers BSM1, BSM2 Figure 2The BSM is an abbreviation for Backside Metal. For example, in the wiring layers BSM1, BSM2, wirings W1, W2 for supplying a power supply potential, a ground potential, and the like are formed, respectively. The wirings W1, W2 are connected to each other via a via VIA1. The wiring W2 is connected to the pad PAD via a via VIA2.

[0040] The wiring W1 is connected to the source of the fin FIN via a TSV formed on the substrate SUB. The TSV is an example of the first via or the second via. The wiring W1 can be connected to a buried wiring BPR (Buried Power Rail) buried in the surface of the substrate SUB via the TSV.

[0041] Note that the transistor formed on the substrate SUB is not limited to the fin FET using the fin, and can be, for example, a planar MOSFET, a nanosheet FET, or a CFET (Complementary FET). In the planar MOSFET and the nanosheet FET as well, the via TSV for supplying a power supply or a ground potential is connected to the source of the transistor. Further, in the case of the CFET, the via TSV for supplying a power supply or a ground potential can be connected to the source closest to the substrate SUB.

[0042] Figure 3 An example of a circuit configured in a standard cell block SCB of Figure 1 The standard cell block SCB has a power supply switching circuit PSW and a standard cell SC. The standard cell SC is connected to a virtual power supply line VVDD and a ground line VSS, and operates by receiving supply of a virtual power supply potential VVDD from the virtual power supply line VVDD.

[0043] The power supply switching circuit PSW has a control circuit CNTL and a switching transistor SWT. The control circuit CNTL is a buffer circuit having inverters IV1, IV2 connected in series between an input signal line IN and an output signal line OUT. Each of the inverters IV1, IV2 is connected to a power supply line TVDD and a ground line VSS and operates. The inverter IV1 inverts the logic of the input signal IN and outputs it as an output signal OUT0. The inverter IV2 inverts the logic of the output signal OUT0 from the inverter IV1 and outputs it as an output signal OUT.

[0044] The power supply line TVDD is an example of the first power supply line, and the power supply potential TVDD is an example of the first potential. The virtual power supply line VVDD is an example of the second power supply line, and the virtual power supply potential VVDD is an example of the second potential. The ground line VSS is an example of the third power supply line, and the ground potential VSS is an example of the third potential.

[0045] The switching transistor SWT is a PMOS transistor with its source connected to the power supply line TVDD and its drain connected to the dummy power supply line VVDD. It operates by receiving the voltage from the output signal OUT0 of the control circuit CNTL as its gate potential. During the conduction period of the switching transistor SWT, the power supply line TVDD is electrically connected to the dummy power supply line VVDD, and the power supply potential TVDD is supplied to the standard cell SC via the dummy power supply line VVDD. During the de-conduction period of the switching transistor SWT, the electrical connection between the power supply line TVDD and the dummy power supply line VVDD is broken, and the dummy power supply line VVDD is set to a floating state. Note that instead of the output of inverter IV1, the input IN of inverter IV1 or the output OUT of inverter IV2 can also be connected to the gate of the switching transistor SWT. This also applies to other implementations.

[0046] Note that the control circuit CNTL can also be configured in a different area than the configuration area of ​​the power switch circuit PSW. Additionally, the output signal OUT can also be supplied to the input terminal IN of another power switch circuit PSW. The switching transistor SWT is an example of a first transistor formed on the substrate SUB and electrically connected between the power line TVDD and the virtual power line VVDD.

[0047] Figure 4 The semiconductor substrate SUB is shown in the plan view with the back side (BS side) arranged in the plan view. Figure 3 This is an example of the positional relationship between the power line TVDD, virtual power line VVDD, ground line VSS, and via VIA1 at the overlapping location of the standard unit block SCB and the power switch circuit PSW. The traces in routing layer BSM1 extend along the X direction, while the traces in routing layer BSM2 extend along the Y direction, which is a second direction different from the X direction. The X direction is an example of a first direction. Figure 4 The symbol ROW indicates the width of the standard cell SC in the Y direction of the wiring layer BSM1.

[0048] The virtual power lines VVDD of the cabling layer BSM1 are arranged in a ROW configuration with two intervals in the Y direction. Between adjacent pairs of virtual power lines VVDD in the Y direction, ground lines VSS extending in the X direction and interrupted at multiple points along the way, and power lines TVDD configured at the locations where ground lines VSS are interrupted are alternately arranged.

[0049] The power switch circuits (PSWs) shown in the thick dashed boxes are, for example, arranged in an interlaced (houndstooth) configuration. Standard cells (SCs) are arranged in areas where power switch circuits (PSWs) are not configured. For example, the power switch circuits (PSWs) are configured such that a pair of adjacent virtual power lines VVDD in the Y direction (two spaced ROWs) overlaps with a power line TVDD extending in the X direction in the plan view.

[0050] By distributing the power lines (TVDD) at locations where the ground line (VSS) is interrupted, a dedicated area with a spacing of ROW width for the power lines (TVDD) is eliminated. Furthermore, the power lines (TVDD) can be distributed only at locations where the power switching circuit (PSW) is located. Therefore, compared to the case of providing a dedicated area with a spacing of ROW width for the power lines (TVDD), the density of the virtual power lines (VVDD) and ground line (VSS) in the wiring layer (BSM1) can be increased, thereby improving the power supply capability to the standard cell (SC).

[0051] In cabling layer BSM2, the power line TVDD, dummy power line VVDD, and ground line VSS are arranged repeatedly in the X direction in this order. The dummy power line VVDD of cabling layers BSM1 and BSM2 are interconnected via vias VIA1 located at the crossover points. The power line TVDD of cabling layers BSM1 and BSM2 are interconnected via vias VIA1 located at the crossover points. The ground line VSS of cabling layers BSM1 and BSM2 are interconnected via vias VIA1 located at the crossover points.

[0052] Note that the configuration of the virtual power line VVDD in the BSM2 routing layer can also be omitted. In this case, the power line TVDD and ground line VSS are alternately arranged along the X direction in the BSM2 routing layer. Furthermore, although not specifically limited, the configuration density of the power switching circuit PSW can be set higher than... Figure 4 Low. In this case, the cutting interval of the grounding wire VSS extending along the X direction is set to be lower than... Figure 4 Width.

[0053] Figure 5 Show Figure 3 and Figure 4 An example of the layout of a power switch circuit (PSW). Figure 5 In the accompanying diagrams, the symbol Mint represents a wiring formed on the metal wiring layer Mint, which is closest to the substrate SUB among multiple metal wiring layers. The symbol LI represents a local wiring formed on a wiring layer closer to the substrate SUB than the Mint layer. The wiring LI can be directly connected to the source and drain of the transistor. The symbol GT represents the gate of the transistor. The symbol VIA represents a via connecting the Mint wiring and the local wiring LI, or a via connecting the Mint wiring and the gate wiring GT.

[0054] The symbol TR(PMOS) denotes a transistor region (source, drain, and channel) of a PMOS transistor. The symbol TR(NMOS) denotes a transistor region (source, drain, and channel) of an NMOS transistor. For example, in a fin-FET, a fin is formed in the region TR. In a nano-sheet FET, a semiconductor layer is formed as a source and a drain in the region TR, and a nano-sheet is formed as a channel between the source and the drain.

[0055] The power switch circuit PSW includes the switching transistors SWT and the control circuit CNTL (buffer circuit) arranged in the X direction in a plan view. For example, the power switch circuit PSW is designed as one unit. The switching transistors SWT are arranged at positions overlapping the virtual power line VVDD and the power line TVDD of the wiring layer BSM1 in a plan view.

[0056] In the switching transistors SWT, the source of the PMOS transistor overlapping the power line TVDD of the wiring layer BSM1 in a plan view is directly connected to the TSV connected to the power line TVDD of the wiring layer BSM1. The TSV directly connected to the source of the PMOS transistor overlapping the power line TVDD of the wiring layer BSM1 in a plan view is an example of the first via. In the switching transistors SWT, the source of the PMOS transistor not overlapping the power line TVDD of the wiring layer BSM1 in a plan view is connected to the source of the PMOS transistor connected to the TSV of the power line TVDD via the local wiring LI. Note that direct connection means that the electric conductor included in the TSV is in contact with the source, the drain, or the like of each transistor, for example, including a case where a part of a multilayer electric conductor included in the TSV is in contact with the source, the drain, or the like of the transistor when the TSV has a multilayer electric conductor.

[0057] In the switching transistors SWT, the drain of the PMOS transistor overlapping the virtual power line VVDD of the wiring layer BSM1 in a plan view is directly connected to the virtual power line VVDD of the wiring layer BSM1 via the TSV. In the switching transistors SWT, the drain of the PMOS transistor not overlapping the virtual power line VVDD of the wiring layer BSM1 in a plan view is connected to the drain of the PMOS transistor connected to the TSV of the virtual power line VVDD via the local wiring LI.

[0058] The control circuit CNTL is arranged at a position overlapping the dummy power line VVDD and the ground line VSS of the wiring layer BSM1 in a plan view. The source of the NMOS transistor of the control circuit CNTL is directly connected to the ground line VSS of the wiring layer BSM1 via the TSV. On the other hand, the control circuit CNTL is not arranged at a position overlapping the power line TVDD of the wiring layer BSM1 in a plan view. Therefore, the TSV (TVDD) cannot be directly connected to the source of the PMOS transistor of the control circuit CNTL (inverters IV1, IV2).

[0059] To this end, the source of the PMOS transistor of the control circuit CNTL is electrically connected to the source of the PMOS transistor of the switching transistor SWT via the local wiring LI and the Mint wiring. Thereby, the source of the PMOS transistor of the control circuit CNTL can be electrically connected to the power line TVDD of the wiring layer BSM1. The PMOS transistor of the inverters IV1, IV2 is an example of the second transistor formed above the substrate SUB. Note that the source of the PMOS transistor of the control circuit CNTL can also be electrically connected to the source of the PMOS transistor of the switching transistor SWT via a wiring layer higher than the Mint wiring.

[0060] In other words, the source of the PMOS transistor of the control circuit CNTL can be electrically connected to the power line TVDD of the wiring layer BSM1 without depending on the layout of the power line TVDD on the wiring layer BSM1 formed on the back surface BS side of the substrate SUB. As a result, the layout freedom of the power supply switching circuit PSW can be improved compared to a case where the source of the PMOS transistor is connected to the power line TVDD without using the local wiring LI and the Mint wiring.

[0061] The source of the PMOS transistor of the inverter IV arranged in the standard cell SC is directly connected to the dummy power line VVDD of the wiring layer BSM1 via the TSV. The source of the NMOS transistor of the inverter IV arranged in the standard cell SC is directly connected to the ground line VSS of the wiring layer BSM1 via the TSV.

[0062] Note that although the control circuit CNTL (inverters IV1, IV2) is included in the power supply switching circuit PSW, it can also be arranged separately from the power supply switching circuit PSW. In this case, the power supply switching circuit PSW and the control circuit CNTL can be designed as different units. In addition, a plurality of power supply switching circuits PSW can also be controlled by one control circuit CNTL.

[0063] Note that the power line TVDD and ground line VSS of cabling layer BSM1 are respectively connected to the corresponding power line TVDD and ground line VSS in cabling layer BSM2 (not shown). Alternatively, if cabling layer BSM2 is configured with a virtual power line VVDD, it can also be connected to the virtual power line VVDD in cabling layer BSM1.

[0064] Figure 6 Show along Figure 5 An example of the cross-section of line X1-X2. The ground line VSS formed on the wiring layer BSM1 on the back side BS is connected to the source S (N-type impurity region) of the NMOS transistor formed on the surface FS via TSV formed on the substrate SUB. Similarly, the power line TVDD formed on the wiring layer BSM1 on the back side BS is connected to the source S (P-type impurity region) of the PMOS transistor formed on the surface FS via TSV formed on the substrate SUB.

[0065] In each fin (FIN), a channel C is disposed between the source (S) and drain (D). A gate GT is disposed on the channel C via a gate insulating film (not shown). The output signal OUT0 from the inverter IV1 of the control circuit CNTL is supplied to the gate GT of the PMOS transistor in the power switch circuit PSW via local wiring LI, mint wiring, and local wiring LI. Note that in Figure 6 In the middle, two cabling layers BSM1 and BSM2 are configured on the BS side of the back, but more than three cabling layers BSM can also be configured.

[0066] Figure 7 Show along Figure 5 Another example of the cross-section of the X1-X2 line. Apart from the fact that the wiring layer BSM1 is formed below the substrate SUB on the back BS side of the substrate SUB, Figure 7 and Figure 6 Their cross-sectional structures are the same. Note that... Figure 7 The wiring layer BSM1 shown is different from the buried wiring BPR which is buried on the surface FS side of the substrate SUB. Figure 2 Alternatively, the wiring layer BSM1 may not be exposed to the back side BS of the substrate SUB, but may be formed inside the substrate SUB below.

[0067] Figure 8 Show along Figure 5 Another example of the cross-section along line X1-X2. Besides the fact that the transistors formed on the substrate SUB are nanosheet FETs, Figure 8 and Figure 5The cross-sectional structure is the same as that of the fin FET. The nanosheet FET includes a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on a surface of the nanosheet NS. Note that the nanosheet FET can also be provided instead of the fin FET shown in FIG. 1. Figure 7 The cross-sectional structure is the same as that of the fin FET. The nanosheet FET includes a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on a surface of the nanosheet NS. Note that the nanosheet FET can also be provided instead of the fin FET shown in FIG. 1.

[0068] Figure 9 The cross-sectional structure is the same as that of the fin FET. The nanosheet FET includes a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on a surface of the nanosheet NS. Note that the nanosheet FET can also be provided instead of the fin FET shown in FIG. 1. Figure 3 The cross-sectional structure is the same as that of the fin FET. The nanosheet FET includes a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on a surface of the nanosheet NS. Note that the nanosheet FET can also be provided instead of the fin FET shown in FIG. 1. Figure 5 The cross-sectional structure is the same as that of the fin FET. The nanosheet FET includes a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on a surface of the nanosheet NS. Note that the nanosheet FET can also be provided instead of the fin FET shown in FIG. 1. Figure 5 The cross-sectional structure is the same as that of the fin FET. The nanosheet FET includes a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on a surface of the nanosheet NS. Note that the nanosheet FET can also be provided instead of the fin FET shown in FIG. 1. Figure 9 The cross-sectional structure is the same as that of the fin FET. The nanosheet FET includes a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on a surface of the nanosheet NS. Note that the nanosheet FET can also be provided instead of the fin FET shown in FIG. 1. Figure 5 The cross-sectional structure is the same as that of the fin FET. The nanosheet FET includes a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on a surface of the nanosheet NS. Note that the nanosheet FET can also be provided instead of the fin FET shown in FIG. 1.

[0069] The cross-sectional structure is the same as that of the fin FET. The nanosheet FET includes a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on a surface of the nanosheet NS. Note that the nanosheet FET can also be provided instead of the fin FET shown in FIG. 1.

[0070] The cross-sectional structure is the same as that of the fin FET. The nanosheet FET includes a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on a surface of the nanosheet NS. Note that the nanosheet FET can also be provided instead of the fin FET shown in FIG. 1.

[0071] The cross-sectional structure is the same as that of the fin FET. The nanosheet FET includes a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on a surface of the nanosheet NS. Note that the nanosheet FET can also be provided instead of the fin FET shown in FIG. 1.

[0072] The cross-sectional structure is the same as that of the fin FET. The nanosheet FET includes a semiconductor layer having a source S and a drain D, a nanosheet NS having a semiconductor material formed between the source S and the drain D, and a gate GT formed via a gate insulating film (not shown) provided on a surface of the nanosheet NS. Note that the nanosheet FET can also be provided instead of the fin FET shown in FIG. 1.

[0073] Note that the control circuit CNTL (inverters IV1, IV2) can also be configured separately from the power supply switching circuit PSW. In this case, the power supply switching circuit PSW and the control circuit CNTL can be designed as different units. A plurality of power supply switching circuits PSW can also be controlled by one control circuit CNTL.

[0074] Note that the dummy power supply line VVDD, the power supply line TVDD, and the ground line VSS of the wiring layer BSM1 are each connected to the corresponding dummy power supply line VVDD, power supply line TVDD, and ground line VSS in the wiring layer BSM2 (not shown). Note that the dummy power supply line VVDD can also not be provided in the wiring layer BSM2.

[0075] Figure 10 A second modification example of the layout of the power supply switching circuit PSW is shown in FIG. 17. In this example, the control circuit CNTL is arranged between the two switching transistors SWT in the X direction in the plan view. Figure 3 Figure 10 In this example, the switching transistor SWT and the control circuit CNTL are arranged in the Y direction in the plan view. As in the example shown in FIG. 16, the switching transistor SWT is arranged at a position overlapping with the dummy power supply line VVDD and the power supply line TVDD of the wiring layer BSM1 in the plan view. The control circuit CNTL is arranged at a position overlapping with the dummy power supply line VVDD and the ground line VSS of the wiring layer BSM1 in the plan view. Figure 5

[0076] The control circuit CNTL (inverters IV1, IV2) is not arranged at a position overlapping with the power supply line TVDD of the wiring layer BSM1 in the plan view. Thus, the source of the PMOS transistor of the control circuit CNTL is electrically connected to the source of the PMOS transistor of the switching transistor SWT via the local wiring LI. As a result, the source of the PMOS transistor of the control circuit CNTL can be electrically connected to the power supply line TVDD of the wiring layer BSM1.

[0077] Note that the control circuit CNTL (inverters IV1, IV2) can also be configured separately from the power supply switching circuit PSW. In this case, the power supply switching circuit PSW and the control circuit CNTL can be designed as different units. In addition, a plurality of power supply switching circuits PSW can be controlled by one control circuit CNTL.

[0078] Figure 11 A third modification example of the layout of the power supply switching circuit PSW is shown in FIG. 18. In this example, the control circuit CNTL is arranged between the two switching transistors SWT in the X direction. Figure 3 Figure 11 In this example, the control circuit CNTL is arranged between the two switching transistors SWT in the X direction. The output signal OUT0 output from the primary inverter IV1 of the control circuit CNTL is commonly supplied to the gates of the PMOS transistors of the two switching transistors SWT via the Mint wiring.

[0079] ​​​The two switching transistors SWT and the control circuit CNTL are configured with two intervals ROW. Note that one or both of the two switching transistors SWT and the control circuit CNTL can be configured at positions different from each other in the Y direction. For example, each of the switching transistors SWT and the control circuit CNTL is designed as a unit different from each other.

[0080] The layout of the elements of each of the switching transistors SWT is the same as that of the switching transistor SWT of Figure 10 The layout of the elements of the control circuit CNTL is the same as that of the control circuit CNTL of Figure 10

[0081] In Figure 11 as well, the control circuit CNTL is not configured at a position overlapping the power supply line TVDD of the wiring layer BSM1 in a plan view. Therefore, the source of the PMOS transistor of the control circuit CNTL is electrically connected to the source of the PMOS transistor of the switching transistor SWT via the Mint wiring and the local wiring LI. Thereby, the source of the PMOS transistor of the control circuit CNTL can be electrically connected to the power supply line TVDD of the wiring layer BSM1.

[0082] Figure 12 A fourth modification example of the layout of the power supply switching circuit PSW of Figure 3 In Figure 12 , the switching transistors SWT and the control circuit CNTL are arranged in the Y direction in a plan view. The layout of the elements of the switching transistors SWT is the same as that of the switching transistor SWT of Figure 10 The layout of the elements of the control circuit CNTL is the same as that of the control circuit CNTL of Figure 10

[0083] In Figure 12 , by respectively breaking the ground line VSS and the dummy power supply line VVDD of the wiring layer BSM1, vacant regions are provided in which two power supply lines TVDD are arranged in the Y direction. That is, the ground line VSS and the power supply line TVDD are alternately arranged in the X direction, and the dummy power supply line VVDD and the power supply line TVDD are alternately arranged in the X direction.

[0084] Thereby, the source of the PMOS transistor of the control circuit CNTL (inverters IV1, IV2) can be directly connected to the power supply line TVDD of the wiring layer BSM1 via the TSV. Note that the two power supply lines TVDD of the wiring layer BSM1 can be collectively arranged as one power supply line TVDD.

[0085] Figure 13 A fourth modification example of the layout of the power supply switching circuit PSW of​​Figure 3 a fifth modification of the layout of the power supply switching circuit PSW. Figure 13 The power supply switching circuit PSW illustrated in FIG. 17 is the same as the power supply switching circuit PSW illustrated in FIG. 16 except that the N-type well tap region NWTP and the P-type well tap region PWTP are arranged between the switching transistor SWT and the control circuit CNTL in the X direction. Figure 5

[0086] The well tap regions NWTP and PWTP are arranged in the X direction. The power supply switching circuit PSW has the same structure as the power supply switching circuit PSW illustrated in FIG. 16 except that the well tap regions NWTP and PWTP are arranged. The well tap region NWTP is an example of the first well tap region, and the well tap region PWTP is an example of the second well tap region. Note that although the well tap regions NWTP and PWTP are arranged between the switching transistor SWT and the control circuit CNTL in the X direction in the power supply switching circuit PSW illustrated in FIG. 16, the arrangement is not limited thereto. For example, the well tap region PWTP can be arranged at a position overlapping with the P-type well region PW on the side opposite to the position overlapping with the control circuit CNTL in the X direction. Figure 5 Figure 13

[0087] The well tap region NWTP is arranged at a position overlapping with the power supply line TVDD of the wiring layer BSM1 in a plan view. The well tap region NWTP is formed of an NMOS transistor whose source and drain are directly connected to the power supply line TVDD of the wiring layer BSM1 via a TSV. Thus, the N-type well region NW, which is a substrate region (a hatched region) of a PMOS transistor, can be supplied with the power supply potential TVDD. The TSV directly connected to the source and the drain of the well tap region NWTP is an example of the second via.

[0088] The well tap region PWTP is arranged at a position overlapping with the ground line VSS of the wiring layer BSM1 in a plan view. The well tap region PWTP is formed of a PMOS transistor whose source and drain are directly connected to the ground line VSS of the wiring layer BSM1 via a TSV. Thus, the P-type well region PW, which is a substrate region (a region other than a hatched region) of an NMOS transistor, can be supplied with the ground potential VSS. The NMOS transistor is an example of a third transistor whose conductivity type is opposite to that of the PMOS transistor. The TSV directly connected to the source and the drain of the well tap region PWTP is an example of the third via.

[0089] Note that the well region NW is an N-type impurity region formed in the substrate SUB and is electrically connected to a channel of a fin-type FET (PMOS). The well region PW is a P-type substrate SUB or a P-type impurity region formed in the substrate SUB and is electrically connected to a channel of a fin-type FET (NMOS).

[0090] ​​​As described above, in the first embodiment, even if the source of the PMOS transistor is not configured at a position overlapping the power supply line TVDD of the wiring layer BSM1 in a plan view, the source of the PMOS transistor can be electrically connected to the power supply line TVDD of the wiring layer BSM1. As a result, compared to a case where the source of the PMOS transistor is connected to the power supply line TVDD without using the local wiring LI and the Mint wiring, the degree of freedom of layout of the power supply switching circuit PSW can be improved.

[0091] By dispersively configuring the power supply line TVDD at a position where the ground line VSS is cut off, a dedicated area for the power supply line TVDD having a width of the interval ROW can not be needed. In addition, the power supply line TVDD can be configured only at a position where the power supply switching circuit PSW is configured. Thereby, compared to a case where a dedicated area for the power supply line TVDD having a width of the interval ROW is provided, the configuration density of the virtual power supply line VVDD and the ground line VSS in the wiring layer BSM1 can be improved, and thus the power supply capability to the standard cell SC can be improved.

[0092] By directly connecting the source and the drain of the NMOS transistor forming the well tap region NWTP to the power supply line TVDD of the wiring layer BSM1 via the TSV, the power supply potential TVDD can be supplied to the well region NW from the back surface BS side of the substrate SUB. By directly connecting the source and the drain of the PMOS transistor forming the well tap region PWTP to the ground line VSS of the wiring layer BSM1 via the TSV, the ground potential VSS can be supplied to the well region PW from the back surface BS side of the substrate SUB.

[0093] Figure 14 An example of the layout of the power supply line configured on the back surface side of the semiconductor substrate in the semiconductor device of the second embodiment is shown. The same elements as those of Figure 4 are assigned with the same symbols, and detailed description is omitted.

[0094] In Figure 14 , the ground line VSS of the wiring layer BSM1 is formed so as to extend along the X direction without interruption. Between a pair of ground lines VSS adjacent to each other in the Y direction, a virtual power supply line VVDD extending along the X direction and being interrupted at a plurality of positions in the middle and a power supply line TVDD configured at a position where the virtual power supply line VVDD is interrupted are alternately configured along the X direction. The power supply switching circuits PSW shown by the thick dashed line frame are staggered (Manazashi-shaped) configured. Figure 14 The other structures of Figure 4 are the same as those of

[0095] By dispersively configuring the power supply line TVDD at a position where the virtual power supply line VVDD is interrupted, as in Figure 4As shown, it is possible to not need a dedicated region for the power supply line TVDD having the width of the interval ROW. In addition, it is possible to configure the power supply line TVDD only at a position where the power switch circuit PSW is configured. Thereby, compared with a case where a dedicated region for the power supply line TVDD having the width of the interval ROW is provided, it is possible to improve the configuration density of the virtual power supply line VVDD and the ground line VSS in the wiring layer BSM1, and thereby it is possible to improve the power supply capability to the standard cell SC.

[0096] Figure 15 An example of a layout of the power switch circuit PSW is shown. The same elements as those of Figure 14 will be assigned with the same symbols, and detailed description will be omitted. In the power switch circuit PSW, the switching transistor SWT and the control circuit CNTL are arranged in the X direction in a plan view. Figure 5

[0097] The PMOS transistor of the switching transistor SWT is configured at a position overlapping with the virtual power supply line VVDD and the power supply line TVDD of the wiring layer BSM1 in a plan view. The control circuit CNTL is configured at a position overlapping with the power supply line TVDD and the ground line VSS of the wiring layer BSM1 in a plan view. The layout of the inverter IV configured in the standard cell SC is the same as the layout of the inverter IV configured in the standard cell SC of Figure 5 .

[0098] In the switching transistor SWT, the source of the PMOS transistor configured at a position overlapping with the power supply line TVDD of the wiring layer BSM1 is directly connected to the power supply line TVDD of the wiring layer BSM1 via a TSV. In the switching transistor SWT, the source of the PMOS transistor configured at a position overlapping with the virtual power supply line VVDD of the wiring layer BSM1 in a plan view is electrically connected to the source of the PMOS transistor connected to the TSV via a local wiring LI and a Mint wiring. Further, in the switching transistor SWT, in a region overlapping with the ground line VSS of the wiring layer BSM1 in a plan view, a dummy transistor DMY (NMOS) is configured.

[0099] In the control circuit CNTL, the source of the PMOS transistor of the inverters IV1, IV2 is directly connected to the power supply line TVDD of the wiring layer BSM1 via a TSV. In the control circuit CNTL, the source of the NMOS transistor of the inverters IV1, IV2 is directly connected to the ground line VSS of the wiring layer BSM1 via a TSV.

[0100] Note that, in Figure 15 , although the switching transistor SWT and the control circuit CNTL are arranged in the X direction in a plan view, as Figure 10 or Figure 12 ​As shown, the switching transistor SWT and the control circuit CNTL can also be arranged in the Y direction in the plan view.

[0101] Figure 16 A modification of the layout of the power supply switching circuit PSW is shown. Figure 14 The same elements as those of the power supply switching circuit PSW of Figure 13 will be assigned the same symbols, and detailed description will be omitted. Figure 16 The power supply switching circuit PSW shown is the same as the power supply switching circuit PSW of Figure 15 except that N-type well tap regions NWTP and P-type well tap regions PWTP are arranged between the switching transistor SWT and the control circuit CNTL arranged in the X direction. The well tap regions NWTP, PWTP are arranged in the Y direction.

[0102] The well tap region NWTP is arranged at a position overlapping the power supply line TVDD of the wiring layer BSM1 in the plan view. The well tap region NWTP is formed of an NMOS transistor whose source and drain are directly connected to the power supply line TVDD of the wiring layer BSM1 via a TSV. Thereby, the N-type well region NW, which is a substrate region of a PMOS transistor (hatched region), can be supplied with the power supply potential TVDD.

[0103] The well tap region PWTP is arranged at a position overlapping the ground line VSS of the wiring layer BSM1 in the plan view. The well tap region PWTP is formed of a PMOS transistor whose source and drain are directly connected to the ground line VSS of the wiring layer BSM1 via a TSV. Thereby, the P-type well region PW, which is a substrate region of an NMOS transistor (region other than the hatched region), can be supplied with the ground potential VSS.

[0104] As described above, the second embodiment can also achieve the same effects as the first embodiment. For example, even in the case where the power supply line TVDD of the wiring layer BSM1 is arranged dispersedly, the source of the PMOS transistor can be electrically connected to the power supply line TVDD of the wiring layer BSM1, and thus the degree of freedom of the layout of the power supply switching circuit PSW can be improved. By arranging the power supply line TVDD dispersedly at a position where the ground line VSS is cut off, the arrangement density of the virtual power supply line VVDD and the ground line VSS in the wiring layer BSM1 can be improved, and thus the power supply capability to the standard cell SC can be improved.

[0105] The present application has been described based on each embodiment above, but the present application is not limited to the elements shown in the above embodiments. With respect to these points, changes can be made within a range not impairing the gist of the present application, and can be appropriately determined in accordance with the application mode thereof.

[0106] Symbol Explanation

[0107] 100 semiconductor device

[0108] BPR Buried routing

[0109] BS Backside

[0110] BSM1, BSM2 Routing layers

[0111] C Channel

[0112] CNTL Control circuit

[0113] D Drain

[0114] DMY Dummy transistor

[0115] FIN Fin

[0116] FS Surface

[0117] GT Gate

[0118] INTR Internal circuit region

[0119] IOC, IOCPI / O unit

[0120] IV, IV1, IV2 Inverter

[0121] LI Local routing

[0122] Mint Routing

[0123] NW Well region

[0124] NWTP Well tap region

[0125] OUT, OUT0 Output signal

[0126] PAD Pad

[0127] PSW Power switch circuit

[0128] PW Well region

[0129] PWTP Well tap region

[0130] ROW Spacing

[0131] S Source

[0132] SC Standard cell

[0133] SCB Standard cell block

[0134] SIG Signal

[0135] SUB Substrate

[0136] SWT Switch transistor

[0137] TR Transistor region

[0138] TVDD power cord

[0139] VIA, VIA1, VIA2 through holes

[0140] VSS grounding wire

[0141] VVDD Virtual Power Line

[0142] W1, W2 wiring

[0143] WL1 and WL2 wiring layers

Claims

1. A semiconductor device comprising: a substrate over which a first via is formed; a first power supply line, a second power supply line, and a third power supply line formed under the substrate, the first power supply line being supplied with a first potential, the second power supply line being supplied with a second potential, and the third power supply line being supplied with a third potential; and a power supply switching circuit having a first transistor and a second transistor, the first transistor being formed over the substrate and electrically connected between the first power supply line and the second power supply line, and the second transistor being formed over the substrate, the first power supply line, the second power supply line, and the third power supply line each extending in a first direction in a plan view, the first transistor has a first source and a first drain, the first transistor is arranged at a position overlapping with the first power supply line in a plan view, the first source is connected to the first via connected to the first power supply line, the second transistor has a second source and a second drain, the second transistor is arranged at a position overlapping with the second power supply line in a plan view, the second source is electrically connected to the first source via a wiring formed over the substrate.

2. The semiconductor device according to claim 1, wherein the third power supply line extends in the first direction and is interrupted at a plurality of positions in the way, the first power supply line is arranged in a region where the third power supply line is interrupted, the second power supply line is arranged in a region adjacent to the third power supply line and the first power supply line arranged in the first direction.

3. The semiconductor device according to claim 1, wherein the second power supply line extends in the first direction and is interrupted at a plurality of positions in the way, the first power supply line is arranged in a region where the second power supply line is interrupted, the third power supply line is arranged in a region adjacent to the second power supply line and the first power supply line arranged in the first direction.

4. The semiconductor device according to any one of claims 1 to 3, wherein a control circuit is connected to a gate of the first transistor, comprising: the second transistor is included in the control circuit.

5. The semiconductor device according to any one of claims 1 to 3, wherein the second transistor is electrically connected between the first power supply line and the second power supply line.

6. The semiconductor device according to any one of claims 1 to 3, wherein the first transistor and the second transistor are arranged in the first direction.

7. The semiconductor device according to any one of claims 1 to 3, wherein the first transistor and the second transistor are arranged in a second direction different from the first direction in a plan view.

8. The semiconductor device according to any one of claims 1 to 3, wherein a first well tap region is arranged at a position overlapping with the first power supply line in a plan view over the substrate and connected to a second via formed on the substrate, the first well tap supplying the first potential to a first well of the first transistor and the second transistor, includes: the second via is connected to the first power supply line. ​ 9. The semiconductor device according to any one of Claims 1 to 3, wherein includes: a second well tap region which is configured at a position coinciding with the third power supply line in a plan view on the upper side of the substrate, and which is connected to a third via hole formed on the substrate, supplies a second well of a third transistor having a conductivity type opposite to that of the first transistor with the third potential, the third via hole is connected to the third power supply line.

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