Signal-to-noise ratio improving system for magnetic resonance imaging and electronic equipment

Abstract

The invention relates to a signal-to-noise ratio improving system for magnetic resonance imaging and electronic equipment, and the system comprises a plurality of collection circuits, a standard signal generation circuit and an FPGA, the standard signal generation circuit is connected with each collection circuit and the FPGA, the standard signal generation circuit is used for converting a standard digital signal output by the FPGA into an analog signal, and the analog signal is used for outputting the analog signal. The analog signals are divided into multiple paths and are respectively input into each acquisition circuit; the acquisition circuit is used for conditioning the analog signal to obtain an actual digital signal; and the FPGA is used for generating a standard digital signal and performing gain calibration and delay compensation on each acquisition circuit according to an analog signal when an actual digital signal is received so as to improve the signal-to-noise ratio of magnetic resonance imaging. The problem of how to improve the signal-to-noise ratio while the imaging requirement is met is solved.

Description

Technical Field

[0001] This application relates to the field of magnetic resonance imaging technology, and in particular to a signal-to-noise ratio improvement system and electronic device for magnetic resonance imaging. Background Technology

[0002] Signal-to-noise ratio (SNR) is a core indicator for measuring the quality of magnetic resonance imaging (MRI). The higher the SNR value, the clearer the image, which is crucial for clinical diagnosis.

[0003] Currently, the signal-to-noise ratio (SNR) can be improved by adjusting imaging device parameters such as voxel size, average number of acquisitions, and sampling bandwidth. However, improving SNR through parameter adjustments conflicts with imaging requirements. For example, increasing the voxel size improves SNR but reduces spatial resolution; increasing the average number of acquisitions or decreasing the sampling bandwidth, while improving SNR to some extent, significantly increases imaging time, conflicting with the need for rapid imaging. Therefore, how to effectively improve the SNR of magnetic resonance imaging (MRI) images while meeting high-end imaging requirements such as ultra-thin slice thickness and rapid imaging—in other words, how to improve SNR while meeting imaging needs—has become a pressing issue for the development of MRI technology.

[0004] There is currently no effective solution to the above problems. Summary of the Invention

[0005] This application provides a signal-to-noise ratio (SNR) improvement system and electronic device for magnetic resonance imaging (MRI) to solve the aforementioned technical problem of "how to improve the SNR while meeting imaging requirements".

[0006] According to one aspect of the embodiments of this application, this application provides a signal-to-noise ratio (SNR) improvement system for magnetic resonance imaging (MRI), including: multiple acquisition circuits, a standard signal generation circuit, and an FPGA (Field-Programmable Gate Array). The standard signal generation circuit is connected to each acquisition circuit and the FPGA respectively. The standard signal generation circuit is used to convert the standard digital signal output by the FPGA into an analog signal, and to divide the analog signal into multiple paths and input them into each acquisition circuit respectively. The acquisition circuit is used to condition the analog signal to obtain an actual digital signal. The FPGA is used to generate the standard digital signal, and when receiving the actual digital signal, to perform gain calibration and delay compensation on each acquisition circuit according to the analog signal, so as to improve the SNR of MRI.

[0007] Optionally, the FPGA includes a direct digital frequency synthesizer, a gain calibration circuit, and a delay compensation circuit. The direct digital frequency synthesizer is connected to the standard signal generation circuit, the gain calibration circuit, and the delay compensation circuit, respectively, and transmits standard digital signals to the standard signal generation circuit, the gain calibration circuit, and the delay compensation circuit.

[0008] Optionally, the gain calibration circuit is used to calculate the gain difference on each acquisition circuit based on the actual digital signal and the standard digital signal, and output a gain control word to the corresponding acquisition circuit based on the gain difference so that the acquisition circuit can adjust the gain.

[0009] Optionally, the FPGA includes a delay compensation circuit for calculating the signal delay on each acquisition circuit based on the actual digital signal and the standard digital signal, and performing delay compensation based on the signal delay to ensure that the data acquired by each acquisition circuit is in phase.

[0010] Optionally, the delay compensation circuit includes multiple flip-flops, and the delay compensation circuit controls the amount of delay of the data on the acquisition circuit by adjusting the number of flip-flops used.

[0011] Optionally, the acquisition circuit includes a digital gain controller, which is connected to the FPGA. The digital gain controller is used to adjust the gain of the acquisition circuit according to the gain control word issued by the FPGA.

[0012] Optionally, the standard signal generation circuit includes a digital-to-analog converter and a power divider. The digital-to-analog converter is used to convert the standard digital signal into an analog signal, and the power divider is used to divide the analog signal into multiple paths and send them to each acquisition circuit respectively.

[0013] Optionally, the acquisition circuit also includes an amplifier, a filter, and an analog-to-digital converter. The amplifier is used to amplify the received analog signal, the filter is used to filter the amplified analog signal, and the analog-to-digital converter is used to convert the filtered analog signal into an actual digital signal.

[0014] Optionally, if the magnetic resonance signals are input into each acquisition circuit in parallel, the acquisition circuit is also used to condition the received magnetic resonance signals and input the obtained digital signals into the FPGA, so that the FPGA can perform accumulation and averaging operations on each digital signal.

[0015] According to another aspect of the embodiments of this application, this application provides an electronic device including the above-described magnetic resonance imaging signal-to-noise ratio improvement system.

[0016] Compared with related technologies, the technical solutions provided in this application have the following advantages:

[0017] This application provides a signal-to-noise ratio (SNR) improvement system for magnetic resonance imaging (MRI), comprising: multiple acquisition circuits, a standard signal generation circuit, and an FPGA. The standard signal generation circuit is connected to each acquisition circuit and the FPGA, respectively. The standard signal generation circuit converts the standard digital signal output from the FPGA into an analog signal, and divides the analog signal into multiple paths, which are then input to each acquisition circuit. The acquisition circuits condition the analog signals to obtain actual digital signals. The FPGA generates the standard digital signal and, upon receiving the actual digital signal, performs gain calibration and delay compensation on each acquisition circuit based on the analog signal, thereby improving the SNR of MRI. By dividing the original acquisition channel into multiple acquisition circuits and then performing gain calibration and delay compensation on each acquisition circuit, the data signal amplitude of each acquisition circuit remains consistent and synchronized in time. This ensures that the signals from each path can be accurately and effectively superimposed in subsequent processing, improving the SNR without affecting imaging requirements, thus solving the problem of improving the SNR while meeting imaging needs. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the composition of an optional magnetic resonance imaging signal-to-noise ratio improvement system according to an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of another optional magnetic resonance imaging signal-to-noise ratio improvement system provided according to an embodiment of this application;

[0022] Figure 3 This is a schematic diagram illustrating an optional gain calibration and delay compensation according to an embodiment of this application;

[0023] Figure 4 This is a schematic diagram of an optional FPGA data processing method provided in an embodiment of this application. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustration and has no specific meaning in itself. Therefore, "module" and "part" may be used interchangeably.

[0026] Signal-to-noise ratio (SNR) is a core indicator for measuring the quality of magnetic resonance imaging (MRI). The higher the SNR value, the clearer the image, which is crucial for clinical diagnosis.

[0027] Currently, the signal-to-noise ratio (SNR) can be improved by adjusting imaging device parameters such as voxel size, average number of acquisitions, and sampling bandwidth. However, improving SNR through parameter adjustments conflicts with imaging requirements. For example, increasing the voxel size improves SNR but reduces spatial resolution; increasing the average number of acquisitions or decreasing the sampling bandwidth, while improving SNR to some extent, significantly increases imaging time, conflicting with the need for rapid imaging. Therefore, how to effectively improve the SNR of magnetic resonance imaging (MRI) images while meeting high-end imaging requirements such as ultra-thin slice thickness and rapid imaging—in other words, how to improve SNR while meeting imaging needs—has become a pressing issue for the development of MRI technology.

[0028] To address the problems mentioned in the background art, according to one aspect of an embodiment of this application, a signal-to-noise ratio improvement system for magnetic resonance imaging is provided, such as... Figure 1 As shown, it includes: multiple acquisition circuits 101, a standard signal generation circuit 102, and an FPGA 103. The standard signal generation circuit 102 is connected to each acquisition circuit 101 and the FPGA 103 respectively. The standard signal generation circuit 102 is used to convert the standard digital signal output by the FPGA 103 into an analog signal, and to divide the analog signal into multiple paths and input them into each acquisition circuit 102 respectively. The acquisition circuit 102 is used to condition the analog signal to obtain the actual digital signal. The FPGA 103 is used to generate the standard digital signal, and when it receives the actual digital signal, to perform gain calibration and delay compensation on each acquisition circuit 102 according to the analog signal to improve the signal-to-noise ratio of magnetic resonance imaging.

[0029] The technical solution for improving the signal-to-noise ratio provided in this application mainly includes a calibration stage and a signal processing stage after calibration.

[0030] The calibration phase mainly includes gain adjustment and delay compensation steps, which can be performed simultaneously.

[0031] The gain adjustment steps are as follows: After receiving the actual digital signals returned by each acquisition circuit, the FPGA compares the actual digital signals with the original standard digital signals through the gain calibration circuit, accurately calculates the gain difference caused by hardware differences (such as inconsistent amplifier gains) of each acquisition circuit, and generates the corresponding gain control word based on the gain difference and sends it to the digital gain controller of the acquisition circuit. The digital gain controller adjusts the gain parameters of the acquisition circuit in real time according to the control word to ensure that the signal gain of each channel is consistent and avoids signal distortion or noise amplification caused by gain imbalance.

[0032] The delay compensation process is as follows: The delay compensation circuit in the FPGA calculates the signal delay of each acquisition circuit by comparing the phase difference between the actual digital signal and the standard digital signal. Since the delay compensation circuit contains multiple flip-flops, it can flexibly control the signal delay by adjusting the number of flip-flops in use. The more flip-flops in use, the longer the delay path the signal travels, thus accurately compensating for the delay differences of different acquisition circuits and ensuring that the digital signals output by all acquisition circuits are completely consistent in phase.

[0033] After gain calibration and delay compensation are completed, the signal processing stage can begin. This includes: when the magnetic resonance signal is input to each acquisition circuit in parallel, the calibrated acquisition circuit conditions the signal (including amplification, filtering, and analog-to-digital conversion) and transmits the resulting digital signal to the FPGA. The FPGA performs accumulation and averaging operations on multiple digital signals, which not only enhances the overall strength of the effective signal but also reduces the impact of random noise (noise cancels out during accumulation due to its randomness), ultimately achieving a significant improvement in the signal-to-noise ratio.

[0034] This application utilizes a standard signal generation circuit, an FPGA, and multiple acquisition circuits. The FPGA generates a standard digital signal, which is then processed by the standard signal generation circuit and input to the acquisition circuits. The FPGA then performs gain calibration and delay compensation based on the actual digital signal returned from the acquisition circuits. This approach eliminates the need to upgrade the magnet field strength, optimize the receiving coil, sacrifice resolution, or extend imaging time, effectively improving the signal-to-noise ratio of magnetic resonance imaging and meeting clinical demands for high-quality magnetic resonance imaging.

[0035] Figure 2The complete block diagram of the magnetic resonance imaging signal-to-noise ratio improvement system provided in this application is shown in the figure. The entire system includes: amplifier 201, digital gain controller 202 (i.e., VGA, Variable Gain Amplifier), filter 203, analog-to-digital converter 204 (i.e., ADC), power divider 205, digital-to-analog converter 206 (i.e., DAC), direct digital frequency synthesizer 207 (i.e., DDS), gain calibration circuit 208, and delay compensation circuit 209. Here, SIG is the input magnetic resonance signal. The direct digital frequency synthesizer 207 (i.e., DDS), gain calibration circuit 208, and delay compensation circuit 209 are all set in FPGA. The delay compensation circuit 209 is equipped with multiple DFFs (D Flip-Flop, bistable D flip-flops).

[0036] Next based on Figure 2 This plan will be explained.

[0037] As an optional embodiment, the FPGA includes a direct digital frequency synthesizer, a gain calibration circuit, and a delay compensation circuit. The direct digital frequency synthesizer is connected to the standard signal generation circuit, the gain calibration circuit, and the delay compensation circuit, respectively, and transmits standard digital signals to the standard signal generation circuit, the gain calibration circuit, and the delay compensation circuit.

[0038] The Direct Digital Synthesizer (DDS) is the core component of the FPGA that generates standard digital signals. These signals are characterized by high stability and high accuracy. This standard digital signal is transmitted to a standard signal generation circuit, providing a reference for subsequent analog signal conversion and multiplexing. Simultaneously, it is transmitted to the gain calibration circuit and delay compensation circuit, serving as the reference standard for calibration calculations. This ensures the consistency of the reference signal during calibration and avoids calibration errors caused by differences in reference signals between different modules.

[0039] Specifically, after the direct digital frequency synthesizer generates a standard digital signal, the first path is sent to the digital-to-analog converter (DAC) of the standard signal generation circuit. The DAC converts the signal into an analog signal, which is then split into multiple inputs to various acquisition circuits by a power divider. The second path is sent to the gain calibration circuit, providing it with the original standard digital signal sample. When the acquisition circuit transmits the conditioned actual digital signal to the FPGA, the gain calibration circuit uses the standard digital signal from the direct digital frequency synthesizer as a reference, compares it with the actual digital signal, calculates the gain difference, and then generates the corresponding gain control word. The third path is sent to the delay compensation circuit, which also serves as the reference for judging signal delay. The delay compensation circuit accurately determines the signal delay of each acquisition circuit by comparing the phase of the standard digital signal and the actual digital signal, and then uses multiple internal triggers to perform targeted delay compensation.

[0040] By providing a unified standard digital signal through a direct digital frequency synthesizer, the standard signal generation circuit, gain calibration circuit, and delay compensation circuit are kept highly synchronized on the signal reference. This reduces errors caused by inconsistent signal references from the source, making gain calibration and delay compensation more accurate, and further improving the system's ability to improve the signal-to-noise ratio of magnetic resonance imaging.

[0041] As an optional embodiment, the gain calibration circuit is used to calculate the gain difference on each acquisition circuit based on the actual digital signal and the standard digital signal, and output a gain control word to the corresponding acquisition circuit based on the gain difference so that the acquisition circuit adjusts the gain.

[0042] The gain calibration circuit compares and analyzes the actual digital signal with the original digital standard signal to accurately calculate the gain difference of each acquisition circuit. For example, if the gain of the standard digital signal is a certain reference value, and the gain of the actual digital signal fed back by a certain acquisition circuit deviates from this reference value, the gain calibration circuit will quantify this deviation into a specific gain difference value through a specific algorithm.

[0043] Based on the calculated gain difference, the gain calibration circuit generates the corresponding gain control word.

[0044] The gain calibration circuit transmits the generated gain control word to the digital gain controller in the corresponding acquisition circuit. The digital gain controller performs precise gain adjustment according to the instructions of the control word, so that the data gain acquired by each acquisition circuit is completely consistent, effectively improving the signal-to-noise ratio of magnetic resonance imaging.

[0045] As an optional embodiment, the FPGA includes a delay compensation circuit for calculating the signal delay on each acquisition circuit based on the actual digital signal and the standard digital signal, and performing delay compensation based on the signal delay to ensure that the data acquired by each acquisition circuit is in phase.

[0046] The delay compensation circuit compares the phase information of the actual digital signal with that of the original digital standard signal to calculate the signal delay of each acquisition circuit. Due to differences in hardware parameters in the amplification, filtering, and analog-to-digital conversion stages that the signal passes through in different acquisition circuits, the actual digital signal reaching the FPGA will be offset on the time axis. This offset is the signal delay.

[0047] After determining the signal delay of each acquisition circuit, the delay compensation circuit can utilize the hardware resources inside the FPGA to perform targeted delay compensation.

[0048] This delay compensation mechanism effectively solves the problem of asynchronous signal transmission in multi-channel acquisition systems, laying the foundation for subsequent FPGA-based accumulation and averaging of multiple digital signals, and helping to further improve the signal-to-noise ratio of magnetic resonance images. Simultaneously, this method of compensation through data delay within the FPGA eliminates the need for additional external hardware, fully utilizing the programmability of the FPGA. It offers advantages such as high flexibility and low cost, and can work in conjunction with gain calibration circuits to jointly optimize the signal quality of magnetic resonance imaging.

[0049] As an optional embodiment, the delay compensation circuit includes multiple flip-flops, which control the amount of delay in the data acquisition circuit by adjusting the number of flip-flops used.

[0050] The delay compensation circuit provided in this application includes multiple flip-flops. By adjusting the number of enabled hardware units and the timing logic, the data transmission delay can be precisely controlled.

[0051] Using synchronous D flip-flops as the basic unit (the mainstream choice is edge-triggered type), the output signal only follows the input signal on the rising (or falling) edge of the clock. Each flip-flop can stably introduce a delay of one clock cycle (Tclk). When multiple flip-flops are cascaded, the data is passed step by step along the cascade path: the input data first enters the first stage flip-flop, is latched on the first clock edge and output to the second stage; the second stage flip-flop latches the data on the second clock edge and passes it to the third stage... and so on. The total delay is the number of flip-flops (N) × clock cycle (Tclk).

[0052] For example, if the signal delay of one acquisition circuit is 5ns, the delay compensation circuit will apply an additional 5ns delay to the digital signal acquired on that circuit; if the delay of another circuit is 3ns, then a 3ns delay will be applied. Through this differentiated compensation method, the digital signals output by all acquisition circuits are synchronized in time, thereby ensuring that the data phase is completely consistent.

[0053] The FPGA calculates the gain difference ΔRG of the acquisition circuit by comparing the standard digital signal (generated by the internal DDS and injected into the acquisition circuit via DAC and power divider) with the signal data returned by the acquisition circuit. It then generates the corresponding gain control word (RG+ΔRG). After receiving the control word, the digital gain controller dynamically adjusts its own gain parameters to compensate for the inherent gain deviation of the hardware channel. Ultimately, it ensures that the signal gain output by each acquisition circuit is consistent with the standard signal, providing a consistent input basis for subsequent multi-channel data synthesis.

[0054] Figure 3 The diagram illustrates the gain calibration and delay compensation provided in this application. During the calibration phase, each acquisition circuit is initially assigned the same initial receiving gain RG. Simultaneously, the DDS outputs a DDS_DATA (corresponding to the standard digital signal of this application) as an internal standard reference signal for the FPGA. The data ADC_DATA (corresponding to the actual digital signal of this application) acquired by each acquisition circuit via the ADC is sent to the FPGA. Upon entering the FPGA, each ADC_DATA is first compared with the standard DDS_DATA to calculate the gain difference ΔRG, and the corresponding adjusted gain RG+ΔRG is output. Then, the delay of each acquired data ADC_DATA is compared with the standard DDS_DATA, and the delay time of each channel is adjusted for delay compensation, ensuring that the phase of each output data channel remains consistent. The data after gain calibration and delay compensation can then undergo digital down-conversion (DDC) processing.

[0055] As an optional embodiment, the acquisition circuit includes a digital gain controller, which is connected to the FPGA. The digital gain controller is used to adjust the gain of the acquisition circuit according to the gain control word issued by the FPGA.

[0056] The digital gain controller provided in this application is a variable gain amplifier (VGA).

[0057] For example, the digital gain controller is 6-bit and has an adjustment precision of 0.5dB. Therefore, the gain control word will generate corresponding instructions to drive the digital gain controller to make the corresponding adjustments based on the magnitude of the gain difference. For instance, when it is calculated that a certain acquisition circuit needs to increase its gain by 2dB, the gain control word will instruct the digital gain controller of that circuit to perform four 0.5dB gain boost operations; if a 1dB gain reduction is needed, the gain control word will instruct the digital gain controller to perform two 0.5dB gain reduction operations, ensuring that the gain adjustment strictly falls within the range of -9.5dB to 22dB.

[0058] As an optional embodiment, the standard signal generation circuit includes a digital-to-analog converter and a power divider. The digital-to-analog converter is used to convert a standard digital signal into an analog signal, and the power divider is used to divide the analog signal into multiple paths and send them to each acquisition circuit respectively.

[0059] The digital-to-analog converter (DAC) and power divider in the standard signal generation circuit, together with the DDS in the FPGA, form a signal chain.

[0060] The digital-to-analog converter converts the digital standard signal output by the DDS into an analog signal, ensuring that it can meet the analog input requirements of the acquisition circuit.

[0061] After receiving the analog standard signal output by the digital-to-analog converter, the power divider divides it into multiple channels with equal amplitude and in phase (the number of channels is the same as the number of acquisition circuits), and sends them to the signal input terminal of each acquisition circuit, so that each acquisition circuit can receive the same standard reference signal synchronously.

[0062] As an optional embodiment, the acquisition circuit also includes an amplifier, a filter, and an analog-to-digital converter. The amplifier is used to amplify the received analog signal, the filter is used to filter the amplified analog signal, and the analog-to-digital converter is used to convert the filtered analog signal into an actual digital signal.

[0063] Amplifiers are used to amplify analog signals to ensure that the signal amplitude meets the processing requirements of subsequent analog-to-digital converters (ADCs).

[0064] Filter modules are used to filter out noise and clutter, and purify the frequency components of analog signals.

[0065] Analog-to-digital converters are used to convert conditioned analog signals into digital signals, preparing them for subsequent digital processing by the FPGA.

[0066] As an optional embodiment, if the magnetic resonance signals are input into each acquisition circuit in parallel, the acquisition circuit is also used to condition the received magnetic resonance signals and input the obtained digital signals into the FPGA, so that the FPGA can perform accumulation and averaging operations on each digital signal.

[0067] The steps by which the acquisition circuit conditions the received magnetic resonance signal are similar to those of the acquisition circuit for processing analog signals, and will not be described in detail here.

[0068] The FPGA receives multiple synchronized digital signals, performs accumulation and averaging operations, adds N signals within the same period point by point and divides by N to generate a single synthesized signal, and then performs digital signal processing such as digital downconversion (DDC). For example, a quadrature local oscillator signal is generated by a numerically controlled oscillator, multiplied by the synthesized signal, and then low-pass filtered to shift the signal to baseband (zero intermediate frequency or low intermediate frequency) for subsequent spectral analysis or data demodulation.

[0069] This application employs a time-domain linear averaging method at the receiver end to effectively improve the system signal-to-noise ratio. That is, within the same time period, two or more signals are acquired simultaneously, and then the two or more signals are added together and averaged.

[0070] Figure 4 The FPGA data processing diagram provided in this application is shown in the figure. The average of n signals (ADC1, ADC2, ..., ADCn) is calculated and the obtained data is processed by digital downconversion (DDC).

[0071] It should be noted that the data acquired by the acquisition circuit in this scheme includes both amplitude and phase, so it is not necessary to accumulate and average the amplitude and phase separately.

[0072] The conventional formula for calculating signal-to-noise ratio (SNR) is: SNR = Psig / Pnoise, where Psig represents the effective signal power of a single channel and Pnoise represents the noise power of a single channel.

[0073] In the technical solution provided in this application, since the input signals of the multi-channel acquisition circuit come from the same signal and each circuit is exactly the same, the acquired signals are also exactly the same. After averaging, the average signal is the same as the signal power of each channel, as shown in the following formula:

[0074]

[0075] Where Psig_aveage represents the power after averaging. This represents the total power after accumulation, and n represents the total number of acquisition circuits.

[0076] However, the noise in each circuit is different. Therefore, the average noise of two or more circuits theoretically approaches zero, and the more average values ​​there are, the closer it gets to zero. So, the average noise of two or more circuits is less than the noise of each individual circuit, as shown in the following formula:

[0077]

[0078] Where Pnoise_aveage represents the averaged noise power.

[0079] This represents the total noise power after accumulation.

[0080] SNRaveage = Psig_aveage / Pnoise_average > SNR. Therefore, in the technical solution of this application, the signal-to-noise ratio is significantly improved after averaging multiple channels.

[0081] In this application, one magnetic resonance signal is simultaneously input to two or more identical acquisition circuits. The delay and gain of the two or more acquisition circuits remain consistent, which facilitates subsequent digital signal synthesis and processing. After being acquired by the ADC, the two or more signals are input to the FPGA for corresponding digital signal processing.

[0082] This application provides a signal-to-noise ratio (SNR) improvement system for magnetic resonance imaging (MRI), comprising: multiple acquisition circuits, a standard signal generation circuit, and an FPGA. The standard signal generation circuit is connected to each acquisition circuit and the FPGA, respectively. The standard signal generation circuit converts the standard digital signal output from the FPGA into an analog signal, and divides the analog signal into multiple paths, which are then input to each acquisition circuit. The acquisition circuits condition the analog signals to obtain actual digital signals. The FPGA generates the standard digital signal and, upon receiving the actual digital signal, performs gain calibration and delay compensation on each acquisition circuit based on the analog signal, thereby improving the SNR of MRI. By dividing the original acquisition channel into multiple acquisition circuits and then performing gain calibration and delay compensation on each acquisition circuit, the data signal amplitude of each acquisition circuit remains consistent and synchronized in time. This ensures that the signals from each path can be accurately and effectively superimposed in subsequent processing, improving the SNR without affecting imaging requirements, thus solving the problem of improving the SNR while meeting imaging needs.

[0083] According to another aspect of the embodiments of this application, this application provides an electronic device including the above-described magnetic resonance imaging signal-to-noise ratio improvement system.

[0084] Optionally, specific examples in this embodiment can refer to the examples described in the above embodiments, and will not be repeated here.

[0085] In specific implementation, the embodiments of this application can be referred to the above embodiments and have corresponding technical effects.

[0086] It is understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described herein, or combinations thereof.

[0087] For software implementation, the techniques described herein can be implemented by units that perform the functions described herein. The software code can be stored in memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0088] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0089] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0090] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0091] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0092] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0093] If the aforementioned function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this application, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks. It should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. In the absence of further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0094] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A signal-to-noise ratio improvement system for magnetic resonance imaging, characterized in that, include: The system includes multiple data acquisition circuits, a standard signal generation circuit, and an FPGA, with the standard signal generation circuit connected to each of the data acquisition circuits and the FPGA. The standard signal generation circuit is used to convert the standard digital signal output by the FPGA into an analog signal, and to divide the analog signal into multiple paths, which are then input into each of the acquisition circuits respectively. The acquisition circuit is used to condition the analog signal to obtain the actual digital signal; The FPGA is used to generate the standard digital signal, and when the actual digital signal is received, to perform gain calibration and delay compensation on each of the acquisition circuits based on the analog signal, so as to improve the signal-to-noise ratio of magnetic resonance imaging.

2. The system according to claim 1, characterized in that, The FPGA includes a direct digital frequency synthesizer, a gain calibration circuit, and a delay compensation circuit. The direct digital frequency synthesizer is connected to the standard signal generation circuit, the gain calibration circuit, and the delay compensation circuit, respectively. The direct digital frequency synthesizer transmits the standard digital signal to the standard signal generation circuit, the gain calibration circuit, and the delay compensation circuit.

3. The system according to claim 2, characterized in that, The gain calibration circuit is used to calculate the gain difference on each of the acquisition circuits based on the actual digital signal and the standard digital signal, and output a gain control word to the corresponding acquisition circuit based on the gain difference, so that the acquisition circuit adjusts the gain.

4. The system according to claim 1, characterized in that, The FPGA includes a delay compensation circuit, which is used to calculate the signal delay on each of the acquisition circuits based on the actual digital signal and the standard digital signal, and to perform delay compensation based on the signal delay to ensure that the data acquired by each acquisition circuit is in phase.

5. The system according to claim 4, characterized in that, The delay compensation circuit includes multiple triggers, and the delay compensation circuit controls the amount of data delay on the acquisition circuit by adjusting the number of triggers used.

6. The system according to claim 3, characterized in that, The acquisition circuit includes a digital gain controller, which is connected to the FPGA. The digital gain controller is used to adjust the gain of the acquisition circuit according to the gain control word issued by the FPGA when it receives the gain control word.

7. The system according to claim 1, characterized in that, The standard signal generation circuit includes a digital-to-analog converter and a power divider. The digital-to-analog converter is used to convert the standard digital signal into the analog signal, and the power divider is used to divide the analog signal into multiple paths and send them to each of the acquisition circuits respectively.

8. The system according to claim 1, characterized in that, The acquisition circuit further includes an amplifier, a filter, and an analog-to-digital converter. The amplifier is used to amplify the received analog signal, the filter is used to filter the amplified analog signal, and the analog-to-digital converter is used to convert the filtered analog signal into the actual digital signal.

9. The system according to claim 1, characterized in that, If the magnetic resonance signals are input in parallel into each of the acquisition circuits, the acquisition circuits are also used to condition the received magnetic resonance signals and input the obtained digital signals into the FPGA, so that the FPGA will perform accumulation and averaging operations on each of the digital signals.

10. An electronic device, characterized in that, The magnetic resonance imaging signal-to-noise ratio enhancement system includes any one of claims 1 to 9.

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