Reference voltage generator

Abstract

The invention provides a voltage generation circuit for a high-efficiency and high-capacity three-dimensional (3D) NAND memory. The voltage generation circuit receives an input control current and outputs a VREF. The voltage generating circuit includes: a first circuit including a first transistor and a second transistor connected in series between a first node receiving an input control current and a supply node; a second circuit including a first resistor and a second resistor connected in series between the first node and the supply node, in which the input control current is shunted between the first circuit and the second circuit; a reference node outputting VREF and connected to the first transistor; a second node between the first resistor and the second resistor and in electrical communication with the second transistor; and a current supply circuit connected to the second node and providing a compensation current affecting the VREF to address a change in the operating temperature.

Description

Technical Field

[0001] This invention relates to a voltage generator. More specifically, this invention relates to a complementary metal-oxide-semiconductor (CMOS) reference voltage generator that generates a reference voltage (VREF) that does not fluctuate due to changes in operating temperature. Background Technology

[0002] As the capacity of three-dimensional (3D) NAND memory increases, more memory data needs to be processed at higher speeds. This increase in memory capacity and the demand for higher speed performance can increase the power consumption of 3D NAND memory. To maintain (i.e., prevent) increased power consumption, operation requires a low reference (and stable) voltage (VREF) or supply voltage that is unaffected by operating temperature. Silicon has a voltage bandgap of approximately 1.2 volts and requires a VREF of approximately 1.2 volts that does not fluctuate based on operating temperature. Traditional reference voltage (VREF) generation circuits suffer from problems such as fluctuations based on operating temperature, insufficient voltage margin, and operation in the saturation region rather than the nonlinear region.

[0003] Therefore, a VREF generation circuit that does not fluctuate based on operating temperature, has sufficient voltage margin, and does not operate in the saturation region is required. Summary of the Invention

[0004] According to an embodiment of the present invention, a voltage generating circuit is provided, which receives an input control current and outputs a reference voltage (VREF). The voltage generating circuit may include: a first circuit including a first transistor and a second transistor connected in series between a first node receiving the input control current and a supply node; a second circuit including a first resistor and a second resistor connected in series between the first node and the supply node, wherein the input control current is shunt between the first circuit and the second circuit; a reference node that outputs the reference voltage (VREF) and is connected to the first transistor in the first circuit; a second node located between the first resistor and the second resistor and electrically connected to the second transistor; and a current supply circuit connected to the second node and providing a compensation current affecting the reference voltage (VREF) to address changes in the operating temperature of the voltage generating circuit.

[0005] According to another embodiment of the present invention, both the first resistor and the second resistor may be adjustable.

[0006] In another embodiment of the invention, the second node may be connected to the gate of the second transistor.

[0007] In another embodiment of the present invention, the first transistor and the second transistor may be NMOS transistors.

[0008] According to an embodiment of the present invention, the reference voltage (VREF) is unaffected by changes in operating temperature because the compensation current has a decreasing slope from a lower operating temperature to a higher operating temperature, the decreasing slope being caused by a negative operating temperature coefficient.

[0009] In another embodiment of the invention, the operating temperature may be in the range of 25°C to 85°C.

[0010] In an embodiment of the present invention, the input control current can be received from a power supply circuit at a first node, wherein the power supply circuit may include: a first power transistor connected in series with the first transistor and the second transistor, receiving power and providing the input control current to the first node; and a current generator that controls the current mirrored to the first power transistor.

[0011] In another embodiment of the invention, the current generator may include: a first branch, (i) including a first current generator transistor connected in series with a second current generator transistor and (ii) located between a power source and a supply node; and a second branch, (i) including a third current generator transistor connected in series with a fourth current generator transistor and a first current generator resistor and (ii) located between a power source and a supply node, wherein the first branch and the second branch are connected in parallel.

[0012] In another embodiment of the present invention, the first current generator transistor and the third current generator transistor may be PMOS transistors, and the second current generator transistor and the fourth current generator transistor may be NMOS transistors.

[0013] According to an embodiment of the present invention, the ratio of the resistance of the first resistor to the resistance of the second resistor may be less than 1.

[0014] In another embodiment of the invention, the ratio of the resistance of the first resistor to the resistance of the second resistor may be approximately 0.2.

[0015] In another embodiment of the invention, a voltage generating circuit is provided, which receives an input control current and outputs a reference voltage (VREF). The voltage generating circuit may include: a first circuit comprising a first transistor and a second transistor connected in series between a first node receiving the input control current and a supply node; a second circuit comprising a first resistor, a second resistor, and a third resistor connected in series between the first node and the supply node, wherein the input control current is shunt between the first circuit and the second circuit; a reference node that outputs the reference voltage (VREF) and is connected to the first transistor in the first circuit; a second node located between the second resistor and the third resistor and electrically connected to the second transistor; and a current supply circuit connected to the second node and providing a compensation current affecting the reference voltage (VREF) to address changes in the operating temperature of the voltage generating circuit.

[0016] According to an embodiment of the present invention, (i) the ratio of the resistance of the second resistor to (ii) the combined resistance of the second resistor and the third resistor can be adjustable to address manufacturing variations.

[0017] In another embodiment of the invention, the ratio of the resistance of the first resistor to the resistance of the second resistor may have a maximum value of 1.

[0018] In an embodiment of the present invention, the current supply circuit may include: a positive bias current circuit system providing a current with a positive temperature coefficient from a lower operating temperature to a higher operating temperature; and a negative bias current circuit system providing a current with a negative temperature coefficient from a lower operating temperature to a higher operating temperature, wherein the compensation current is a combination of a current with a positive temperature coefficient and a current with a negative temperature coefficient.

[0019] According to an embodiment of the invention, at higher operating temperatures, the combination of a current with a positive temperature coefficient and a current with a negative temperature coefficient results in a compensation current having an approximate value of 0 amperes.

[0020] In another embodiment of the present invention, the first transistor and the second transistor may be NMOS transistors.

[0021] In an embodiment of the present invention, a voltage generating circuit is provided, which receives an input control current and outputs a reference voltage (VREF). The voltage generating circuit may include: a first circuit including a first transistor and a second transistor connected in series between a first node receiving the input control current and a supply node; a second circuit including a first resistor, a second resistor, a third resistor, and a fourth resistor connected in series between the first node and the supply node, wherein the input control current is shunt between the first circuit and the second circuit; a reference node that outputs the reference voltage (VREF) and is connected to the first transistor in the first circuit; a second node located between the first resistor and the second resistor and electrically connected to the second transistor; and a current supply circuit connected to the second node and providing a compensation current that affects the reference voltage (VREF) to address changes in the operating temperature of the voltage generating circuit.

[0022] In another embodiment of the invention, (i) the resistance of the first resistor and (ii) the first ratio of the combined resistance of the first resistor and the second resistor are adjustable to address manufacturing variations, and (i) the resistance of the third resistor and (ii) the second ratio of the combined resistance of the third resistor and the fourth resistor are adjustable to address manufacturing variations.

[0023] In another embodiment of the invention, the second ratio may be less than 1 and the first ratio may be less than the second ratio.

[0024] The above embodiments of the present invention can be implemented by providing a VREF and a non-transitory computer-readable recording medium on which instructions are recorded, such that when executed by a processor, the processor performs the operation of the voltage generation circuit and the method of providing the VREF.

[0025] Other embodiments and advantages of the present invention can be seen in the following figures, detailed description and review of the claims. Attached Figure Description

[0026] Figure 1 A conventional reference voltage (VREF) generation circuit 100 with insufficient voltage margin (e.g., the difference between the input voltage and the output voltage) is shown.

[0027] Figure 2 A conventional VREF generation circuit 200 operating in the saturation region is shown (e.g., as a closed switch).

[0028] Figure 3 A conventional VREF generating circuit 300 is shown that provides VREF that varies according to operating temperature.

[0029] Figure 4 Showing removal by Figure 2 and Figure 3The VREF circuit 400 causes a linear change in VREF relative to the operating temperature.

[0030] Figure 5 Showing based on Figure 3 The conventional VREF circuit 300 has a VREF circuit 500, which has an additional power supply circuit system that provides the input control current IB.

[0031] Figure 6A For reference Figure 3 The discussed IN2 component is plotted as a graph depicting the relationship between the IN2 current and temperature in °C.

[0032] Figure 6B For reference Figure 3 A graph of the 1 / (K2×RDS2) component discussed, wherein the graph depicts the relationship between the voltage of 1 / (K2×RDS2) and the temperature in °C.

[0033] Figure 7 For reference Figure 3 The graph of the threshold voltage Vth2 component of the transistor N2 discussed herein depicts the relationship between the voltage Vth2 and the temperature in °C.

[0034] Figure 8 To show the curves of voltage VG, voltage VREF, and voltage VDS2+Vth2 in the temperature range of 25°C to 85°C.

[0035] Figure 9 The diagram shows the elimination of the linear change in VREF with respect to temperature. Figure 4 The VREF circuit 400 has a VREF circuit 900, which has an additional power supply circuit system that provides the input control current IB.

[0036] Figure 10 For reference Figure 4 A graph showing the value of the compensation current Icomp, wherein the graph depicts the relationship between the compensation current Icomp and the temperature in °C.

[0037] Figure 11A For reference and Figure 3 The related equations discuss Figure 9 A graph of the IN2 component, wherein the graph depicts the relationship between the current of IN2 and the temperature in °C.

[0038] Figure 11B For reference and Figure 3 The related equations discuss Figure 9A graph of the 1 / (K2×RDS2) component, wherein the graph depicts the relationship between the 1 / (K2×RDS2) voltage and the temperature in °C.

[0039] Figure 12 To show the temperature range from 25°C to 85°C Figure 9 The curves of voltage VG, voltage VREF, and voltage VDS2+Vth2.

[0040] Figure 13 To illustrate the effect of not applying compensation current Icomp for each process corner. Figure 5 The change of VREF relative to temperature.

[0041] Figure 14 Showing something similar Figure 4 The VREF circuit 400 and VREF circuit 1400 differ in that resistor R2 is replaced by resistors R2A and R2B, and VREF circuit 1400 has a different compensation current Icomp configuration.

[0042] Figure 15 Showing contains Figure 14 The VREF circuit 1400 and the VREF circuit 1500 have additional circuitry that provides compensation current Icomp through various additional transistors and resistors.

[0043] Figure 16A To show the passage Figure 15 The curve of the current IP7 of transistor P7 in the VREF circuit 1500, where the current IP7 has a negative temperature coefficient TC.

[0044] Figure 16B To show the passage Figure 15 The curve of the current IN7 of transistor N7 in the VREF circuit 1500, where the current IN7 has a positive temperature coefficient TC.

[0045] Figure 16C To show Figure 15 A graph showing the value of the compensation current Icomp of the VREF circuit 1500 at process corner TT, wherein the compensation current is determined by the current IP7 with a negative temperature coefficient TC (see [reference]). Figure 16A ) and the current IN7 with a positive temperature coefficient TC (see Figure 16B )produce.

[0046] Figure 17A To show in Figure 14 and Figure 15The graph shows the current IN2 through transistor N2 with different R2A / R2 ratios in VREF circuits 1400 and 1500.

[0047] Figure 17B To show the different temperature values ​​and in Figure 14 and Figure 15 The graph shows the voltage values ​​of the 1 / (K2×RDS2) component using different R2A / R2 ratios within the VREF circuits 1400 and 1500.

[0048] Figure 17C To show the effect at different temperature values Figure 14 and Figure 15 The graph shows the voltage values ​​of VG with different R2A / R2 ratios in VREF circuits 1400 and 1500.

[0049] Figure 17D To show the effect at different temperature values Figure 14 and Figure 15 The graph shows the voltage values ​​of VREF with different R2A / R2 ratios in VREF circuits 1400 and 1500.

[0050] Figure 18 To illustrate the temperature range between 25°C and 85°C Figure 14 and Figure 15 The VREF curves of different process angles FF, FS, TT, SF and SS using different R2A / R2 ratios in VREF circuits 1400 and 1500.

[0051] Figure 19 Showing something similar Figure 14 The VREF circuit 1400 and VREF circuit 1900 differ in that resistor R1 is similar to... Figure 14 The resistor R2 is replaced by resistors R2A and R2B in the same way as resistors R1A and R1B, and the VREF circuit 1900 has different compensation current Icomp configurations.

[0052] Figure 20 To show Figure 19 The curve of the compensation current Icomp of the VREF circuit 1900.

[0053] Figure 21A To show Figure 19 The curves of VG voltage values ​​of the VREF circuit 1900 under different R1B / R1 ratios and R2A / R2 ratios within a temperature range of 25℃ to 85℃.

[0054] Figure 21B To show Figure 19 The curves of the VREF circuit 1900 under different R1B / R1 ratios and R2A / R2 ratios within a temperature range of 25°C to 85°C.

[0055] Figure 21C To show Figure 19 The VREF curves of the VREF circuit 1900 with different R1B / R1 ratios and R2A / R2 ratios, and different process angles FF, FS, TT, SF, and SS, are shown between temperatures of 25°C and 85°C.

[0056] Figure 22 Showing something similar Figure 9 The VREF circuit 900 and VREF circuit 2200 differ in that... Figure 9 The NMOS transistor N1 has been replaced by the PMOS transistor P8.

[0057] Figure 23 To show Figure 22 The curve of the compensation current Icomp with positive temperature coefficient TC for the VREF circuit 2200.

[0058] Figure 24 To show when Figure 23 The compensation current Icomp is applied to Figure 22 The graph shows the values ​​of voltage VREF, voltage VG, and voltage VDS2+Vth2 of transistor N2 when the VREF circuit 2200 is in operation.

[0059] Figure 25 To show Figure 22 The VREF curves of the VREF circuit 2200 with different R1B / R1 ratios of 0.66, 0.96, 1.0 and 0.98 and different process angles FF, FS, TT, SF and SS of R2A / R2 (resistance) ratio of 0.87 are shown.

[0060] Figure 26 This illustrates a VREF circuit 2600 that uses only NMOS transistors, wherein the VREF circuit 2600 is similar to Figure 4 The VREF circuit 400 differs in that transistor N1 is replaced by transistors N1A and N1B.

[0061] Explanation of reference numerals in the attached figures:

[0062] 100, 200, 300: Traditional VREF generation circuits

[0063] 400, 500, 900, 1400, 1500, 1900, 2200, 2600: VREF circuit

[0064] 402: First Circuit

[0065] 404: Second Circuit

[0066] 406: First Node

[0067] 408: Supply Node

[0068] 410: Second Node

[0069] 412: Circuit / Compensation Current

[0070] 414: Reference Node

[0071] 902: Additional power supply circuit system

[0072] 904: Power Supply

[0073] 1402, 1902: Nodes

[0074] 1502, 1504: Current mirror circuit system

[0075] IB: Input control current

[0076] Icomp: Compensation current

[0077] IN2, IN7, IP7: Current

[0078] MN, N1, N1A, N1B, N2, N3, N4, N5, N6, N7: NMOS transistors

[0079] MP, P1, P2, P3, P4, P5, P6, P7, P8: PMOS transistors

[0080] Q1, Q2: Bipolar Junction Transistor

[0081] R1, R1A, R1B, R2, R2A, R2B, R3, R4: Resistors

[0082] VDS2+Vth2: Voltage

[0083] VG: Voltage / Node

[0084] VREF: Reference Voltage

[0085] Vth2: Threshold voltage Detailed Implementation

[0086] refer to Figures 1 to 26 Implementation methods of embodiments of the present invention are provided.

[0087] Figure 1 A conventional reference voltage (VREF) generation circuit 100 with insufficient voltage margin (e.g., the difference between the input voltage and the output voltage) is shown, which is undesirable when providing VREF.

[0088] Specifically, the VREF generation circuit 100 includes bipolar junction transistors (BJTs) Q1 and Q2 in parallel configuration, wherein resistors R2 and R3 and PMOS transistor P1 are connected in series with BJT transistor Q2, and wherein resistor R1 is connected in series with BJT transistor Q1.

[0089] Figure 2 A conventional VREF generation circuit 200 that can operate in the saturation region and is temperature dependent is shown (e.g., as a closed switch with no gain).

[0090] For example, the transistors MP (PMOS transistor) and MN (NMOS transistor) of the VREF generation circuit 200 operate in the saturation region (e.g., the difference between the gate-to-source voltages (Vgs) of MP and MN causes saturation, which is the opposite of operation in the linear region of the transistor).

[0091] The operating characteristics of the VREF generation circuit 200 are described in the following equations.

[0092]

[0093] For the MN transistor, V GSn V is the gate-to-source voltage. thn For the threshold voltage, I D The drain voltage is µ. n For the effective mobility characteristics of charge carriers, C ox For oxide capacitors, β µn or (β) vthn ) represents the gain, W n L is the channel width of the MN transistor. n Let T be the channel length of transistor MN, T be the ambient temperature (e.g., the temperature of the surrounding environment), and T0 be the reference temperature. r This is the desired temperature for VREF to have a zero temperature coefficient. A similar variable is provided for the MP transistor in the above equation. Figure 2The temperature dependence of VREF in can be set to zero by the resistor (resistance) ratio in (1a) and the aspect ratios of the MP transistor and the MN transistor in (1b). The resistor ratio and the aspect ratio depend on the temperature coefficients of the threshold voltages and carrier mobilities of the MP transistor and the MN transistor, and these temperature coefficients can only be extracted from dedicated MP transistor test structures and MN transistor test structures, and not from VREF measurements. If, during manufacturing, β µp or β µn or (β vthp / β vthn ) deviates due to local mismatches between the MN transistor and the MP transistor, it will inevitably affect the temperature dependence of VREF. Figure 3 FIG. shows a conventional VREF generation circuit 300 that provides a VREF that changes according to the operating temperature.

[0094] Specifically, Figure 3 FIG. shows a VREF circuit that includes NMOS transistors. Figure 3 It includes NMOS transistors N1 and N2 in series and resistors R1 and R2 in series. Transistors N1 and N2 are in parallel with resistors R1 and R2. An input control current IB is shunted between a branch including transistors N1 and N2 and a branch including resistors R1 and R2. VG represents the gate voltage of transistor N2 and is at a node between resistors R1 and R2 in series. The branch including transistors N1 and N2 and the branch including resistors R1 and R2 are between the source of the input control current IB and a supply node (e.g., ground). The operating characteristics of the conventional VREF generation circuit 300 are provided in the equations listed below.

[0095]

[0096] According to Kirchoff's Voltage Law, VREF = VG(1 + R1 / R2). If transistor N1 operates in the saturation region, if transistor N2 operates in the linear region, and if the drain voltage of N2 or VDS2 (i.e., the drain-to-source voltage of transistor N2) satisfies VDS2 + Vth2 < VG, then VG is expressed by equation (2a). Additionally, the or the temperature coefficient (TC) of VG can be expressed as a , and linear combination. The same applies to VREF, such that VREF is temperature-dependent based on the temperature coefficient TC.

[0097] Figure 4 Showing removal by Figure 2 and Figure 3 VREF circuit 400 (e.g., voltage generating circuit) generates VREF circuit 200 and VREF circuit 300, which linearly change VREF with respect to operating temperature.

[0098] Figure 4 The VREF circuit 400 is similar to Figure 3 The VREF circuit 300 includes NMOS transistors N1 and NMOS transistor N2 connected in series between a first node 406 receiving the input control current (IB) and a supply node (such as ground), and further includes resistors R1 and R2. Resistors R1 and R2 may be adjustable resistors. Additionally, all other resistors described herein with respect to the invention may be adjustable. Furthermore, the VREF circuit 400 includes a current supply, such as a compensation current Icomp provided to the VG node. The compensated VREF (to address temperature variations) and the resulting temperature coefficient TC are expressed by equations (3a) and (3b). Therefore, the temperature coefficient TC generated by the compensation current Icomp can be designed to achieve a VREF with a zero temperature coefficient TC. As described above... Figure 3 The equations for IN2 and 1 / (K2×RDS2) still apply. Figure 4 .

[0099] The combination of transistors N1 and N2 can be referred to as the first circuit 402, and the combination of (adjustable) resistors R1 and R2 can be referred to as the second circuit 404. As shown, the first circuit 402 includes transistors N1 and N2 connected in series between a first node 406 receiving the input control current (IB) and a supply node (e.g., ground) 408. Transistor N1 can be referred to as the first transistor and transistor N2 can be referred to as the second transistor. The second circuit 404 includes adjustable resistors R1 and R2 connected in series between the first node 406 receiving the input control current (IB) and the supply node 408. Resistor R1 can be referred to as the first resistor and resistor R2 can be referred to as the second resistor.

[0100]

[0101] The first circuit 402 and the second circuit 404 can be configured in parallel relative to each other. Additionally, the VREF circuit 400 includes a second node (VG) 410 located between the first resistor R1 and the second resistor R2 and in electrical communication with the transistor N2 (e.g., the gate of the resistor N2). Further, as shown, an input control current (IB) is split between the first circuit 402 and the second circuit 404 (at the first node 406), and VREF is output from the first circuit 402, as provided at the first node 406 connected to the transistor N1. The gate of the transistor N1 can also be connected to VREF. VREF is output at the reference node 414. A circuit (e.g., a current supply circuit) 412 can provide a compensation current Icomp (e.g., a temperature compensation current) that varies within the operating temperature range of the VREF circuit 400 under the influence of internal and external conditions, in order to reduce or eliminate fluctuations in VREF as the operating temperature changes. The performance of the VREF circuit 400 is discussed in more detail below with reference to various graphs.

[0102] Figure 5 Shows a VREF circuit 500 of a conventional VREF circuit 300 based on Figure 3 which has an additional power supply circuitry that provides an input control current IB.

[0103] The power supply circuitry includes PMOS transistors P1, PMOS transistors P2, and PMOS transistors P3 configured in parallel with each other. Additionally, the NMOS transistor N4 is in series with the transistor P2, and the NMOS transistor N3 and the resistor R3 are in series with the transistor P1. The branch including the transistor P2 and the transistor N4 is located between the power supply and the supply node, and the branch including the transistor P1 and the transistor N3 and the resistor R3 is also located between the power supply and the supply node.

[0104] To satisfy VDS2 + Vth2 < VG (for the transistor N2), Figure 5 a circuit can implement the transistor N1 with a voltage threshold of 600 millivolts, the transistor N2 with a voltage threshold of 200 millivolts, and the transistor P3 with a voltage threshold of 800 millivolts to provide the input control current IB. The input control current IB is mirrored from a current generator including PMOS transistors P1, PMOS transistors P2, NMOS transistors N3, NMOS transistors N4, and the resistor R3. The resistor R1 / resistor R2 (resistance) ratio can be set to 0.2. The resistor R1 / resistor R2 ratio can be 1 or less than 1.

[0105] Once current flows through resistors R1 and R2, the initial voltage VG enables (turns on) transistor N2, allowing transistor N1 to begin conducting current from its drain to its source. Therefore, current is shunted from resistors R1 and R2 back to transistors N1 and N2. A new VG is then achieved, and current continues to shun until a stable state is reached. At this point, VG is higher than the voltage threshold Vth of transistor N2, and the output VREF is higher than the voltage threshold Vth of transistor N1. In other words, at this point, VREF = VG(1+R1 / R2) > Vth1 = 600 mV or VG > 600 mV / (1+R1 / R2) = 600 mV / 1.2 = 500 mV. Therefore, VG is higher than 500 mV or 2.5 times higher than the voltage threshold Vth of transistor N2. In any case, the VREF output from VREF circuit 500 changes according to operating conditions for the same reason as the VREF output from VREF circuit 300.

[0106] Figure 6A To illustrate the above reference Figure 3 The graph of the IN2 component is discussed, which depicts the relationship between the current of IN2 and the temperature in °C. As shown, the value of the current IN2 through transistor N2 increases with increasing temperature (e.g., with a positive temperature coefficient TC represented by a positive (increasing) slope).

[0107] Figure 6B To illustrate the above reference Figure 3 The graph of the 1 / (K2×RDS2) component is discussed, which depicts the relationship between the voltage of 1 / (K2×RDS2) and the temperature in °C. As shown, the voltage value of 1 / (K2×RDS2) increases with increasing temperature (e.g., with a positive temperature coefficient TC).

[0108] Figure 7 To illustrate the above reference Figure 3 The graph depicts the threshold voltage Vth2 component of transistor N2, illustrating the relationship between Vth2 and temperature in °C. As shown, the voltage value of Vth2 decreases with increasing temperature (e.g., with a negative temperature coefficient TC represented by a negative (decreasing) slope). Specifically, the negative temperature coefficient TC is approximately -3.32E⁻³ / °C. (Return to reference above) Figure 3 The linear combination of equation (2a), 1 / (K2×RDS2) and Vth2 gives VG a positive temperature coefficient TC of 3.75E-4 / degree (°C).

[0109] Figure 8To show graphs of voltage VG, voltage VREF, and voltage VDS2+Vth2 in the temperature range from 25°C to 85°C, where VREF is 754 millivolts at 85°C and 737 millivolts at 25°C, resulting in a 17-millivolt difference between 25°C and 85°C. Additionally, Figure 8 The graph shows that VG increases between 25°C and 85°C, while VDS2+Vth2 decreases between 25°C and 85°C. This positive temperature coefficient TC of VREF is undesirable.

[0110] Figure 9 Showing a VREF circuit 900 (e.g., a voltage generation circuit) that includes eliminating the linear change of VREF with respect to temperature, and the VREF circuit 900 has an additional power supply circuitry that provides an input control current IB. Figure 4 The description of components in the VREF circuit 900 that are the same as those in the VREF circuit 400 is omitted. Similar to

[0111] An additional power supply circuitry 902 is added to the VREF circuit 400 of Figure 5 . Similar to Figure 9 The additional power supply circuitry 902 of Figure 4 contains transistors P1, P2, P3, N3, N4, and resistor R3. Figure 5 Figure 9 The power supply circuitry 902 of

[0112] Transistor P3 can be referred to as the first power transistor, which is in series with the first transistor (transistor N1) and the second transistor (transistor N2). Transistors P1, P2, N3, N4, and resistor R3 can be referred to as a current generator that provides / controls the current mirrored to the first power transistor (transistor P3). For example, the current generator can include a first branch that includes transistor P2 (e.g., the first current generator transistor) in series with transistor N4 (e.g., the second current generator transistor), where the first branch is between power supply 904 and supply node 408. The current generator can include a second branch that includes transistor P1 (e.g., the third current generator transistor) in series with transistor N3 (e.g., the fourth current generator transistor) and resistor R3 (e.g., the first current generator transistor). The first branch of the current generator is in parallel with the second branch of the current generator, where the gates of transistors P1 and P2 are connected together and the gates of transistors N3 and N4 are connected together.

[0113] The power supply circuitry 902 is configured to satisfy VDS2+Vth2 < VG (for transistor N2). Figure 9 ​The VREF circuit 900 can be implemented using transistor N1 with a voltage threshold of 600 mV, transistor N2 with a voltage threshold of 200 mV, and transistor P3 with a voltage threshold of 800 mV to provide the input control current IB. Similar to... Figure 5 The input control current IB is a mirror image of a current generator containing PMOS transistors P1, PMOS transistor P2, NMOS transistors N3 and NMOS transistor N4, and resistor R3. The resistor R1 / R2 ratio can be set to 0.2. The resistor R1 / R2 ratio can be 1 or less than 1, and can have a maximum value of 1.

[0114] Figure 9 The VREF circuit 900 provides a temperature-compensated current Icomp, making VREF no longer temperature-dependent. The power supply circuit system 902 can be implemented using any VREF circuit system described herein.

[0115] Figure 10 To illustrate the above reference Figure 4 The graph depicts the relationship between the compensation current Icomp and temperature in °C. As shown, the compensation current Icomp has a negative temperature coefficient TC that can be used to remove any changes in VREF based on operating temperature variations.

[0116] For example, at a temperature of 85°C, the compensation current Icomp is 0 amperes, and at a temperature of 25°C, the compensation current Icomp provides current (e.g., 120 nanoamperes) at node VG to maintain VREF at approximately 754 millivolts between 85°C and 25°C (see [link to documentation]). Figure 12 The following section will discuss this in more detail compared to VREF.

[0117] In response to the compensation current Icomp providing approximately 120 nanoamps at node VG (e.g., at approximately 25°C), the gate voltage of transistor N2 increases. Subsequently, transistor N2 can operate in a deeper linear region, allowing it to conduct more current. Therefore, both VDS2 and RDS2 (of transistor N2) = VDS2 / IN2 begin to decrease, and 1 / (K2×RDS2) of equation (2a) increases. Furthermore, VG begins to increase at 25°C to raise VREF to 17 mV at 25°C. Additionally, since the compensation current Icomp introduces a negative second term for VREF at 25°C in equation (3a), VG at 25°C is greater than VG at 85°C.

[0118] Figure 11A To illustrate, please refer to the above references. Figure 3 The equations described are discussed Figure 9 The curve of the IN2 component, where Figure 11A The graph depicts the relationship between the current IN2 and temperature in °C. As shown, the value of IN2 increases with increasing temperature (e.g., it has a positive temperature coefficient TC). Furthermore, compared to... Figure 6A (Regarding the value of IN2 in VREF circuit 300 and VREF circuit 500) Figure 11A The value of IN2 in (regarding VREF circuit 900) is 90 nanoamps higher at a temperature of 25°C (e.g., 850 nanoamps versus 940 nanoamps).

[0119] Figure 11B To illustrate, please refer to the above references. Figure 3 The equations described are discussed Figure 9 A graph showing the 1 / (K²×RDS²) component of the voltage is plotted, depicting the relationship between 1 / (K²×RDS²) of the voltage and temperature in °C. As shown, the value of 1 / (K²×RDS²) increases with increasing temperature (e.g., having a positive temperature coefficient TC). Furthermore, compared to... Figure 6B The value of 1 / (K2×RDS2) in (regarding VREF circuit 300 and VREF circuit 500) Figure 11B The value of 1 / (K2×RDS2) in (regarding VREF circuit 900) is approximately 50.5 mV higher at a temperature of 25°C (e.g., 395 mV vs. 445.5 mV).

[0120] Figure 12 To demonstrate the use of [technology / method] within a temperature range of 25°C to 85°C Figure 9 The voltage values ​​of VG, VREF and VDS2+Vth2 of the VREF circuit 900.

[0121] like Figure 12 As shown, VREF is 754 millivolts at both 25°C and 85°C, exhibiting a zero temperature coefficient TC. Furthermore, Figure 12 The curves show that VG decreases between 25℃ and 85℃, and VDS2+Vth2 also decreases between 25℃ and 85℃.

[0122] In addition, such as Figure 12As shown, the reference voltage VREF exhibits a zero temperature coefficient TC, which is achieved through two temperature coefficients TCs between the voltage at the matched node VG and the compensation current Icomp (at a typical process corner (TT)). Circuit manufacturing can lead to so-called process corner variations that can affect the operating characteristics of the circuit and other components. Process corners include slow-slow (SS), slow-fast (SF), typical-typical (TT), fast-slow (FS), and fast-fast (FF). Therefore, due to manufacturing offsets, the voltage VERF at a process corner can deviate from the TT corner to other corners, such as FF, SS, FS, and SF.

[0123] Figure 13 To illustrate the situation for each process corner, without applying the compensation current Icomp (before applying the compensation current Icomp). Figure 5 The graph shows the change of VREF relative to temperature. Specifically, Figure 13 The graph shows the difference in VREF between temperatures of 25°C and 85°C for each process angle. The technique for compensating for variations between process angles is to develop a compensation current Icomp with adjustable temperature coefficients TCs.

[0124] Figure 14 Showing something similar Figure 4 The VREF circuit 1400 (e.g., a voltage generation circuit) differs from the VREF circuit 400 in that resistor R2 is replaced by resistors R2A and R2B, and the VREF circuit 1400 has a different compensation current Icomp configuration. (Details regarding the VREF circuit 1400 are omitted.) Figure 4 The components of the VREF circuit 400 are described in the same way as the components described above.

[0125] As mentioned, the second circuit 404 of the VREF circuit 1400 includes resistors R2B and R2A, replacing resistor R2 in the VREF circuit 400. Resistor R2B can be referred to as the second resistor and resistor R2A as the third resistor, such that the second circuit 404 includes three resistors, where resistor R1 is the first resistor, resistor R2B is the second resistor, and resistor R2A is the third resistor. Additionally, the VREF circuit 1400 implements another technique for compensating for temperature conditions by changing the connection nodes of the compensation current Icomp, such as... Figure 14 As shown in the figure.

[0126] For example, the difference between VREF circuit 1400 and VREF circuit 400 is that VREF circuit 1400 includes a node 1402 (e.g., a second node) located between resistors R2A and R2B, where node 1402 receives a compensation current Icomp 412. This contrasts with VREF circuit 400, where node (VG) receives a compensation current Icomp 412.

[0127] Specifically, in VREF circuit 1400, Figure 4 Resistor R2 can be replaced by resistors R2A and R2B, and the connection node for the compensation current Icomp can be placed between resistors R2A and R2B. The branch currents of resistors R2A and R2B can be expressed as IR2A (current resistor R2A) - compensation current Icomp = IR2B (current resistor R2B) = IR1 (current resistor R1).

[0128] The following text provides Figure 14 Some of the operating characteristics of the VREF circuit 1400. VREF and The derivation is provided in equations (4a) and (4b) listed below. Furthermore, the second term in equation (4b) now has an additional factor (R2A / R2) depending on the connection node of the compensation current Icomp. Because resistors R2A and R2B are adjustable, the ratio of (R2A / R2) (e.g., the resistance ratio) can be adjusted after manufacturing to eliminate the drift of the temperature coefficient TC of VREF at the process corner. The resistance value of R2 is a combination of the resistance values ​​of resistors R2A and R2B. The ratio of (i) the resistance of the third resistor (R2A) to the combined resistance of (ii) the second resistor (R2B) and the third resistor (R2A) is adjustable to accommodate manufacturing variations.

[0129]

[0130] Return to reference Figure 10 The compensation current Icomp has approximately zero current at 85°C and has a negative temperature coefficient TC. Figure 10 The compensation current Icomp can be achieved by implementing two bias currents of similar (but opposite) values. For example, the compensation current Icomp can be derived by subtracting a bias current with a positive temperature coefficient TC from a bias current with a negative temperature coefficient TC. See below for reference. Figure 15 Discuss the circuit system used to achieve this objective. The compensation current Icomp can be generated using other techniques.

[0131] Figure 15 Showing contains Figure 14The VREF circuit 1400 and VREF circuit 1500 (e.g., a voltage generation circuit) have additional circuitry to provide a compensation current Icomp via various additional transistors and resistors. Similar to... Figure 9 ,exist Figure 15 The diagram shows transistors P1, P2, P3, N3, N4, and resistor R3. Transistor P3 can be implemented to provide current IB. Furthermore, current IB is mirrored by a current generator comprising PMOS transistors P1, PMOS transistor P2, NMOS transistors N3, NMOS transistor N4, and resistor R3.

[0132] The VREF circuit 1500 further includes a negative bias voltage with a current mirror circuit system 1502 and a positive bias voltage with a current mirror circuit system 1504. The negative bias circuit system with current mirror 1502 provides a current with a negative temperature coefficient TC (from a lower operating temperature to a higher operating temperature, such as from 25°C to 85°C). The positive bias voltage with current mirror circuit system 1504 provides a current with a positive temperature coefficient TC (from a lower operating temperature to a higher operating temperature, such as from 25°C to 85°C).

[0133] Specifically, the negative bias portion of the current mirror circuit system 1502 includes PMOS transistors P4, PMOS transistors P5, PMOS transistors P6, NMOS transistors N5 and NMOS transistors N6, and resistor R4, which can achieve a negative temperature coefficient (TC) bias current. The negative bias mirror portion of the current mirror circuit system 1502 includes PMOS transistor P7. The positive bias portion of the current mirror circuit system 1504 includes transistors P1, P2, N3, and N4, which can achieve a positive temperature coefficient (TC) bias current, and resistor R3. The positive bias mirror portion of the current mirror circuit system 1504 includes NMOS transistor N7. The negative temperature coefficient TC bias current provided by the bias portion of the current mirror circuit system 1502 (e.g., transistors P4, P5, P6, N5, N6, and resistor R4) can be mirrored into the negative bias mirror portion of the current mirror circuit system 1502 (e.g., PMOS transistor P7). Similarly, the positive temperature coefficient TC bias current provided by the positive bias of the current mirror circuit system 1504 (e.g., transistors P1, P2, N3, N4, and resistor R3) can be mirrored into the positive bias mirror portion of the current mirror circuit system 1504 (e.g., NMOS transistor N7). To ensure that the compensation current Icomp is approximately 0 amperes at 85°C, the current IP7 through transistor P7 and the current IN7 through transistor N7 should be approximately equal at 85°C.

[0134] The negative bias circuit system 1502 and the positive bias circuit system 1504 can be implemented by any VREF circuit system described herein.

[0135] Figure 16A Showing through Figure 15 The graph shows the current IP7 of transistor P7 in the VREF circuit 1500, where the current IP7 has a negative temperature coefficient TC, such that the current IP7 has an approximate value of 703 nanoamperes at approximately 25°C and an approximate value of 575 nanoamperes at approximately 85°C. Figure 16A Used for process angle TT.

[0136] Figure 16B To show the passage Figure 15 The graph shows the current IN7 of transistor N7 in the VREF circuit 1500, where the current IN7 has a positive temperature coefficient TC, such that at approximately 25°C, the current IN7 has an approximate value of 487 nanoamperes, and at approximately 85°C, the current IN7 has an approximate value of 575 nanoamperes. Figure 16B Used for process angle TT.

[0137] To achieve similar values ​​for current IP7 and current IN7 at 85°C, the mirror ratio of transistor P7 and transistor N7 can be adjusted accordingly (for example, the sizes of transistor P7 and transistor N7 can be selected accordingly to achieve the desired values ​​for IP7 and IN7).

[0138] Figure 16C To show Figure 15 A graph showing the value of the compensation current Icomp (as discussed above) of the VREF circuit 1500 at process corner TT, wherein the compensation current Icomp is composed of the combined current IP7 with a negative temperature coefficient TC (see [link to relevant documentation]). Figure 16A ) and the current IN7 with a positive temperature coefficient TC (see Figure 16B The compensation current Icomp is equal to the current IP7 minus the current IN7. At 25°C, the compensation current Icomp is approximately 216 nanoamps, which is approximately equal to the current IP7 (703 nanoamps) minus the current IN7 (487 nanoamps). Furthermore, at 85°C, the compensation current Icomp is approximately 0 amps, which is approximately equal to the value of IP7 (575 nanoamps) minus the value of IN7 (575 nanoamps).

[0139] and Figure 10 In comparison, Figure 10 The compensation current Icomp at 25°C is approximately 120 nanoamperes. Figure 16C The compensation current Icomp is 216 nanoamperes, which is greater than... Figure 10 The compensation current Icomp is greater than 96 nanoamperes. To achieve the desired compensation current Icomp value at 25°C (e.g., 120 nanoamperes). Figure 15 The VREF circuit can be implemented Figure 14 The method of VREF circuit is to adjust the ratio of resistor R2A to resistor R2B.

[0140] Figure 17A , Figure 17B , Figure 17C , Figure 17D as well as Figure 18 Showing for Figure 14 and Figure 15 The VREF circuits 1400 and 1500 use curves with different R2A / R2 ratios.

[0141] Specifically, Figure 17A To show in Figure 14 and Figure 15 The graph shows the current IN2 through transistor N2 using different R2A / R2 ratios within VREF circuits 1400 and 1500. For example, using an R2A / R2 ratio of 0.78, the current IN2 is approximately 978 nanoamps at 25°C and approximately 1.067 microamps at 85°C. Using an R2A / R2 ratio of 0.56, the current IN2 is approximately 941 nanoamps at 25°C and approximately 1.067 microamps at 85°C. Reducing the R2A / R2 ratio from 0.78 to 0.56 results in a much smaller current IN2 at 25°C.

[0142] Figure 17B To show the different temperature values ​​and in Figure 14 and Figure 15 The graphs show the voltage values ​​of the 1 / (K2×RDS2) component using different R2A / R2 ratios within VREF circuits 1400 and 1500. With an R2A / R2 ratio of 0.78, the voltage of 1 / (K2×RDS2) is approximately 466 mV at 25°C and approximately 451 mV at 85°C. With an R2A / R2 ratio of 0.56, the voltage of 1(K2×RDS2) is approximately 445 mV at 25°C and approximately 451 mV at 85°C. Reducing the R2A / R2 ratio from 0.78 to 0.56 results in a much smaller voltage value for the 1(K2×RDS2) component at 25°C.

[0143] Figure 17C To show the effect at different temperature values Figure 14 and Figure 15The graphs show the voltage values ​​of VG using different R2A / R2 ratios within VREF circuits 1400 and 1500. With an R2A / R2 ratio of 0.78, the voltage of VG is approximately 687 mV at 25°C and approximately 627 mV at 85°C. With an R2A / R2 ratio of 0.56, the voltage of VG is approximately 666 mV at 25°C and approximately 627 mV at 85°C. Reducing the R2A / R2 ratio from 0.78 to 0.56 results in a significantly lower voltage value of VG at 25°C.

[0144] Figure 17D To show the effect at different temperature values Figure 14 and Figure 15 The graphs show the voltage values ​​of VREF using different R2A / R2 ratios within VREF circuits 1400 and 1500. With an R2A / R2 ratio of 0.78, the VREF voltage is approximately 760.2 mV at 25°C and approximately 753.7 mV at 85°C. With an R2A / R2 ratio of 0.56, the VG voltage is approximately 753.7 mV at 25°C and approximately 753.7 mV at 85°C. Reducing the R2A / R2 ratio from 0.78 to 0.56 results in a slight decrease in the VREF voltage value at 25°C and provides the desired zero temperature coefficient TC for VREF.

[0145] Furthermore, reducing the R2A / R2 ratio from 0.78 to 0.56 causes the second term in Equation 4a (i.e., (R2A / R2)×R1×Icomp) to also become smaller. Therefore, as Figure 17D As shown, VREF gradually decreases from 760.2 mV (R2A / R2 ratio of 0.78) to 753.7 mV (R2A / R2 ratio of 0.56) at 25 °C, where a temperature coefficient of 0 is achieved between the two R2A / R2 ratios at 85 °C.

[0146] Figure 18 To illustrate the temperature range between 25°C and 85°C Figure 14 and Figure 15 The VREF curves for different process angles FF, FS, TT, SF, and SS using different R2A / R2 ratios are shown in VREF circuits 1400 and 1500. As shown, VREF is very consistent across different temperature ranges.

[0147] Figure 19 Showing something similar Figure 14 The VREF circuit 1400 and VREF circuit 1900 (e.g., voltage generating circuit) differ in that resistor R1 is connected in a manner similar to resistor R2. Figure 14 The resistors R2A and R2B in the circuit are replaced by resistors R1A and R1B, where the VREF circuit 1900 has different compensation current Icomp configurations. (Details regarding the VREF circuit 1900 are omitted.) Figure 14 The components of the VREF circuit 1400 are described in the same way as the components described above.

[0148] As mentioned, the second circuit 404 of the VREF circuit 1900 includes resistors R1B and R1A, replacing resistor R1 in the VREF circuit 1400. Resistor R1B can be referred to as the first resistor, resistor R1A as the second resistor, resistor R2A as the fourth resistor, and resistor R2B as the third resistor. Additionally, the VREF circuit 1900 implements another technique for compensating for temperature conditions by changing the connection points of the compensation current Icomp, such as... Figure 19 As shown in the figure.

[0149] For example, the difference between VREF circuit 1900 and VREF circuit 1400 is that VREF circuit 1900 includes a node (e.g., a second node) 1902 located between resistors R1A and R1B, where node 1902 receives a compensation current Icomp 412. This contrasts with VREF circuit 1400, in which the node receiving the compensation current Icomp is located between resistors R2A and R2B.

[0150] The following text provides Figure 19 Some of the operating characteristics of VREF circuits.

[0151] VREF and are provided in equations (5a) and (5b) listed below. The derivation is as follows: In equations (5a) and (5b), the term (R1B / R1) replaces the term (R2A / R2) in equations (4a) and (4b). The term R1 represents the combined resistance of resistors R1A and R1B.

[0152]

[0153] (i) The first ratio of the resistance of the first resistor (resistor R1B) to the combined resistance (R1) of the first resistor (R1B) and the second resistor (R1A) is adjustable to address manufacturing variations. Additionally, the second ratio of (i) the resistance of the fourth resistor (R2A) to the combined resistance (R2) of the third resistor (R2B) and the fourth resistor (R2A) is adjustable to address manufacturing variations. In an embodiment, the second ratio is less than or equal to 1, and the first ratio is less than the second ratio. Alternatively, the first ratio may be greater than the second ratio. Furthermore, both the first and second ratios may have a maximum value of 1.

[0154] Figure 20 To show Figure 19 The graph shows the compensation current Icomp of the VREF circuit 1900. As shown, the compensation current Icomp has an approximate value of 100 nanoamperes at a temperature of 25°C and an approximate value of 0 amperes at a temperature of 85°C.

[0155] Figure 21A To show Figure 19 The graph shows the voltage values ​​of VG for the VREF circuit 1900 at different R1B / R1 and R2A / R2 ratios over a temperature range of 25°C to 85°C. For an R2A / R2 ratio of 0.98 (close to its maximum value of 1), the voltage value of VG is 656 mV at 25°C and 627.5 mV at 85°C. Using R1B / R1 ratios of 0.72 and 0.44, the voltage values ​​of VG at 25°C are approximately 649 mV and 641.5 mV, respectively. When the R1B / R1 ratio is 0.72 or 0.44, the R2A / R2 ratio can be 1 or less and can have a maximum value of 1. At 85°C, for each of the R1B / R1 ratios of 0.72 and 0.44, the voltage value of VG is approximately 627.5 mV. Additionally, when the R2A / R2 ratio is 0.98, the R1B / R1 ratio can be 1 or less than 1 and can have a maximum value of 1.

[0156] Figure 21B To show Figure 19The graph shows the voltage values ​​of the VREF circuit 1900 at different R1B / R1 and R2A / R2 ratios within a temperature range of 25°C to 85°C. For an R2A / R2 ratio of 0.98 (close to its maximum value of 1), a VREF with zero temperature coefficient TC cannot be achieved. For R1B / R1 ratios of 0.72 and 0.44, the VREF voltage values ​​at 25°C are approximately 752 mV and 753.5 mV, respectively. At 85°C, the VREF voltage value is approximately 753.5 mV for each of the R1B / R1 and R2A / R2 ratios of 0.98, 0.72, and 0.44. As shown, by connecting the second node of the compensation current Icomp between resistors R1A and R1B and gradually decreasing the R1B / R1 ratio from 0.72 to 0.44, the VREF at 25°C is approximately equal to the VREF at 85°C (e.g., 753.5 mV).

[0157] Figure 21C To show Figure 19 The VREF curves of the VREF circuit 1900 with different R1B / R1 ratios and R2A / R2 ratios, and different process angles FF, FS, TT, SF, and SS, are shown between temperatures of 25°C and 85°C.

[0158] Figure 22 Showing something similar Figure 9 The VREF circuit 900 and VREF circuit 2200 (e.g., voltage generation circuit) differ in that... Figure 9 The NMOS transistor N1 has been replaced by the PMOS transistor P8.

[0159] Figure 9 The VREF circuit 900 meets the requirements from 25°C to 85°C. = 0 (or equation (3b) = 0), which uses a relatively small ,in Figure 10 The curve shows the negative temperature coefficient of the compensation current Icomp, and Figure 12 The curve shows the negative temperature coefficient of voltage VG.

[0160] For other embodiments, = 0 can be achieved when the compensation current Icomp and voltage VG do not have negative temperature coefficients. For example, such as Figure 9 The NMOS transistor N1 with a voltage threshold of 600 mV shown can be used as follows: Figure 22 The PMOS transistor P8 shown has a voltage threshold of 700 mV. Replace it with a transistor P8. Figure 22This VREF circuit 2200 can achieve a positive temperature coefficient TC for compensating current Icomp.

[0161] Figure 23 To show Figure 22 The curve of the compensation current Icomp of the VREF circuit 2200 with a positive temperature coefficient TC shows that the compensation current Icomp is approximately -340 nanoamperes at a temperature of 25°C and approximately 0 amperes at a temperature of 85°C.

[0162] Figure 24 To show when Figure 23 The compensation current Icomp is applied to Figure 22 The graph shows the values ​​of voltage VREF, voltage VG, and voltage VDS2+Vth2 of transistor N2 in the VREF circuit 2200. Figure 24 As shown, from a temperature of 25°C to a temperature of 85°C, voltage VG has a positive temperature coefficient TC, voltage VREF has a zero temperature coefficient, and VDS2+Vth2 has a negative temperature coefficient TC.

[0163] Figure 25 To show Figure 22 The VREF curves of the VREF circuit 2200 with different R1B / R1 ratios of 0.66, 0.96, 1.0 and 0.98 and different process angles FF, FS, TT, SF and SS with an R2A / R2 ratio of 0.87 are shown. Figure 24 VREF is shown as Figure 25 The TT, where R1B / R1=1, and the corresponding equation (3b) from above is approximately zero. Different process angles can also deviate from Icomp and VG, where equation (3b) which is approximately zero may not hold. Changing the ratio of R1B / R1 and / or R2A / R2 can set equations (4b) and / or (5b) from above to approximately zero. At different process angles, the resulting temperature coefficient TC of VREF has the lowest drift rather than no drift.

[0164] The VGS voltage of the NMOS transistor in the linear region can be used to generate the reference voltage VREF. The connection node for compensating the current Icomp (e.g., located at...) Figure 14 and Figure 15 The resistors R2B and R2A (between resistors R2B and R2A) can be used to eliminate the drift of the temperature coefficient TC of VREF. The temperature coefficient TC of VREF can be modified after manufacturing by measuring VREF, as per relevant regulations. Figure 14 and Figure 15 As described.

[0165] The embodiments described herein can be applied to VREF circuits with temperature variations dominated by fluctuations in MOS threshold voltage and carrier mobility.

[0166] Figure 26 This illustrates a VREF circuit 2600 (e.g., a voltage generation circuit) that uses only NMOS transistors, wherein the VREF circuit 2600 is similar to Figure 4 The VREF circuit 400 differs in that transistor N1 is replaced by transistors N1A and N1B.

[0167] in addition, Figure 4 The VREF circuit 400 includes resistors R1 and R2, and NMOS transistors N1 and NMOS transistor N2. According to the KVL rule, VREF = VG(1 + R1 / R2). Assume... Figure 4 Transistor N1 operates in the saturation region and transistor N2 operates in the linear region. To satisfy VDS² + Vth² < VG, Figure 9 The embodiment employs an NMOS transistor N1 with a voltage threshold of 600 mV and an NMOS transistor N2 with a voltage threshold of 200 mV, wherein transistor N1 can also be replaced by multiple stacked NMOS transistors with a voltage threshold of 200 mV. For example, Figure 4 In the VREF circuit 400, transistor N1 can be replaced by two stacked NMOS transistors N1A and NMOS transistor N1B, such as... Figure 26 As shown in the diagram, transistors N1A, N1B, and N2 can all be NMOS transistors with a voltage threshold of 200 millivolts.

[0168] This invention is not limited to compensating for temperatures between 25°C and 85°C. For example, the VREF circuit described herein can compensate for temperature ranges between -10°C and 110°C, or even larger temperature ranges. The embodiments described herein can be implemented in memory devices, microcontrollers, system-on-a-chip (SoC), and other components that will be apparent to those skilled in the art as requiring precise and consistent VREF voltages across different temperature ranges.

[0169] Other embodiments of the methods described in this section may include a non-transitory computer-readable storage medium storing instructions executable by a processor to perform any of the methods described above. Yet another embodiment of the methods described in this section may include a system comprising memory and one or more processors operable to execute instructions stored in memory to perform any of the methods described above.

[0170] Any data structures and programming code described or mentioned above are stored in various implementations on a computer-readable storage medium, which may be any device or medium capable of storing programming code and / or data for use by a computer system. This includes, but is not limited to, volatile memory, non-volatile memory, application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), magnetic and optical storage devices, or other media known or developed hereafter capable of storing computer-readable media, such as disk drives, magnetic tapes, compact discs (CDs), digital versatile discs (DCDs), or digital video discs (DVDs).

[0171] Although the invention has been disclosed with reference to the preferred embodiments and examples detailed above, it should be understood that these examples are intended to be illustrative rather than restrictive. Modifications and combinations will readily occur to those skilled in the art upon consideration, and such modifications and combinations will be within the spirit of the invention and the scope of the appended claims.

Claims

1. A voltage generating circuit, the voltage generating circuit receiving an input control current and outputting a reference voltage (VREF), the voltage generating circuit comprising: The first circuit includes a first transistor and a second transistor connected in series between a first node receiving the input control current and a supply node; The second circuit includes a first resistor and a second resistor connected in series between the first node and the supply node. The input control current is shunt between the first circuit and the second circuit; The reference node outputs the reference voltage (VREF) and is connected to the first transistor of the first circuit; The second node is located between the first resistor and the second resistor and is electrically connected to the second transistor; as well as A current supply circuit, connected to the second node, provides a compensation current that affects the reference voltage (VREF) to address changes in the operating temperature of the voltage generation circuit.

2. The voltage generating circuit according to claim 1, wherein both the first resistor and the second resistor are adjustable.

3. The voltage generating circuit according to claim 1, wherein the second node is connected to the gate of the second transistor.

4. The voltage generating circuit according to claim 1, wherein the first transistor and the second transistor are NMOS transistors.

5. The voltage generating circuit according to claim 1, wherein the reference voltage (VREF) is unaffected by changes in operating temperature because the compensation current has a decreasing slope from a lower operating temperature to a higher operating temperature, the decreasing slope being caused by a negative operating temperature coefficient.

6. The voltage generating circuit according to claim 5, wherein the operating temperature is in the range of 25°C to 85°C.

7. The voltage generating circuit of claim 1, wherein the input control current is received from the power supply circuit at the first node, and wherein the power supply circuit comprises: A first power transistor, connected in series with the first transistor and the second transistor, receives power and provides the input control current to the first node; and A current generator controls the current mirrored to the first power transistor.

8. The voltage generating circuit of claim 7, wherein the current generator comprises: The first branch, (i) includes a first current generator transistor, which is connected in series with a second current generator transistor and (ii) is located between the power source and the supply node; and The second branch (i) includes a third current generator transistor connected in series with a fourth current generator transistor and a first current generator resistor and (ii) is located between the power source and the supply node, wherein the first branch is connected in parallel with the second branch.

9. The voltage generating circuit according to claim 8, wherein the first current generator transistor and the third current generator transistor are PMOS transistors, and the second current generator transistor and the fourth current generator transistor are NMOS transistors.

10. The voltage generating circuit according to claim 1, wherein the ratio of the resistance of the first resistor to the resistance of the second resistor is less than 1.

11. The voltage generating circuit of claim 10, wherein the ratio is approximately 0.

2.

12. A voltage generating circuit, the voltage generating circuit receiving an input control current and outputting a reference voltage (VREF), the voltage generating circuit comprising: The first circuit includes a first transistor and a second transistor connected in series between a first node receiving the input control current and a supply node; The second circuit includes a first resistor, a second resistor, and a third resistor connected in series between the first node and the supply node. The input control current is shunt between the first circuit and the second circuit; The reference node outputs the reference voltage (VREF) and is connected to the first transistor of the first circuit; The second node is located between the second resistor and the third resistor and is electrically connected to the second transistor; as well as A current supply circuit, connected to the second node, provides a compensation current that affects the reference voltage (VREF) to address changes in the operating temperature of the voltage generation circuit.

13. The voltage generating circuit according to claim 12, wherein (i) the ratio of the resistance of the third resistor to (ii) the combined resistance of the second resistor and the third resistor is adjustable.

14. The voltage generating circuit of claim 13, wherein the ratio has a maximum value of 1.

15. The voltage generating circuit of claim 12, wherein the current supply circuit comprises: A positive bias current circuit system provides a current with a positive temperature coefficient from a lower operating temperature to a higher operating temperature; and A negative bias current circuit system provides a current with a negative temperature coefficient from the lower operating temperature to the higher operating temperature. The compensation current is a combination of the current having the positive temperature coefficient and the current having the negative temperature coefficient.

16. The voltage generating circuit of claim 15, wherein at the higher operating temperature, the combination of the current having the positive temperature coefficient and the current having the negative temperature coefficient results in the compensation current having an approximate value of 0 amperes.

17. The voltage generating circuit according to claim 12, wherein the first transistor and the second transistor are NMOS transistors.

18. A voltage generating circuit, the voltage generating circuit receiving an input control current and outputting a reference voltage (VREF), the voltage generating circuit comprising: The first circuit includes a first transistor and a second transistor connected in series between a first node receiving the input control current and a supply node; The second circuit includes a first resistor, a second resistor, a third resistor, and a fourth resistor connected in series between the first node and the supply node. The input control current is shunt between the first circuit and the second circuit; The reference node outputs the reference voltage (VREF) and is connected to the first transistor of the first circuit; The second node is located between the first resistor and the second resistor and is electrically connected to the second transistor; as well as A current supply circuit, connected to the second node, provides a compensation current that affects the reference voltage (VREF) to address changes in the operating temperature of the voltage generation circuit.

19. The voltage generating circuit according to claim 18, wherein: (i) the resistance of the first resistor and (ii) the first ratio of the combined resistance of the first resistor and the second resistor are adjustable; and (i) The second ratio of the resistance of the fourth resistor to (ii) the combined resistance of the third resistor and the fourth resistor is adjustable.

20. The voltage generating circuit of claim 19, wherein the first ratio and the second ratio have a maximum value of 1.

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