Memory controller, operating method thereof, and memory device including same

Abstract

Embodiments of the present disclosure relate to a memory controller, an operating method thereof, and a memory device including the same. According to an embodiment of the present disclosure, a memory controller can effectively manage error detection data, and may include: an error detection circuit configured to receive write data from outside and generate error detection data corresponding to the write data; a data compression circuit configured to compress the write data to generate compressed data corresponding to partial logical addresses among a plurality of logical addresses, the plurality of logical addresses corresponding to the write data; and a mapping data controller configured to manage mapping data including a mapping relationship between the plurality of logical addresses and a physical address of the memory device, and store the physical address mapped to the partial logical address, the error detection data, and compression information related to the compression data in the mapping data.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0061868, filed on May 10, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to a semiconductor device, and more specifically, to a memory controller for compressing and storing data, a method of operating the controller, and a storage device including the memory controller. Background Technology

[0004] A storage device is a means of storing data under the control of a host computer, a mobile terminal such as a smartphone or tablet, or various electronic devices. A storage device may include a memory device for storing data and a memory controller for controlling the memory device.

[0005] When a storage device receives data from a host, it can compress and store the data. When the storage device decompresses the compressed data and transmits the decompressed data back to the host, it can perform error detection operations to check data integrity. For error detection operations, the storage device can generate and manage error detection data for the raw data received from the host. Summary of the Invention

[0006] Embodiments of this disclosure provide a memory controller capable of effectively managing error detection data, a method of operating the controller, and a storage device including the memory controller.

[0007] According to embodiments of this disclosure, a memory controller may include: an error detection circuit configured to receive write data from an external source and generate error detection data corresponding to the write data; a data compression circuit configured to compress the write data to generate compressed data corresponding to a portion of a plurality of logical addresses, the plurality of logical addresses corresponding to the write data; and a mapping data controller configured to manage mapping data including mapping relationships between the plurality of logical addresses and physical addresses of a memory device, and to store in the mapping data the physical addresses mapped to the portion of the logical addresses, the error detection data, and compression information related to the compressed data.

[0008] According to embodiments of this disclosure, a method for operating a memory controller is provided. The memory controller controls a memory device and a buffer memory. The memory device stores data, and the buffer memory temporarily stores data to be provided to the memory device or data received from the memory device. The method may include: receiving write data and a plurality of logical addresses corresponding to the write data from an external source; generating error detection data corresponding to the write data; compressing the write data to generate compressed data corresponding to a portion of the plurality of logical addresses; providing the compressed data to the buffer memory; storing in mapping data the physical addresses mapped to the portion of the logical addresses, the error detection data, and compression information related to the compressed data; and controlling the compressed data to move from the buffer memory to the memory device.

[0009] The mapping data stores: the mapped physical address in a portion of the storage area allocated to each of the multiple logical addresses included in the mapping data; and error detection data and compression information in the remaining storage area of ​​the allocated storage area, excluding the portion of the storage area.

[0010] Storing error detection data and compression information may include: in response to the compression ratio of the written data being greater than or equal to a preset threshold, storing error detection data and compression information in the mapped data.

[0011] According to embodiments of this disclosure, a method for operating a memory controller is provided. The memory controller controls a memory device and a buffer memory. The memory device stores data, and the buffer memory temporarily stores data to be provided to the memory device or data received from the memory device. The method may include: receiving a read request from an external source corresponding to a plurality of logical addresses; obtaining the physical address of a portion of the logical addresses mapped to the plurality of logical addresses from mapping data; controlling compressed data stored in the memory device to move to the buffer memory based on the obtained physical address; decompressing the compressed data moved to the buffer memory based on compression information stored in the mapping data; performing an error detection operation on the decompressed data based on error detection data stored in the mapping data; and providing the decompressed data to an external source according to the error detection operation.

[0012] According to embodiments of this disclosure, a storage device may include: a memory device configured to store data; a buffer memory configured to temporarily store data provided from the memory device or data to be provided to the memory device; and a memory controller configured to receive write data from an external source, generate error detection data corresponding to the write data, compress the write data to generate compressed data, control the buffer memory to store the write data, store in mapping data a physical address indicating the location of the compressed data, compression information associated with the compressed data, and error detection data, and control the buffer memory and the memory device to store the compressed data.

[0013] According to this disclosure, the memory controller can effectively manage error detection data. Attached Figure Description

[0014] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0015] Figure 2 This is a diagram illustrating compressed data according to an embodiment of the present disclosure.

[0016] Figure 3 This is a diagram illustrating the storage of physical addresses, error detection data, and compression information in mapping data according to an embodiment of the present disclosure.

[0017] Figure 4 This is a diagram illustrating the storage of physical addresses, error detection data, and compression information in mapping data according to another embodiment of the present disclosure.

[0018] Figure 5 This is a diagram illustrating the storage of physical addresses, error detection data, and compression information in mapping data according to yet another embodiment of the present disclosure.

[0019] Figure 6 This is a diagram illustrating the execution of a write operation according to an embodiment of the present disclosure.

[0020] Figure 7 This is a diagram illustrating the execution of a read operation according to an embodiment of the present disclosure.

[0021] Figure 8 This is a flowchart illustrating an operation method of a memory controller according to an embodiment of the present disclosure.

[0022] Figure 9 This is a flowchart illustrating another method of operation of a memory controller according to an embodiment of the present disclosure. Detailed Implementation

[0023] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this disclosure are shown merely to illustrate embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described herein.

[0024] Figure 1 This is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0025] Reference Figure 1 The storage device 50 may be a device that stores data under the control of a host 400 such as a cellular phone, smartphone, MP3 player, laptop computer, server computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0026] Storage device 50 may include memory device 100, buffer memory 200 and memory controller 300.

[0027] Storage device 50 can be configured as one of the following: SSD, MMC and eMMC multimedia cards, Universal Serial Bus (USB) storage devices, Universal Flash Storage (UFS) devices, Peripheral Component Interconnect (PCI), PCI-E card type storage devices, Compact Flash (CF) cards, Smart Media Cards, and Memory Sticks.

[0028] The storage device 50 can be manufactured as one of various types of packages. For example, the storage device 50 can be manufactured as any of the following package types: POP (Package-on-Package), System-in-Package (SIP), System-on-Chip (SOC), Multi-Chip Package (MCP), Chip-on-Board (COB), Wafer-Level Fabrication Package (WFP), and Wafer-Level Stacked Package (WSP).

[0029] The memory device 100 can store data. The memory device 100 may include multiple memory blocks for storing data. Each memory block may include multiple memory cells.

[0030] In this embodiment, the memory device 100 may be a non-volatile memory, in which data is not lost even when power is disconnected. For ease of description, in this disclosure, the memory device 100 is a NAND flash memory.

[0031] In this embodiment, the memory device 100 may receive commands and addresses from the memory controller 300. The memory device 100 may perform operations indicated by the commands on a region selected by the address. For example, the memory device 100 may perform write operations (or programming operations), read operations, and erase operations.

[0032] The buffer memory 200 can temporarily store data provided from the memory device 100 or data to be provided to the memory device 100.

[0033] In this embodiment, the memory device 100 may be volatile memory, in which data is lost when power is disconnected. For example, the memory device may be configured as dynamic random access memory (DRAM), static random access memory (SRAM), etc.

[0034] The memory controller 300 can control the overall operation of the storage device 50.

[0035] When power is applied to storage device 50, memory controller 300 can execute firmware. When storage device 100 is a flash memory device, the firmware (FW) may include: a host interface layer (HIL) that controls communication with host 400; a flash translation layer (FTL) that controls communication between host 400 and storage device 100; and a flash interface layer (FIL) that controls communication with storage device 100.

[0036] In this embodiment, the memory controller 300 can receive data and logical block addresses (LBAs) from the host 400, and can convert the logical block addresses to physical block addresses (PBAs). The physical block addresses (PBAs) indicate the addresses of memory cells in the memory device 100 containing data to be stored. In this disclosure, logical block addresses and "logical address" or "logical address" can be used to have the same meaning. In this disclosure, physical block addresses and "physical address" or "physical address" can be used to have the same meaning.

[0037] In an embodiment, the memory controller 300 may provide the memory device 100 with commands, addresses or data corresponding to the corresponding operation according to the request of the host 400, so as to perform programming operation, read operation or erase operation.

[0038] In this embodiment, the memory controller 300 can independently generate commands, addresses, and data regardless of requests from the host 400, and transmit these commands, addresses, and data to the memory device 100. For example, the memory controller 300 can provide commands, addresses, and data to the memory device 100 to perform programming and read operations involved in internal operations such as wear leveling, read recycling, and garbage collection.

[0039] In this embodiment, the memory controller 300 may include a processor 310, a memory 320, a host interface 330, a memory interface 340, a memory operation controller 350, an error detection circuit 360, a data compression circuit 370, a mapped data controller 380, and a communication bus 390. The processor 310, memory 320, host interface 330, memory interface 340, memory operation controller 350, error detection circuit 360, data compression circuit 370, and mapped data controller 380 can communicate with each other via the communication bus 390.

[0040] The processor 310 can execute firmware, code, or one or more commands that include information required for the operation of the memory controller 300.

[0041] The memory 320 can be used as a buffer memory, cache memory, operation memory, etc.

[0042] In addition, memory 320 may store firmware, code, and one or more commands, including information required for the operation of memory controller 300.

[0043] The memory controller 300 can communicate with external devices (e.g., host 400, application processor, etc.) via the host interface 330.

[0044] The memory controller 300 can communicate with the memory device 100 through the memory interface 340. The memory controller 300 can transmit commands, addresses, control signals, etc. to the memory device 100 and receive data through the memory interface 340.

[0045] The memory operation controller 350 can control the operation of the memory device 100 and the buffer memory 200.

[0046] For example, the memory operation controller 350 can generate commands for controlling the memory device 100 and the buffer memory 200. Furthermore, the memory operation controller 350 can translate logical addresses provided by the host 400 into physical addresses based on mapping data.

[0047] Furthermore, the memory operation controller 350 can control the buffer memory 200 to store write data provided by the host 400, compressed data obtained by compressing the write data, etc. Additionally, the memory operation controller 350 can control the transfer of data stored in the buffer memory 200 to the memory device 100 according to a request from the host 400.

[0048] Furthermore, when the memory operation controller 350 receives a read request corresponding to multiple logical addresses from the host 400, the memory operation controller 350 can receive read data, compressed data, etc. from the memory device 100 based on the mapped physical addresses corresponding to the multiple logical addresses, and can provide the received read data, compressed data, etc. to the buffer memory 200.

[0049] Error detection circuit 360 can generate error detection data (e.g., parity, CRC data, etc.) corresponding to the write data provided from the host.

[0050] In this embodiment, the error detection circuit 360 can perform error detection operations on the written data based on error detection data. For example, cyclic redundancy check (CRC) technology can be used to perform error detection operations. In this case, the error detection data can be CRC data. For example, the error detection circuit 360 can generate error detection data by performing encoding based on the written data. The error detection circuit 360 can detect errors by performing decoding on the read data or decompressed data based on the error detection data. The error detection circuit 360 can request that the decompressed data be provided to the host 400 based on the result of the error detection operation.

[0051] In the above example, the error detection operation is described as using CRC technology, but the embodiments of this disclosure are not limited to this, and various technologies that can detect errors in data can be used in the error detection operation.

[0052] Furthermore, the error detection circuit 360 can perform error correction when data is stored in or read from the memory device 100. For example, the error detection circuit 360 can perform error correction code (ECC) encoding based on the data to be written to the memory device 100. The encoded data can then be transmitted to the memory device 100. The error correction circuit 360 can also perform error correction code decoding on the data received from the memory device 100.

[0053] The data compression circuit 370 can compress the written data and generate compressed data. The compressed data can be stored in the buffer memory 200 and the memory device 100 via the memory operation controller 350.

[0054] Furthermore, based on a read request from the host 400, the read data read from the memory device 100 can be stored in the buffer memory 200. In this case, when it is determined that the read data is compressed, the data compression circuit 370 can decompress the read data according to the compression information stored in the mapping data.

[0055] The mapping data controller 380 can manage mapping data, which includes the mapping relationship between logical addresses provided by the host 400 and physical addresses of the memory device 100.

[0056] In an embodiment, the mapping data controller 380 may store physical addresses mapped to logical addresses corresponding to compressed data, error detection data, and compression information associated with the compressed data in the mapping data. For example, the mapping data controller 380 may store physical addresses in a portion of a storage area allocated to multiple logical addresses corresponding to the written data in the mapping data, and store compression information and error detection data in the remaining portion of the storage area.

[0057] The host 400 can communicate with the storage device 50 using at least one of the following communication standards or interfaces: Universal Serial Bus (USB), Serial AT Accessory (SATA), Serial Attached SCSI (SAS), High Speed ​​Chip Interconnect (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI High Speed ​​(PCIe), Non-Volatile Memory High Speed ​​(NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Reduced Load DIMM (LRDIMM).

[0058] Figure 2 This is a diagram illustrating compressed data according to an embodiment of the present disclosure.

[0059] Reference Figure 2 When the data compression circuit 370 receives the write data WDATA and the corresponding logical addresses LA1 to LA4 from the host 400, the data compression circuit 370 can compress the write data WDATA. The compressed data WDATA can then be provided to the buffer memory 200.

[0060] The data compression circuit 370 can compress the written data WDATA and generate compressed data CDATA corresponding to a portion of the logical addresses LA1 to LA3 among multiple logical addresses LA1 to LA4. For example, in Figure 2In this configuration, the data compression rate is 25%, and the data size allocated to each logical address is the same. In this case, the data compression circuit 370 can compress write data WDATA, which has a size corresponding to multiple logical addresses LA1 to LA4, into compressed data CDATA, which has a size corresponding to a portion of logical addresses LA1 to LA3. In this case, the physical addresses PA1 to PA3 corresponding to the compressed data can be mapped to the partial logical addresses LA1 to LA3. The mapping data controller 380 can store the physical addresses PA1 to PA3 mapped to the partial logical addresses LA1 to LA3 in the mapping data.

[0061] After the mapped physical addresses PA1 to PA3 are stored in the storage area AREA allocated to multiple logical addresses LA1 to LA4 in the mapped data, an empty storage area can be generated. That is, by compressing the data, the storage area used in the mapped data can be reduced, and free storage areas can be created. Therefore, the mapped data controller 380 can store error detection data and compression information in the empty storage area through data compression. For example, the mapped data controller 380 can allocate the storage area AREA to each of the multiple logical addresses LA1 to LA4. The mapped data controller 380 can store the physical address, error detection data, and compression information in the storage area AREA allocated to each of the multiple logical addresses LA1 to LA4.

[0062] In this embodiment, when the compression ratio of the written data is equal to or greater than a preset threshold, the mapping data controller 380 can store error detection data and compression information in the mapping data. The compression ratio and threshold can be set differently depending on the embodiment. When the compression ratio of the written data is less than the preset threshold, the error detection data and compression information can be stored in the memory 320 or buffer memory 200 in the memory controller 300 instead of in the mapping data.

[0063] In an embodiment, the compression ratio can be determined according to a predetermined strategy and can be information pre-stored in the data compression circuit 370.

[0064] In this embodiment, the mapping data controller 380 can compare the size of the storage region AREA allocated to multiple logical addresses LA1 to LA4 with the size of the storage region corresponding to physical addresses PA1 to PA3, and check the compression ratio of the written data based on the comparison result. Furthermore, the mapping data controller 380 can check the size of the storage region that is empty due to data compression based on the comparison result.

[0065] In this embodiment, the mapping data controller 380 can determine the priority of data or information to be stored in the mapping data based on the size of the empty storage area resulting from data compression. For example, when the size of the empty storage area is greater than or equal to a predetermined size, the mapping data controller 380 can store error detection data and compression information in the mapping data. As another example, when the size of the empty storage area is less than the predetermined size, the error detection data and compression information can be stored in the memory 320 or buffer memory 200 of the memory controller 300 instead of in the mapping data.

[0066] Furthermore, the mapping data controller 380 can determine the type of error detection data based on the size of the empty storage area resulting from data compression. For example, the mapping data controller 380 can store error detection data for error detection techniques, as the size of the empty storage area in the mapping data increases, requiring more capacity for the error detection data of the error detection techniques.

[0067] In an embodiment, when the size of the empty storage area resulting from data compression is greater than a predetermined size, the mapping data controller 380 can provide information about the remaining unstored areas in the storage area AREA to the processor 310 or the host 400. For example, when the data compression ratio is set to 50% or greater, the mapping data controller 380 can store physical addresses, error detection data, and compression information in the mapped data, and then provide information about the remaining unstored areas to the processor 310 or the host 400. However, in the above example, information about the remaining unstored areas is provided when the data compression ratio is 50% or greater, but the embodiments of this disclosure are not limited to this. The data compression ratio can be set differently depending on the embodiment.

[0068] Reference Figures 3 to 5 Provide a detailed example of storing physical addresses, error detection data, and compression information in the mapping data.

[0069] Figure 3 This is a diagram illustrating the storage of physical addresses, error detection data, and compression information in mapping data according to an embodiment of the present disclosure.

[0070] Reference Figure 3In one embodiment, the mapping data controller 380 may store physical addresses PA1 to PA3 and compression information CINFO in the storage area AREA allocated to a portion of logical addresses LA1 to LA3 within the storage area AREA allocated to each of the plurality of logical addresses LA1 to LA4, and may store error detection data EDDATA in the remaining storage area. The compression information CINFO may include data CBIT indicating whether written data is compressed and at least one of offset data OFFSET1 to OFFSET3 indicating the location of the physical address stored in the storage area AREA allocated to each of the plurality of logical addresses.

[0071] exist Figure 3 In this context, written data can be compressed at a rate of 25%.

[0072] For example, in the storage area allocated to the first logical address LA1, a first physical address PA1 mapped to the first logical address LA1, data CBIT indicating whether the data stored in the first physical address PA1 is compressed, and first offset data OFFSET1 indicating the location where the first physical address PA1 is stored can be stored. Specifically, when the size of the storage area allocated to the first logical address LA1 is 32 bits, 1 bit can be allocated to the data CBIT, 2 bits can be allocated to the first offset data OFFSET1, and the remaining bits can be allocated to the first physical address PA1. That is, Figure 3 The size of the first physical address PA1 shown can be greater than Figure 2 The first physical address PA1 shown is 3 bits smaller than its value.

[0073] Furthermore, in the storage area allocated to the second logical address LA2, the second physical address PA2 mapped to the second logical address LA2, the data CBIT indicating whether the data stored in the second physical address PA2 is compressed, and the second offset data OFFSET2 indicating the location of the stored second physical address PA2 can be stored. Specifically, when the size of the storage area allocated to the second logical address LA2 is 32 bits, 1 bit can be allocated to the data CBIT, 2 bits can be allocated to the second offset data OFFSET2, and the remaining bits can be allocated to the second physical address PA2. That is, Figure 3 The size of the second physical address PA2 shown can be greater than Figure 2 The second physical address PA2 shown is 3 bits smaller than its value.

[0074] Furthermore, in the storage area allocated to the third logical address LA3, the third physical address PA3 mapped to the third logical address LA3 can be stored, along with data CBIT indicating whether the data stored at the third physical address PA3 is compressed, and third offset data OFFSET3 indicating the location of the stored third physical address PA3. Specifically, when the size of the storage area allocated to the third logical address LA3 is 32 bits, 1 bit can be allocated to the data CBIT, 2 bits can be allocated to the third offset data OFFSET3, and the remaining bits can be allocated to the third physical address PA3. That is to say, Figure 3 The size of the third physical address PA3 shown can be greater than Figure 2 The third physical address PA3 shown is 3 bits smaller than its value.

[0075] Furthermore, error detection data EDDATA can be stored in the memory area allocated to the fourth logical address LA4. Error detection data EDDATA can be used to detect errors during the decompression of compressed data stored in the first to third physical addresses PA1 to PA3. For example, error detection circuit 360 can generate error detection data EDDATA based on the encoding of the written data according to various error detection techniques. Error detection circuit 360 can detect errors by performing decoding on read or decompressed data based on error detection data EDDATA.

[0076] In an embodiment, the error detection data EDDATA can be data used in various error detection techniques such as CRC, ECC, Frame Check Sequence (FCS), parity check, checksum, header error control (HEC), backward error correction (BEC), and forward error correction (FEC).

[0077] In an embodiment, the size of the error detection data EDDATA can be equal to or greater than the size of the storage area allocated to at least one logical address.

[0078] Furthermore, the compressed information CINFO can be further stored in the storage area allocated to the fourth logical address LA4.

[0079] Figure 4 This is a diagram illustrating the storage of physical addresses, error detection data, and compression information in mapping data according to another embodiment of the present disclosure.

[0080] Reference Figure 4 The written data can be compressed at a rate of 50%.

[0081] For example, in the storage area allocated to the first logical address LA1, a first physical address PA1 mapped to the first logical address LA1, data CBIT indicating whether the data stored in the first physical address PA1 is compressed, and a first offset data OFFSET1 indicating the location where the first physical address PA1 is stored can be stored. Specifically, when the size of the storage area allocated to the first logical address LA1 is 32 bits, 1 bit can be allocated to the data CBIT, 2 bits can be allocated to the first offset data OFFSET1, and the remaining bits can be allocated to the first physical address PA1.

[0082] Furthermore, in the storage area allocated to the second logical address LA2, a second physical address PA2 mapped to the second logical address LA2, data CBIT indicating whether the data stored in the second physical address PA2 is compressed, and second offset data OFFSET2 indicating the location where the second physical address PA2 is stored can be stored. Specifically, when the size of the storage area allocated to the second logical address LA2 is 32 bits, 1 bit can be allocated to the data CBIT, 2 bits can be allocated to the second offset data OFFSET2, and the remaining bits can be allocated to the second physical address PA2.

[0083] Furthermore, error detection data EDDATA can be stored in the memory areas allocated to the third logical address LA3 and the fourth logical address LA4. EDDATA can be used to detect errors during the decompression of compressed data stored at the first physical address PA1 and the second physical address PA2. As the size of EDDATA increases, the accuracy of error detection can be improved.

[0084] Furthermore, the compressed information CINFO can be further stored in the storage areas allocated to the third logical address LA3 and the fourth logical address LA4.

[0085] Figure 5 This is a diagram illustrating the storage of physical addresses, error detection data, and compression information in mapping data according to yet another embodiment of the present disclosure.

[0086] Reference Figure 5 The mapping data controller 380 can store physical addresses PA1 and PA2 in a portion of a storage area AREA allocated to each of the multiple logical addresses LA1 to LA4, and can store error detection data EDDATA and compressed information CINFO in the remaining storage area.

[0087] For example, the mapping data can sequentially store data CBIT indicating whether the data stored at the first physical address PA1 is compressed, first offset data OFFSET1, and the first physical address PA1. One bit can be allocated to the data CBIT, two bits can be allocated to the first offset data OFFSET1, and bits corresponding to the size of the storage area allocated to a logical address can be allocated to the first physical address PA1.

[0088] Furthermore, the mapping data can sequentially store data CBIT indicating whether the data stored at the second physical address PA2 is compressed, second offset data OFFSET2, and the second physical address PA2. One bit can be allocated to data CBIT, two bits can be allocated to the second offset data OFFSET2, and bits corresponding to the size of the storage area allocated to a logical address can be allocated to the second physical address PA2.

[0089] In addition, the mapping data can store error detection data EDDATA in the remaining storage area.

[0090] Furthermore, the mapped data can be further stored in the remaining storage area as compressed information (CINFO).

[0091] exist Figures 3 to 5 The diagram shows one bit allocated to the data CBIT and two bits allocated to the offset data OFFSET1, OFFSET2, and OFFSET3, but embodiments of this disclosure are not limited thereto. For example, the data CBIT may be allocated more than one bit, and the offset data OFFSET1, OFFSET2, and OFFSET3 may be allocated more than two bits or less than two bits.

[0092] Figure 6 This is a diagram illustrating the execution of a write operation according to an embodiment of the present disclosure.

[0093] Reference Figure 6 When the host 400 receives write data WDATA and logical address LA, the memory operation controller 350 can receive logical address LA through the host interface 330, and the error detection circuit 360 and data compression circuit 370 can receive write data WDATA through the host interface 330.

[0094] Error detection circuit 360 can generate error detection data EDDATA corresponding to the written data WDATA, and provide error detection data EDDATA to mapping data controller 380.

[0095] The data compression circuit 370 can compress the written data WDATA to generate compressed data CDATA, and provide the compressed data CDATA to the buffer memory. Furthermore, the data compression circuit 370 can provide compression information CINFO associated with the compressed data CDATA to the mapping data controller 380.

[0096] The memory operation controller 350 can translate the logical address LA into a physical address PA and provide the physical address PA to the mapping data controller 380. The physical address PA can correspond to the size of the compressed data CDATA.

[0097] The mapping data controller 380 can store physical address PA, error detection data EDDATA, and compressed information CINFO in the mapping data.

[0098] The memory operation controller 350 can generate a write command based on the host's clear request and provide the write command WCMD and physical address PA to the memory device 100 to control the reception and storage of compressed data CDATA stored in the buffer memory 200.

[0099] Although Figure 6 Although not shown in the diagram, error detection data can be added and transmitted during the transfer of compressed data CDATA between buffer memory 200 and memory device 100. The error detection data may differ from the error detection data corresponding to the written data. For example, buffer memory 200 may generate error detection data for compressed data CDATA and provide both the compressed data CDATA and the error detection data to memory device 100. Memory device 100 can receive the compressed data CDATA and the error detection data and perform error detection based on the error detection data to check the integrity of the compressed data CDATA. Furthermore, the compressed data CDATA can be encoded with an error correction code by error detection circuit 360, and the data encoded with the error correction code can be transmitted to memory device 100.

[0100] In addition, Figure 6 In this embodiment, the written data is compressed and stored in the buffer memory 200, but the embodiments of this disclosure are not limited thereto. For example, the buffer memory 200 may store the written data, and the written data may be compressed before being transferred to the memory device 100.

[0101] Figure 7 This is a diagram illustrating the execution of a read operation according to an embodiment of the present disclosure.

[0102] Reference Figure 7When the host 400 receives a read request REQ and the logical address LA corresponding to the read request REQ, the memory operation controller 350 can receive the read request REQ and the logical address LA through the host interface 330.

[0103] The memory operation controller 350 can convert the logical address LA into the physical address PA based on the mapping data included in the mapping data controller 380, according to the read request REQ.

[0104] The memory operation controller 350 can generate a read command RCMD and provide the read command RCMD and physical address PA to the memory device 100 to control the transfer of read data stored in the memory device 100 at the location indicated by the physical address PA to the buffer memory 200.

[0105] Although Figure 7 Although not shown in the diagram, error detection data can be added and transmitted during the transfer of read data RDATA between buffer memory 200 and memory device 100. The error detection data may differ from the error detection data EDDATA corresponding to the decompressed data. For example, memory device 100 can generate error detection data for read data RDATA and provide both RDATA and error detection data to buffer memory 200. Buffer memory 200 can receive read data RDATA and error detection data and perform error detection based on the error detection data to check the integrity of read data RDATA. Furthermore, read data RDATA can be decoded using error correction codes by error detection circuit 360, and the decoded data can be stored in buffer memory 200.

[0106] The data compression circuit 370 can decompress compressed data based on compression information stored in the mapping data. For example, the data compression circuit 370 can determine whether the read data RDATA is compressed data based on the compression information. Specifically, when the physical address PA is stored together with the compression information, the data compression circuit 370 can determine that the read data RDATA is compressed data. In this case, the data compression circuit 370 can generate the original data ODATA by decompressing the read data RDATA.

[0107] The error detection circuit 360 can perform error detection operations on the decompressed data based on the error detection data stored in the mapping data.

[0108] For example, error detection circuit 360 can perform an error detection operation on raw data ODATA based on error detection data, and can generate a pass signal PASS when the error detection operation is successful. Error detection circuit 360 can provide the pass signal PASS to data compression circuit 370. Data compression circuit 370 can provide raw data ODATA to host 400 through host interface 330 in response to the pass signal PASS. As another example, when the error detection operation fails, error detection circuit 360 can request data compression circuit 370 to decompress again or read data from memory device 100 again. As yet another example, when the error detection operation fails, error detection circuit 360 can provide a read failure signal to host 400 through host interface 330.

[0109] Figure 8 This is a flowchart illustrating an operation method of a memory controller according to an embodiment of the present disclosure. Figure 8 The method shown can be, for example, by Figure 1 The memory controller 300 shown in the diagram performs this action. Specifically, Figure 8 The method shown in the diagram can be a flowchart describing a method by which the memory controller 300 controls a write operation according to a write request from the host 400.

[0110] Reference Figure 8 In operation S801, the memory controller 300 can receive write data and multiple logical addresses corresponding to the write data from the host 400.

[0111] In operation S803, the memory controller 300 can generate error detection data corresponding to the written data.

[0112] In operation S805, the memory controller 300 can compress the written data and generate compressed data corresponding to a portion of the logical addresses among multiple logical addresses.

[0113] In operation S807, the memory controller 300 can provide compressed data to the buffer memory 200.

[0114] In operation S809, the memory controller 300 can store in the mapped data physical addresses mapped to partial logical addresses, error detection data, and compression information related to compressed data.

[0115] For example, the memory controller 300 may store the physical address mapped to the partial logical address in a portion of the memory region allocated to each of the plurality of logical addresses included in the mapping data. The memory controller 300 may also store error detection data and compression information in the remaining memory region, excluding the partial memory region, allocated to each of the plurality of logical addresses.

[0116] Furthermore, the memory controller 300 can store error detection data and compression information in the mapped data in response to the fact that the compression ratio of the written data is equal to or greater than a preset threshold.

[0117] In operation S811, the memory controller 300 can control the movement of compressed data from the buffer memory 200 to the memory device 100.

[0118] Figure 9 This is a flowchart illustrating another method of operation of a memory controller according to an embodiment of the present disclosure. Figure 9 The method shown can be, for example, by Figure 1 The memory controller 300 shown in the diagram performs this action. Specifically, Figure 9 The method shown in the diagram may be a flowchart describing a method by which the memory controller 300 controls a read operation according to a read request from the host 400.

[0119] Reference Figure 9 In operation S901, the memory controller 300 can receive read requests corresponding to multiple logical addresses from the host 400.

[0120] In operation S903, the memory controller 300 can obtain the physical addresses mapped to multiple logical addresses from the mapping data.

[0121] In operation S905, the memory controller 300 can control the movement of compressed data stored in the memory device 100 to the buffer memory 200 based on the obtained physical address.

[0122] In operation S907, the memory controller 300 can decompress the compressed data moved to the buffer memory 200 based on the compression information stored in the mapping data.

[0123] In operation S909, the memory controller 300 can perform error detection operations on the decompressed data based on error detection data stored in the mapped data.

[0124] In operation S911, the memory controller 300 can provide the decompressed data to the host 400 according to the error detection operation.

[0125] According to embodiments of this disclosure, the memory controller can effectively manage error detection data.

[0126] While embodiments of this disclosure have been shown and described with reference to specific examples, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0127] In the above embodiments, all operations may be selectively performed or some operations may be omitted. In each embodiment, the operations are not necessarily performed in the described order and may be rearranged. The embodiments disclosed in this specification and drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure.

[0128] Embodiments of this disclosure have been described in the accompanying drawings and specification. Although specific terminology is used herein, it is only for describing embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein. Furthermore, embodiments can be combined to form other embodiments.

Claims

1. A memory controller, comprising: An error detection circuit receives written data from the outside and generates error detection data corresponding to the written data. A data compression circuit compresses the written data to generate compressed data corresponding to a portion of a plurality of logical addresses, wherein the plurality of logical addresses correspond to the written data. as well as A mapping data controller manages mapping data that includes mapping relationships between the plurality of logical addresses and physical addresses of memory devices, and stores in the mapping data the physical addresses mapped to the partial logical addresses, the error detection data, and compression information related to the compressed data.

2. The memory controller according to claim 1, wherein, The compression information includes at least one of the following: data indicating whether the written data is compressed, and at least one of the following: offset data indicating the location where the physical address is stored in the storage area allocated to each of the plurality of logical addresses.

3. The memory controller according to claim 1, wherein, The mapping data controller: The storage area is allocated to each of the plurality of logical addresses, and The physical address, the error detection data, and the compression information are stored in a storage area allocated to each of the plurality of logical addresses.

4. The memory controller according to claim 3, wherein, The mapping data controller: The physical address and the compression information are stored in a portion of the storage area allocated to each of the plurality of logical addresses, and in a portion of the storage area allocated to the portion of the logical addresses. The error detection data is stored in the remaining storage area of ​​the storage area allocated to each of the plurality of logical addresses, excluding the storage area allocated to the partial logical addresses.

5. The memory controller according to claim 3, wherein, The mapping data controller: The physical address is stored in a portion of the storage area allocated to each of the plurality of logical addresses, and The error detection data and the compression information are stored in the remaining storage area, excluding the partial storage area, within the storage area allocated to each of the plurality of logical addresses.

6. The memory controller according to claim 1, wherein, The mapping data controller: When the compression ratio of the written data is equal to or greater than a preset threshold, the error detection data and the compression information are stored in the mapping data.

7. The memory controller according to claim 1, further comprising: Memory operation controller: The control buffer stores the compressed data, and According to an external request, the buffer memory and the memory device are controlled to transfer the compressed data from the buffer memory to the memory device.

8. The memory controller according to claim 7, wherein, The memory operation controller: The compressed data is received from the memory device based on the physical address stored in the mapping data, and The received compressed data is provided to the buffer memory.

9. The memory controller according to claim 8, wherein, The data compression circuit decompresses the compressed data based on the compression information stored in the mapping data.

10. The memory controller according to claim 9, wherein, The error detection circuit performs error detection operations on the decompressed data based on the error detection data stored in the mapping data.

11. A method of operating a memory controller, the memory controller controlling a memory device and a buffer memory, the memory device storing data, the buffer memory temporarily storing data to be provided to the memory device or data received from the memory device, the method comprising: Receive read requests from external sources that correspond to multiple logical addresses; Obtain the physical address of a portion of the logical addresses mapped to the plurality of logical addresses from the mapping data; Based on the obtained physical address, the compressed data stored in the memory device is moved to the buffer memory; The compressed data moved to the buffer memory is decompressed based on the compression information stored in the mapping data; Error detection is performed on the decompressed data based on the error detection data stored in the mapping data; as well as The decompressed data is provided to the outside based on the error detection operation.

12. The method according to claim 11, wherein, Performing the error detection operation includes: In response to the error detection operation being successful, a pass signal is generated.

13. The method according to claim 12, wherein, The decompressed data provided to external parties includes: In response to the pass signal, the decompressed data is provided to the outside.

14. The method of claim 11, further comprising: In response to the failure of the error detection operation, the process returns to decompressing the compressed data that has been moved to the buffer memory.

15. The method of claim 11, further comprising: In response to the failure of the error detection operation, the compressed data stored in the memory device is moved to the buffer memory based on the obtained physical address.

16. The method of claim 11, further comprising: In response to the failure of the error detection operation, a read failure signal is provided to the outside.

17. A storage device, comprising: Memory devices that store data; A buffer memory temporarily stores data provided from or to be provided to the memory device. as well as Memory controller: Receive and write data from external sources. Generate error detection data corresponding to the written data. The written data is compressed to generate compressed data. The buffer memory is controlled to store the written data. The mapping data stores the physical address indicating the location where the compressed data is stored, compression information associated with the compressed data, and the error detection data. The buffer memory and the memory device are controlled to store the compressed data.

18. The storage device according to claim 17, wherein, The memory controller: The physical address is stored in a portion of a storage area allocated to multiple logical addresses corresponding to the written data in the mapped data, and The compression information and the error detection data are stored in the remaining portion of the storage area.

19. The storage device according to claim 17, wherein, The memory controller: According to the read request, the memory device and the buffer memory are controlled to store the read data read from the memory device in the buffer memory, and In response to determining that the read data is compressed, the read data is decompressed according to the compression information stored in the mapping data.

20. The storage device according to claim 19, wherein, The memory controller: Error detection is performed on the decompressed data based on the error detection data stored in the mapping data, and The decompressed data is provided to the outside based on the result of the error detection operation.

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