Floating-point number processing method, apparatus, device, storage medium, and program product

Abstract

Embodiments of the present disclosure disclose a floating-point number processing method, device, equipment, storage medium and program product, wherein the device comprises a multiply-add operation unit, and the method comprises: in response to a target instruction representing rounding down of a target floating-point number, detecting whether the target floating-point number meets a preset condition; in the case that the target floating-point number meets the preset condition, taking a floating-point number value corresponding to the target floating-point number as an output result of the target instruction; in the case that the target floating-point number does not meet the preset condition, using a calculation channel of the multiply-add operation unit, determining a state of multiply-add operation matched with the target floating-point number based on an effective value of the target floating-point number, and determining the output result of the target instruction based on the matched state of multiply-add operation. In this way, the processing of the floor instruction is realized by reusing the calculation channel of the multiply-add operation unit, the circuit area consumption and the calculation power consumption during processing when the floor calculation unit is separately set are saved, and the processing efficiency is improved.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of computer technology, and in particular to a floating-point number processing method, apparatus, device, storage medium, and program product. Background Technology

[0002] The floor instruction is a mathematical operation instruction for floating-point numbers. It is used to round down to the nearest integer, that is, to the largest integer not greater than a given value.

[0003] In related technologies, a separate floor calculation unit is set up in the Arithmetic and Logic Unit (ALU) to complete the calculation of the floor function. The floor calculation unit is processed in parallel with other calculation units in the ALU, and a selector selects one of the calculation results from the floor calculation unit and the calculation results from other calculation units for output.

[0004] However, this method of setting up separate floor computing units leads to an increase in circuit area, as well as an increase in computing power consumption and a decrease in computing efficiency. Summary of the Invention

[0005] In view of the above, the present disclosure provides at least one floating-point number processing method, apparatus, device, storage medium, and program product.

[0006] The technical solution of this disclosure embodiment is implemented as follows:

[0007] On one hand, embodiments of this disclosure provide a floating-point number processing method applied to a floating-point number processing device, the floating-point number processing device including a multiply-accumulate operation unit, and the floating-point number processing method including:

[0008] The response characterizes the target instruction that rounds down the target floating-point number, and checks whether the target floating-point number meets the preset conditions. If the target floating-point number meets the preset conditions, the floating-point value corresponding to the target floating-point number is used as the output result of the target instruction. If the target floating-point number does not meet the preset conditions, the calculation path of the multiply-accumulate unit is used to determine the state of the multiply-accumulate operation that matches the target floating-point number based on the valid value of the target floating-point number, and the output result of the target instruction is determined based on the state of the matching multiply-accumulate operation.

[0009] In some embodiments, the above-mentioned detection of whether the target floating-point number meets the preset conditions includes: determining that the target floating-point number meets the first preset condition when the target floating-point number is 0, or the target floating-point number is infinity (INF), or the target floating-point number is not a number (NaN); determining that the target floating-point number meets the second preset condition when the fractional part of the target floating-point number has a valid value and the target floating-point number is greater than 0; and determining that the target floating-point number meets the third preset condition when the integer part of the target floating-point number does not have a valid value but the fractional part has a valid value and the target floating-point number is less than 0. The preset conditions include the first preset condition, the second preset condition, and the third preset condition.

[0010] In some embodiments, the above-mentioned method of using the floating-point value corresponding to the target floating-point number as the output result of the target instruction when the target floating-point number meets the preset conditions includes: using the target floating-point number as the output result of the target instruction when the target floating-point number meets the first preset condition; using the first floating-point value as the output result of the target instruction when the target floating-point number meets the second preset condition; and using the second floating-point value as the output result of the target instruction when the target floating-point number meets the third preset condition.

[0011] In some embodiments, determining the state of a multiply-accumulate operation matching the target floating-point number based on the valid value of the target floating-point number includes: using the window state detection module of the multiply-accumulate unit, when the integer part of the target floating-point number has a valid value but the fractional part of the target floating-point number does not have a valid value, determining the state of the matching multiply-accumulate operation as a first target state; the calculation window of the window selection module of the multiply-accumulate unit in the first target state includes the integer part and the fractional part of the target floating-point number; using the window state detection module of the multiply-accumulate unit, when both the integer part and the fractional part of the target floating-point number have valid values, determining the state of the matching multiply-accumulate operation as a second target state; the calculation window of the window selection module in the second target state includes the integer part of the target floating-point number.

[0012] In some embodiments, the floating-point number processing method further includes: determining that the integer part of the target floating-point number has no valid value but the fractional part has a valid value when the exponent of the target floating-point number is less than a first exponent threshold; the first exponent threshold is determined based on the exponent offset of the target floating-point number; determining that the integer part of the target floating-point number has a valid value but the fractional part has no valid value when the exponent of the target floating-point number is greater than a second exponent threshold; the second exponent threshold is determined based on the exponent offset of the target floating-point number and the mantissa width of the target floating-point number; and determining that both the integer part and the fractional part of the target floating-point number have valid values ​​when the exponent of the target floating-point number is greater than the first exponent threshold and less than the second exponent threshold.

[0013] In some embodiments, determining the output result of the target instruction based on the state of the matched multiply-accumulate operation includes: using the window selection module of the multiply-accumulate unit to determine the mantissa and exponent of the addition based on the state of the matched multiply-accumulate operation; and using the mantissa addition module of the multiply-accumulate unit to determine the output result of the target instruction based on the sign bit, mantissa, and exponent of the target floating-point number.

[0014] In some embodiments, the window selection module utilizing the multiply-add operation unit determines the mantissa and exponent based on the state of the matched multiply-add operation, including: when the state of the matched multiply-add operation is a first target state, assigning a first value to the first addend of the calculation window of the window selection module in the first target state; placing the mantissa of the target floating-point number in the highest bit of the calculation window of the window selection module in the first target state, and truncating the target number of bits from the highest bit downwards and assigning it to the second addend of the calculation window of the window selection module in the first target state; the target number of bits is determined based on the bit width of the calculation window of the window selection module in the first target state, and the calculation window of the window selection module in the first target state includes the integer part and the fractional part of the target floating-point number; determining the mantissa based on the first addend and the second addend; and using the exponent of the target floating-point number as the exponent.

[0015] In some embodiments, the window selection module utilizing the multiply-accumulate unit described above determines the mantissa and exponent based on the state of the matched multiply-accumulate operation, including: when the state of the matched multiply-accumulate operation is a second target state, determining the number of right shift bits for the target floating-point number based on the bit width of the calculation window of the window selection module in the first target state, the bit width of the calculation window of the window selection module in the second target state, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and a bit width threshold; the right shift bits are used to retain the integer part of the target floating-point number in the calculation window; the mantissa of the target floating-point number is placed in the calculation window of the window selection module in the second target state according to the right shift bits of the target floating-point number; the mantissa of the addition is determined based on the mantissa of the placed target floating-point number and the sign bit of the target floating-point number; and the exponent is determined based on the exponent offset of the target floating-point number and the bit width of the calculation window of the window selection module in the second target state.

[0016] In some embodiments, determining the addition mantissa based on the mantissa and sign bit of the placed target floating-point number includes: determining the first addend of the calculation window of the window selection module in the second target state based on the sign bit of the target floating-point number; truncating the target number of bits from the mantissa of the placed target floating-point number downwards and assigning it to the second addend of the calculation window of the window selection module in the second target state; and determining the addition mantissa based on the first addend and the second addend.

[0017] In some embodiments, determining the first addend of the calculation window of the window selection module in the second target state based on the sign bit of the target floating-point number includes: assigning a first value to the first addend of the calculation window of the window selection module in the second target state when the sign bit of the target floating-point number indicates that the target floating-point number is positive; and assigning a second value to the first addend of the calculation window of the window selection module in the second target state when the sign bit of the target floating-point number indicates that the target floating-point number is negative.

[0018] On the other hand, embodiments of this disclosure provide a floating-point number processing device, which includes: a floating-point value output module, used to detect whether a target floating-point number meets a preset condition; when the target floating-point number meets the preset condition, determining the output result of a target instruction representing the acquisition of the fractional part of the target floating-point number based on the floating-point value corresponding to the target floating-point number; and a multiply-accumulate operation unit, used to determine the state of a multiply-accumulate operation matching the target floating-point number based on the valid value of the target floating-point number when the target floating-point number does not meet the preset condition, and determining the output result of the target instruction based on the state of the matching multiply-accumulate operation.

[0019] In some embodiments, the floating-point processing apparatus further includes: a right shift bit determination module, configured to determine the right shift bit of the target floating-point number based on the bit width of the calculation window of the window selection module in the first target state, the bit width of the calculation window of the window selection module in the second target state, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and a bit width threshold when the state of the matched multiply-accumulate operation is the second target state.

[0020] In some embodiments, the floating-point processing device further includes: a selector, configured to output the processing result of the floating-point value output module when the target floating-point number meets a preset condition, and to output the processing result of the multiplication-addition unit when the target floating-point number does not meet the preset condition.

[0021] In some embodiments, the multiply-add unit includes a window selection module, and the floating-point processing device further includes: an addend compensation module, configured to assign a first value to the first addend of the calculation window of the window selection module in the second target state when the sign bit of the target floating-point number indicates that the target floating-point number is positive; and to assign a second value to the first addend of the calculation window of the window selection module in the second target state when the sign bit of the target floating-point number indicates that the target floating-point number is negative.

[0022] In another aspect, embodiments of this disclosure provide a computer device, including a memory and a processor. The memory stores a computer program that can run on the processor, and the processor executes the program to implement some or all of the steps in the above-described method.

[0023] In another aspect, embodiments of this disclosure provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above-described method.

[0024] In another aspect, embodiments of this disclosure provide a computer program including computer-readable code, which, when executed in a computer device, causes a processor in the computer device to perform some or all of the steps in the above-described method.

[0025] In another aspect, embodiments of this disclosure provide a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method.

[0026] In this embodiment, the processing of the floor instruction for rounding down floating-point numbers is divided into two cases: one where the floating-point value corresponding to the target floating-point number can be directly output, and the other where the multiplication-accumulation module needs to be reused for processing. These two cases are distinguished by preset conditions. When the target floating-point number meets the preset conditions, the floating-point value corresponding to the target floating-point number is directly output. When the target floating-point number does not meet the preset conditions, the state of the multiplication-accumulation operation is reused to process the floor instruction. Thus, by reusing the computational path of the multiplication-accumulation operation to process the floor instruction, the circuit area consumption of setting up a separate floor calculation unit is saved. During processing, the computational path of the multiplication-accumulation operation is directly reused without using a separate floor calculation unit, which saves the computational power consumption of the floor instruction and improves processing efficiency.

[0027] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of this disclosure. Attached Figure Description

[0028] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0029] Figure 1 A schematic diagram illustrating the composition structure of a floating-point number provided in an embodiment of this disclosure;

[0030] Figure 2 This is a schematic diagram of a separately configured foror computing unit provided in an embodiment of the present disclosure;

[0031] Figure 3 This is a schematic diagram of the structure of a multiply-accumulate module provided in an embodiment of the present disclosure;

[0032] Figure 4 A schematic diagram of a calculation window for a multiply-accumulate module provided in an embodiment of this disclosure;

[0033] Figure 5 A schematic diagram of the implementation process of a floating-point number processing method provided in this embodiment of the present disclosure. Figure 1 ;

[0034] Figure 6 A schematic diagram of the implementation process of a floating-point number processing method provided in this embodiment of the present disclosure. Figure 2 ;

[0035] Figure 7 A schematic diagram illustrating the implementation process of the addition mantissa in a floating-point number processing method provided in this embodiment of the present disclosure;

[0036] Figure 8 This is a schematic diagram illustrating the implementation process of a floating-point processing device provided in an embodiment of the present disclosure;

[0037] Figure 9 This is a schematic diagram of the hardware entity of a computer device provided in an embodiment of this disclosure. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0039] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0040] The terms “first / second / third” are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that “first / second / third” may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this disclosure.

[0042] To better understand the floating-point number processing method provided in the embodiments of this disclosure, the solutions in related technologies will be described below.

[0043] A floating-point number consists of 1 sign bit, n exponent bits, and m mantissa bits. The sign bit indicates whether the floating-point number is positive or negative (e.g., 0 for positive, 1 for negative). The exponent bits represent the range of the value. The mantissa bits represent the precision of the value, that is, the decimal part. n and m are both positive integers greater than or equal to 1. Figure 1 As shown, taking a 32-bit floating point (FP32) as an example, the 32-bit width includes 23 mantissa bits (bits 0 to 23), 8 exponent bits (bits 24 to 30), and 1 sign bit (bit 31).

[0044] The `floor` instruction is a commonly used floating-point instruction. Its behavior is as follows: Given any floating-point number `x`, if the decimal part of `x` is 0, then `floor(x)` equals `x`. If the decimal part of `x` is not 0, then `floor(x)` equals the integer value closest to `x` on the negative infinity side. If `x` equals `INF` or `NAN`, then `floor(x)` equals `x` itself. The following examples illustrate this:

[0045] 1. x = +3.0f, floor(x) = +3.0f; the decimal part of x is 0, floor(x) is equal to x itself.

[0046] 2. When x = -5.0f, floor(x) = -5.0f; when the decimal part of x is 0, floor(x) equals x itself.

[0047] 3. x = +3.8f, floor(x) = +3.0f; the decimal part of x is non-zero, and floor(x) is equal to the nearest integer in the direction of negative infinity.

[0048] 4. x = -0.8f, floor(x) = -1.0f; the decimal part of x is non-zero, and floor(x) is equal to the nearest integer in the direction of negative infinity.

[0049] 5. x = ±0.0f, floor(x) = ±0.0f; x equals 0, floor(x) equals 0.

[0050] 6. x = ±inf, floor(x) = ±inf; x equals infinity, floor(x) equals infinity.

[0051] 7. x = NAN, floor(x) = NAN; x is an invalid number, floor(x) is an invalid number.

[0052] In related technologies, such as Figure 2As shown, a separate floor calculation unit is usually set up in the ALU to complete the calculation of floor instructions. A selector selects one of the calculation results from the floor calculation and the calculation results of other calculation units for output.

[0053] The use of independent floor calculation units in related technologies has the following disadvantages:

[0054] 1. Independent floor calculation units will lead to an increase in circuit area;

[0055] 2. A selector needs to be added to the critical path, which increases the computation time;

[0056] 3. Independent floor computing units lead to increased power consumption in fused multiply-add (FMA).

[0057] This disclosure provides a floating-point number processing method that reuses the computational path of the multiply-accumulate module during calculation, enabling the processing of floor instructions without increasing computational power consumption and circuit overhead. The multiply-accumulate module will be described below.

[0058] Suppose the multiply-accumulate module to be designed is used to calculate the multiplication and addition of three floating-point numbers. These three floating-point numbers are src0, src1, and src2, and the calculation method is defined as src0 * src1 + src2. Correspondingly, the sign bits of these three floating-point numbers are named sgn0, sgn1, and sgn2, the exponents are named exp0, exp1, and exp2, and the mantissas are named mat0, mat1, and mat2.

[0059] Figure 3 It is an FMA (Floating-Point Arithmetic) path that supports mixed operations of FP32 (32-bit floating-point numbers) and FP16 (16-bit floating-point numbers). Details are as follows:

[0060] Figure 3 The source operand extraction module is used to extract the FP32 or FP16 data to be calculated from each input source operand.

[0061] Figure 3 The exponent adjustment module is used to adjust the exponent offset of each source operand according to the data format of the source operand, so that floating-point numbers of different formats are unified under the FP32 format.

[0062] Figure 3 The leading zero detection module in the src2 is used to calculate the number of leading zeros in the mantissa.

[0063] Figure 3The exponential subtraction module in the code is used to calculate the difference between exp2 and exp01 (the sum of exp0 and exp1).

[0064] Figure 3 The window state detection module is used to detect whether the current instruction is running in state one, state two, state three, or state four.

[0065] Figure 3 The mantissa shift module in the code is used to right-shift mat2 based on the window state and the difference between exp2 and exp01.

[0066] Figure 3 The mantissa multiplication module is used to calculate mat0*mat1 to obtain mat01.

[0067] Figure 3 The addition exponent calculation module is used to select exp2 or exp01 as the exponent after exponent alignment, i.e., exp_add, according to the window state.

[0068] Figure 3 The window selection module is used to extract the parts addin0 and addin1 to be added and subtracted from mat2 and mat01 after displacement, according to the window state.

[0069] Figure 3 The mantissa addition module in the code is used to perform addition or subtraction operations on addin0 and addin1.

[0070] Figure 3 The leading zero prediction module in the code is used to calculate the number of leading zeros in the result after adding or subtracting addin0 and addin1.

[0071] Figure 3 The normalization operation module in the code is used to normalize the exponent and mantissa after addition.

[0072] The total bit width of the calculation window is mat_width_tmp*4+7 bits. The bit width of the addition window when the multiplication and addition operation is in state one and state two is mat_width_tmp*2+6 bits, and the bit width of the addition window when the multiplication and addition operation is in state three and state four is mat_width_tmp*2+6 bits.

[0073] like Figure 4As shown, taking single-precision floating-point numbers as an example, mat_width_tmp is 23. In this case, the total bit width of the calculation window is 99 bits. The bit width of the addition window is 52 bits when the multiplication-addition operation is in state one and state two, and also 52 bits when the multiplication-addition operation is in state three and state four. From high to low, the calculation window is divided into three parts, each with a length of 26 bits (highest part), 50 bits (second highest part), and 23 bits respectively.

[0074] Initially, mat2 is placed at the highest position of the highest part of the calculation window, and mat01 is placed at the highest position of the second highest part of the calculation window. Then, based on the relationship between exp2 and exp01, mat2 is shifted downwards within the calculation window.

[0075] If exp01+27-exp2<0, then exp2 is considered to be much greater than exp01, and mat2 is not shifted. Otherwise, mat2 needs to be shifted right by exp01+27-exp2 positions. After the shift, the mantissa mat_add is calculated.

[0076] State 1: If 0 > exp01 + 27 - exp2, then set addin0 = 0, and extract the highest and second-highest bits (51 bits) of mat2 from the shifted window as addin1. Then, perform addition or subtraction operations on addin0 and addin1 to obtain mat_add. Treat all mat01 bits as sticky bits. Correspondingly, select the addition exponent as exp_add = exp2.

[0077] State 2: If 26 > exp01 + 27 - exp2 >= 0, and the highest and second-highest bits of the shifted window (51 bits total) are truncated to mat01 as addin0 = 0, then the highest and second-highest bits of the shifted window (51 bits total) are truncated to mat2 as addin1. Then, addin0 and addin1 are added or subtracted to obtain mat_add. The untruncated mat01 bits in the second-highest part are considered sticky bits. Correspondingly, the addition exponent is chosen as exp_add = exp01 + 27. The highest and second-highest bits of the shifted window (51 bits total) are truncated to mat2 as addin1, that is, addin1 = shf_mat2[mat_width_tmp*4 + 6: mat_width_tmp*2 + 2].

[0078] State 3: If 76 > exp01 + 27 - exp2 >= 26, then truncate the second-highest portion of the window after displacement (50 bits total, mat01) as addin0, and truncate the second-highest portion of the window after displacement (50 bits total, mat2) as addin1. Then perform addition or subtraction operations on addin0 and addin1 to obtain mat_add. Treat mat2 in the lowest part of the window as sticky bits. And correspondingly, choose the addition exponent as exp_add = exp01.

[0079] State 4: If exp01 + 27 - exp2 >= 76, then extract the second-highest portion of the window after displacement, totaling 50 bits (mat01), as addin0, and set addin1 = 0. Then, perform addition or subtraction operations on addin0 and addin1 to obtain mat_add. Treat all mat2 bits as sticky bits. Correspondingly, select the addition exponent as exp_add = exp01.

[0080] Finally, after checking for leading zeros in the mantissa of the addition, the mantissa and exponent of the addition are adjusted according to the specific situation to obtain the floating-point result after normalization.

[0081] The floating-point number processing method provided in the embodiments of this disclosure will be described in detail below.

[0082] This disclosure provides a floating-point number processing method that can be applied to a computer device equipped with a multiply-accumulate unit. The multiply-accumulate unit performs fused multiply-accumulate operations, and its computational path can also be referred to as a fused multiply-accumulate path. This method can be implemented by hardware circuitry within the computer device, such as configuring the computational path of the multiply-accumulate unit in the arithmetic and logic unit of a central processing unit (CPU) or a graphics processing unit (GPU). Figure 5 This is a schematic diagram illustrating the implementation flow of a floating-point number processing method provided in an embodiment of this disclosure, as shown below. Figure 5 As shown, the method includes the following steps 501 to 503:

[0083] Step 501: Respond to the target instruction that represents the rounding down of the target floating-point number, and detect whether the target floating-point number meets the preset conditions.

[0084] The target instruction is used to round down the target floating-point number. For example, the target instruction is a floor instruction for the target floating-point number. The target floating-point number is any floating-point number that needs to be processed.

[0085] The preset conditions are used to determine whether the floating-point value corresponding to the floating-point number can be directly output. For example, floating-point values ​​can include, but are not limited to: 0, NAN, INF, and -1.0. NAN indicates that it is not a number, i.e., not a valid numeric value; this usually occurs in certain mathematical operations, such as 0 divided by 0, or certain illegal mathematical operations, resulting in NAN. INF represents infinity; positive infinity represents a very large positive number, and negative infinity represents a very large negative number. Infinity usually appears in division by 0 operations, or when the value exceeds the range that a floating-point number can represent.

[0086] In one feasible implementation, the preset conditions may include: a condition for determining whether to directly output the floating-point number itself, a condition for determining whether to directly output 0, and a condition for determining whether to directly output -1.0.

[0087] In some implementations, step 501 can be specifically implemented as follows: when the target floating-point number is 0, or the target floating-point number is infinity (INF), or the target floating-point number is not a number (NaN), determine that the target floating-point number satisfies a first preset condition; when the fractional part of the target floating-point number has a valid value and the target floating-point number is greater than 0, determine that the target floating-point number satisfies a second preset condition; when the integer part of the target floating-point number does not have a valid value but the fractional part has a valid value and the target floating-point number is less than 0, determine that the target floating-point number satisfies a third preset condition; the preset conditions include the first preset condition, the second preset condition, and the third preset condition.

[0088] In some implementations, if the target floating-point number does not meet the first preset condition, the second preset condition, and the third preset condition, it is determined that the target floating-point number does not meet the preset conditions.

[0089] If the integer part of the target floating-point number has no significant value but the fractional part has significant value, it means that the target floating-point number is a pure decimal.

[0090] The first preset condition is used to determine whether to directly output the floating-point number itself. For example, the first preset condition can be that the floating-point number is 0, INF (infinity), or NaN (not a number). If the target floating-point number is 0, INF, or NaN, then the target floating-point number is determined to meet the first preset condition.

[0091] The second preset condition is used to determine whether 0 can be directly output. For example, the second preset condition can be whether the floating-point number is a pure decimal greater than 0. If the target floating-point number is a pure decimal and is greater than 0, then the target floating-point number is determined to meet the second preset condition.

[0092] The third preset condition is used to determine whether -1.0 can be directly output. For example, the third preset condition can be whether the floating-point number is a pure decimal less than 0. If the target floating-point number is a pure decimal and the target floating-point number is less than 0, then the target floating-point number is determined to meet the third preset condition.

[0093] Step 502: If the target floating-point number meets the preset conditions, the floating-point value corresponding to the target floating-point number is used as the output result of the target instruction.

[0094] In some implementations, step 502 can be specifically implemented as follows: if the target floating-point number satisfies the first preset condition, the target floating-point number is used as the output result of the target instruction; if the target floating-point number satisfies the second preset condition, the floating-point value corresponding to the target floating-point number is determined as the first floating-point value, and the first floating-point value is used as the output result of the target instruction; if the target floating-point number satisfies the third preset condition, the floating-point value corresponding to the target floating-point number is determined as the second floating-point value, and the second floating-point value is used as the output result of the target instruction.

[0095] The first floating-point value is 0, and the second floating-point value is -1.0.

[0096] For example, if the target floating-point number is 0, output 0 directly. If the target floating-point number is INF, output INF directly; if the target floating-point number is NaN, output NaN directly. If the target floating-point number is a pure decimal greater than 0, output 0 directly. If the target floating-point number is a pure decimal less than 0, output -1.0 directly.

[0097] It should be noted that if the target floating-point number satisfies at least one of the first, second, and third preset conditions, the target floating-point number is considered to have met the preset conditions.

[0098] In some implementations, a floating-point number can be added to the output module to detect whether the target floating-point number meets the preset conditions; if the target floating-point number meets the preset conditions, the output result of the target instruction representing the acquisition of the fractional part of the target floating-point number is determined based on the floating-point value corresponding to the target floating-point number.

[0099] Step 503: If the target floating-point number does not meet the preset conditions, the calculation path of the multiply-accumulate unit is used to determine the state of the multiply-accumulate operation that matches the target floating-point number based on the effective value of the target floating-point number, and the output result of the target instruction is determined based on the state of the matched multiply-accumulate operation.

[0100] The target floating-point number does not meet the preset conditions, which means that the target floating-point number is neither 0, INF, NaN, nor a pure decimal; that is, the target floating-point number can be a pure integer or a floating-point number that has both integer and decimal parts.

[0101] It should be noted that when the target floating-point number does not meet the preset conditions, the output result of the target instruction is determined by using the calculation path of the multiply-accumulate unit. In this way, the processing of the floor instruction is realized by using the calculation path of the multiply-accumulate unit, which can save the circuit area consumption when setting up a separate floor calculation unit, and can also save the calculation power consumption of the floor instruction, thereby improving the processing efficiency.

[0102] In some implementations, step 503 can be specifically implemented as follows: if the target floating-point number is a pure integer, it is determined that it meets the state one of multiplication and addition operation, and the target floating-point number is processed according to the state one of multiplication and addition operation to obtain the output result of the target instruction. If the target floating-point number is a floating-point number that contains both integers and decimals, it is determined that it meets the state three of multiplication and addition operation, and the target floating-point number is processed according to the state three of multiplication and addition operation to obtain the output result of the target instruction.

[0103] In this embodiment, the processing of the floor instruction (target instruction) for rounding down floating-point numbers is divided into two cases: one where the floating-point value corresponding to the target floating-point number can be directly output, and the other where the computational path of the multiply-accumulate unit needs to be reused. These two cases are distinguished by preset conditions. When the target floating-point number meets the preset conditions, the floating-point value corresponding to the target floating-point number is directly output. When the target floating-point number does not meet the preset conditions, the computational path of the multiply-accumulate unit is reused to process the floor instruction. Thus, by reusing the computational path of the multiply-accumulate unit to process the floor instruction, the circuit area consumption of setting up a separate floor computational unit is saved. During processing, the computational path of the multiply-accumulate unit is directly reused instead of a separately set floor computational unit, saving computational power consumption of the floor instruction and improving processing efficiency.

[0104] This disclosure provides a floating-point number processing method, which can be executed by the processor of a computer device. For example... Figure 6 As shown, the method includes the following steps 601 to 607:

[0105] Step 601: Respond to the target instruction that represents the rounding down of the target floating-point number, and detect whether the target floating-point number meets the preset conditions.

[0106] Step 602: If the target floating-point number meets the preset conditions, the floating-point value corresponding to the target floating-point number is used as the output result of the target instruction.

[0107] Here, steps 601 to 602 correspond to steps 501 to 502 mentioned above, and can be implemented with reference to the specific implementation of steps 501 to 502 mentioned above.

[0108] Step 603: If the target floating-point number does not meet the preset conditions, determine whether the integer part and the fractional part of the target floating-point number have valid values.

[0109] In some implementations, the specific implementation of "determining whether the integer part and the fractional part of the target floating-point number have valid values" in step 603 can be as follows: determining whether the integer part and the fractional part of the target floating-point number have valid values ​​based on the relationship between the exponent of the target floating-point number and the first exponent threshold and the second exponent threshold.

[0110] Both the first and second exponent thresholds are determined based on the floating-point data format supported by the multiply-accumulate operation. In one feasible implementation, the first exponent threshold can be determined based on the exponent bit width of the supported floating-point data format; the second exponent threshold can be determined based on the exponent and mantissa bit widths of the supported floating-point data format. For example, if the multiply-accumulate operation supports single-precision floating-point (FP32) calculations, and the single-precision floating-point exponent has 8 bits and the mantissa bit width is 23 bits, then the first exponent threshold is 2. 8 -1=127, the second exponential threshold is 2. 8 -1 + 23 - 1 = 149. Here, the first exponent threshold also refers to the exponent offset of the target floating-point number.

[0111] Furthermore, the specific implementation of "determining whether the integer and fractional parts of the target floating-point number have valid values ​​based on the relationship between the target floating-point number and the first and second exponent thresholds" can be as follows: If the exponent of the target floating-point number is less than the first exponent threshold, determine that the integer part of the target floating-point number does not have a valid value, but the fractional part does; the first exponent threshold is determined based on the exponent offset of the target floating-point number; if the exponent of the target floating-point number is greater than the second exponent threshold, determine that the integer part of the target floating-point number has a valid value, but the fractional part does not; the second exponent threshold is determined based on the exponent offset and the mantissa width of the target floating-point number; if the exponent of the target floating-point number is greater than the first exponent threshold and less than the second exponent threshold, determine that both the integer and fractional parts of the target floating-point number have valid values.

[0112] Taking single-precision floating-point numbers as an example, if the exponent of the target floating-point number is less than 127 (the first exponent threshold), then the integer part of the target floating-point number is determined to have no valid value, but the fractional part has a valid value; that is, the target floating-point number is a pure decimal. If the exponent of the target floating-point number is greater than 127 and less than 149, then both the integer and fractional parts of the target floating-point number are determined to have valid values; that is, the target floating-point number has both integers and fractions. If the exponent of the target floating-point number is greater than 149 (the second exponent threshold), then the integer part of the target floating-point number is determined to have a valid value, but the fractional part does not have a valid value; that is, the target floating-point number is a pure integer.

[0113] Step 604: Using the window state detection module of the multiply-accumulate operation unit, when the integer part of the target floating-point number has a valid value but the fractional part of the target floating-point number does not have a valid value, determine the state of the matching multiply-accumulate operation as the first target state; the calculation window of the window selection module of the multiply-accumulate operation unit in the first target state includes the integer part and the fractional part of the target floating-point number.

[0114] The first target state refers to Figure 4 State 1 of the multiplication and addition operation.

[0115] In some implementations, when the target floating-point number is a pure integer, the state of the multiply-accumulate operation that matches the current floor instruction is determined to be state one.

[0116] Step 605: Using the window state detection module of the multiply-accumulate operation unit, if both the integer part and the fractional part of the target floating-point number have valid values, determine that the state of the matching multiply-accumulate operation is the second target state; the calculation window of the window selection module in the second target state contains the integer part of the target floating-point number.

[0117] Here, steps 603 to 605 and steps 604 to 605 all correspond to "determining the state of the multiplication and addition operation that matches the target floating-point number based on the effective value of the target floating-point number" in the aforementioned step 503. In implementation, the specific implementation method of the aforementioned step 503 can be referred to.

[0118] The second target state refers to Figure 4 State three of the multiplication and addition operation.

[0119] In some implementations, when the target floating-point number has both integer and decimal parts, the state of the multiply-accumulate operation that matches the current floor instruction is determined to be state three.

[0120] Step 606: Using the window selection module of the multiplication-addition unit, determine the mantissa and exponent of addition based on the state of the matched multiplication-addition operation.

[0121] In some implementations, step 606 can be specifically implemented as follows: when the target floating-point number is a pure integer, process the target floating-point number according to the state one of multiplication and addition to obtain the addition mantissa; and use the exponent of the target floating-point number as the addition exponent.

[0122] In some implementations, step 606 can also be implemented as follows: when the target floating-point number has both integer and decimal parts, process the target floating-point number according to state three of the multiplication-addition operation to obtain the addition mantissa; determine the addition exponent based on the exponent offset of the target floating-point number and the bit width of the calculation window under state three.

[0123] Step 607: Using the mantissa addition module of the multiply-accumulate unit, determine the output result of the target instruction based on the sign bit of the target floating-point number, the mantissa of the addition, and the exponent of the addition.

[0124] Here, steps 606 to 607 correspond to "determining the output result of the target instruction based on the state of the matched multiplication and addition operation" in step 503 above. When implementing, the specific implementation method of step 503 above can be referred to.

[0125] In one feasible implementation, the sign bit, mantissa, and exponent of the target floating-point number are organized into a floating-point data format through a normalization module to obtain the output result of the target instruction.

[0126] In some embodiments, when the state of the matched multiply-accumulate operation is the first target state, step 606 can be implemented by the following steps 6061 to 6064:

[0127] Step 6061: If the state of the matched multiplication-addition operation is the first target state, assign the first value to the first addend of the calculation window of the window selection module in the first target state.

[0128] The first value is 0. For example, the state in the matched multiplication-addition operation is the first target state ( Figure 4 In state one, assign 0 to Figure 4 In state one, addmin0 (the first addend).

[0129] Step 6062: Place the mantissa of the target floating-point number into the highest bit of the calculation window of the window selection module in the first target state, and truncate the target number of bits from the highest bit downwards and assign it to the second addend of the calculation window of the window selection module in the first target state; the target number of bits is determined based on the bit width of the calculation window of the window selection module in the first target state, and the calculation window of the window selection module in the first target state includes the integer part and the fractional part of the target floating-point number.

[0130] The target number of bits is used to extract the effective portion of the mantissa of the target floating-point number after it has been arranged.

[0131] Taking single-precision floating-point numbers as an example, when the state of the multiplication and addition operation that matches the target floating-point number is state one, the truncation bits of addin1 are 51 bits from high to low in the calculation window of the first target state.

[0132] For example, such as Figure 7 In the first scenario shown, the state of the matched multiplication-addition operation is the first target state ( Figure 4 In state one, the mantissa of the target floating-point number is placed as mat2 in the highest bit of the calculation window, and 51 bits are truncated from the highest bit and assigned to it. Figure 4 In state one, addmin1 (the second addend).

[0133] Step 6063: Determine the mantissa based on the first addend and the second addend.

[0134] In some implementations, the state of the matched multiply-accumulate operation is the first target state ( Figure 4 In state one, the first addend and the second addend are added to obtain the mantissa.

[0135] For example, the state of the matched multiply-accumulate operation is the first target state ( Figure 4 In state one, the first addend is 0, the second addend is mat2, and the mantissa of the addition is mat2+0.

[0136] Step 6064: Use the exponent of the target floating-point number as the addition exponent.

[0137] For example, the state of the matched multiply-accumulate operation is the first target state ( Figure 4 In state one, set the addition exponent exp_add=exp2.

[0138] The floor instruction operates on a single floating-point number, while multiply-accumulate operations operate on three floating-point numbers. During processing, the object operated on by the floor instruction is treated as the third floating-point number in the multiply-accumulate operation. Figure 3 In src2), the first floating-point number ( Figure 3 src0 in the second floating-point number ( Figure 3 In the implementation, if the target floating-point number is a pure integer, then the state of the multiplication-addition operation is state one (…). Figure 4 In the method described in State 1, addin0=0 is set, the target floating-point number is placed in the highest bit of the calculation window in State 1, and mat2 within the first 51 bits is used as addin1. Then, the addition operation of addin0 and addin1 is performed to obtain mat_add (the mantissa of the addition). Here, all mat01 are regarded as sticky bits, and the addition exponent is selected as exp_add=exp2.

[0139] In some embodiments, when the state of the matched multiply-accumulate operation is the second target state, step 606 can be implemented by the following steps 6065 to 6068:

[0140] Step 6065: When the state of the matched multiply-add operation is the second target state, based on the bit width of the calculation window of the window selection module in the first target state, the bit width of the calculation window of the window selection module in the second target state, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and the bit width threshold, determine the number of right shift bits of the target floating-point number; the number of right shift bits is used to retain the integer part of the target floating-point number in the calculation window.

[0141] If the target floating-point number has both integer and decimal parts, it is processed according to the state three of the multiplication-addition operation. The processing logic is to extract only the integer part of mat2 through the calculation window to participate in the operation, remove the decimal part of mat2, and assign the first addend of the calculation window according to the sign bit.

[0142] During multiplication and addition operations, mat2 is shifted to the right based on the state of the calculation window; similarly, the state of the matched multiplication and addition operation is the second target state ( Figure 4 In state three, the target floating-point number also needs to be right-shifted.

[0143] First target state ( Figure 4 The bit width of the calculation window under state one and the second target state Figure 4 In state three, the bit width of the calculation window is mat_width_tmp*2+6. Taking single-precision floating-point numbers as an example, the bit width of the calculation window in state one and state three is 52 bits.

[0144] In some implementations, step 6065 can be specifically implemented as follows: performing an addition operation on the bit width of the calculation window in the first target state and the bit width of the calculation window in the second target state, and then removing the overlapping bit width of the calculation window in the first target state and the calculation window in the second target state to obtain the first right shift number; adjusting the mantissa of the target floating-point number according to the exponent offset of the target floating-point number to obtain the second right shift number; and performing a subtraction operation on the first right shift number, the second right shift number, and the bit width threshold to obtain the right shift number.

[0145] For example, using single-precision floating-point numbers as an example, refer to... Figure 4 The bit width of the calculation window in the first target state and the bit width of the calculation window in the second target state are both 23*2+6, and the bit width of the two windows overlapping is 28. Therefore, the first right shift bit is (23*2+6)*2-28=76. The exponent offset of the target floating-point number is 2. 8 -1, the mantissa of the target floating-point number is exp2, and the second right shift number is: exp2 - (2 8 -1). The bit width threshold is 1, at which point the right shift bits are 76 - (exp2 - (2 8 -1))=202-exp2.

[0146] Step 6066: Based on the right shift bits of the target floating-point number, place the mantissa of the target floating-point number into the calculation window of the window selection module in the second target state.

[0147] like Figure 7 In the third scenario shown, based on the number of right shifts of the target floating-point number, the mantissa of the target floating-point number is placed in the calculation window of the second target state, so that the bit corresponding to the exponent of 0 in mat2 is shifted to the lowest bit of the calculation window of the second target state. At this time, only the integer part of mat2 is retained in the calculation window of the second target state, and the decimal part of mat2 is removed.

[0148] Step 6067: Determine the addition mantissa based on the mantissa of the target floating-point number after placement and the sign bit of the target floating-point number.

[0149] In some implementations, step 6067 can be specifically implemented as follows: based on the sign bit of the target floating-point number, determine the first addend of the calculation window of the window selection module in the second target state; truncate the target number of bits in the mantissa of the placed target floating-point number from the high bit downwards, and assign it to the second addend of the calculation window of the window selection module in the second target state; determine the addition mantissa based on the first addend and the second addend.

[0150] In some implementations, the specific implementation of "determining the first addend of the calculation window in the second target state based on the sign bit of the target floating-point number" can be as follows: when the sign bit of the target floating-point number indicates that the target floating-point number is positive, a first value is assigned to the first addend of the calculation window in the second target state by the window selection module; when the sign bit of the target floating-point number indicates that the target floating-point number is negative, a second value is assigned to the first addend of the calculation window in the second target state by the window selection module.

[0151] The first value is 0, and the second value is 1.

[0152] For example, when the target floating-point number is positive, assign 0 to the second target state. Figure 4 In case 3), the first addend of the calculation window is addin0; 51 bits of the mantissa of the target floating-point number after placement are truncated from the high-order bits and assigned to the second addend of the calculation window in the second target state. At this time, the mantissa of the addition is mat2 with 0 added after discarding the decimal part.

[0153] When the target floating-point number is negative, assign 1 to the second target state. Figure 4 In case 3), the second addend of the calculation window, addin1, is obtained by truncating 51 bits of the mantissa of the target floating-point number after placement from the high-order bits down and assigning it to the second addend of the calculation window in the second target state. At this time, the mantissa of the addition is mat2 plus 1 after discarding the decimal part.

[0154] Step 6068: Determine the addition exponent based on the exponent offset of the target floating-point number and the bit width of the calculation window of the window selection module in the second target state.

[0155] In one feasible implementation, the addition exponent is determined based on the exponent offset of the target floating-point number, the bit width of the calculation window in the second target state, and a threshold for the number of bits to be removed. The threshold for the number of bits to be removed is the three bits extended within the calculation window.

[0156] In one feasible implementation, the bit width of the calculation window and the threshold of the number of bits to be removed in the second target state are subtracted, and then the result of the subtraction is added to the exponent offset of the target floating-point number to obtain the additive exponent.

[0157] For example, taking single-precision floating-point numbers as an example, the exponent offset of the target floating-point number is 2. 8 -1, the bit width of the calculation window in the second target state is 52, the threshold for the number of bits to be removed is 3, and the addition exponent is 2. 8 -1 + 52 - 3 = 176.

[0158] For example, such as Figure 7As shown, when the target floating-point number contains both integers and decimals, the window is truncated according to the multiplication and addition operations, and exp_add=176 is set. If src2 is positive, after truncating, addin0=0, addin1=mat2 (discarding the decimal part), and the mantissa of the addition is actually mat2 (discarding the decimal part) + 0. If src2 is negative, after truncating, addin0=1, addin1=mat2 (discarding the decimal part), and the mantissa of the addition is actually mat2 (discarding the decimal part) + 1.

[0159] In this embodiment, the processing of the floor instruction for rounding down floating-point numbers is divided into two cases: one where the floating-point value corresponding to the target floating-point number can be directly output, and the other where the multiplication-accumulation module needs to be reused for processing. These two cases are distinguished by preset conditions. When the target floating-point number meets the preset conditions, the floating-point value corresponding to the target floating-point number is directly output. When the target floating-point number does not meet the preset conditions, the state of the multiplication-accumulation operation is reused to process the floor instruction. Thus, by reusing the computational path of the multiplication-accumulation operation to process the floor instruction, the circuit area consumption of setting up a separate floor calculation unit is saved. During processing, the computational path of the multiplication-accumulation operation is directly reused without using a separate floor calculation unit, which saves the computational power consumption of the floor instruction and improves processing efficiency.

[0160] The following describes the application of the floating-point number processing method provided in this embodiment in a real-world scenario, using single-precision floating-point numbers as an example.

[0161] The embodiments disclosed herein embed the floor instruction into the algorithm of the FMA instruction, implementing both floor and FMA instructions with the same circuitry without increasing power consumption or circuit overhead.

[0162] In this embodiment, the src2 of the FMA is used as the input to the floor instruction, and src0 and src1 are set to 0. The floor instruction is calculated using the FMA path as follows:

[0163] If both exp2 and mat2 are equal to 0, then src2 is determined to be equal to 0, and 0 is output directly.

[0164] If exp2 < 127, then src2 is determined to be a pure decimal. If src2 > 0, then 0 is output directly; if src2 < 0, then -1.0 is output directly.

[0165] If src2 is not 0 and is not a pure decimal, then the floating-point value cannot be directly output and the FMA path needs to be reused for calculation.

[0166] If exp2 > 149, then src2 is determined to be a pure integer. If src2 is determined to be a pure integer, then it is considered to belong to state one of the FMA calculation path; otherwise, it is considered to belong to state three of the FMA calculation path.

[0167] Then calculate the displacement value of mat2. If src2 is determined to be a pure integer, then set the right shift value of mat2 to 0. Otherwise, the decimal part of mat2 should be shifted to the right out of the second highest part of the window, so that the bit corresponding to the exponent of 0 in mat2 is shifted to the lowest bit of the second highest part of the window. Therefore, the right shift value of mat2 needs to be set to 202-exp2. After obtaining the displacement value, place mat2 in the highest position of the window and then shift it to the right according to the displacement value.

[0168] If it belongs to state one, the window is truncated according to state one of the FMA path. After truncation, addin0 equals 0, that is, the mantissa addition is mat2+0. And set exp_add=exp2, and after normalization, src2 will be output as is.

[0169] If it belongs to state three, the window is truncated according to state three of the FMA path, and exp_add = 176 is set. If src2 is positive, addin0 = 0 after truncating, that is, the mantissa addition is actually mat2 + 0 with the decimal part discarded. If src2 is negative, addin0 = 1 needs to be set after truncating the window, so the final mantissa addition is actually mat2 + 1 with the decimal part discarded. After normalization, the final calculation result is output.

[0170] Figure 7 The displacement and calculation window for the floor command is shown.

[0171] In summary, the approach to implementing the floor instruction in this disclosed embodiment involves the following steps:

[0172] 1. Determine if src2 is a special value that can be directly output, such as 0, nan, or a pure decimal.

[0173] 2. Set src0 and src1 to 0, and place mat2 at the highest position in the window.

[0174] 3. If src2 cannot contain decimals, then no shifting is required.

[0175] 4. If src2 may contain decimals, move the decimal part of the last digit completely to the right out of the calculation window. If src2 < 0, set mat01 to 1 to perform the addition operation.

[0176] 5. After setting up exp_add, perform the normalization operation.

[0177] In order to Figure 3 The floor instruction is embedded in the FMA path in this disclosure embodiment. Figure 3 The circuit structure shown has the following modules added, such as Figure 8 As shown.

[0178] The `floor` instruction floating-point value output detection module is used to detect whether `src2` is 0, a pure decimal, or `NAN` or `INF`. If `src2` is 0, it should output 0; if `src2` is a pure decimal greater than 0, it should output 0; if `src2` is a pure decimal less than 0, it should output -1.0; if `src2` is `NAN`, it should output `NAN`; if `src2` is `INF`, it should output `INF`.

[0179] The selector is used to select the corresponding floating-point value for output when the floor instruction floating-point value output detection module detects that a floating-point value needs to be output; otherwise, it selects the result from the normalization module. In fact, the FMA instruction usually also needs to output floating-point values ​​such as 0, INF, and NAN, and this selector does not add any circuit overhead.

[0180] The `floor` instruction displacement calculation module calculates the value of right shifting `mat2` in the `floor` instruction. If `mat2` is a pure integer, it sets `s2_all_int=1` and outputs `flr_shf_val=0`; otherwise, it outputs `flr_shf_val=202-exp2`. The `s2_all_int` flag is then sent to the window state detection module, the addition exponent calculation module, and the `floor` instruction compensation module. When executing the `floor` instruction, the window state detection module sets the window state to state one upon receiving `s2_all_int=1`; otherwise, it sets the window state to state three. When executing the `floor` instruction, the addition exponent calculation module sets `exp_add=exp2` upon receiving `s2_all_int=1`; otherwise, it sets `exp_add=176`. When executing the `floor` instruction, the mantissa displacement module right-shifts `mat2` according to `flr_shf_val`.

[0181] The floor instruction compensation module, when executing the floor instruction, if src2 is less than 0 and not a purely positive number, will modify addin0 to 1.

[0182] It should be noted that the embodiments disclosed herein can achieve at least the following technical effects:

[0183] 1. The embodiments of this disclosure save the area of ​​a separate floor computing unit by embedding floor instructions into the FMA path.

[0184] 2. In this embodiment of the present disclosure, since a separate floor calculation unit is not used, the power consumption of this part of the circuit is saved when calculating floor instructions.

[0185] Based on the foregoing embodiments, this disclosure provides a floating-point number processing device, which includes various units and modules included in each unit. It can be implemented by a processor in a computer device; of course, it can also be implemented by specific logic circuits. In the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA), etc.

[0186] This disclosure provides a floating-point processing apparatus, which includes:

[0187] Floating-point value output module (corresponding) Figure 8 The floor instruction floating-point value output detection module is used to detect whether the target floating-point number meets the preset conditions; if the target floating-point number meets the preset conditions, the output result of the target instruction representing the acquisition of the fractional part of the target floating-point number is determined based on the floating-point value corresponding to the target floating-point number.

[0188] Multiply-add unit (corresponding) Figure 8 The part that reuses the FMA computing path is used to determine the state of the multiply-accumulate operation that matches the target floating-point number based on the valid value of the target floating-point number when the target floating-point number does not meet the preset conditions, and to determine the output result of the target instruction based on the state of the matched multiply-accumulate operation.

[0189] In some implementations, such as Figure 8 As shown, the multiply-accumulate unit includes a window selection module, and the floating-point processing device further includes:

[0190] Right shift bit determination module (corresponding) Figure 8 The floor instruction shift value calculation module is used to determine the number of right shifts of the target floating-point number based on the bit width of the calculation window of the window selection module in the first target state, the bit width of the calculation window of the window selection module in the second target state, the mantissa of the target floating-point number, the exponent offset of the target floating-point number, and the bit width threshold when the state of the matched multiply-accumulate operation is the second target state.

[0191] In some embodiments, the floating-point processing apparatus further includes:

[0192] Selector (corresponding) Figure 8The selector in the text is used to output the processing result of the floating-point value output module when the target floating-point number meets the preset conditions, and to output the processing result of the multiply-accumulate unit when the target floating-point number does not meet the preset conditions.

[0193] In some embodiments, the floating-point processing apparatus further includes:

[0194] Addend compensation module (corresponding) Figure 8 The floor instruction compensation module is used to assign a first value to the first addend of the calculation window of the window selection module in the second target state when the sign bit of the target floating-point number indicates that the target floating-point number is positive; and to assign a second value to the first addend of the calculation window of the window selection module in the second target state when the sign bit of the target floating-point number indicates that the target floating-point number is negative.

[0195] The descriptions of the apparatus embodiments above are similar to those of the method embodiments above, and have similar beneficial effects. In some embodiments, the functions or modules included in the apparatus provided in this disclosure can be used to perform the methods described in the method embodiments above. For technical details not disclosed in the apparatus embodiments of this disclosure, please refer to the descriptions of the method embodiments of this disclosure for understanding.

[0196] It should be noted that, in the embodiments of this disclosure, if the above-described floating-point number processing method is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiments of this disclosure, or the part that contributes to related technologies, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk. Thus, the embodiments of this disclosure are not limited to any specific hardware, software, or firmware, or any combination of hardware, software, and firmware.

[0197] This disclosure provides a computer device including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the program, it implements some or all of the steps in the above-described method.

[0198] This disclosure provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements some or all of the steps in the above-described method. The computer-readable storage medium may be transient or non-transient.

[0199] This disclosure provides a computer program including computer-readable code, wherein when the computer-readable code is executed in a computer device, a processor in the computer device performs some or all of the steps in the above-described method.

[0200] This disclosure provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0201] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between them, while their similarities or commonalities can be referenced interchangeably. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above method embodiments and have similar beneficial effects. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product of this disclosure, please refer to the descriptions of the method embodiments of this disclosure for understanding.

[0202] It should be noted that, Figure 9 This is a schematic diagram of a hardware entity of a computer device in an embodiment of this disclosure, such as... Figure 9 As shown, the hardware entity of the computer device 900 includes: a processor 901, a communication interface 902, and a memory 903, wherein:

[0203] Processor 901 typically controls the overall operation of computer device 900.

[0204] Communication interface 902 enables computer devices to communicate with other terminals or servers over a network.

[0205] The memory 903 is configured to store instructions and applications executable by the processor 901, and can also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 901 and various modules in the computer device 900. It can be implemented using flash memory or random access memory (RAM). Data transfer between the processor 901, the communication interface 902, and the memory 903 can be performed via bus 904.

[0206] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0207] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0208] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0209] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0210] In addition, each functional unit in the various embodiments of this disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0211] Those skilled in the art will understand that all or part of the steps of the above method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it performs the steps of the above method embodiments. The aforementioned storage medium includes various media that can store program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks.

[0212] Alternatively, if the integrated units described above are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this disclosure, or the part that contributes to related technologies, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the methods described in the various embodiments of this disclosure. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, ROM, magnetic disks, or optical disks.

[0213] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method of floating-point number processing, characterized by, The application relates to a floating point number processing method applied to a floating point number processing device, wherein the floating point number processing device comprises a multiply-add operation unit, and the floating point number processing method comprises the following steps: In response to a target instruction representing a down-rounding operation on a target floating point number, it is detected whether the target floating point number satisfies a preset condition; In the case that the target floating point number satisfies the preset condition, a floating point number value corresponding to the target floating point number is taken as an output result of the target instruction; In the case that the target floating point number does not satisfy the preset condition, in the case that an integer part of the target floating point number has a valid value but a decimal part of the target floating point number does not have a valid value, a state of a matched multiply-add operation is determined as a first target state, and the output result of the target instruction is determined based on the first target state; in the case that the integer part and the decimal part of the target floating point number both have valid values, a state of a matched multiply-add operation is determined as a second target state, and the output result of the target instruction is determined based on the second target state; the first target state and the second target state are two different states in the multiply-add operation.

2. The floating-point number processing method according to claim 1, wherein The detection of whether the target floating point number satisfies the preset condition comprises: In the case that the target floating point number is 0, or the target floating point number is infinite, or the target floating point number is not a number, it is determined that the target floating point number satisfies a first preset condition; In the case that the decimal part of the target floating point number has a valid value and the target floating point number is greater than 0, it is determined that the target floating point number satisfies a second preset condition; In the case that the integer part of the target floating point number does not have a valid value but the decimal part has a valid value and the target floating point number is less than 0, it is determined that the target floating point number satisfies a third preset condition; the preset condition comprises the first preset condition, the second preset condition and the third preset condition.

3. The floating-point number processing method according to claim 2, wherein The taking, in the case that the target floating point number satisfies the preset condition, of the floating point number value corresponding to the target floating point number as the output result of the target instruction comprises: In the case that the target floating point number satisfies the first preset condition, the target floating point number is taken as the output result of the target instruction; In the case that the target floating point number satisfies the second preset condition, a first floating point number value is taken as the output result of the target instruction; In the case that the target floating point number satisfies the third preset condition, a second floating point number value is taken as the output result of the target instruction.

4. The floating-point number processing method according to any one of claims 1 to 3, characterized by, The determination of the state of the multiply-add operation matched with the target floating point number based on a valid value of the target floating point number comprises: In the case that the integer part of the target floating point number has a valid value but the decimal part of the target floating point number does not have a valid value, a window state detection module of the multiply-add operation unit determines that the state of the matched multiply-add operation is the first target state; a calculation window of a window selection module of the multiply-add operation unit in the first target state comprises the integer part and the decimal part of the target floating point number. The window state detection module of the multiply-add operation unit determines that the state of the matched multiply-add operation is a second target state when both the integer part and the decimal part of the target floating-point number have valid values; and the calculation window of the window selection module in the second target state contains the integer part of the target floating-point number.

5. The floating-point number processing method according to claim 4, wherein The floating-point processing method further includes: When the exponent of the target floating-point number is less than a first exponent threshold, it is determined that the integer part of the target floating-point number has no valid value, but the decimal part of the target floating-point number has a valid value; the first exponent threshold is determined based on the exponent offset of the target floating-point number; When the exponent of the target floating-point number is greater than a second exponent threshold, it is determined that the integer part of the target floating-point number has a valid value, but the decimal part of the target floating-point number has no valid value; the second exponent threshold is determined based on the exponent offset of the target floating-point number and the mantissa bit width of the target floating-point number; When the exponent of the target floating-point number is greater than the first exponent threshold and less than the second exponent threshold, it is determined that both the integer part and the decimal part of the target floating-point number have valid values.

6. The floating-point number processing method according to any one of claims 1 to 3, characterized by, Based on the state of the matched multiply-add operation, the output result of the target instruction is determined, including: The window selection module of the multiply-add operation unit determines the add mantissa and the add exponent based on the state of the matched multiply-add operation; The mantissa addition module of the multiply-add operation unit determines the output result of the target instruction based on the sign bit of the target floating-point number, the add mantissa and the add exponent.

7. The floating-point number processing method according to claim 6, wherein The window selection module of the multiply-add operation unit determines the add mantissa and the add exponent based on the state of the matched multiply-add operation, including: In the case that the state of the matched multiply-add operation is the first target state, a first value is assigned to a first addend of the calculation window of the window selection module in the first target state; The mantissa of the target floating-point number is placed in the highest bit of the calculation window of the window selection module in the first target state, and a target bit number is assigned to a second addend of the calculation window of the window selection module in the first target state from high to low; the target bit number is determined based on the bit width of the calculation window of the window selection module in the first target state, and the calculation window of the window selection module in the first target state contains the integer part and the decimal part of the target floating-point number; The add mantissa is determined based on the first addend and the second addend; The exponent of the target floating-point number is taken as the add exponent.

8. The floating-point number processing method according to claim 6, wherein The window selection module of the multiply-add operation unit determines the add mantissa and the add exponent based on the state of the matched multiply-add operation, including: In a case where the state of the matched multiply-add operation is a second target state, a right shift number of the target floating-point number is determined based on a bit width of a calculation window of the window selection module in a first target state, a bit width of a calculation window of the window selection module in a second target state, a mantissa of the target floating-point number, an exponent offset of the target floating-point number, and a bit width threshold; the right shift number is used to retain an integer part of the target floating-point number in a calculation window; The mantissa of the target floating-point number is placed into the calculation window of the window selection module in the second target state according to the right shift number of the target floating-point number; An addition mantissa is determined based on the placed mantissa of the target floating-point number and a sign bit of the target floating-point number; An addition exponent is determined based on the exponent offset of the target floating-point number and the bit width of the calculation window of the window selection module in the second target state.

9. The floating-point number processing method according to claim 8, wherein, The determination of the addition mantissa based on the placed mantissa of the target floating-point number and the sign bit of the target floating-point number comprises: A first addend of the calculation window of the window selection module in the second target state is determined based on the sign bit of the target floating-point number; A target number of bits in the placed mantissa of the target floating-point number is truncated from a high bit downwards, and is assigned to a second addend of the calculation window of the window selection module in the second target state; The addition mantissa is determined based on the first addend and the second addend.

10. The floating-point number processing method according to claim 9, wherein The determination of the first addend of the calculation window of the window selection module in the second target state based on the sign bit of the target floating-point number comprises: In a case where the sign bit of the target floating-point number indicates that the target floating-point number is a positive number, a first number value is assigned to the first addend of the calculation window of the window selection module in the second target state; In a case where the sign bit of the target floating-point number indicates that the target floating-point number is a negative number, a second number value is assigned to the first addend of the calculation window of the window selection module in the second target state.

11. A floating-point number processing device, characterized by comprising: The floating-point processing apparatus comprises: a floating-point value output module configured to detect whether a target floating-point number satisfies a preset condition, and in a case where the target floating-point number satisfies the preset condition, determine an output result of a target instruction indicating a decimal part of the target floating-point number based on a floating-point value corresponding to the target floating-point number; a multiply-add operation unit configured to, in a case where the target floating-point number does not satisfy the preset condition, in a case where an integer part of the target floating-point number has a valid value but a decimal part of the target floating-point number does not have a valid value, determine that a state of a matched multiply-add operation is a first target state, and determine the output result of the target instruction based on the first target state; in a case where the integer part and the decimal part of the target floating-point number both have valid values, determine that the state of the matched multiply-add operation is a second target state, and determine the output result of the target instruction based on the second target state; the first target state and the second target state are two different states in the multiply-add operation.

12. The floating-point number processing apparatus according to claim 11, wherein The multiply-add operation unit comprises a window selection module, and the floating-point processing apparatus further comprises: The right shift number determination module is configured to, when the state of the matched multiply-add operation is a second target state, determine a right shift number of the target floating-point number based on a bit width of a calculation window of the window selection module in a first target state, a bit width of a calculation window of the window selection module in a second target state, a mantissa of the target floating-point number, an exponent offset of the target floating-point number, and a bit width threshold.

13. The floating-point number processing apparatus according to claim 11 or 12, wherein The floating-point number processing apparatus further comprises: The selector is configured to, when the target floating-point number satisfies the preset condition, output a processing result of the floating-point number value output module; and when the target floating-point number does not satisfy the preset condition, output a processing result of the multiply-add operation unit.

14. The floating-point number processing apparatus according to claim 11 or 12, wherein The multiply-add operation unit comprises a window selection module, and the floating-point number processing apparatus further comprises: The addend compensation module is configured to, when the sign bit of the target floating-point number indicates that the target floating-point number is a positive number, assign a first number value to a first addend of the calculation window of the window selection module in the second target state; and when the sign bit of the target floating-point number indicates that the target floating-point number is a negative number, assign a second number value to the first addend of the calculation window of the window selection module in the second target state.

15. A computer device comprising a memory and a processor, the memory storing a computer program capable of running on the processor, characterized in that, The processor executes the program to implement the steps of the method in any one of claims 1 to 10.

16. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 10. 17.A computer program product, comprising a non-transitory computer-readable storage medium storing a computer program, wherein the computer program is read and executed by a computer to implement the steps of the method in any one of claims 1 to 10.

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