Branch instruction block execution method and related equipment

Abstract

The invention provides a branch instruction block execution method and related equipment. The branch instruction block execution method comprises the following steps: executing an initialized branch condition instruction; executing the target jump instruction and the conventional instruction stream; executing a branch variable reading instruction to respectively write two branch variables in the target storage interval into a first source register and a second source register corresponding to the branch instruction; executing a branch variable modification instruction to adjust a branch variable in the first source register or a branch variable in the second source register; a branch instruction is executed in conjunction with the branch variable in the first source register and the branch variable in the second source register. Before a first source register and a second source register are modified, a reliable branch variable is read from a target storage interval, so that it is guaranteed that the modified branch variable is matched with the cycle index of a branch instruction, and the branch variables in the first source register and the second source register are reliable; therefore, the controllability of branch instruction jump is ensured.

Description

Technical Field

[0001] This invention relates to the field of processors, and more specifically, to a method and related apparatus for executing branch instruction blocks. Background Technology

[0002] With the rapid development of artificial intelligence and high-performance computing, processor architectures face increasingly higher demands for parallel computing. The VLIW (Very Long Instruction Word) architecture, due to its high parallelism and simple hardware implementation, is widely used in the field of dedicated processors. VLIW is an explicit parallel instruction computation architecture that packages multiple instructions that can be executed in parallel into a very long instruction word. Unlike traditional superscalar processors, VLIW shifts the complexity of instruction scheduling from hardware to the compiler, thereby simplifying processor design.

[0003] RISC-V is an open and free instruction set architecture (ISA) with advantages such as high scalability and flexibility, attracting the attention and participation of many companies and academics. In the RISC-V instruction set, branch instructions are important tools for changing the program execution flow based on specific conditions. These instructions compare the values ​​of two registers to determine whether to jump to a target address, thus implementing conditional control structures such as if-else statements and while loops.

[0004] The controllability of branch instruction jumps directly affects the execution of instructions, which has become one of the problems of concern to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a branch instruction block execution method and related apparatus to improve the above-mentioned problems.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, embodiments of the present invention provide a branch instruction block execution method, the branch instruction block execution method comprising: Executing the initialization branch condition instruction includes: randomly generating two initial branch variables according to the target constraint condition, and writing the two initial branch variables into the target storage area, wherein the target constraint condition corresponds to the target loop number corresponding to the branch instruction, and the target difference between the two initial branch variables is an integer multiple of the target loop number; Execute a target jump instruction and a regular instruction stream, wherein the target jump instruction is the jump instruction corresponding to the branch instruction, and the regular instruction stream is the intermediate instruction between the target jump instruction and the branch instruction in the original instruction set; Execute the read branch variable instruction to write the two branch variables in the target storage area into the first source register and the second source register corresponding to the branch instruction, respectively; Execute the branch variable modification instruction to adjust the branch variable in the first source register or the branch variable in the second source register; Execute the store branch variable instruction to update the branch variable in the first source register and the branch variable in the second source register to the target storage range; The branch instruction is executed by combining the branch variables in the first source register and the branch variables in the second source register.

[0007] Optionally, the two branch variables in the target storage area are a first branch variable and a second branch variable, and the step of executing the read branch variable instruction to write the two branch variables in the target storage area into the first source register and the second source register corresponding to the branch instruction respectively includes: Write the first branch variable in the target storage area into the first source register corresponding to the branch instruction; Write the second branch variable in the target storage area into the second source register corresponding to the branch instruction.

[0008] Optionally, executing the branch variable modification instruction to adjust the branch variable in the first source register or the branch variable in the second source register includes: The first branch variable in the first source register or the second branch variable in the second source register is adjusted according to a preset amplitude, wherein the preset amplitude matches the target number of loops and the target difference.

[0009] Optionally, executing the branch instruction by combining the branch variables in the first source register and the branch variables in the second source register includes: Based on the branch variables in the first source register and the branch variables in the second source register, determine whether the loop condition is met; If the loop condition is met, the target jump instruction and the normal instruction stream are executed repeatedly; If the loop condition is not met, the branch instruction block will complete execution.

[0010] Optionally, the loop condition is any one of the following: the first branch variable is greater than or equal to the second branch variable, the first branch variable is less than the second branch variable, and the first branch variable is not equal to the second branch variable.

[0011] Optionally, the process of assembling and rewriting the original instruction set to generate various branch instruction blocks includes: Add a corresponding initial instruction number to each instruction in the original instruction set; The original instruction set is traversed and identified. When the nth instruction is identified as a branch instruction, one instruction is selected from the first n-1 instructions in the original instruction set as the target jump instruction of the nth instruction. Before the target jump instruction of the nth instruction, insert the corresponding initialization branch condition instruction of the nth instruction; Before the nth instruction, the corresponding instructions for reading branch variables, modifying branch variables, and storing branch variables are inserted sequentially to generate the branch instruction block corresponding to the nth instruction.

[0012] Optionally, after selecting one instruction from the first n-1 instructions of the original instruction set as the target jump instruction for the nth instruction, the method further includes: Generate a jump identifier based on the target jump instruction of the nth instruction; The jump identifier is added to the nth instruction and its corresponding target jump instruction respectively.

[0013] Optionally, the inserted read branch variable instruction includes the first read address of the first source register and the second read address of the second source register of the nth instruction, wherein the first read address and the second read address belong to the target memory range; The inserted branch variable modification instruction includes the preset range, modification object, and modification direction corresponding to the nth instruction. The modification object is the first source register or the second source register of the nth instruction. The inserted storage branch variable instruction, the first write address of the first source register and the second write address of the second source register of the nth instruction, the first write address and the second write address belong to the target storage range.

[0014] Secondly, embodiments of the present invention provide a random instruction generator that implements the above-described branch instruction block execution method.

[0015] Thirdly, embodiments of the present invention provide an electronic device including the aforementioned random instruction generator.

[0016] Compared to existing technologies, the branch instruction block execution method and related device provided in this invention execute an initialization branch condition instruction, including: randomly generating two initial branch variables according to target constraints and writing the two initial branch variables into a target storage area, wherein the target constraints correspond to the target loop number corresponding to the branch instruction, and the target difference between the two initial branch variables is an integer multiple of the target loop number; executing a target jump instruction and a regular instruction stream, wherein the target jump instruction is the jump instruction corresponding to the branch instruction, and the regular instruction stream is the intermediate instruction between the target jump instruction and the branch instruction in the original instruction set; executing a read branch variable instruction to write the two branch variables in the target storage area into the first source register and the second source register corresponding to the branch instruction, respectively; executing a modify branch variable instruction to adjust the branch variable in the first source register or the branch variable in the second source register; executing a store branch variable instruction to update the branch variable in the first source register and the branch variable in the second source register to the target storage area; and executing the branch instruction by combining the branch variable in the first source register and the branch variable in the second source register. Before modifying the first and second source registers, reliable branch variables are read from the target memory area to ensure that the modified branch variables match the number of iterations of the branch instruction. The branch variables in the first and second source registers are reliable, thus ensuring the controllability of the branch instruction jump.

[0017] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating the branch instruction block execution method provided in an embodiment of the present invention.

[0020] Figure 2 This is a schematic diagram of sub-step S26 provided in an embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram illustrating the process of each branch instruction block provided in an embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0023] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0024] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0026] In the description of this invention, it should be noted that the terms "upper," "lower," "inner," "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed when in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0027] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set" and "connection" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0028] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0029] This invention provides a branch instruction block execution method, which can be, but is not limited to, applied to the random instruction generator described below. It enables controllable forward jumps of branch instructions and ensures the correctness of instruction execution. Please refer to... Figure 1 , Figure 1 This is a flowchart illustrating the branch instruction block execution method provided in an embodiment of the present invention. The branch instruction block execution method includes steps S21 to S26, which are described in detail below.

[0030] S21, execute the initialization branch condition instruction.

[0031] The initialization branch condition instruction is the first instruction in the branch instruction block.

[0032] Execute the initialization branch condition instruction, including: randomly generating two initial branch variables (first branch variable and second branch variable) according to the target constraint conditions, and writing the two initial branch variables into the target storage area (which may be, but is not limited to, a storage area in memory).

[0033] Here, the two initial branch variables are designated as the first branch variable and the second branch variable, respectively. The target constraint corresponds to the target loop number corresponding to the branch instruction (in the branch instruction block). The target difference between the two initial branch variables (i.e., the target difference between the initial first branch variable and the initial second branch variable) is an integer multiple of the target loop number.

[0034] S22, execute the target jump instruction and the normal instruction stream.

[0035] Among them, the target jump instruction is the jump instruction corresponding to the branch instruction, and the regular instruction stream is the intermediate instruction between the target jump instruction and the branch instruction in the original instruction set (the instruction set before assembly rewriting).

[0036] It should be understood that after the initialization of branch condition instructions is completed, the target jump instruction and the normal instruction flow are executed.

[0037] S23, execute the read branch variable instruction to write the two branch variables in the target storage area into the first source register and the second source register corresponding to the branch instruction, respectively.

[0038] After executing the target jump instruction and the regular instruction stream, execute the instruction to read the branch variable.

[0039] S24, execute the branch variable modification instruction to adjust the branch variable in the first source register or the branch variable in the second source register.

[0040] After executing the command to read the branch variable, execute the command to modify the branch variable.

[0041] S25, execute the store branch variable instruction to update the branch variable in the first source register and the branch variable in the second source register to the target storage range.

[0042] After executing the instruction to modify branch variables and adjusting the branch variables, the instruction to store branch variables is executed. At this time, the target storage area stores the first and second branch variables modified during this loop.

[0043] Optionally, executing the store branch variable instruction includes: updating the first branch variable in the first source register to the target storage area as the new first branch variable; and updating the second branch variable in the second source register to the target storage area as the new second branch variable.

[0044] S26, combine the branch variables in the first source register and the branch variables in the second source register to execute the branch instruction.

[0045] When executing a target jump instruction and the regular instruction stream, the values ​​in the first and second source registers may be modified, making the branch variables unreliable and affecting the controllability of the branch jump. In this embodiment of the invention, before modifying the first and second source registers, reliable branch variables are read from the target storage area. This ensures that the modified branch variables match the loop count of the branch instruction, and that the branch variables in the first and second source registers are reliable, thereby ensuring the controllability of the branch instruction jump.

[0046] In one optional implementation, the two branch variables in the target storage area are a first branch variable and a second branch variable. S23, execute the read branch variable instruction to write the two branch variables in the target storage area into the first source register and the second source register corresponding to the branch instruction, respectively, including S231 and S232, which are described in detail below.

[0047] S231, write the first branch variable in the target storage range into the first source register corresponding to the branch instruction.

[0048] S232, write the second branch variable in the target storage range into the second source register corresponding to the branch instruction.

[0049] Optionally, S24, execute a branch variable modification instruction to adjust the branch variable in the first source register or the branch variable in the second source register, including: adjusting the first branch variable in the first source register or the second branch variable in the second source register according to a preset magnitude, wherein the preset magnitude matches the target loop count and the target difference, and the preset magnitude is equal to the target difference divided by the target loop count.

[0050] Based on the foregoing, regarding the content in S26, this embodiment of the invention also provides an optional implementation method, please refer to... Figure 2 , Figure 2 This is a schematic diagram of a sub-step S26 provided in an embodiment of the present invention. S26, combining the branch variables in the first source register and the branch variables in the second source register, executes a branch instruction, including: S261: Determine whether the loop condition is met based on the branch variables in the first source register and the branch variables in the second source register. If the loop condition is met, repeat S22; otherwise, execute S262.

[0051] If the loop condition is met, the target jump instruction and the regular instruction flow are executed repeatedly. The branch instruction includes an identifier for the target jump instruction, which can be the program counter value of the target jump instruction or prefix information added to the target jump instruction.

[0052] S262, the branch instruction block has been executed.

[0053] After the branch instruction block has been executed, other instructions following the branch instruction block in the original instruction set can be executed.

[0054] Optionally, the loop condition is any one of the following: the first branch variable is greater than or equal to the second branch variable, the first branch variable is less than the second branch variable, and the first branch variable is not equal to the second branch variable.

[0055] The loop condition can be determined based on the branch instruction type. The loop condition for beq is that the first branch variable is equal to the second branch variable. The loop conditions for bge and bgeu are that the first branch variable is greater than or equal to the second branch variable. The loop conditions for blt and bltu are that the first branch variable is less than the second branch variable. The loop condition for bne is that the first branch variable is not equal to the second branch variable.

[0056] In one alternative implementation, the step size of a forward jump branch instruction cannot exceed 4kb, where the step size is the instruction length between the target jump instruction and the branch instruction.

[0057] Building upon the preceding text, this invention also provides an optional implementation method for the process of assembling and rewriting the original instruction set to generate various branch instruction blocks. Please refer to [link / reference needed]. Figure 3 , Figure 3 This is a schematic diagram illustrating the process of generating branch instruction blocks according to an embodiment of the present invention. The process of assembling and rewriting the original instruction set to generate branch instruction blocks includes: S11 to S14, which are described in detail below.

[0058] S11 adds the corresponding initial instruction number to each instruction in the original instruction set.

[0059] S12, traverse and identify the original instruction set. When the nth instruction is identified as a branch instruction, select one from the first n-1 instructions in the original instruction set as the target jump instruction for the nth instruction.

[0060] Here, the nth instruction is the instruction with initial instruction number n in the original instruction set, and it can be randomly selected from the first n-1 instructions in the original instruction set as the target jump instruction of the nth instruction. Optionally, the instruction length between the target jump instruction of the nth instruction and the nth instruction itself cannot exceed 4kb.

[0061] S13, before the target jump instruction of the nth instruction, insert the corresponding initialization branch condition instruction of the nth instruction.

[0062] The initialization branch condition instruction corresponding to the nth instruction includes the target constraint condition corresponding to the nth instruction.

[0063] S14. Before the nth instruction, insert the corresponding instructions for reading branch variables, modifying branch variables, and storing branch variables in sequence to generate the branch instruction block corresponding to the nth instruction.

[0064] Optionally, after selecting one instruction (randomly) from the first n-1 instructions in the original instruction set as the target jump instruction for the nth instruction, the method further includes: generating a jump identifier based on the target jump instruction of the nth instruction (for example, if the initial instruction number of the target jump instruction of the nth instruction is 9, the jump identifier can be 9b, and the jump identifier is also called prefix information); and adding the jump identifier to the nth instruction and its corresponding target jump instruction respectively (to determine the jump object during subsequent execution).

[0065] Optionally, the inserted read branch variable instruction includes the first read address of the first source register and the second read address of the second source register of the nth instruction, where the first read address and the second read address belong to the target memory range; the inserted modify branch variable instruction includes the preset magnitude, the modification object, and the modification direction (increase or decrease) corresponding to the nth instruction, where the modification object is the first source register or the second source register of the nth instruction; the inserted store branch variable instruction includes the first write address of the first source register and the second write address of the second source register of the nth instruction, where the first write address and the second write address belong to the target memory range.

[0066] Optionally, the first read address is equal to the first write address, and the second read address is equal to the second write address.

[0067] This invention also provides a random instruction generator that implements the above-described branch instruction block execution method.

[0068] This invention also provides an electronic device, including the random instruction generator described above.

[0069] In summary, the branch instruction block execution method and related device provided by the embodiments of the present invention execute an initialization branch condition instruction, including: randomly generating two initial branch variables according to target constraints, and writing the two initial branch variables into a target storage area, wherein the target constraints correspond to the target loop number corresponding to the branch instruction, and the target difference between the two initial branch variables is an integer multiple of the target loop number; executing a target jump instruction and a regular instruction stream, wherein the target jump instruction is the jump instruction corresponding to the branch instruction, and the regular instruction stream is the intermediate instruction between the target jump instruction and the branch instruction in the original instruction set; executing a read branch variable instruction to write the two branch variables in the target storage area into the first source register and the second source register corresponding to the branch instruction, respectively; executing a modify branch variable instruction to adjust the branch variable in the first source register or the branch variable in the second source register; executing a store branch variable instruction to update the branch variable in the first source register and the branch variable in the second source register to the target storage area; and executing the branch instruction by combining the branch variable in the first source register and the branch variable in the second source register. Before modifying the first and second source registers, reliable branch variables are read from the target memory area to ensure that the modified branch variables match the number of iterations of the branch instruction. The branch variables in the first and second source registers are reliable, thus ensuring the controllability of the branch instruction jump.

[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0071] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A method for executing branch instruction blocks, characterized in that, The branch instruction block execution method includes: Executing the initialization branch condition instruction includes: randomly generating two initial branch variables according to the target constraint condition, and writing the two initial branch variables into the target storage area, wherein the target constraint condition corresponds to the target loop number corresponding to the branch instruction, and the target difference between the two initial branch variables is an integer multiple of the target loop number; Execute a target jump instruction and a regular instruction stream, wherein the target jump instruction is the jump instruction corresponding to the branch instruction, and the regular instruction stream is the intermediate instruction between the target jump instruction and the branch instruction in the original instruction set; Execute the read branch variable instruction to write the two branch variables in the target storage area into the first source register and the second source register corresponding to the branch instruction, respectively; Execute the branch variable modification instruction to adjust the branch variable in the first source register or the branch variable in the second source register; Execute the store branch variable instruction to update the branch variable in the first source register and the branch variable in the second source register to the target storage range; The branch instruction is executed by combining the branch variables in the first source register and the branch variables in the second source register.

2. The branch instruction block execution method as described in claim 1, characterized in that, The two branch variables in the target storage area are the first branch variable and the second branch variable. The step of executing the read branch variable instruction to write the two branch variables in the target storage area into the first source register and the second source register corresponding to the branch instruction, respectively, includes: Write the first branch variable in the target storage area into the first source register corresponding to the branch instruction; Write the second branch variable in the target storage area into the second source register corresponding to the branch instruction.

3. The branch instruction block execution method as described in claim 2, characterized in that, The execution of the branch variable modification instruction to adjust the branch variable in the first source register or the branch variable in the second source register includes: The first branch variable in the first source register or the second branch variable in the second source register is adjusted according to a preset amplitude, wherein the preset amplitude matches the target number of loops and the target difference.

4. The branch instruction block execution method as described in claim 3, characterized in that, The step of combining the branch variables in the first source register and the branch variables in the second source register to execute the branch instruction includes: Based on the branch variables in the first source register and the branch variables in the second source register, determine whether the loop condition is met; If the loop condition is met, the target jump instruction and the normal instruction stream are executed repeatedly; If the loop condition is not met, the branch instruction block will complete execution.

5. The branch instruction block execution method as described in claim 4, characterized in that, The loop condition is any one of the following: the first branch variable is greater than or equal to the second branch variable, the first branch variable is less than the second branch variable, or the first branch variable is not equal to the second branch variable.

6. The branch instruction block execution method as described in claim 1, characterized in that, The process of assembling and rewriting the original instruction set to generate various branch instruction blocks includes: Add a corresponding initial instruction number to each instruction in the original instruction set; The original instruction set is traversed and identified. When the nth instruction is identified as a branch instruction, one instruction is selected from the first n-1 instructions in the original instruction set as the target jump instruction of the nth instruction. Before the target jump instruction of the nth instruction, insert the corresponding initialization branch condition instruction of the nth instruction; Before the nth instruction, the corresponding instructions for reading branch variables, modifying branch variables, and storing branch variables are inserted sequentially to generate the branch instruction block corresponding to the nth instruction.

7. The branch instruction block execution method as described in claim 6, characterized in that, After selecting one instruction from the first n-1 instructions of the original instruction set as the target jump instruction for the nth instruction, the method further includes: Generate a jump identifier based on the target jump instruction of the nth instruction; The jump identifier is added to the nth instruction and its corresponding target jump instruction respectively.

8. The branch instruction block execution method as described in claim 6, characterized in that, The inserted read branch variable instruction includes the first read address of the first source register and the second read address of the second source register of the nth instruction, wherein the first read address and the second read address belong to the target memory area; The inserted branch variable modification instruction includes the preset range, modification object, and modification direction corresponding to the nth instruction. The modification object is the first source register or the second source register of the nth instruction. The inserted storage branch variable instruction, the first write address of the first source register and the second write address of the second source register of the nth instruction, the first write address and the second write address belong to the target storage range.

9. A random instruction generator, characterized in that, The random instruction generator performs the method according to any one of claims 1-8.

10. An electronic device, characterized in that, Includes the random instruction generator as described in claim 9.

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