Data processing apparatus and method, processor and chip

Abstract

The present disclosure relates to a data processing device and method, a processor and a chip, and relates to the technical field of computers, the data processing device comprising a processing module and a driving module; the processing module acquires address information of each thread in a first instruction in a case where it is judged that the to-be-processed instruction is the first instruction, wherein the first instruction is a multi-thread parallel loading instruction, and the address information of different threads is independent of each other; and the driving module determines a parallel loading result according to the address information of each thread in the first instruction, wherein the address information is used to determine an off-chip address and an on-chip address of each thread, and the thread is used to load data at a position indicated by the off-chip address to a position indicated by the on-chip address. The embodiment of the present disclosure can implement different data accesses in multi-thread parallel execution, and significantly improves the computing efficiency.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of computer, and particularly relates to a data processing apparatus and method, a processor and a chip. BACKGROUND

[0002] Processor chips, such as Graphics Processing Unit (GPU), play an increasingly important role in graphics and general computing scenarios due to their high parallel processing nature. The graphics processing in the GPU is usually placed in a fixed pipeline, and the general part is placed in a programmable pipeline. As an access to the video memory, the Load Store Unit (LSU) plays a crucial role in the programmable pipeline, and provides a load function (such as loading the data stored in the video memory to the storage unit in the programmable pipeline through the cache) or a storage function (such as writing the data processed in the programmable pipeline to the video memory through the cache).

[0003] The generic memory access of the GPU can include access to the private memory, the local memory and the global memory. In the related art, the GPU performs read and write of the global memory to the local memory, and needs to select a dedicated read and write path or a software and hardware joint solution according to the specific application scenario, and the solution is spliced by the behavior of the global memory to the private memory and the private memory to the local memory. The flexibility and efficiency of these solutions need to be further improved. SUMMARY

[0004] The present disclosure provides a data processing apparatus and method, a processor and a chip.

[0005] According to an aspect of the present disclosure, a data processing apparatus is provided, which comprises a processing module and a driving module, the processing module is connected to the driving module; the processing module acquires address information of each thread in a first instruction when it is determined that the first instruction is to be processed, wherein the first instruction is a multi-thread parallel load instruction, and the address information of different threads is independent of each other; the driving module determines a parallel load result according to the address information of each thread in the first instruction, wherein the address information is used to determine an off-chip address and an on-chip address of each thread, and the thread is used to load data at a position indicated by the off-chip address to a position indicated by the on-chip address.

[0006] In one possible implementation, the processing module includes a first preprocessing component, wherein the first preprocessing component determines the instruction to be processed as the first instruction when it detects that the instruction to be processed carries a preset identifier; the first preprocessing component obtains the destination address of each thread in the first instruction, wherein the destination address is the base address of the on-chip address; the first preprocessing component determines the maximum destination address and the minimum destination address among all destination addresses.

[0007] In one possible implementation, the first preprocessing component determines the maximum and minimum destination addresses among all destination addresses, including: the first preprocessing component determines a preset maximum value and a preset minimum value; the first preprocessing component performs multiple rounds of comparisons on all destination addresses based on the preset maximum value and the identity matrix to obtain the minimum destination address; and the first preprocessing component performs multiple rounds of comparisons on all destination addresses based on the preset minimum value and the identity matrix to obtain the maximum destination address.

[0008] In one possible implementation, the processing module includes a second preprocessing component, wherein the second preprocessing component receives the maximum destination address and the minimum destination address from the first preprocessing component; the second preprocessing component performs an out-of-bounds check on the first instruction based on the maximum destination address, the minimum destination address, and the size of the loaded data for each thread, and obtains a check result; if the check result indicates that the first instruction has not passed the out-of-bounds check, the second preprocessing component terminates the first instruction.

[0009] In one possible implementation, the processing module further includes a parameter acquisition component and an off-chip address acquisition component. The parameter acquisition component is used to acquire operands from the instruction to be processed, or to generate a first access request for acquiring operands in the instruction to be processed, wherein the operands are used to determine the segment address of the on-chip address. The off-chip address acquisition component is used to generate a second access request for acquiring the off-chip base address and off-chip offset address of each thread in the instruction to be processed.

[0010] In one possible implementation, the driver module determines the parallel loading result based on the address information of each thread in the first instruction, including: the driver module determining the on-chip address corresponding to each thread based on the destination address and the operand corresponding to each thread; the driver module determining the off-chip address corresponding to each thread based on the off-chip base address and off-chip offset address corresponding to each thread; and the driver module loading data in parallel from multiple independent off-chip addresses to multiple independent on-chip addresses based on the off-chip address and the on-chip address of each thread in the first instruction.

[0011] In one possible implementation, the driver module determines the parallel loading result based on the address information of each thread in the first instruction, including: the driver module processes all threads in the first instruction in parallel at one time to determine the parallel loading result; or, the driver module processes multiple threads of different parts of the first instruction in parallel each time until all threads in the first instruction are processed multiple times to obtain the parallel loading result.

[0012] In one possible implementation, the processing module further includes a data acquisition component, which, when the instruction to be processed is the first instruction, transmits the first instruction to the driver module; when the instruction to be processed is a storage instruction, the data acquisition component generates a third access request to acquire the data to be stored in the instruction to be processed; the driver module is further configured to store the data to be stored corresponding to each thread in the storage instruction in parallel into multiple independent off-chip addresses, wherein the off-chip address of each thread is determined based on the off-chip base address and the off-chip offset address.

[0013] In one possible implementation, the second preprocessing component is further configured to split the first instruction if the check result indicates that the first instruction has passed the out-of-bounds check, to obtain a first split result. The split result includes one or more second instructions, a first identifier corresponding to the last second instruction in the one or more second instructions, and a second identifier corresponding to each second instruction. The second identifier is used to indicate the ranking of the second instruction in the first instruction. In response to receiving the second identifier, the driver module loads data in parallel from multiple independent off-chip addresses to multiple independent on-chip addresses according to the off-chip address and the on-chip address of each thread in the second instruction corresponding to the second identifier.

[0014] In one possible implementation, the first preprocessing component is further configured to pass through the instruction to be processed to the second preprocessing component when it is detected that the instruction to be processed does not carry the preset identifier; the second preprocessing component is further configured to split the instruction to be processed to obtain a second splitting result.

[0015] In one possible implementation, the data processing device further includes an interface module, which collects at least one of the first access request from the parameter acquisition component, the second access request from the off-chip address acquisition component, and the third access request from the data acquisition component, and sends the operands returned by the first access request, the off-chip base address and off-chip offset address returned by the second access request, and the data to be stored returned by the third access request to the driver module.

[0016] In one possible implementation, the off-chip address is an address in global memory, and the on-chip address is an address in local memory.

[0017] According to one aspect of this disclosure, a data processing method is provided, the method being applied to a data processing apparatus, the data processing apparatus comprising: a processing module and a driving module, the processing module being connected to the driving module; the method comprising: the processing module, upon determining that the instruction to be processed is a first instruction, acquiring address information of each thread in the first instruction, wherein the first instruction is a multi-threaded parallel loading instruction, and the address information of different threads is independent of each other; the driving module determining a parallel loading result based on the address information of each thread in the first instruction, wherein the address information is used to determine the off-chip address and on-chip address of each thread, and the thread is used to load data at the location indicated by the off-chip address to the location indicated by the on-chip address.

[0018] In one possible implementation, the processing module includes a first preprocessing component. When the processing module determines that the instruction to be processed is a first instruction, it obtains the address information of each thread in the first instruction, including: the first preprocessing component determining that the instruction to be processed is the first instruction when it detects that the instruction to be processed carries a preset identifier; the first preprocessing component obtaining the destination address of each thread in the first instruction, wherein the destination address is the base address of the on-chip address; and the first preprocessing component determining the maximum and minimum destination addresses among all destination addresses.

[0019] In one possible implementation, the first preprocessing component determines the maximum and minimum destination addresses among all destination addresses, including: the first preprocessing component determines a preset maximum value and a preset minimum value; the first preprocessing component performs multiple rounds of comparisons on all destination addresses based on the preset maximum value and the identity matrix to obtain the minimum destination address; and the first preprocessing component performs multiple rounds of comparisons on all destination addresses based on the preset minimum value and the identity matrix to obtain the maximum destination address.

[0020] In one possible implementation, the processing module includes a second preprocessing component, and the method further includes: the second preprocessing component receiving the maximum destination address and the minimum destination address from the first preprocessing component; the second preprocessing component performing an out-of-bounds check on the first instruction based on the maximum destination address, the minimum destination address, and the size of the loaded data for each thread, and obtaining a check result; and the second preprocessing component terminating the first instruction if the check result indicates that the first instruction has not passed the out-of-bounds check.

[0021] In one possible implementation, the processing module further includes a parameter acquisition component and an off-chip address acquisition component to acquire address information of each thread in the first instruction, including: the parameter acquisition component is used to acquire operands from the instruction to be processed, or to generate a first access request for acquiring operands in the instruction to be processed, wherein the operands are used to determine the segment address of the on-chip address; the off-chip address acquisition component is used to generate a second access request for acquiring the off-chip base address and off-chip offset address of each thread in the instruction to be processed.

[0022] In one possible implementation, the driver module determines the parallel loading result based on the address information of each thread in the first instruction, including: the driver module determining the on-chip address corresponding to each thread based on the destination address and the operand corresponding to each thread; the driver module determining the off-chip address corresponding to each thread based on the off-chip base address and off-chip offset address corresponding to each thread; and the driver module loading data in parallel from multiple independent off-chip addresses to multiple independent on-chip addresses based on the off-chip address and the on-chip address of each thread in the first instruction.

[0023] In one possible implementation, the driver module determines the parallel loading result based on the address information of each thread in the first instruction, including: the driver module processes all threads in the first instruction in parallel at one time to determine the parallel loading result; or, the driver module processes multiple threads of different parts of the first instruction in parallel each time until all threads in the first instruction are processed multiple times to obtain the parallel loading result.

[0024] In one possible implementation, the processing module further includes a data acquisition component, and the method further includes: the data acquisition component, when the instruction to be processed is the first instruction, passing the first instruction to the driver module; the data acquisition component, when the instruction to be processed is a storage instruction, generating a third access request to acquire the data to be stored in the instruction to be processed; the driver module stores the data to be stored corresponding to each thread in the storage instruction in parallel into multiple independent off-chip addresses, wherein the off-chip address of each thread is determined based on the off-chip base address and the off-chip offset address.

[0025] In one possible implementation, the method further includes: the second preprocessing component, when the check result indicates that the first instruction has passed the out-of-bounds check, splits the first instruction to obtain a first splitting result, the splitting result including one or more second instructions, a first identifier corresponding to the last ranked second instruction among the one or more second instructions, and a second identifier corresponding to each second instruction, the second identifier being used to indicate the ranking of the second instruction in the first instruction; the driver module, in response to receiving the second identifier, loads data in parallel from multiple independent off-chip addresses to multiple independent on-chip addresses according to the off-chip address and the on-chip address of each thread in the second instruction corresponding to the second identifier.

[0026] In one possible implementation, the first preprocessing component is further configured to pass through the instruction to be processed to the second preprocessing component when it is detected that the instruction to be processed does not carry the preset identifier; the second preprocessing component is further configured to split the instruction to be processed to obtain a second splitting result.

[0027] In one possible implementation, the data processing device further includes an interface module, which is used to collect at least one of the first access request from the parameter acquisition component, the second access request from the off-chip address acquisition component, and the third access request from the data acquisition component, and send the operands returned by the first access request, the off-chip base address and off-chip offset address returned by the second access request, and the data to be stored returned by the third access request to the driver module.

[0028] In one possible implementation, the off-chip address is an address in global memory, and the on-chip address is an address in local memory.

[0029] According to one aspect of this disclosure, a processor is provided, the processor including the data processing means described above.

[0030] According to one aspect of this disclosure, a chip is provided that includes the processor described above.

[0031] In this embodiment of the disclosure, when the processing module determines that the instruction to be processed is a first instruction, it obtains the address information of each thread in the first instruction, wherein the first instruction is a multi-threaded parallel loading instruction, and the address information of different threads is independent of each other; the driving module determines the parallel loading result based on the address information of each thread in the first instruction, wherein the address information is used to determine the off-chip address and on-chip address of each thread, and the thread is used to load the data at the position indicated by the off-chip address to the position indicated by the on-chip address.

[0032] In this way, since the address information of multiple threads is independent of each other, multiple independent address information can be accessed in parallel. This provides a scheme for each thread to independently address both off-chip global memory and on-chip local memory, which is beneficial for providing more flexible interfaces to the software. It allows threads to execute different data accesses in parallel without having to wait for other threads, thus significantly improving computational efficiency.

[0033] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0034] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0035] Figure 1 A schematic diagram of a data processing apparatus according to an embodiment of the present disclosure is shown.

[0036] Figure 2 Another schematic diagram of a data processing apparatus according to an embodiment of the present disclosure is shown.

[0037] Figure 3 A schematic diagram of an instruction acquisition module according to an embodiment of the present disclosure is shown.

[0038] Figure 4 A schematic diagram of a parameter acquisition component according to an embodiment of the present disclosure is shown.

[0039] Figure 5 A schematic diagram of another parameter acquisition component according to an embodiment of the present disclosure is shown.

[0040] Figure 6 A schematic diagram of a first preprocessing component according to an embodiment of the present disclosure is shown.

[0041] Figure 7 A schematic diagram illustrating the determination of the minimum destination address according to an embodiment of the present disclosure is shown.

[0042] Figure 8 A schematic diagram of a second preprocessing component according to an embodiment of the present disclosure is shown.

[0043] Figure 9 A schematic diagram of an off-chip address acquisition component according to an embodiment of the present disclosure is shown.

[0044] Figure 10 A schematic diagram of a state machine according to an embodiment of the present disclosure is shown.

[0045] Figure 11 A schematic diagram of a data acquisition component according to an embodiment of the present disclosure is shown.

[0046] Figure 12 A schematic diagram of a driver module according to an embodiment of the present disclosure is shown.

[0047] Figure 13 A flowchart illustrating a data processing method according to an embodiment of the present disclosure is shown.

[0048] Figure 14 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. Detailed Implementation

[0049] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0050] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0051] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0052] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0053] Figure 1 A schematic diagram of a data processing apparatus according to an embodiment of the present disclosure is shown, such as Figure 1As shown, the data processing device includes: a processing module 2 and a driving module 3, wherein the processing module 2 is connected to the driving module 3; when the processing module 2 determines that the instruction to be processed is a first instruction, it obtains the address information of each thread in the first instruction, wherein the first instruction is a multi-threaded parallel loading instruction, and the address information of the multiple threads contained in the first instruction is independent of each other; the driving module 3 determines the parallel loading result according to the address information of each thread in the first instruction, wherein the address information is used to determine the off-chip address and on-chip address of each thread, and the thread is used to load the data at the position indicated by the off-chip address to the position indicated by the on-chip address.

[0054] Since the address information of multiple threads is independent of each other, threads can perform different data accesses in parallel without synchronizing and waiting for other threads, which can significantly improve computational efficiency.

[0055] In one possible implementation, the data processing device may be located in a processor, which may be a newly designed processor or an improved version of an existing processor chip. The types of processor chips may include, but are not limited to: Central Processing Unit (CPU), Graphics Processing Unit (GPU), General-Purpose Computing on Graphics Processing Units (GPGPU), Neural Network Processing Unit (NPU), Tensor Processing Unit (TPU), Digital Signal Processor (DSP), Application Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), etc.

[0056] In one possible implementation, the processing module 2 and the driving module 3 can be implemented using integrated circuits composed of general analog components, digital circuit components, etc. This disclosure does not limit the specific implementation method.

[0057] In one possible implementation, processing module 2 receives a pending instruction. Processing module 2 can determine whether the pending instruction carries a preset identifier. If the pending instruction carries a preset identifier, it can determine that the pending instruction is a first instruction, which is a multi-threaded parallel loading instruction. The address information of the multiple threads contained in the first instruction is independent of each other. Processing module 2 can obtain the address information of each thread in the first instruction. The multi-threaded parallelism can be all threads in the first instruction running in parallel, or only some threads in the first instruction running in parallel; the embodiments of this disclosure do not limit this.

[0058] In one possible implementation, the driver module 3 can determine the parallel loading result based on the address information of each thread in the first instruction, including: the driver module 3 processes all threads in the first instruction in parallel at one time to determine the parallel loading result; or, the driver module 3 processes multiple threads of different parts of the first instruction in parallel each time until all threads in the first instruction are processed multiple times to obtain the parallel loading result.

[0059] Assuming the number of threads in the first instruction is not particularly large and meets the transmission bandwidth requirements, driver module 3 can, within one clock cycle, send the loaded data from the off-chip address of each thread to the corresponding on-chip address in parallel, based on the address information of all threads in the first instruction. Alternatively, assuming the number of threads in the first instruction is particularly large and does not meet the transmission bandwidth requirements, driver module 3 can, within each clock cycle, send the loaded data from the off-chip address of each of the partial threads to the corresponding on-chip address in parallel, based on the address information corresponding to the partial threads in the first instruction, until the loaded data from the off-chip address of each thread in the first instruction has been sent to the corresponding on-chip address.

[0060] For example, assuming the first instruction contains 32 threads, each thread can independently address global memory and local memory, driver module 3 can process all 32 threads in parallel at once, or it can process 8 threads in four batches. The embodiments of this disclosure do not limit the number of threads contained in the first instruction.

[0061] In this way, depending on the actual application scenario, all or some threads in the first instruction can be processed in parallel at once, further improving the flexibility and adaptability of the data processing device.

[0062] In one possible implementation, the off-chip address is an address in global memory, and the on-chip address is an address in local memory.

[0063] For the read / write requirements from global memory to local memory, compared with related technologies that use global memory (such as video memory outside the GPU) to private memory (such as various levels of cache within the GPU), and then from private memory to local memory (such as storage units inside the programmable pipeline within the GPU), which requires the use of private memory as an intermediary, it is not flexible and efficient enough.

[0064] The data processing apparatus of this disclosure can access multiple independent address information in parallel by executing multi-threaded parallel loading instructions, providing a scheme for each thread to independently address both global and local memory, thus offering a more flexible interface to the software. Furthermore, the data processing apparatus can process multiple threads in the first instruction in parallel per clock cycle, thereby increasing the loading bandwidth from global memory to local memory and further improving data processing efficiency.

[0065] In one possible implementation, the number of threads included in the first instruction may be a first preset value (e.g., 32) or a second preset value (e.g., 128), where the second preset value is greater than the first preset value. The first preset value is the maximum number of threads that the processing module 2 can process at one time. The processing module 2 is further configured to split the first instruction according to the first preset value to obtain one or more second instructions, and a first identifier corresponding to the last second instruction in the one or more second instructions. The driving module 3 is further configured to determine the processing result of each second instruction and generate a trigger signal representing the completion of the first instruction according to the first identifier.

[0066] For example, in response to receiving a pending instruction from the instruction acquisition module, if the pending instruction is determined to be a first instruction, the processing module 2 can further split the first instruction according to a first preset value to obtain one or more second instructions, and a first identifier corresponding to the last second instruction among the one or more second instructions. For example, assuming the number of threads corresponding to the first instruction A is a first preset value, the processing module 2 can split the first instruction A according to the first preset value to obtain a second instruction, and a first identifier corresponding to the second instruction.

[0067] For example, assuming the number of threads corresponding to the first instruction B is a second preset value, the processing module 2 can split the first instruction B according to the first preset value to obtain multiple second instructions, namely: second instruction 1 to second instruction K, and the first identifier corresponding to the last second instruction K among the K second instructions, where K is the quotient of the second preset value divided by the first preset value.

[0068] The driver module 3 is unaware of whether the number of threads carried by the first instruction is a first preset value or a second preset value. Based on the splitting result of the front-end processing module 2, the driver module 3 can obtain the split second instruction each time and determine the processing result of each second instruction. Since the second instruction indicated by the first identifier is at the end of the sequence, if the second instruction corresponding to the first identifier is completed, it means that the first instruction before the split corresponding to the second instruction has also been completed. Therefore, if any second instruction has the first identifier, a trigger signal indicating the completion of the first instruction can be generated after obtaining the processing result of the second instruction.

[0069] The data processing apparatus of this disclosure is compatible with multiple thread bundle sizes, such as a first instruction with a first preset number of threads and a first instruction with a second preset number of threads, exhibiting high versatility for software code developed on different hardware platforms. Furthermore, it provides software with the ability to explore various thread bundle specifications for performance optimization.

[0070] In one possible implementation, the driver module 3 determines the parallel processing result of the second instruction in each clock cycle based on the address information of each thread in the second instruction; the driver module 3 determines the parallel loading result of the first instruction based on the parallel processing results of multiple second instructions determined in multiple clock cycles, where T is an integer greater than 1.

[0071] In this way, the data processing device of this disclosure embodiment can also process a portion of the threads in the split second instruction in parallel each clock cycle, so as to adapt to more parallel scenarios and improve the flexibility and applicability of the data processing device.

[0072] Figure 2 Another schematic diagram of a data processing apparatus according to an embodiment of the present disclosure is shown below. Figure 2 For example, the data processing apparatus of the present disclosure will be described by way of example.

[0073] In one possible implementation, such as Figure 2 As shown, in addition to the processing module 2 and the driver module 3, the data processing device may also include an instruction acquisition module 1 and an interface module 4. The instruction acquisition module 1, the processing module 2, and the driver module 3 are interconnected. The processing module 2 and the driver module 3 are also connected to the interface module 4. When each module accesses an external register, the interface module 4 can collect the access requests in a unified manner, send the access requests according to the corresponding register interface format, and return the corresponding returned data to each module in order.

[0074] In one possible implementation, the instruction acquisition module 1 can cache at least one instruction to be processed according to the order in which it receives instructions to be processed from the upstream module (e.g., the instruction issuing module of the graphics processor), and generate a corresponding instruction number for each instruction to be processed. The instruction number is used to indicate the order in which the instruction acquisition module 1 receives the instructions to be processed, so that when other modules execute the corresponding instruction to be processed, they can extract instruction information from the instruction acquisition module 1 according to the number.

[0075] In one possible implementation, the instruction to be processed can be encapsulated into a data packet according to a preset protocol format, which may include signals of multiple domain segments, such as: a first signal segment Valid, a second signal segment Enable, an identifier signal segment Wave id, a mode signal segment Wave mode, a mask information segment Active mask, and an accompanying information segment Sidebanddata.

[0076] The first signal field segment Valid has a bit width of 1 bit, which is used to indicate the validity of the instruction to be processed sent by the instruction issuing module of the graphics processor. 1 indicates that the instruction to be processed sent by the instruction issuing module of the graphics processor is valid, and 0 indicates that the instruction to be processed sent by the instruction issuing module of the graphics processor is invalid.

[0077] The second signal field segment Enable has a bit width of 1 bit, which is used to indicate the validity of the instruction to be processed received by the data processing device. 1 indicates that the instruction to be processed received by the data processing device is valid, and 0 indicates that the instruction to be processed received by the data processing device is invalid.

[0078] The width of the wave id identifier signal field can be 5 bits, which is used to distinguish the instructions to be processed corresponding to different sub-tasks.

[0079] The width of the Wave mode signal field can be 1 bit, used to indicate whether the number of threads M corresponding to the instruction to be processed is a first preset value or a second preset value, where the second preset value is greater than the first preset value.

[0080] The Active mask field has a bit width of 128 bits and is used to indicate the validity of each of the multiple threads carried by the instruction to be processed.

[0081] The Sideband data field can have a bit width of 202 and is used to describe the specific operational details or context of the instruction to be processed, such as immediate values, mode flags, opcodes, address codes, and other additional information.

[0082] It should be understood that the embodiments of this disclosure do not limit the bit width of each field in the instruction to be processed, and can be set according to the actual application scenario.

[0083] In one possible implementation, Figure 3 A schematic diagram of an instruction acquisition module according to an embodiment of the present disclosure is shown, such as... Figure 3 As shown, the instruction acquisition module 1 may include a management unit, a first queue, and a second queue. In response to receiving a pending instruction, the management unit of the instruction acquisition module 1 is responsible for caching the accompanying information within each pending instruction to the first queue, and for numbering each pending instruction according to the order in which they are received, generating an instruction number corresponding to each pending instruction. The management unit then sends the operation information (e.g., identification signals, mode signals, mask information) and instruction number of the pending instruction to the second queue for caching. Thus, when other modules at each level execute a pending instruction, they only need to send the corresponding instruction number to the instruction acquisition module 1, and the instruction acquisition module 1 can extract the corresponding operation information (e.g., identification signals, mode signals, mask information) and accompanying information of that pending instruction and send them to the respective modules.

[0084] In the example, the first queue may contain H+1 (e.g., 8) queue units, i.e., queue unit 0 to queue unit H. Each queue unit can store the accompanying information of one instruction to be processed. The first queue can store a maximum of H+1 instructions to be processed. When the first queue reaches its maximum space, the data processing device will back-pressure the front-end module (e.g., the instruction issuing module of the graphics processor) to stop receiving instructions to be processed. When an instruction to be processed is completed, the device receives an instruction to be processed end signal from the driver module 3, which can release the space of the queue unit inside the instruction acquisition module 1.

[0085] In the example, for any pending instruction with a thread count of either a first or a second preset value, the instruction acquisition module 1 caches the accompanying information of the pending instruction in its first queue. Operational information (such as identifier signals, pattern signals, and mask information) is cached in the second queue by passing it from one sub-module to the next.

[0086] In one possible implementation, such as Figure 2 As shown, the processing module 2 includes a parameter acquisition component 20, a first preprocessing component 21, a second preprocessing component 22, an off-chip address acquisition component 23, and a data acquisition component 24.

[0087] like Figure 2As shown, the parameter acquisition component 20 is connected to the instruction acquisition module 1, the interface module 4, and the first preprocessing component 21. The parameter acquisition component 20 can be used to obtain operands from the instruction to be processed, or to generate a first access request for obtaining operands from the instruction to be processed. The operands are used to determine the segment address of the on-chip address.

[0088] For example, in response to receiving an instruction number from the instruction acquisition module 1, the parameter acquisition component 20 acquires operands from the instruction to be processed corresponding to the instruction number, or generates a first access request for acquiring operands from the instruction to be processed corresponding to the instruction number. The operands are contained in the accompanying information field of the instruction to be processed. The instruction to be processed may carry one or more operands, which may be values, addresses, variables, registers, constants, etc. Embodiments of this disclosure do not limit the type and number of operands carried by the instruction to be processed.

[0089] Figure 4 A schematic diagram of a parameter acquisition component according to an embodiment of the present disclosure is shown, such as... Figure 4 As shown, in response to receiving an instruction number from the instruction acquisition module 1, the parameter acquisition component 20 can read the accompanying information of the instruction to be processed corresponding to the instruction number from the instruction acquisition module 1, and determine the operand of the instruction to be processed based on the accompanying information of the instruction to be processed.

[0090] Since the instruction to be processed can carry multiple operands, for example, the instruction to be processed can carry at least one operand from the first to the fifth operand, the parameter acquisition component 20 will judge the parameters such as the first operand, the second operand, the third operand, the fourth operand, and the fifth operand respectively. When the operand corresponding to the instruction to be processed is an immediate value, the corresponding operand status changes to the end state, which means that the operand carried by the accompanying information in the instruction to be processed is an immediate value result. Otherwise, in order to access the corresponding register (such as the first register, the second register, and the third register) to obtain the return result, the interface module 4 can send a first access request to the corresponding register to obtain the operand.

[0091] The first and second operands can be used to control the number of loop jumps in the two-dimensional direction of multiple threads in the instruction to be processed. For example, the first operand can control the number of loop jumps in the first dimension (e.g., the row direction), and the second operand can control the number of loop jumps in the second dimension (e.g., the column direction). The third operand can be an offset value used to adjust the offset of each loop jump in the instruction to be processed. The fourth operand is the operand required for other special instructions besides load and store instructions (e.g., instructions to be processed carrying a preset identifier). The fifth operand can be used when the subsequent component performs out-of-bounds detection. It should be understood that the embodiments of this disclosure only use the first to fifth operands as examples, and the type and number of operands carried by the instruction to be processed are not limited.

[0092] Regardless of whether the number of threads in the current pending instruction is a first preset value or a second preset value, the operands carried within the pending instruction are valid within that instruction. Therefore, the processing logic of the parameter acquisition component 20 is the same for both pending instructions with the first and second preset thread counts. The parameter acquisition component 20 can obtain the operands in the pending instruction; it acquires operands regardless of whether the number of threads in the current pending instruction is the first or second preset value.

[0093] Figure 5 A schematic diagram of another parameter acquisition component according to an embodiment of the present disclosure is shown, such as... Figure 5 As shown, in response to receiving an instruction number from the instruction acquisition module 1, the parameter acquisition component 20 can read the accompanying information of the instruction to be processed corresponding to that instruction number from the instruction acquisition module 1. If the parameter acquisition component 20 detects that the accompanying information of the instruction to be processed carries identification information, it indicates that the instruction to be processed is the first instruction, i.e., a multi-threaded parallel loading instruction. The parameter acquisition component 20 will also send access requests to obtain the first to third parameters. The first to third parameters can be used by subsequent components when determining the segment address of the on-chip address. If the parameter acquisition component 20 does not detect that the accompanying information of the instruction to be processed carries identification information, the parameter acquisition component 20 does not need to send access requests to obtain the first to third parameters. The first parameter can be 96 bits of data, with each 3 bits corresponding to one thread. Thus, the first parameter for each thread can be configured between 0 and 7. The embodiments of this disclosure do not limit the specific format of the first to third parameters.

[0094] like Figure 2As shown, the first preprocessing component 21 is connected to the instruction acquisition module 1, the interface module 4, the parameter acquisition component 20, and the second preprocessing component 22. In response to receiving an instruction number from the parameter acquisition component 20, the first preprocessing component 21, upon detecting that the instruction to be processed corresponding to the instruction number carries a preset identifier, determines the instruction to be processed as the first instruction. The first preprocessing component 21 acquires the destination address of each thread in the first instruction, wherein the destination address is the base address of the on-chip address. The first preprocessing component 21 determines the maximum and minimum destination addresses among all destination addresses.

[0095] Figure 6 A schematic diagram of a first preprocessing component according to an embodiment of the present disclosure is shown, such as... Figure 6 As shown, the first preprocessing component 21 can determine whether the current instruction to be processed carries a preset identifier. If the current first instruction does not carry a preset identifier, it means that the current instruction to be processed is not the first instruction, and the instruction to be processed is bypassed and passed to the next-level second preprocessing component 22. Here, the first instruction is a multi-threaded parallel loading instruction, indicating that the first instruction is a loading instruction, and the threads contained in the loading instruction are independent of each other. Considering that some or all threads of the first instruction can access multiple independent destination addresses in parallel within the same clock cycle, the subsequent driver module 3 can determine the parallel loading result of the first instruction, or the parallel loading result of certain threads within the first instruction, within one clock cycle during the process of determining the processing result of the first instruction.

[0096] If the current first instruction carries a preset identifier, it indicates that the current instruction to be processed is the first instruction. The first preprocessing component 21 can send an access request to the interface module 4 to obtain the destination address of each thread in the first instruction, and use the interface module 4 to perform external access, such as accessing the local memory on the GPU chip.

[0097] After the interface module 4 receives the return result from the external access, it returns the received destination address as return data to the first preprocessing component 21. For example, for a first instruction with a thread count of a first preset value (e.g., M=32), the returned destination address contains 32 data items, each data item being 32 bits (each data item can correspond to the destination address of one thread); as another example, for a first instruction with a thread count of a second preset value (e.g., M=128), the returned destination address contains 128 data items, each data item being 32 bits (each data item can correspond to the destination address of one thread). It should be understood that the embodiments of this disclosure only use 32 bits per thread destination address as an example, and the number of bits in the destination address can be set according to the actual application scenario.

[0098] The first preprocessing component 21 obtains the destination address of each thread in the first instruction, and can compare and process all destination addresses to determine the maximum and minimum destination addresses among all destination addresses.

[0099] In one possible implementation, the first preprocessing component 21 determines a preset maximum value and a preset minimum value; the first preprocessing component 21 performs multiple rounds of comparisons on all destination addresses based on the preset maximum value and the identity matrix to obtain the minimum destination address; the first preprocessing component 21 performs multiple rounds of comparisons on all destination addresses based on the preset minimum value and the identity matrix to obtain the maximum destination address.

[0100] For example, assuming the first instruction contains M threads (e.g., 32 or 128), considering the balance between resources and performance, the first preprocessing component 21 can compare P (e.g., P=8) destination addresses each time. Assuming the destination address is a 32-bit signed number, the binary representation of the maximum value of a 32-bit signed number is 32'b011111111111111111111111111111111, and its corresponding decimal representation is 2147483647; the binary representation of the minimum value of a 32-bit signed number is 32'b100000000000000000000000000000000, and its corresponding decimal representation is -2147483648; the first preprocessing component 21 will first set the preset maximum value to 2147483647 when searching for the minimum value of the destination address, and the first preprocessing component 21 will first set the preset minimum value to -2147483648 when searching for the maximum value of the destination address.

[0101] Figure 7 A schematic diagram illustrating the determination of the minimum destination address according to an embodiment of this disclosure is shown, such as... Figure 7 As shown, the destination addresses of the P threads that the first preprocessing component 21 can retrieve are compared with the preset maximum value to obtain the initial minimum destination address; subsequently, the destination addresses of the P threads (e.g., P=8) can be retrieved each time and compared with the minimum destination address obtained last time, until the minimum destination address among the M threads of the first instruction is obtained.

[0102] In each comparison, an identity matrix can be used to record the data, with the data 1 located at the diagonal position of the identity matrix. For example... Figure 7 As shown, A~J represent the destination address corresponding to each thread retrieved in the current iteration and the minimum destination address determined in the previous iteration, respectively. When obtaining the minimum destination address each time, the destination address A is compared with the other destination addresses in turn. If A is greater than the other destination addresses, then the (A,...) row of the identity matrix is ​​filled with 1 and the (...,A) column of the identity matrix is ​​filled with 0.

[0103] For example, when comparing A and B, if A is greater than B, fill in 1 at row A, column B of the identity matrix, i.e., (A,B)=1, and fill in 0 at row B, column A of the identity matrix, i.e., (B,A)=0; if A is less than or equal to B, fill in 0 at row A, column B of the identity matrix, i.e., (A,B)=0, and fill in 1 at row B, column A of the identity matrix, i.e., (B,A)=1.

[0104] After several comparisons, if A is the minimum value among the P+1 data points, then all results in column A will be 1, and the results in the other columns will be either 1 or 0. This can be represented by X. Performing a bitwise AND operation on each column of the comparison results will result in column A being 1 and the results in the other columns being 0. At this point, A is the minimum result among the P data points (e.g., P=8). This result is assigned to the minimum destination address. The minimum destination address is then compared with the next round of P destination addresses (e.g., P=8). After a total of M / P rounds of comparisons, the final result is obtained, which is the minimum destination address among the M destination addresses. Similarly, the maximum destination address among the M destination addresses can be obtained through a similar operation, which will not be elaborated here.

[0105] It should be understood that for a first instruction with a first preset number of threads (e.g., M=32), determining the minimum destination address (or maximum destination address) requires M / P=4 rounds of comparisons. For a first instruction with a second preset number of threads (e.g., M=128), determining the minimum destination address (or maximum destination address) requires M / P=16 rounds of comparisons.

[0106] The first preprocessing component 21 can obtain the maximum and minimum destination addresses among the destination addresses in the first instruction by using the identity matrix as an auxiliary tool to perform multiple rounds of comparisons, consuming a small amount of computing resources.

[0107] like Figure 2 As shown, the second preprocessing component 22 is connected to the instruction acquisition module 1, the interface module 4, the first preprocessing component 21, and the off-chip address acquisition component 23. The second preprocessing component 22 receives the maximum destination address and the minimum destination address from the first preprocessing component 21. The second preprocessing component 22 can perform an out-of-bounds check on the first instruction based on the maximum destination address, the minimum destination address, and the size of the loaded data for each thread, obtaining a check result. If the check result indicates that the first instruction has not passed the out-of-bounds check, the second preprocessing component 22 terminates the first instruction. If the check result indicates that the first instruction has passed the out-of-bounds check, the second preprocessing component 22 can pass the first instruction to the off-chip address acquisition component 23.

[0108] The second preprocessing component 22 is further configured to split the first instruction when the check result indicates that the first instruction has passed the boundary check, to obtain a first split result. The split result includes one or more second instructions, a first identifier corresponding to the last ranked second instruction among the one or more second instructions, and a second identifier corresponding to each second instruction. The second identifier is used to indicate the ranking of the second instruction in the first instruction.

[0109] For example, assuming that the number of threads corresponding to the first instruction A is a first preset value, the second preprocessing component 22 can split the first instruction A according to the first preset value to obtain a second instruction, as well as a first identifier and a second identifier corresponding to the second instruction.

[0110] For example, assuming the number of threads corresponding to the first instruction B is a second preset value, the second preprocessing component 22 can split the first instruction B according to the first preset value to obtain multiple second instructions, namely: second instruction 1 to second instruction K, and the second identifier of each instruction in the K second instructions, and the first identifier corresponding to the last second instruction K in the K second instructions.

[0111] The first identifier indicates that the corresponding second instruction is in the last position, and the second identifier indicates the order in which the corresponding second instruction is placed. It should be understood that the first and second identifiers can be combinations of numbers, letters, and special symbols. The embodiments of this disclosure do not limit the specific form of the first and second identifiers, and they can be set according to specific application scenarios.

[0112] In one possible implementation, the processing module 2 splits the first instruction corresponding to any instruction number according to the first preset value to obtain one or more second instructions, and the first identifier corresponding to the last second instruction among the one or more second instructions. This includes: using the second preprocessing component 22 of the processing module 2 to split the first instruction corresponding to any instruction number according to the first preset value to obtain one or more second instructions, and the first identifier corresponding to the last second instruction among the one or more second instructions.

[0113] In one possible implementation, the second preprocessing component 22 is configured to: receive the maximum and minimum destination addresses from the first preprocessing component 21; and when the load target of the first instruction is a preset register, determine the size of the data loaded by the load instruction into the preset register based on the operands of the first instruction; perform an out-of-bounds check on the first instruction based on the maximum and minimum destination addresses and the size of the data loaded by the load instruction into the preset register, and obtain a check result; and if the check result indicates that the first instruction passes the out-of-bounds detection, split the first instruction corresponding to any instruction number according to the first preset value to obtain one or more second instructions, and a first identifier corresponding to the last second instruction among the one or more second instructions.

[0114] In the case where the first instruction carries a preset identifier, the first instruction can be checked for out-of-bounds based on the size of the data loaded into the preset register by the loading instruction, the maximum destination address and the minimum destination address among the M destination addresses of the first instruction, and the check result can be obtained.

[0115] Figure 8 A schematic diagram of a second preprocessing component according to an embodiment of the present disclosure is shown, such as... Figure 8 As shown, in response to receiving an instruction number from the parameter acquisition component 20, the second preprocessing component 22 can read the accompanying information of the instruction to be processed corresponding to the instruction number from the instruction acquisition module 1. Based on the accompanying information of the instruction to be processed, it determines whether the current instruction to be processed is a load instruction. If the current instruction to be processed is not a load instruction, it means that the current instruction to be processed is another type of instruction besides a load instruction, such as a store instruction. The second preprocessing component 22 can directly perform split processing on the current instruction to be processed to obtain the split result. It should be understood that the split processing process performed by the second preprocessing component 22 is the same regardless of whether the instruction to be processed is the first instruction.

[0116] During the splitting process, the second preprocessing component 22 can read the mode signal of the first instruction corresponding to the instruction number received by itself from the instruction acquisition module 1. Based on the mode signal, it can determine the number of threads in the current first instruction. If the number of threads in the first instruction is a first preset value, it splits into a second instruction, or splits to the last second instruction of a first instruction with a number of threads equal to the second preset value. Then, it sets a first identifier for the second instruction and terminates the second preprocessing component 22. Otherwise, it executes the complete first instruction with a number of threads equal to the second preset value in a loop at the granularity of the first preset value until it splits to the last second instruction of a first instruction with a number of threads equal to the second preset value, at which point the second preprocessing component 22 terminates.

[0117] Among them, the first instruction with the number of threads being the first preset value can be split into a second instruction, which is both the first second instruction and the last second instruction in the sequence.

[0118] If the current instruction to be processed is a load instruction, and the load target is a preset register (e.g., the first register, the second register), then it will check whether the operand has been read back from the corresponding register (e.g., check whether the first operand and the second operand have been read back from the corresponding register). If it has been read back, the size of the loaded data will be calculated. At the same time, it will be determined whether the fifth operand has returned. If it has returned, then it will be checked for out-of-bounds error together with the result of the calculation of the size of the loaded data (e.g., the size of the space occupied by the loaded data).

[0119] Alternatively, if the currently pending instruction carries a preset identifier, it indicates that the currently pending instruction is the first instruction, which supports local multi-threaded parallel loading instructions. The bounds check requires the minimum destination address (or maximum destination address) from the processing result of the first preprocessing component 21. The sum of the minimum destination address (or maximum destination address) and the segment address index is compared with 0. If it is greater than 0, the lower bounds check is passed. If the sum of the minimum destination address (or maximum destination address), the segment address index, and the loaded data is less than the upper bounds check (e.g., a preset value), the upper bounds check is passed. Only when both the lower and upper bounds checks are satisfied can the first instruction carrying the preset identifier pass the bounds check. The segment address index can be used to adjust the offset of the destination address and can be determined by the fourth operand returned by the first access request.

[0120] If the loaded data of the current first instruction fails the out-of-bounds check, the first instruction is discarded and reported. If the loaded data of the current first instruction passes the out-of-bounds check, the current first instruction can be directly split. The specific splitting process can be found above and will not be repeated here.

[0121] In this way, the second preprocessing component 22 can perform out-of-bounds checks for scenarios where the instruction to be processed is a load instruction and the load target is a preset register, and it can also perform out-of-bounds checks for first instructions carrying preset flags, thus offering greater flexibility. Furthermore, regardless of whether the number of threads for the current first instruction is a first preset value or a second preset value, it will be split according to the granularity of the first preset value. When a first instruction with a number of threads of the first preset value is split into a second instruction, or when a first instruction with a number of threads of the second preset value is split into a last second instruction, the second preprocessing component 22 ends its workflow. Thus, by using the same workflow, it can be compatible with both first instructions with a number of threads of the first preset value and first instructions with a number of threads of the second preset value.

[0122] In one possible implementation, the first instruction corresponding to the instruction number is split according to the first preset value to obtain one or more second instructions, a first identifier corresponding to the last second instruction among the one or more second instructions, and a second identifier corresponding to each second instruction. This includes: the second preprocessing component 22, in response to the first instruction having a thread count of a second preset value, obtaining mask information of the first instruction, wherein the number of bits in the mask information is determined by the second preset value, and the mask information is used to indicate the validity of each thread in the first instruction; and splitting the mask information of the first instruction according to the bitwise OR result of the number of bits of each first preset value of the mask information to obtain multiple second instructions, a first identifier corresponding to the last second instruction among the multiple second instructions, and a second identifier corresponding to each second instruction.

[0123] For example, assuming the first preset value is 32 and the second preset value is 128, the active mask information for the first instruction of both the 32-thread and 128-thread threads has 128 bits. Specifically, for the first instruction of the 32-thread thread, the first 32 bits of the 128-bit active mask information (i.e., active mask [31:0]) are valid; for the first instruction of the 128-thread thread, all 128 bits of the active mask information (i.e., active mask [128:0]) are valid. It should be understood that the embodiments of this disclosure only use a first preset value of 32 and a second preset value of 128 as examples, and the specific values ​​of the first and second preset values ​​are not limited.

[0124] The second preprocessing component 22 will split the current first instruction according to the mode signal. When the mode signal indicates that the number of threads of the current first instruction is 32, the mask information active mask[31:0] of the current first instruction is valid, and the mask information active mask[127:32] is invalid. The split second instruction can be determined according to the mask information active mask[31:0]. The second preprocessing component 22 will set a first identifier for the second instruction. For example, the first identifier of the second instruction can be set to 0, indicating that the split second instruction is the last ranked second instruction. The splitting of the first instruction with 32 threads is completed.

[0125] When the mode signal indicates that the number of threads for the current first instruction is 128, the mask information active mask[127:0] of the current first instruction is valid. The second preprocessing component 22 will perform a bitwise OR operation on the current mask information signal every 32 bits. When the bitwise OR result of the mask information active mask[31:0] signal is 1, the second flag is set to 0, and the first second instruction after splitting is determined according to the mask information active mask[31:0].

[0126] When the result of the bitwise OR operation of the mask information active mask[63:32] signal is 1, the second identifier is set to 1, and the second second instruction after splitting is determined according to the mask information active mask[63:32].

[0127] When the result of the bitwise OR operation of the mask information active mask[95:64] signal is 1, the second identifier is set to 2, and the third second instruction after splitting is determined according to the mask information active mask[95:64].

[0128] When the result of the bitwise OR operation of the mask information active mask[127:96] signal is 1, the second identifier is set to 3, and the fourth second instruction after splitting is determined according to the mask information active mask[127:96]. The first identifier is set for the second instruction. For example, the first identifier of the second instruction can be set to 1, indicating that the fourth second instruction after splitting is the last second instruction. The splitting of the first instruction with 128 threads is completed.

[0129] If the bitwise OR result of the mask information active mask[127:96] signal is 0, then when the second identifier is 2, the first identifier signal is set to 1, indicating that the third split second instruction is the last ranked second instruction, and the splitting of the first instruction with 128 threads is completed.

[0130] The second identifier is used to indicate the order of the second instruction. For example, if the second identifier corresponding to the second instruction is set to 0, it means that the second instruction is the first in order; if the second identifier corresponding to the second instruction is set to 1, it means that the second instruction is the second in order; if the second identifier corresponding to the second instruction is set to 2, it means that the second instruction is the third in order; and if the second identifier corresponding to the second instruction is set to 3, it means that the second instruction is the fourth in order.

[0131] By setting a first identifier and a second identifier, two instruction structures can be satisfied: a first instruction with a first preset number of threads and a first instruction with a second preset number of threads. This helps to simplify the complexity of hardware design and improve the compatibility of the data processing device.

[0132] like Figure 2 As shown, the off-chip address acquisition component 23 is connected to the instruction acquisition module 1, the interface module 4, the second preprocessing component 22, and the data acquisition component 24. The off-chip address acquisition component 23 is used to generate a second access request to acquire the off-chip base address and off-chip offset address of each thread in the instruction to be processed (including the first instruction). For example, in response to receiving the instruction number and the second identifier from the second preprocessing component 22, the off-chip address acquisition component 23 can use a state machine to generate a second access request to acquire the off-chip base address and off-chip offset address of the second instruction corresponding to the instruction number and the second identifier. The second identifier is used to indicate the order of the second instructions.

[0133] Figure 9 A schematic diagram of an off-chip address acquisition component according to an embodiment of the present disclosure is shown, such as... Figure 9 As shown, in response to receiving an instruction number from the second preprocessing component 22, the off-chip address acquisition component 23 can read the accompanying information of the first instruction before splitting corresponding to the instruction number from the instruction acquisition module 1, and determine the off-chip base address and off-chip offset address of the first instruction based on the accompanying information of the first instruction before splitting. Simultaneously, the off-chip address acquisition component 23 can read the mode signal corresponding to the instruction number from the instruction acquisition module 1, thereby determining the number of threads of the first instruction before splitting based on the mode signal.

[0134] The off-chip address acquisition component 23 can determine the off-chip base address and off-chip offset address carried in the first instruction before splitting the current second instruction. When the off-chip base address comes from the corresponding register (e.g., any one of the first register, second register, and third register), in order to obtain the off-chip base address, the second access request of the corresponding register can be sent to the interface module 4. When the off-chip offset address during execution comes from the corresponding register (e.g., the fourth register), the off-chip address acquisition component 23 will send the second access request to obtain the off-chip base address first, and then send the second access request to obtain the off-chip offset address.

[0135] For a first instruction with a thread count of a first preset value or a second preset value, the first instruction will be split into multiple second instructions, namely segment0 / segment1 / segment2 / segment3, in the second preprocessing component 22 at the front end; when the off-chip address acquisition component 23 sends a second access request for the off-chip base address and the off-chip offset address, it will determine whether the off-chip base address and the off-chip offset address need to access the corresponding register.

[0136] If access to the corresponding register is required, the off-chip address acquisition component 23 will determine the mode signal of the first instruction before splitting the instruction number. If the mode signal indicates the first instruction with a thread number of the first preset value, then the second access request will be directly generated and sent to the interface module 4 based on the base address and offset address carried in the first instruction. Then the interface module 4 will send the corresponding second access request to the corresponding register.

[0137] If the mode signal indicates a first instruction with a thread count of the second preset value, a second access request will be generated based on the off-chip base address and off-chip offset address carried in the first instruction before splitting, and the second identifier of the second instruction after splitting. This ensures that the off-chip base address returned by the subsequent second access request is determined based on the base address, offset address, and second identifier. For example: the first second instruction segment0 obtained from splitting the first instruction will have its off-chip base address determined by the base address and offset address with the second identifier 0 added; the second second instruction segment1 obtained from splitting the first instruction will have its off-chip base address determined by the base address and offset address with the second identifier 1 added; the third second instruction segment2 obtained from splitting the first instruction will have its off-chip base address determined by the base address and offset address with the second identifier 2 added; and the fourth second instruction segment3 obtained from splitting the first instruction will have its off-chip base address determined by the base address and offset address with the second identifier 3 added.

[0138] To simplify the process, for scenarios where the base address and offset address originate from registers, if it is the first instruction with a thread count of a first preset value, then sending a second access request is sufficient; if it is the first instruction with a thread count of a second preset value, accessing the second access request corresponding to the first second instruction segment0 obtained from the first instruction splitting can obtain the valid off-chip base address of the first sorted second instruction. The off-chip base addresses of other sorted second instructions can be determined based on the off-chip base address of the first second instruction segment0, i.e., the second identifier corresponding to the other second instructions.

[0139] The off-chip address acquisition component 23 can obtain the off-chip base address and off-chip offset address of the first instruction before splitting, thereby determining the off-chip base address and off-chip offset address of each second instruction after splitting.

[0140] Optionally, the processes of obtaining the off-chip base address and the off-chip offset address can be controlled by a state machine. Figure 10 A schematic diagram of a state machine according to an embodiment of the present disclosure is shown, such as... Figure 10 As shown, when the external base address is in the first register, the state machine initially enters the first state. When the first transition condition is met, such as the external base address being in the first register and the current instruction not exceeding the bounds and the current state machine being in the first state, the state machine will transition to the second state. At this time, it will initiate the action of reading the external base address from the first register and issue a read request. When the second transition condition is met, such as when the enable signal corresponding to the currently issued read request completes the handshake, the state machine completes the state transition to the third state. After the external base address and external offset address of the current instruction are read, a pop signal will be generated, and this pop signal will be used as the third transition condition. When the third transition condition is met, the state machine can transition from the current state to the first state, indicating that it can receive the next instruction.

[0141] For external base addresses located in the first register, the third register, or the first register, there can be an independent state machine for judgment. When the external offset address is in the fourth register, there is also an independent state machine for control. If the external offset address is empty in an instruction, that is, it is not necessary to obtain the corresponding result from the fourth register, the end signal corresponding to the external offset address will be set. At this time, the state of the external base address can be determined according to the pop signal to determine whether it is in the first state and whether it needs to be set.

[0142] In this way, multiple state machines can independently control the behavior of each operand, and the states of all state machines can be cleared only when the third transition condition is met, which is conducive to unified management.

[0143] like Figure 2 As shown, the data acquisition component 24 is connected to the instruction acquisition module 1, the interface module 4, the external address acquisition component 23, and the driver module 3. When the instruction to be processed is the first instruction, the data acquisition component 24 transmits the first instruction to the driver module 3. When the instruction to be processed is a storage instruction, the data acquisition component 24 generates a third access request to retrieve the data to be stored in the instruction to be processed. In response to receiving the instruction number and the second identifier from the external address acquisition component 23, the data acquisition component 24 generates a third access request to retrieve the data to be stored in the instruction to be processed corresponding to the instruction number and the second identifier.

[0144] For example, if the instruction to be processed corresponding to the instruction number is a storage instruction, the operands and mask information corresponding to the second instruction (the second instruction obtained by splitting the instruction to be processed) are obtained according to the second identifier; based on the operands and mask information corresponding to the second instruction, a third access request is generated to obtain the data information in the second instruction corresponding to the instruction number and the second identifier.

[0145] Figure 11 A schematic diagram of a data acquisition component according to an embodiment of the present disclosure is shown, such as... Figure 11 As shown, in response to receiving the instruction number from the off-chip address acquisition component 23, the data acquisition component 24 can read the accompanying information of the instruction to be processed before splitting corresponding to the instruction number from the instruction acquisition module 1. Based on the accompanying information of the instruction to be processed before splitting, it can determine whether the instruction to be processed is the first instruction. If it is the first instruction, there is no need to acquire the data to be stored. The data acquisition component 24 can directly end the process and pass it through to the next-level driver module 3.

[0146] If the instruction to be processed is not the first instruction, for example, if the instruction to be processed is a stored instruction different from the first instruction, then a two-dimensional iterative operation will be performed based on the operands corresponding to the second instruction (e.g., the first operand and the second operand), and the mask information fragment read from the instruction acquisition module 1 based on the instruction number and the second identifier. The first operand can control the number of loop jumps in the first dimension (e.g., the row direction), and the second operand can control the number of loop jumps in the second dimension (e.g., the column direction).

[0147] During the iterative operation in the two-dimensional direction, if the data information of a certain thread is in the corresponding register (e.g., the first register, the second register), a third access request to retrieve the data information can be sent to the corresponding register through the interface module 4. When the iterative operation in the two-dimensional direction is completed, the data acquisition component 24 can directly end the process and send the instruction number to the next-level driver module 3.

[0148] In both the first instruction scenario with a first preset number of threads and the first instruction scenario with a second preset number of threads, the workflow of the data acquisition component 24 can only end after all the second instructions obtained from the splitting of the first instruction have been executed according to the splitting results of the second preprocessing component 22.

[0149] Using the data acquisition component 24, the amount of data information can be calculated based on the first operand, the second operand, and the mask information, and a third access request for acquiring the data information can be generated, so that the subsequent driver module 3 can write the data information returned by the third access request to an external address.

[0150] It should be understood that for the first instruction (the load instruction that is partially multi-threaded and parallel), it is not necessary to obtain data through the data acquisition component 24. Therefore, the data acquisition component 24 can pass the corresponding instruction information through the driver module 3 for subsequent processing.

[0151] In one possible implementation, the interface module 4 collects at least one of the first access request from the parameter acquisition component 20, the second access request from the off-chip address acquisition component 23, and the third access request from the data acquisition component 24, and sends the operands returned by the first access request, the off-chip base address and off-chip offset address returned by the second access request, and the data to be stored returned by the third access request to the driver module 3.

[0152] When modules at all levels need to access external registers, interface module 4 collects access requests in a unified manner, such as the first access request from parameter acquisition component 20, the second access request from off-chip address acquisition component 23, and the third access request from data acquisition component 24, and sends the access requests according to the corresponding register interface format, and returns the corresponding return data to modules at all levels in order.

[0153] In one possible implementation, the driver module 3 determines the on-chip address corresponding to each thread based on the destination address and the operand corresponding to each thread; the driver module 3 determines the off-chip address corresponding to each thread based on the off-chip base address and off-chip offset address corresponding to each thread; the driver module 3 loads data in parallel from multiple independent off-chip addresses to multiple independent on-chip addresses based on the off-chip address and the on-chip address of each thread in the first instruction.

[0154] When the instruction to be processed is a first instruction (a multi-threaded parallel load instruction), the driver module 3, in response to receiving the second identifier, loads data in parallel from multiple independent off-chip addresses to multiple independent on-chip addresses according to the off-chip address and the on-chip address of each thread in the second instruction corresponding to the second identifier; or, when the instruction to be processed is a storage instruction, the driver module 3 is further configured to store the data to be stored corresponding to each thread in the storage instruction into multiple independent off-chip addresses in parallel, wherein the off-chip address of each thread is determined based on the off-chip base address and the off-chip offset address.

[0155] Figure 12 A schematic diagram of a driver module according to an embodiment of the present disclosure is shown, such as... Figure 12As shown, the driver module 3 can collect the corresponding operands and calculate the corresponding off-chip addresses according to the current second instruction, and perform a two-dimensional iterative operation. The processing results of the second instruction are then packaged and sent to the subsequent module.

[0156] When the driver module 3 receives an instruction number from the processing module 2 (e.g., the data acquisition component 24 in the processing module 2), it can read the accompanying information of the instruction to be processed before splitting the instruction number from the instruction acquisition module 1, and determine whether the second instruction is a loading instruction or a storage instruction based on the accompanying information. If the second instruction is neither a loading instruction nor a storage instruction, the driver module 3 can end the current process.

[0157] When the second instruction is a load instruction or a store instruction, before starting the two-dimensional loop iteration operation, the driver module 3 will first collect the data information of the current second instruction, as well as the off-chip base address and off-chip offset address. After completing the collection, it will wait to see if the operand corresponding to the current second instruction (e.g., the fifth operand) is ready. When the above operation is completed, the instruction preparation signal will be set, indicating that the preparation of the current second instruction is complete and the two-dimensional loop iteration operation can begin.

[0158] During the cyclic iteration operation in the two-dimensional direction, the control jump is performed based on the operands corresponding to the second instruction (e.g., the first operand and the second operand), the mask information fragments read from the instruction acquisition module 1 based on the instruction number and the second identifier. The iteration process is similar to that of the data acquisition component 24, and will not be described in detail here.

[0159] During the iterative operation in the two-dimensional direction, the off-chip address and on-chip address corresponding to the second instruction are calculated. The off-chip address is the address of the external video memory of the processor (e.g., the graphics processor), and the on-chip address is the address of the internal memory of the processor (e.g., the graphics processor).

[0160] In the example, the off-chip address = off-chip base address + off-chip offset address + off-chip jump address. The off-chip base address and off-chip offset address can be used to determine the starting address of each thread's access to the processor's external video memory, that is, the address of the first iteration access to the processor's external video memory during the two-dimensional loop iteration operation. The off-chip jump address can be used to determine the offset between the address of the current iteration access to the processor's external video memory and the starting address during the two-dimensional loop iteration operation. The off-chip jump address can be determined based on the number of loop iterations and the operands returned by the first access request (such as the second operand and the third operand). The embodiments of this disclosure do not limit the specific method of determining the off-chip jump address, and can be set according to the actual application scenario.

[0161] The on-chip address = destination address + segment address + on-chip jump address. The destination address is determined based on the first preprocessing component 21. Each thread can correspond to an independent destination address; for example, each thread can independently address the processor's (e.g., GPU's) global memory and local memory. The driver module 3 can process the destination addresses of N (e.g., N=4) threads per clock cycle. The segment address can be determined based on the operands returned by the first access request, for example... Figure 5 The first parameter, second parameter, and third parameter are shown. The on-chip jump address can be used to determine the offset between the address of the processor's internal memory (e.g., a register) accessed in the current iteration and the destination address during the two-dimensional cyclic iteration operation. The on-chip jump address can be determined based on the number of cyclic iterations and the operands returned by the first access request (e.g., the first operand, the second operand, and the fourth operand). The embodiments of this disclosure do not limit the specific determination method of the segment address and the on-chip jump address, and can be set according to the actual application scenario.

[0162] To mitigate computational complexity, driver module 3 can first calculate the segment address and the intra-chip jump address before performing an addition operation with the destination address when processing intra-chip address calculations. The segment address and intra-chip jump address further enhance addressing flexibility, making it suitable for a wider range of application scenarios.

[0163] Based on the above calculations, driver module 3 will process load instructions and store instructions differently. For example, for load instructions, driver module 3 will concatenate and send the off-chip addresses of 8 parallel threads at once; for store instructions, driver module 3 will concatenate the off-chip addresses of 4 parallel threads and their corresponding data information at once, thereby filling the corresponding bit fields. For load instructions with local multi-threaded parallelism, driver module 3 can process the off-chip addresses of 4 parallel threads per cycle.

[0164] The driver module 3 is unaware of the number of threads in the instructions to be processed. Based on the splitting result of the second preprocessing component 22, the driver module 3 always sees a sequence of instructions with a thread count of the first preset value (e.g., any split second instruction). However, for the first instruction with a thread count of the first preset value, a trigger signal indicating the completion of the first instruction is generated at the end of each second instruction. This trigger signal can instruct the processor's flow control mechanism (fence mechanism) to execute other instructions in the next stage. But for the second instruction with a thread count of the second preset value, the second preprocessing component 22 splits it into multiple second instructions, and marks the last second instruction with a first identifier. When the driver module 3 encounters a first identifier, it executes the second instruction corresponding to the current first identifier and then generates a trigger signal indicating the completion of the first instruction. This trigger signal can instruct the processor's flow control mechanism (fence mechanism) to execute other instructions in the next stage. The driver module 3 does not generate a trigger signal for second instructions without a first identifier.

[0165] The driver module 3 can package the information obtained by the front-end model and send it to the back-end control module for merging processing according to the format corresponding to the first preset value of the number of threads and the second preset value of the number of threads. It is compatible with the first instruction with multiple thread bundle scales (e.g., the number of threads is the first preset value and the number of threads is the second preset value).

[0166] In summary, the data processing apparatus of this disclosure, since each of the N threads in the M threads of the first instruction can access N independent destination addresses in parallel, provides a scheme where each thread can independently address both global and local memory, offering a more flexible interface to the software and improving the loading bandwidth from global memory to local memory. Furthermore, the data processing apparatus can process a portion of the threads in the first instruction in parallel each clock cycle, further improving data processing efficiency.

[0167] It is understood that the various embodiments mentioned in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above-described solutions of specific implementation methods, the specific execution order of each module should be determined by its function and possible internal logic.

[0168] In addition, this disclosure also provides data processing methods, electronic devices, computer-readable storage media, programs, corresponding technical solutions and descriptions, and see the corresponding records in the method section, which will not be repeated here.

[0169] Figure 13 A flowchart illustrating a data processing method according to an embodiment of this disclosure is shown, such as... Figure 13As shown, the method is applied to a data processing device, which includes a processing module and a driving module, wherein the processing module is connected to the driving module, and the method includes:

[0170] In step S11, when the processing module determines that the instruction to be processed is the first instruction, it obtains the address information of each thread in the first instruction, wherein the first instruction is a multi-threaded parallel loading instruction and the address information of different threads is independent of each other.

[0171] In step S12, the driver module determines the parallel loading result based on the address information of each thread in the first instruction. The address information is used to determine the off-chip address and on-chip address of each thread, and the thread is used to load the data at the location indicated by the off-chip address to the location indicated by the on-chip address.

[0172] In one possible implementation, the processing module includes a first preprocessing component, and step S11 may include: when the first preprocessing component detects that the instruction to be processed carries a preset identifier, it determines that the instruction to be processed is the first instruction; the first preprocessing component obtains the destination address of each thread in the first instruction, wherein the destination address is the base address of the on-chip address; the first preprocessing component determines the maximum destination address and the minimum destination address among all destination addresses.

[0173] In one possible implementation, the first preprocessing component determines the maximum and minimum destination addresses among all destination addresses, including: the first preprocessing component determines a preset maximum value and a preset minimum value; the first preprocessing component performs multiple rounds of comparisons on all destination addresses based on the preset maximum value and the identity matrix to obtain the minimum destination address; and the first preprocessing component performs multiple rounds of comparisons on all destination addresses based on the preset minimum value and the identity matrix to obtain the maximum destination address.

[0174] In one possible implementation, the processing module includes a second preprocessing component, and the method further includes: the second preprocessing component receiving the maximum destination address and the minimum destination address from the first preprocessing component; the second preprocessing component performing an out-of-bounds check on the first instruction based on the maximum destination address, the minimum destination address, and the size of the loaded data for each thread, and obtaining a check result; and the second preprocessing component terminating the first instruction if the check result indicates that the first instruction has not passed the out-of-bounds check.

[0175] In one possible implementation, the processing module further includes a parameter acquisition component and an off-chip address acquisition component. Step S11 may include: the parameter acquisition component is used to acquire operands from the instruction to be processed, or to generate a first access request for acquiring operands in the instruction to be processed, wherein the operands are used to determine the segment address of the on-chip address; the off-chip address acquisition component is used to generate a second access request for acquiring the off-chip base address and off-chip offset address of each thread in the instruction to be processed.

[0176] In one possible implementation, step S12 may include: the driver module determining the on-chip address corresponding to each thread based on the destination address and the operand corresponding to each thread; the driver module determining the off-chip address corresponding to each thread based on the off-chip base address and off-chip offset address corresponding to each thread; and the driver module loading data in parallel from multiple independent off-chip addresses to multiple independent on-chip addresses based on the off-chip address and the on-chip address of each thread in the first instruction.

[0177] In one possible implementation, step S12 may include: the driver module processing all threads in the first instruction in parallel at one time to determine the parallel loading result; or, the driver module processing multiple threads of different parts of the first instruction in parallel each time until all threads in the first instruction are processed multiple times to obtain the parallel loading result.

[0178] In one possible implementation, the processing module further includes a data acquisition component, and the method further includes: the data acquisition component, when the instruction to be processed is the first instruction, passing the first instruction to the driver module; the data acquisition component, when the instruction to be processed is a storage instruction, generating a third access request to acquire the data to be stored in the instruction to be processed; the driver module stores the data to be stored corresponding to each thread in the storage instruction in parallel into multiple independent off-chip addresses, wherein the off-chip address of each thread is determined based on the off-chip base address and the off-chip offset address.

[0179] In one possible implementation, the method further includes: the second preprocessing component, when the check result indicates that the first instruction has passed the out-of-bounds check, splits the first instruction to obtain a first splitting result, the splitting result including one or more second instructions, a first identifier corresponding to the last ranked second instruction among the one or more second instructions, and a second identifier corresponding to each second instruction, the second identifier being used to indicate the ranking of the second instruction in the first instruction; the driver module, in response to receiving the second identifier, loads data in parallel from multiple independent off-chip addresses to multiple independent on-chip addresses according to the off-chip address and the on-chip address of each thread in the second instruction corresponding to the second identifier.

[0180] In one possible implementation, the first preprocessing component is further configured to pass through the instruction to be processed to the second preprocessing component when it is detected that the instruction to be processed does not carry the preset identifier; the second preprocessing component is further configured to split the instruction to be processed to obtain a second splitting result.

[0181] In one possible implementation, the data processing device further includes an interface module, which is used to collect at least one of the first access request from the parameter acquisition component, the second access request from the off-chip address acquisition component, and the third access request from the data acquisition component, and send the operands returned by the first access request, the off-chip base address and off-chip offset address returned by the second access request, and the data to be stored returned by the third access request to the driver module.

[0182] In one possible implementation, the off-chip address is an address in global memory, and the on-chip address is an address in local memory.

[0183] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0184] This disclosure also provides a processor, which includes the data processing apparatus described above.

[0185] This disclosure also provides a chip that includes the processor described above.

[0186] This disclosure also proposes an electronic device including the processor described above.

[0187] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described method.

[0188] Electronic devices can be provided as terminals, servers, or other forms of devices, such as user equipment (UE), mobile devices, user terminals, terminals, cellular phones, cordless phones, personal digital assistants (PDAs), handheld devices, computing devices, in-vehicle devices, wearable devices, etc.

[0189] Figure 14 A block diagram of an electronic device according to an embodiment of the present disclosure is shown. For example, electronic device 1900 may be provided as a server or terminal device. (Refer to...) Figure 14 The electronic device 1900 includes a processing component 1922, which further includes one or more processors, and memory resources represented by memory 1932 for storing instructions, such as application programs, that can be executed by the processing component 1922. The application programs stored in memory 1932 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1922 is configured to execute instructions to perform the methods described above.

[0190] Electronic device 1900 may also include a power supply component 1926 configured to perform power management of electronic device 1900, a wired or wireless network interface 1950 configured to connect electronic device 1900 to a network, and an input / output interface 1958. Electronic device 1900 can operate on an operating system stored in memory 1932, such as a Microsoft Server operating system (Windows Server). TM Apple's graphical user interface-based operating system (Mac OS X) TM ), a multi-user, multi-process computer operating system (Unix) TM Linux is a free and open-source Unix-like operating system. TM ), an open-source Unix-like operating system (FreeBSD) TM (or similar.)

[0191] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1932 including computer program instructions that can be executed by a processing component 1922 of an electronic device 1900 to perform the above-described method.

[0192] This disclosure can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of this disclosure.

[0193] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, (but not limited to) electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0194] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0195] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing the status information of the computer-readable program instructions to implement various aspects of this disclosure.

[0196] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0197] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0198] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0199] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0200] The computer program product can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0201] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0202] Those skilled in the art will understand that, in the above-described method of the specific implementation, the order in which each step is written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of each step should be determined by its function and possible internal logic.

[0203] If the technical solution of this application involves personal information, the product using this technical solution has clearly informed the user of the personal information processing rules and obtained the user's voluntary consent before processing the personal information. If the technical solution of this application involves sensitive personal information, the product using this technical solution has obtained the user's separate consent before processing the sensitive personal information, and also meets the requirement of "express consent". For example, at personal information collection devices such as cameras, clear and prominent signs are set up to inform users that they have entered the scope of personal information collection and that personal information will be collected. If an individual voluntarily enters the collection scope, it is deemed that they have agreed to the collection of their personal information; or on the personal information processing device, with clear signs / information informing users of the personal information processing rules, authorization is obtained from the individual through pop-up information or by asking the individual to upload their personal information; wherein, the personal information processing rules may include information such as the personal information processor, the purpose of personal information processing, the processing method, and the types of personal information processed.

[0204] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A data processing apparatus, characterized in that, The data processing device includes: a processing module and a driving module, wherein the processing module is connected to the driving module; When the processing module determines that the instruction to be processed is the first instruction, it obtains the address information of each thread in the first instruction. The address information is determined by the address obtained by the parameter acquisition component, the first preprocessing component, and the off-chip address acquisition component included in the processing module. The first instruction is a multi-threaded parallel loading instruction, and the address information of different threads is independent of each other. The driver module determines the parallel loading result based on the address information of each thread in the first instruction. The address information is used to determine the off-chip address and on-chip address of each thread. The thread is used to load the data at the location indicated by the off-chip address to the location indicated by the on-chip address. The off-chip address is the address of global memory, and the on-chip address is the address of local memory.

2. The data processing apparatus according to claim 1, characterized in that, The processing module includes a first preprocessing component, wherein... When the first preprocessing component detects that the instruction to be processed carries a preset identifier, it determines that the instruction to be processed is the first instruction. The first preprocessing component obtains the destination address of each thread in the first instruction, wherein the destination address is the base address of the on-chip address; The first preprocessing component determines the maximum and minimum destination addresses among all destination addresses.

3. The data processing apparatus according to claim 2, characterized in that, The first preprocessing component determines the maximum and minimum destination addresses among all destination addresses, including: The first preprocessing component determines a preset maximum value and a preset minimum value; The first preprocessing component performs multiple rounds of comparisons on all destination addresses based on the preset maximum value and the identity matrix to obtain the minimum destination address; The first preprocessing component performs multiple rounds of comparisons on all destination addresses based on the preset minimum value and the identity matrix to obtain the maximum destination address.

4. The data processing apparatus according to claim 2 or 3, characterized in that, The processing module includes a second preprocessing component, wherein... The second preprocessing component receives the maximum destination address and the minimum destination address from the first preprocessing component; The second preprocessing component performs an out-of-bounds check on the first instruction based on the maximum destination address, the minimum destination address, and the size of the data loaded by each thread, and obtains the check result; If the check result indicates that the first instruction has not passed the out-of-bounds check, the second preprocessing component terminates the first instruction.

5. The data processing apparatus according to claim 2, characterized in that, The processing module further includes a parameter acquisition component and an off-chip address acquisition component, wherein, The parameter acquisition component is used to acquire operands from the instruction to be processed, or to generate a first access request for acquiring operands from the instruction to be processed, wherein the operands are used to determine the segment address of the on-chip address; The off-chip address acquisition component is used to generate a second access request to acquire the off-chip base address and off-chip offset address of each thread in the instruction to be processed.

6. The data processing apparatus according to claim 5, characterized in that, The driver module determines the parallel loading result based on the address information of each thread in the first instruction, including: The driver module determines the on-chip address corresponding to each thread based on the destination address and the operands corresponding to each thread; The driver module determines the off-chip address corresponding to each thread based on the off-chip base address and off-chip offset address corresponding to each thread; The driver module loads data in parallel from multiple independent external addresses to multiple independent internal addresses according to the external address and the internal address of each thread in the first instruction.

7. The data processing apparatus according to claim 1, characterized in that, The driver module determines the parallel loading result based on the address information of each thread in the first instruction, including: The driver module processes all threads in the first instruction in parallel at one time to determine the parallel loading result. Alternatively, the driving module may process multiple threads of different parts of the first instruction in parallel each time until all threads of the first instruction have been processed multiple times to obtain the parallel loading result.

8. The data processing apparatus according to claim 5, characterized in that, The processing module further includes a data acquisition component, which, when the instruction to be processed is the first instruction, transmits the first instruction to the driving module. When the instruction to be processed is a storage instruction, the data acquisition component generates a third access request to acquire the data to be stored in the instruction to be processed. The driver module is also used to store the data to be stored corresponding to each thread in the storage instruction into multiple independent off-chip addresses in parallel. The off-chip address of each thread is determined based on the off-chip base address and the off-chip offset address.

9. The data processing apparatus according to claim 4, characterized in that, The second preprocessing component is further configured to split the first instruction when the check result indicates that the first instruction has passed the boundary check, to obtain a first split result. The split result includes one or more second instructions, a first identifier corresponding to the last ranked second instruction among the one or more second instructions, and a second identifier corresponding to each second instruction. The second identifier is used to indicate the ranking of the second instruction in the first instruction. In response to receiving the second identifier, the driver module loads data in parallel from multiple independent off-chip addresses to multiple independent on-chip addresses according to the off-chip address and the on-chip address of each thread in the second instruction corresponding to the second identifier.

10. The data processing apparatus according to claim 5, characterized in that, The first preprocessing component is further configured to pass through the instruction to be processed to the second preprocessing component when it is detected that the instruction to be processed does not carry the preset identifier; The second preprocessing component is also used to split the instruction to be processed to obtain a second splitting result.

11. The data processing apparatus according to claim 8, characterized in that, The data processing device further includes an interface module, which collects at least one of the first access request from the parameter acquisition component, the second access request from the off-chip address acquisition component, and the third access request from the data acquisition component, and sends the operands returned by the first access request, the off-chip base address and off-chip offset address returned by the second access request, and the data to be stored returned by the third access request to the driver module.

12. A data processing method, characterized in that, The method is applied to a data processing device, which includes a processing module and a driving module, wherein the processing module is connected to the driving module. The method includes: When the processing module determines that the instruction to be processed is the first instruction, it obtains the address information of each thread in the first instruction. The address information is determined by the address obtained by the parameter acquisition component, the first preprocessing component, and the off-chip address acquisition component included in the processing module. The first instruction is a multi-threaded parallel loading instruction, and the address information of different threads is independent of each other. The driver module determines the parallel loading result based on the address information of each thread in the first instruction. The address information is used to determine the off-chip address and on-chip address of each thread. The thread is used to load the data at the location indicated by the off-chip address to the location indicated by the on-chip address. The off-chip address is the address of global memory, and the on-chip address is the address of local memory.

13. A processor, characterized in that, The processor includes the data processing apparatus as described in any one of claims 1 to 11.

14. A chip, characterized in that, The chip includes the processor as described in claim 13.

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