Memory data migration method and electronic device

Abstract

The application discloses a memory data migration method and electronic equipment, and relates to the technical field of computers, which comprises the following steps: determining the access heat of a storage device accepted by a computing node based on the memory access task and the address mapping table executed by an exchange controller, so as to determine a source device and a candidate data unit; calculating the performance score of the candidate data unit after being stored in the storage device according to the access parameter of the candidate data unit and the state parameter of the storage device, so as to determine a data unit to be migrated and a target device; realizing the identification of hot and cold data from the perspective of a computer fast interconnection memory heterogeneous system, and improving the rationality of data migration based on the quantitative performance score; and controlling the migration of the data unit to be migrated from the source device to the target device, and updating the address mapping table, so as to not only avoid the influence of the data migration task on the host work of the computing node, but also realize a hot and cold data migration scheme without host awareness in the computer fast interconnection memory heterogeneous system.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a memory data migration method and electronic device. Background Technology

[0002] With the development of computer interconnect technology, memory expansion technology based on Compute Express Link (CXL) allows high-performance computing nodes to be flexibly connected to Compute Express Link (CXL) memory via CXL switches, thus enabling flexible memory connection methods. In heterogeneous CXL memory systems, storage devices with varying read / write performance exist. Therefore, it is necessary to rationally allocate matching storage media based on the frequency of data access to the storage devices, thereby improving system performance and resource utilization. However, the current reliance on the host operating system for hot / cold data identification and migration control places a significant workload on the host and negatively impacts the performance of heterogeneous CXL memory systems.

[0003] Improving the efficiency of hot and cold data migration in heterogeneous computer memory interconnect systems is a technical problem that needs to be solved by those skilled in the art. Summary of the Invention

[0004] This invention provides a memory data migration method and electronic device to at least solve the problem of low efficiency in cold and hot data migration in heterogeneous computer memory interconnection systems in related technologies.

[0005] This invention provides a memory data migration method, comprising:

[0006] Based on the memory access tasks executed by the switching controller and the address mapping table, the access frequency of the storage device to compute nodes is determined.

[0007] Based on access frequency, the source device in the storage device and the candidate data units in the source device are determined;

[0008] Based on the access parameters of the candidate data units and the status parameters of the storage device, calculate the performance score after storing the candidate data units in the storage device; based on the performance score, determine the data units to be migrated and the target device;

[0009] The system controls the migration of the data unit to be migrated from the source device to the target device and updates the address mapping table.

[0010] The computing node, the switching controller, and the storage device are connected based on the Computer Fast Interconnect Protocol; the address mapping table is a mapping table between the system physical address of the computing node and the device physical address of the storage device.

[0011] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described memory data migration methods when executing the computer program.

[0012] This invention determines the access frequency of storage devices to compute nodes based on memory access tasks executed by the switching controller and the address mapping table. Based on the access frequency, it identifies the source device and candidate data units within the source device. Then, based on the access parameters of the candidate data units and the status parameters of the storage device, it calculates a performance score after storing the candidate data units in the storage device. Finally, it determines the data units to be migrated and the target device based on the performance score. This achieves hot and cold data identification from the perspective of heterogeneous interconnect memory systems, and the quantitative performance score improves the rationality of data migration. Controlling the migration of data units from the source device to the target device and updating the address mapping table not only avoids the data migration task affecting the host operation of the compute nodes but also implements a host-insensitive hot and cold data migration scheme in heterogeneous interconnect memory systems. This avoids application interruptions on compute nodes caused by hot and cold data migration, improving the overall stability of the heterogeneous interconnect memory system. Attached Figure Description

[0013] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 An architecture diagram of a computer rapid interconnection system provided in an embodiment of the present invention;

[0015] Figure 2 This is a flowchart of a memory data migration method provided in an embodiment of the present invention. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0017] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0018] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] Here, we will first explain some key terms used in the embodiments of the present invention.

[0020] In traditional operating systems, cross-media data migration is typically scheduled by kernel threads, achieved through locking page tables, pausing access, copying data, and updating mappings. This mechanism has significant drawbacks: firstly, the host needs to participate in every page migration operation, increasing system complexity and scheduling overhead; secondly, to ensure data consistency, it often blocks upper-layer applications from accessing the target page, impacting response latency, especially in high-concurrency, high-real-time scenarios. This problem is particularly severe in high-concurrency, low-latency scenarios of rapidly interconnected computer systems. Therefore, there is an urgent need for a cross-media data migration mechanism that is transparent to host access, requires no modification to page tables, and does not trigger interruptions. Furthermore, consideration should be given to how to push control logic down to the device side, enabling asynchronous, automatic, and transparent data transfer through hardware.

[0021] To address the aforementioned issues, this invention provides a memory data migration scheme. It determines the access frequency of the storage device to compute nodes based on the memory access tasks executed by the switching controller and the address mapping table. Based on the access frequency, it identifies the source device and candidate data units within the source device. Using the access parameters of the candidate data units and the status parameters of the storage device, it calculates a performance score after storing the candidate data units in the storage device. Based on the performance score, it determines the data units to be migrated and the target device. This achieves hot and cold data identification from the perspective of heterogeneous memory systems in the Fast Interconnect (HIT) architecture, and the quantified performance score improves the rationality of data migration. It controls the migration of the data units to be migrated from the source device to the target device and updates the address mapping table. This not only avoids the data migration task affecting the host operation of the compute nodes but also provides a host-insensitive hot and cold data migration scheme in HIT heterogeneous memory systems, preventing application interruptions on compute nodes caused by hot and cold data migration and improving the overall stability of the HIT heterogeneous memory system.

[0022] Figure 1 This is an architecture diagram of a computer rapid interconnection system provided in an embodiment of the present invention.

[0023] The specific application environment architecture or specific hardware architecture on which the execution of the memory data migration method depends is described here.

[0024] like Figure 1 As shown, Compute Express Link (CXL) is an open standard that supports cache coherency, high bandwidth, and low latency interconnection. It can be used to build system architectures that pool computing power, pool memory, and decouple resources. Through the Compute Express Link protocol, the system can connect remote Compute Express Link memory devices (CXL Type 3 memory devices) to the host system, enabling cross-node sharing and dynamic on-demand expansion of memory resources.

[0025] This invention focuses on heterogeneous memory systems in computer rapid interconnect systems, addressing the issues of hot and cold data identification and data migration in storage devices with multiple storage media.

[0026] In a high-speed interconnect system, the first port of the switch controller connects to the compute node, and the second port connects to the storage device. At the hardware level, the compute node and the switch controller, as well as the switch controller and the storage device, can be connected via a high-speed serial computer expansion bus (Peripheral Component Interconnect Express, PCIe). At the protocol level, the compute node and the switch controller, as well as the switch controller and the storage device, are connected via the high-speed interconnect protocol.

[0027] The number of compute nodes can be one or more. The types of compute nodes can include general-purpose compute nodes and accelerated compute nodes. General-purpose compute nodes are the host machines, with a Central Processing Unit (CPU) as their computing core. Accelerated compute nodes use accelerator cards as their computing core, which can include, but are not limited to, Graphics Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs).

[0028] The number of storage devices can be one or more, configured as high-speed interconnect memory for the computer. The type of storage device can be one or more, including but not limited to Dynamic Random Access Memory (DRAM) and Solid State Drive (SSD). Because different types of storage media have significant differences in latency, bandwidth, cost, and energy efficiency—for example, DRAM has lower latency and higher bandwidth, suitable for hot data; while SSDs have larger capacities but higher latency, suitable for cold data—it is necessary to accurately identify cold and hot data in the memory media and allocate them accordingly to the matching memory media to ensure system performance and resource utilization.

[0029] The switching controller is used to forward data between compute nodes and storage devices, that is, to forward the memory access tasks of compute nodes to storage devices. The types of memory access tasks include read data tasks and write data tasks, and forward the data read from the storage device or the write completion information back to the compute node.

[0030] There can be one or more switching controllers. If there are multiple switching controllers, they can be fully interconnected, meaning that any two switching controllers are directly connected to each other. This ensures that the access path length is the same when any computing node in a heterogeneous memory system accesses any storage device.

[0031] Furthermore, the computer rapid interconnect system provided in this embodiment of the invention may also include a migration controller for performing the steps of the memory data migration method.

[0032] The migration controller can be implemented using the management controller within a CXL switch. The management controller in a switch is a higher-level controller that manages the switching controller and can be implemented using a microprocessor (mCPU). Alternatively, the migration controller can be implemented using a device other than a switch.

[0033] The embodiments of the present invention provide a memory data migration method. Referring to the architecture of the computer fast interconnect memory heterogeneous system described in the above embodiments, and in conjunction with the execution flow of the memory data migration method, the method is described in detail below.

[0034] Figure 2 This is a flowchart of a memory data migration method provided in an embodiment of the present invention.

[0035] like Figure 2 As shown, the memory data migration method provided in this embodiment of the invention may include: S201: determining the access heat of the storage device to the computing node based on the memory access tasks executed by the switching controller and the address mapping table.

[0036] S202: Based on access frequency, determine the source device in the storage device and the candidate data units in the source device.

[0037] S203: Calculate the performance score after storing the candidate data unit in the storage device based on the access parameters of the candidate data unit and the status parameters of the storage device; determine the data unit to be migrated and the target device based on the performance score.

[0038] S204: Control the migration of the data unit to be migrated from the source device to the target device and update the address mapping table.

[0039] The compute nodes, switching controllers, and storage devices are connected based on the Computer Fast Interconnect Protocol; the address mapping table is a mapping table between the system physical address (SPA) of the compute nodes and the device physical address (DPA) of the storage devices.

[0040] The memory data migration method provided in this embodiment of the invention can be applied to the migration controller described in the above embodiments. The functional modules set up to implement the specific steps may include a hot and cold data identification module, a unified scheduling and coordination management module, a hybrid media-aware mapping module, a migration control module, and an address mapping controller (Remapping Unit).

[0041] For S201, the compute node issues a memory access task to the storage device based on the system physical address. The switching controller queries its local address mapping table to determine the corresponding storage device and the physical address of the target device, and then forwards the memory access task to the corresponding storage device. During this process, the migration controller obtains information about the memory access task and the address mapping table by accessing the switching controller, so as to identify hot and cold data units in the storage device and control data migration.

[0042] In S201, the access frequency of data units in the storage device can be monitored by a cold / hot data identification module deployed on the migration controller to identify candidate cold and hot data as candidate data units. Specifically, the migration controller monitors the memory access tasks executed by the switching controller and obtains the address mapping table on which the switching controller is based to determine the physical address of the device accessed by the memory access task, thereby recording the access frequency of data units in the storage device.

[0043] In this embodiment of the invention, the data unit used for monitoring can be a page, which is the basic unit for memory management by the operating system. The operating system divides the virtual memory space into fixed-size blocks, each called a page. Common page sizes include 4KB and 8KB. The system physical address of a page is the physical memory address used by the host operating system to maintain the page, i.e., the physical memory address seen by the host. Each page is allocated a fixed-size contiguous memory region in physical memory. Assuming the page size in the system is 4KB, physical memory allocation starts from address 0. Page 0: physical address range is 0 to 4095 (0x0000 to 0x0FFF), page 1: physical address range is 4096 to 8191 (0x1000 to 0x1FFF)... and so on. The device physical address is the actual address of the page in the storage device. In this embodiment of the invention, the hot / cold data identification module can use the initial address and size of the page as address information for page monitoring.

[0044] The migration controller deploys a unified scheduling and coordination management module to achieve unified scheduling and coordination management of memory data migration in heterogeneous memory systems with rapid computer interconnection.

[0045] If the migration controller is the management controller in the switch, then the unified scheduling and coordination management module can be the Fabric Management (FM) module deployed in the management controller in the switch.

[0046] If the migration controller uses a device other than a switch, then after the structured management module performs the initialization of the storage device, the unified scheduling and coordination management module interacts with the structured management module to implement subsequent functions.

[0047] Based on the structured management module, the management controller performs unified scheduling and coordination management of compute nodes and storage devices of multiple storage media types connected to the computer fast interconnect memory heterogeneous system. Specifically, it can execute tasks such as storage device initialization, resource scheduling, data migration task instruction issuance, and migration status tracking, serving as the core of the control logic for memory data migration tasks. During the system initialization phase of the computer fast interconnect memory heterogeneous system, the structured management module performs discovery and registration operations on the storage devices connected to the system. This includes recording performance parameters such as capacity, bandwidth, and latency of each storage device, and establishing a system topology diagram that clarifies the connection relationships, routing paths, and load distribution between devices. The structured management module also supports hot-swapping capabilities and updates the memory pool topology and configuration table in real time, providing dynamic support for subsequent resource allocation and migration.

[0048] During system operation, the hot and cold data identification module monitors the access frequency of data units in the storage devices of the computer's rapidly interconnected memory heterogeneous system based on the system topology diagram.

[0049] For S202, the migration controller can maintain a heat monitoring table through the hot and cold data identification module to record the access heat of data units in the storage device. Based on the pre-configured filtering conditions for the data units to be migrated, it can select candidate data units from the data units and report the candidate data units to the unified scheduling and coordination management module so that the unified scheduling and coordination management module can determine the data units to be migrated from the candidate data units.

[0050] For S203, the hot and cold data identification module can identify the information of candidate data units and report it to the unified scheduling and coordination management module. The unified scheduling and coordination management module controls the calculation of the performance score after storing the candidate data units in the storage device based on the access parameters of the candidate data units and the status parameters of the storage device. Based on the performance score, the data units to be migrated and the target device are determined.

[0051] Specifically, for candidate hot data reported by the hot / cold data identification module, the unified scheduling and coordination management module can check the availability of storage devices with higher performance than the source device in the computer's high-speed interconnect memory heterogeneous system. If available, it selects a target device, assigns a target physical address, and coordinates the source and target devices to initiate migration. For candidate cold data reported by the hot / cold data identification module, the unified scheduling and coordination management module can check the availability of storage devices with lower performance than the source device in the computer's high-speed interconnect memory heterogeneous system. If available, it selects a target device, assigns a target physical address, and coordinates the source and target devices to initiate migration. In other words, the unified scheduling and coordination management module performs pairing and access arbitration between the source address in the source device and the target address in the target device before data migration, monitors the migration process to ensure the migration is complete, error-free, and promptly cleans up old data in the source device.

[0052] In addition, the structured management module can also be used to maintain interface with system-level topology configuration interfaces (such as Advanced Configuration and Power Interface (ACPI), System Resource Affinity Table (SRAT), etc.). To support hot-swapping of devices, sharing among multiple hosts, or to optimize host scheduling strategies when the migration scale is large, the structured management module can selectively update the system description table (in addition to ACPI and SRAT, it can also include the Heterogeneous Memory Attribute Table (HMAT), Cache Hierarchy Discovery Table (CDAT), etc.) to help the host operating system perceive macro-level changes in topology or resource status, but this does not affect the access transparency of the individual page migration process.

[0053] The address mapping controller, deployed within the management controller of the switch, maintains the mapping relationship between the system physical address of the host system and the device physical address of the storage device, and works in conjunction with each CXL Type 3 memory device. In this embodiment of the invention, the address mapping controller needs to ensure address transparency during cross-media page migration, ensuring that the host's logical address (i.e., the system physical address) remains unchanged, while the actual physical location of the data unit (device physical address) is dynamically adjusted according to system policies, thereby achieving data migration capabilities that are imperceptible to the application.

[0054] During system operation, an address mapping controller maintains an address mapping table between system physical addresses and device physical addresses. Each entry records the device physical address and media information corresponding to a system physical address. When a compute node initiates a memory access request, the request first reaches the switch. The address mapping controller then queries the mapping relationship of the target data unit in the memory access request, resolves the target storage device to be accessed and its physical address within the target storage device, and forwards the memory access request to the target storage device for execution. This process is completely transparent to the host (compute node), requiring no modification to page tables or virtual address mappings, ensuring no awareness at the operating system level.

[0055] During the data migration process, after the data unit to be migrated is successfully migrated to the target device, the address of the data unit to be migrated is redirected by the address mapping controller. The system physical address of the data unit to be migrated points to the device physical address of the source device, which is then updated to point to the device physical address of the target device.

[0056] To enhance resource awareness and cross-media scheduling efficiency during the hot and cold data migration process, this invention employs a hybrid media-aware decision module to coordinate with a unified scheduling and coordination management module and an address mapping controller to comprehensively evaluate the status parameters of each storage device in a heterogeneous computer memory interconnect system. By combining the access parameters of candidate data units, the system intelligently determines the most suitable target device for storing candidate data units, thereby achieving the dual goals of optimal performance and maximized resource utilization, and realizing an efficient memory migration strategy.

[0057] For S204, the direct memory access (DMA) channel between the source and target devices can be invoked through a pre-deployed migration control module, enabling data migration from the source device to the target device without the host's awareness.

[0058] The migration control module is deployed on the storage controller of the storage device and is used to call the storage device's direct memory access engine to perform data migration.

[0059] The memory data migration method provided in this embodiment of the invention is applied. The unified scheduling and coordination management module issues migration instructions to the migration control module of the source device and the migration control module of the target device, and calls the direct memory access engine of the source device and the direct memory access engine of the target device to complete the data transfer task asynchronously in hardware without interrupting host access.

[0060] The memory data migration method provided in this invention determines the access frequency of the storage device to compute nodes based on the memory access tasks executed by the switching controller and the address mapping table. Based on the access frequency, it identifies the source device and candidate data units within the source device. Using the access parameters of the candidate data units and the status parameters of the storage device, it calculates a performance score after storing the candidate data units in the storage device. Based on the performance score, it determines the data units to be migrated and the target device. This achieves hot and cold data identification from the perspective of heterogeneous interconnect memory systems, and the quantitative performance score improves the rationality of data migration. By controlling the migration of the data units to be migrated from the source device to the target device and updating the address mapping table, it not only avoids the data migration task affecting the host operation of the compute nodes but also implements a host-insensitive hot and cold data migration scheme in heterogeneous interconnect memory systems. This avoids application interruptions on compute nodes caused by hot and cold data migration and improves the overall stability of the heterogeneous interconnect memory system.

[0061] Based on the above embodiments, the present invention further describes the steps for identifying hot and cold data.

[0062] In this embodiment of the invention, determining the source device and candidate data units in the storage devices based on access frequency may include: classifying the storage devices into at least two categories according to their read / write speeds; arranging them from high to low read / write speeds, creating a first frequency monitoring table for the first category of storage devices and a second frequency monitoring table for the last category of storage devices; determining candidate cold data units in the corresponding storage devices as candidate data units based on the first frequency monitoring table, and determining the storage device containing the candidate data units as the source device; determining candidate hot data units in the corresponding storage devices as candidate data units based on the second frequency monitoring table, and determining the storage device containing the candidate data units as the source device.

[0063] In other words, for storage devices using high-performance storage media, only the cold data within the data units can be monitored, allowing for migration to lower-performance storage devices once cold data is detected. Conversely, for storage devices using low-performance storage media, only the hot data within the data units can be monitored, allowing for migration to higher-performance storage devices once hot data is detected.

[0064] Of course, the terms "high-performance" and "low-performance" storage media are relative. In this embodiment of the invention, the storage media can be arranged from high to low read / write speeds to determine the performance of the storage devices. For example, if there are two types of storage devices, DRAM and SSD, then DRAM has a higher read / write speed than SSD. For DRAM storage devices, only a first heat monitoring table can be set to monitor cold data, while for SSD storage devices, only a second heat monitoring table can be set to monitor hot data.

[0065] In some optional embodiments of the present invention, the first heat monitoring table can be used to record the access frequency corresponding to all data units in the storage device. Determining candidate cold data units in the corresponding storage device as candidate data units based on the first heat monitoring table may include: determining data units with access frequencies lower than a first preset frequency as candidate cold data units.

[0066] In some optional embodiments of the present invention, the first heat monitoring table can also be used to record the access records of all data units in the storage device during the first monitoring period. Determining candidate cold data units in the corresponding storage device as candidate data units based on the first heat monitoring table may include: if there is a data unit with no access records for two consecutive first monitoring periods, then that data unit is determined as a candidate cold data unit.

[0067] In other words, when monitoring cold data in storage devices with high-performance storage media, it is necessary to monitor the access frequency of all data units in the storage device because it is necessary to select the data unit with the reciprocal of the hotness.

[0068] In some optional embodiments of the present invention, the second heat monitoring table can be used to record data units in the storage device whose access frequency is higher than a second preset frequency. Determining candidate hot data units in the corresponding storage device as candidate data units based on the second heat monitoring table may include: determining the data units recorded in the second heat monitoring table as candidate hot data units.

[0069] In some optional embodiments of the present invention, the second heat monitoring table can also be used to record the memory access tasks received by the storage device, and determine the access frequency of the corresponding target data unit based on the memory access task records. Determining the candidate hot data units in the corresponding storage device as candidate data units based on the second heat monitoring table may include: arranging the data units from high to low according to the access frequency recorded in the second heat monitoring table, and determining the first preset number of data units as candidate hot data units.

[0070] In other words, when monitoring cold data in storage devices with low-performance storage media, since it is only necessary to monitor the data units with higher access frequency, and it is not necessary to know the access frequency of all data units, it is sufficient to record the access frequency of the data units with the highest access frequency.

[0071] When there are three or more storage media types in a computer fast interconnect memory heterogeneous system, a first hot monitoring table can be created for the storage device with the highest read / write speed to monitor cold data, a second hot monitoring table can be created for the storage device with the lowest read / write speed to monitor hot data, and a first hot monitoring table and a second hot monitoring table can be created for the remaining storage devices to monitor cold and hot data.

[0072] The embodiments of the present invention employ different hot and cold data monitoring strategies for storage devices with different read and write speeds, which is beneficial for targeted optimization of hot and cold data identification in different storage devices with different read and write speeds.

[0073] Based on the above embodiments, the present invention further describes the steps for calculating performance scores.

[0074] In this embodiment of the invention, S203, which calculates the performance score after storing the candidate data unit in the storage device based on the access parameters of the candidate data unit and the status parameters of the storage device, may include: determining a first matching degree parameter between the candidate data unit and the storage device based on the access parameters of the candidate data unit and the performance attribute parameters of the storage device; and calculating the performance score after storing the candidate data unit in the storage device based on the first matching degree parameter and the status parameters of the storage device.

[0075] In specific implementation, the first matching degree parameter between the candidate data unit and the storage device is determined based on the access parameters of the candidate data unit and the performance attribute parameters of the storage device. This may include: pre-establishing a first correspondence table between the access parameters of the data unit and the performance attribute parameters of the storage device; and querying the first correspondence table based on the access parameters of the candidate data unit and the performance attribute parameters of the storage device to determine the first matching degree parameter.

[0076] The access parameters for candidate data units can include at least one of the following: access frequency, read / write ratio, sequential parameters, and random parameters. Specifically, one or more types of access parameters can be set into multiple levels according to a range. For a type of storage device, each level can correspond to a matching degree parameter. For example, high-frequency random access is more suitable for DRAM, while sequential read / write is more suitable for SSD. The higher the matching degree parameter, the more suitable the data unit is for storage in that type of storage medium.

[0077] Based on the first matching degree parameter and the state parameters of the storage device, the performance score after storing the candidate data units in the storage device can be calculated, which may include: obtaining the first weight corresponding to the first matching degree parameter and the second weight corresponding to the state parameters of the storage device; and using the first weight and the second weight to perform a weighted summation calculation on the first matching degree parameter and the state parameters of the storage device to obtain the performance score.

[0078] The status parameters of the storage device include at least one of the following: bandwidth utilization of the storage device, average access latency of the storage device, and remaining capacity of the storage device.

[0079] In other words, the access parameters of candidate data units and the status parameters of each storage device in the current scheduling cycle can be collected and substituted into a preset performance scoring model to obtain the performance score of the candidate data units after they are stored in the storage device. This performance scoring model can be expressed by the following formula:

[0080] ;

[0081] in, For the first The candidate data unit is stored in the first... Performance ratings after each storage device; For the first The candidate data unit and the first Matching parameters for each storage device The weights for the matching degree parameter; For the first The bandwidth evaluation parameter of the first storage device can be used to represent the bandwidth evaluation parameter of the second storage device. The bandwidth usage of the storage device reflects the bandwidth usage of the first storage device. The current bandwidth availability of each storage device The weights for bandwidth evaluation parameters; For the first Average access latency per storage device Weights for average access latency; For the first Remaining available capacity of each storage device The weight of the remaining available capacity.

[0082] In the above performance scoring model, That is, the first weight. , , This is the second weight.

[0083] The aforementioned performance scoring model can be implemented based on the software module of the migration controller. The memory data migration method provided in this embodiment of the invention may further include: obtaining system operating status parameters of the host computer's rapid interconnect system; and updating the first weight and the second weight based on the system operating status parameters. That is, the first and second weights can be dynamically adjusted and adaptively updated based on system operating feedback.

[0084] In this embodiment of the invention, dynamically adjusting and adaptively updating the first and second weights based on system operation feedback may include: using the access parameters of the candidate data units and the state parameters of the storage device as context inputs to train a linear model for approximating the performance gains after storing the candidate data units in the storage device.

[0085] Specifically, it can be based on the online learning mechanism of the linear context multi-arm problem Bandit (Linear Confidence Upper Bound LinUCB). This mechanism incorporates the feature information of each candidate data unit-storage device pair. (Including the access parameters of the candidate data units and the state parameters of the storage devices mentioned above) as context input, a linear model is learned to approximate the performance gains after the migration.

[0086] Specifically, the performance scoring model described above can be expressed in vector form as follows (essentially a formula, just expressed differently):

[0087] ;

[0088] in, Indicates the first The candidate data unit is stored in the first... Performance ratings after each storage device Represents the weight vector. This indicates contextual input.

[0089] Weight vector The LinUCB algorithm is used for online updates, and the update process is as follows: (1) Parameter initialization: module maintains matrix with vector ,in For feature dimension, It is a regularization factor.

[0090] (2) Estimation and selection: Calculation The current estimated vector For each candidate storage device Calculate its upper confidence score :

[0091] ;

[0092] in, Reflecting the expected return under known characteristics, For uncertainty compensation terms, parameters This is a hyperparameter that controls the degree of exploration and is related to the desired confidence probability level. A larger value is chosen for high confidence, and a smaller value is chosen for fast convergence. In engineering practice, it is determined and adjusted through experiments. The theoretical values ​​that can be used as initial settings are:

[0093] ;

[0094] in, It is the probability of tolerable failure.

[0095] The storage device with the highest score was ultimately selected. As the target device.

[0096] (3) Performance feedback: After the migration is completed, the system calculates the actual performance feedback based on the changes in page latency before and after the migration and the migration cost. :

[0097] ;

[0098] in, This represents the average access latency before the migration. This represents the average access latency after the migration. To avoid small constants with a denominator of 0, and For configurable weights, typically The primary goal is to ensure delayed benefits.

[0099] (4) Parameter update based on r:

[0100] , .

[0101] This leads to the gradual correction of the parameter estimation vector. This enables adaptive optimization of weights based on system operating state parameters.

[0102] The performance scoring model described above can also be embedded as hardware logic, meaning it can be implemented using the logic circuitry of a programmable controller. Programmable controllers can be, but are not limited to, field-programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs).

[0103] In this embodiment of the invention, step S203 involves calculating a performance score after storing the candidate data units in the storage device based on the access parameters of the candidate data units and the status parameters of the storage device; determining the data units to be migrated and the target device based on the performance score, which may include: determining the first migration quantity of data units to be migrated corresponding to the current scheduling cycle; determining the first candidate data unit among the candidate data units based on the access parameters of the candidate data units; calculating the performance score after storing the first candidate data unit in the storage device based on the access parameters of the first candidate data unit and the status parameters of the storage device; and determining the first candidate data units of the first migration quantity as the data units to be migrated based on the performance score.

[0104] In practical applications, the scheduling capability of a switch's switching controller is limited, meaning the number of data units it can support for parallel migration is finite, and it is also affected by the load of the switching controller performing memory access tasks at the current moment. Therefore, when executing the memory data migration method provided in this embodiment of the invention, the scheduling cycle can be divided into time units. For this scheduling cycle, the first number of data units to be migrated that can be migrated in parallel is determined based on the load of the switching controller. That is, in this scheduling cycle, a corresponding number of data units to be migrated are selected to be migrated in parallel.

[0105] Then, based on the access parameters of the candidate data units, a second number of first candidate data units to be migrated is selected from the candidate data units, where the second number of migrations is greater than the first number of migrations. When determining the first candidate data unit, the most urgent candidate data units can be selected as the first data units to be migrated based on the urgency of the migration of all candidate data units waiting to be scheduled in this scheduling cycle.

[0106] In this embodiment of the invention, the candidate data units include candidate cold data units and candidate hot data units. For candidate data units of the same type, the urgency of migrating the selected data units can be comprehensively evaluated based on their access frequency and the remaining capacity of the storage device. When both candidate cold data units and candidate hot data units exist, normalized calculation formulas for the two types of candidate data units can be set to quantify and rank the urgency of migration for each type, and then combine this ranking with the remaining capacity of the storage device to comprehensively evaluate the urgency of migration.

[0107] Therefore, for the most urgent first data unit to be migrated, its performance score with all storage devices in the system can be calculated, and the storage device with the highest performance score can be selected as the target device. If the target device is the same as the source device, the information of the next first data unit to be migrated is read, and its performance score with all storage devices in the system is calculated, and so on, until the first number of data units to be migrated are selected from the first data units to be migrated.

[0108] In some optional embodiments of the present invention, the performance scores between all candidate data units and all storage devices can be directly calculated. Then, in step S203, determining the data units to be migrated and the target devices based on the performance scores may include: determining the first migration quantity of data units to be migrated corresponding to the current scheduling cycle; sorting the candidate data units in descending order of performance scores, determining the combination of the first migration quantity of candidate data units and the corresponding storage devices that are not candidate data units, using the candidate data units as the data units to be migrated in the current scheduling cycle, and using the corresponding storage devices as the target devices.

[0109] Traditional data migration schemes, which directly migrate cold data to low-performance storage media and hot data to high-performance storage media, are prone to resource mismatch. However, this invention provides a method for determining the data unit to be migrated and its corresponding target device. By considering the compatibility between the data unit's access characteristics and media attributes, it constructs an access-aware, storage media modeling, and learning-based scoring mechanism, ensuring that the data unit falls into its most suitable storage medium. This improves performance while further reducing overall memory costs. Furthermore, the hybrid media-aware decision module provided in this invention has good scalability and evolution capabilities. With the diversification of memory media (such as the introduction of new types of memories like NVDIMM, ReRAM, and PCM), the performance scoring model only needs to expand the media attribute dimensions and matching rules to support scheduling decisions for new types of devices. The entire scheduling strategy can be embedded in hardware logic or implemented through hardware-software collaboration, making it suitable for various deployment modes and computing platforms.

[0110] Based on the above embodiments, the present invention further describes the steps for controlling data migration.

[0111] In this embodiment of the invention, controlling the migration of data units to be migrated from a source device to a target device may include: sending information about the source device, the target device, and the data units to be migrated to the corresponding switching controller, so that the switching controller, based on the direct memory access module of the source device and the direct memory access module of the target device, forwards the data units to be migrated from the source device to the target device via the corresponding switching controller.

[0112] In this embodiment of the invention, the memory data migration logic of a computer rapidly interconnecting heterogeneous memory system is pushed down to the device side. After receiving the migration instruction from the unified scheduling and coordination management module, the migration control module automatically completes the subsequent transfer execution and consistency guarantee.

[0113] In its implementation, the migration control module first collaborates with the local direct memory access engine to initialize the source address (DPA_src) and target address (DPA_dst), and then initiates the data transfer process. The direct memory access channel, using page granularity (typically 4KB) or larger block granularity (such as 2MB big pages), writes the contents of the data units to be migrated from the source device to the target device via the computer's Fast Interconnect Memory (CXL.mem) path, achieving end-to-end data transfer.

[0114] Since the entire migration process is asynchronous within the device, and host access requests may continue to occur before direct memory access is completed, it is necessary to address the issues of "read / write conflicts during migration" and "data consistency." To address this, this embodiment of the invention employs a lightweight dual-path buffering mechanism. Its basic principle is to maintain a pair of mirrored buffer structures between the source and target addresses. During the data migration process involving direct memory access, the source device continues to act as the server for host access requests, and all read and write requests are responded to normally. For write operations, the migration control module synchronously copies the written data to the target buffer of the target device, or uses write replay logging to record the write trajectory, rewriting it to the target address after the migration is complete, thereby ensuring that the page data seen by the host remains consistent.

[0115] After completing the data transfer process for the data units to be migrated, the migration control module triggers a consistency verification process to confirm that the target address has been completely overwritten and is consistent with the state of the source address. At this point, the migration control module sends a mapping switch request to the address mapping controller in the switch's management controller. The address mapping controller can then perform an atomic-level mapping update from the system physical address to the device physical address. The host side is completely unaware of this process; the access path is redirected by the address mapping controller to the new address of the target device, without causing any application interruption.

[0116] This invention provides a memory data migration method based on a computer rapid interconnect system that can be deployed in a CXL switching architecture rack with multi-host capabilities. The method includes the following key hardware units: at least one computing node capable of running a general-purpose x86 server operating system; a migration controller deploying the hot / cold data identification module, unified scheduling and coordination management module, and hybrid media awareness decision module provided by this invention, which can be implemented based on the management controller in the switch, which also includes an address mapping controller; at least two CXL Type 3 memory expansion devices, such as a high-performance CXL-DRAM and a large-capacity CXL-SSD; and a migration control module deployed on each storage device.

[0117] The implementation steps may include: Step 1: System initialization and topology awareness.

[0118] During the system power-on startup phase, the structured management module in the management controller starts first, identifying and initializing all connected compute nodes and storage devices that serve as CXL Type 3 memory. This includes: enumerating the CXL Type 3 devices present in the system; identifying their device type (DRAM or SSD), capacity, bandwidth, latency, and other key performance indicators; constructing a system topology map and registering resource tables, identifying inter-device link paths, NUMA attributes, etc.; initializing the mapping table structure of the address mapping controller, establishing the initial system physical address → device physical address mapping relationship; and interfacing with the host operating system's ACPI / SRAT and other topology management tables to complete system awareness.

[0119] Step 2: Collect page access behavior and identify hot and cold pages.

[0120] During system operation, compute nodes continuously initiate read and write requests to the CXL memory pool. The migration controller, running a hot / cold data identification module, interacts with the switching controller in the switch to obtain information on memory access tasks, statistically analyzes the access frequency of data units on each storage device, and filters out candidate data units that need to be migrated. The hot / cold data identification module reports the address information of the candidate data units to the unified scheduling and coordination management module for scheduling decisions.

[0121] Step 3: Scheduling decision and target medium evaluation.

[0122] After receiving information about candidate data units, the unified scheduling and coordination management module calls the hybrid media awareness module to select target devices. The hybrid media awareness module collects access parameters of candidate data units (such as frequency, read / write ratio, and randomness), evaluates the status parameters of all storage devices in the system (such as remaining capacity, bandwidth utilization, and average access latency), calls the performance scoring model to calculate the performance score of candidate data units on each storage device, selects the optimal combination of candidate data units and their corresponding storage devices as the data units to be migrated and their corresponding target devices, and returns the address information of the data units to be migrated and the information of the target devices (which can be device numbers).

[0123] Step 4: Migration preparation and address mapping freeze.

[0124] The unified scheduling and coordination management module generates migration instructions based on the address information of the data unit to be migrated and the information of the target device. These instructions may include the physical address of the source device, the physical address of the target device, and the corresponding system physical address. The migration instructions are then sent to both the source and target devices to initiate the direct memory access data transfer process. Furthermore, the host's access to the data unit to be migrated still points to the physical address of the source device, and the source device will respond accordingly.

[0125] Step 5: Page data transfer and consistency assurance.

[0126] The migration control modules within both the source and target devices initiate the Direct Memory Access engine, copying the content of the data units to be migrated from the source device to the target device at a granularity of data units (which can be pages) along the computer's high-speed interconnect link. To ensure data consistency during the migration process, the following mechanisms can be employed: During migration, the source device continues to respond to host requests; for write operations, a double-shot caching or write log mechanism is used to synchronously update the data to the target buffer; after the migration is complete, a consistency check is performed to ensure that the content of the target page is consistent with the source page.

[0127] Step 6: Address mapping switch and resource update.

[0128] Once data migration is complete and target address consistency verification passes, the migration control module sends a "mapping switch request" to the address mapping controller. The address mapping controller then performs the following operations: atomically updates the system physical address → device physical address mapping entry, setting the target address as the new mapping address; updates the corresponding entry for the device physical address in the address mapping controller for subsequent quick table lookups; and notifies the unified scheduling and coordination management module to release the resources of the source address and reclaim the old device physical address. This switch is completely transparent to the host operating system, access paths are automatically updated, and no page table modification or service interruption is required.

[0129] Step 7: Migration complete and status cleanup.

[0130] After the migration is completed, the unified scheduling and coordination management module updates the system topology resource table and device load status. The system can then continue to perform a new round of hot and cold data identification and migration scheduling, forming a continuously dynamically optimized resource management cycle.

[0131] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0132] Embodiments of the present invention also provide a memory data migration apparatus, which may include: a hot / cold data identification module, used to determine the access heat of the storage device to compute nodes based on the memory access tasks executed by the switching controller and the address mapping table; a unified scheduling and coordination management module, used to determine the source device and candidate data units in the source device according to the access heat; a hybrid media-aware decision module, used to calculate the performance score after storing the candidate data units in the storage device according to the access parameters of the candidate data units and the status parameters of the storage device; and determine the data units to be migrated and the target device according to the performance score; and a migration control module, used to control the migration of the data units to be migrated from the source device to the target device and update the address mapping table; wherein, the compute nodes, the switching controller, and the storage device are connected based on the Computer Rapid Interconnect Protocol; and the address mapping table is a mapping table of the system physical address of the compute node and the device physical address of the storage device.

[0133] In this embodiment of the invention, the hybrid media-aware decision module calculates a performance score after storing the candidate data unit in the storage device based on the access parameters of the candidate data unit and the status parameters of the storage device. This may include: determining a first matching degree parameter between the candidate data unit and the storage device based on the access parameters of the candidate data unit and the performance attribute parameters of the storage device; and calculating a performance score after storing the candidate data unit in the storage device based on the first matching degree parameter and the status parameters of the storage device.

[0134] In this embodiment of the invention, the hybrid media-aware decision module determines a first matching degree parameter between the candidate data unit and the storage device based on the access parameters of the candidate data unit and the performance attribute parameters of the storage device. This may include: pre-establishing a first correspondence table of matching degree parameters between the access parameters of the data unit and the performance attribute parameters of the storage device; and querying the first correspondence table based on the access parameters of the candidate data unit and the performance attribute parameters of the storage device to determine the first matching degree parameter.

[0135] In this embodiment of the invention, the hybrid media-aware decision module calculates a performance score after storing candidate data units in the storage device based on a first matching degree parameter and a state parameter of the storage device. This may include: obtaining a first weight corresponding to the first matching degree parameter and a second weight corresponding to the state parameter of the storage device; and using the first weight and the second weight to perform a weighted summation calculation on the first matching degree parameter and the state parameter of the storage device to obtain a performance score.

[0136] In this embodiment of the invention, the hybrid media sensing decision module can also be used to obtain the system operating status parameters of the computer rapid interconnect system in which it is located; and update the first weight and the second weight according to the system operating status parameters.

[0137] In this embodiment of the invention, the unified scheduling and coordination management module determines the source devices and candidate data units within the storage devices based on access frequency. This can include: classifying the storage devices into at least two categories based on read / write speeds; arranging them from highest to lowest read / write speed, creating a first frequency monitoring table for the top category of storage devices and a second frequency monitoring table for the bottom category of storage devices; determining candidate cold data units within the corresponding storage devices as candidate data units based on the first frequency monitoring table, and determining the storage device containing the candidate data unit as the source device; and determining candidate hot data units within the corresponding storage devices as candidate data units based on the second frequency monitoring table, and determining the storage device containing the candidate data unit as the source device.

[0138] In this embodiment of the invention, the first heat monitoring table can be used to record the access frequency corresponding to all data units in the storage device; the unified scheduling and coordination management module determines the candidate cold data units in the corresponding storage device as candidate data units according to the first heat monitoring table, which may include: determining data units with access frequencies lower than a first preset frequency as candidate cold data units.

[0139] In this embodiment of the invention, the second heat monitoring table is used to record data units in the storage device whose access frequency is higher than a second preset frequency; the unified scheduling and coordination management module determines the candidate hot data units in the corresponding storage device as candidate data units based on the second heat monitoring table, which may include: determining the data units recorded in the second heat monitoring table as candidate hot data units.

[0140] In this embodiment of the invention, the hybrid media-aware decision module calculates a performance score after storing the candidate data units in the storage device based on the access parameters of the candidate data units and the status parameters of the storage device; and determines the data units to be migrated and the target device based on the performance score, which may include: determining the first migration quantity of data units to be migrated corresponding to the current scheduling cycle; determining the first candidate data unit among the candidate data units based on the access parameters of the candidate data units; calculating the performance score after storing the first candidate data unit in the storage device based on the access parameters of the first candidate data unit and the status parameters of the storage device; and determining the first candidate data units of the first migration quantity as the data units to be migrated based on the performance score.

[0141] In this embodiment of the invention, the migration control module controls the migration of the data unit to be migrated from the source device to the target device, which may include: sending the information of the source device, the information of the target device, and the information of the data unit to be migrated to the corresponding switching controller, so that the switching controller forwards the data unit to be migrated from the source device to the target device through the corresponding switching controller based on the direct memory access module of the source device and the direct memory access module of the target device.

[0142] For a description of the features in the embodiment corresponding to the memory data migration device, please refer to the relevant description in the embodiment corresponding to the memory data migration method, which will not be repeated here.

[0143] Embodiments of the present invention also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described embodiments of the memory data migration method.

[0144] Embodiments of the present invention also provide a non-volatile storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described memory data migration method embodiments at runtime.

[0145] In one exemplary embodiment, the aforementioned non-volatile storage medium may include, but is not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0146] Embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described memory data migration method embodiments.

[0147] Embodiments of the present invention also provide another computer program product, including a non-volatile storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described memory data migration method embodiments.

[0148] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0149] The present invention has provided a detailed description of a memory data migration method and electronic device. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of these embodiments are only intended to aid in understanding the method and core ideas of the invention. It should be noted that those skilled in the art can make various improvements and modifications to the invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A memory data migration method, characterized in that, include: Based on the memory access tasks executed by the switching controller and the address mapping table, the access frequency of the storage device to compute nodes is determined. Based on access frequency, the source device in the storage device and the candidate data units in the source device are determined; Based on the access parameters of the candidate data unit and the status parameters of the storage device, calculate the performance score after storing the candidate data unit in the storage device; Based on the performance score, the data units to be migrated and the target devices are determined; By invoking the direct memory access channel between the source device and the target device through a pre-deployed migration control module, the data unit to be migrated is controlled to migrate from the source device to the target device without the host's awareness, and the address mapping table is updated. The computing node, the switching controller, and the storage device are connected based on the Computer Fast Interconnect Protocol; the address mapping table is a mapping table between the system physical address of the computing node and the device physical address of the storage device. The step of determining the source device in the storage device and the candidate data units in the source device based on access popularity includes: The storage devices are classified into at least two categories based on their read and write speeds; Arrange the storage devices in descending order of read / write speed, create a first heat monitoring table for at least one of the top categories of storage devices, and create a second heat monitoring table for at least one of the bottom categories of storage devices. Based on the first heat monitoring table, the candidate cold data unit in the corresponding storage device is determined as the candidate data unit, and the storage device where the candidate data unit is located is determined as the source device; Based on the second heat monitoring table, the candidate hot data unit in the corresponding storage device is determined as the candidate data unit, and the storage device where the candidate data unit is located is determined as the source device.

2. The memory data migration method according to claim 1, characterized in that, Based on the access parameters of the candidate data units and the status parameters of the storage device, a performance score is calculated after storing the candidate data units in the storage device, including: Based on the access parameters of the candidate data unit and the performance attribute parameters of the storage device, a first matching degree parameter between the candidate data unit and the storage device is determined; Based on the first matching degree parameter and the status parameter of the storage device, the performance score after storing the candidate data unit in the storage device is calculated.

3. The memory data migration method according to claim 2, characterized in that, Based on the access parameters of the candidate data unit and the performance attribute parameters of the storage device, a first matching degree parameter between the candidate data unit and the storage device is determined, including: A first correspondence table is pre-established between the access parameters of data units and the performance attribute parameters of the storage device; The first matching degree parameter is determined by querying the first corresponding table based on the access parameters of the candidate data unit and the performance attribute parameters of the storage device.

4. The memory data migration method according to claim 2, characterized in that, Based on the first matching degree parameter and the status parameters of the storage device, the performance score after storing the candidate data unit in the storage device is calculated, including: Obtain the first weight corresponding to the first matching degree parameter and the second weight corresponding to the state parameter of the storage device; The performance score is obtained by weighted summation of the first matching degree parameter and the state parameter of the storage device using the first weight and the second weight.

5. The memory data migration method according to claim 4, characterized in that, Also includes: Obtain the system operating status parameters of the computer's Fast Interconnect system; The first weight and the second weight are updated based on the system operating status parameters.

6. The memory data migration method according to claim 2, characterized in that, The access parameters for the candidate data unit include at least one of the following: access frequency, read / write ratio, sequential parameter, and random parameter corresponding to the candidate data unit.

7. The memory data migration method according to claim 2, characterized in that, The status parameters of the storage device include at least one of the following: the bandwidth utilization of the storage device, the average access latency of the storage device, and the remaining capacity of the storage device.

8. The memory data migration method according to claim 1, characterized in that, Based on the access parameters of the candidate data unit and the status parameters of the storage device, calculate the performance score after storing the candidate data unit in the storage device; Based on the performance score, the data units to be migrated and the target devices are determined, including: Determine the first migration quantity of the data unit to be migrated corresponding to the current scheduling cycle; The first candidate data unit among the candidate data units is determined based on the access parameters of the candidate data units; Based on the access parameters of the first candidate data unit and the status parameters of the storage device, calculate the performance score after storing the first candidate data unit in the storage device; Based on the performance score, the first candidate data unit of the first migration quantity is determined as the data unit to be migrated.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the memory data migration method as described in any one of claims 1 to 8 when executing the computer program.

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