A failure oscillation interval determination method, temperature control method and related device

Abstract

The application provides a failure oscillation interval determination method and temperature control method and related equipment. In the i-th test stage, the width of the failure oscillation interval is set as the i-th width, the current chip temperature of the processor is obtained according to a preset period interval, an error integral temperature control strategy is executed to obtain a current frequency point corresponding to the current chip temperature, and the current frequency point is used as the running frequency of the processor in the current period. Whether the current chip temperature exceeds the target temperature in the i-th test stage is monitored. If not, the i-th width is determined as the target width of the failure oscillation interval, and the lower limit of the failure oscillation interval is determined. The failure oscillation interval when the error integral temperature control strategy is executed is determined, so that when the chip temperature is in the failure oscillation interval, the updating of the integral error is stopped, the adjustment range of the temperature is changed, and the chip temperature is prevented from oscillating around the target temperature or the oscillation range is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip temperature control, in particular to a failure oscillation interval determination method, a temperature control method and related equipment. BACKGROUND

[0002] With the popularity of intelligence and Internet, the use frequency of electronic devices such as mobile phones and computers in life is increasing, which brings great convenience to people. In electronic devices, the processor is a relatively important component structure, and the running state of the processor directly affects the entire electronic device. When the processor runs in a high-performance high-power mode, it often causes the temperature to be too high, and even causes the processor to be damaged. Therefore, when the temperature of the processor is too high, the running power consumption needs to be reduced to achieve the purpose of cooling, which will cause the performance of the processor to decrease.

[0003] Therefore, an error integral temperature control strategy is introduced to regulate the temperature of the processor. When the error integral temperature control strategy is executed, the processor temperature will oscillate above and below the target temperature, which will cause the processor temperature to be higher than the target temperature, affecting the safety of the processor. SUMMARY

[0004] The purpose of the present application is to provide a failure oscillation interval determination method, a temperature control method and related equipment to improve the above problems.

[0005] In order to achieve the above purpose, the technical solutions adopted by the embodiments of the present application are as follows:

[0006] In a first aspect, the present application provides a failure oscillation interval determination method, which comprises:

[0007] In the ith test stage, the width of the failure oscillation interval is set to the ith width, the current chip temperature of the processor is obtained at a preset period interval, if the current chip temperature reaches the effective temperature starting point, the error integral temperature control strategy is executed to obtain the current frequency point corresponding to the current chip temperature, and the current frequency point is taken as the running frequency of the processor in the current period;

[0008] Wherein, the effective temperature starting point is the temperature starting point at which the error integral temperature control strategy takes effect under the current environment temperature, the effective temperature starting point is not more than the lower limit of the failure oscillation interval, the upper limit of the failure oscillation interval is the target temperature, the target temperature is the steady-state temperature corresponding to the target frequency point under the current environment temperature, the target frequency point is the highest frequency point in the frequency point corresponding to the steady-state temperature lower than the maximum temperature under the current environment temperature, i is greater than or equal to 1, and the first width is 0, the ith width is less than the ith+1 width;

[0009] It is monitored whether the current chip temperature exceeds the target temperature in the ith test stage.

[0010] If the current chip temperature exceeds the target temperature, i is set to i+1, and the i-th test is repeated;

[0011] If the current chip temperature does not exceed the target temperature, the i-th width is determined as the target width of the failure oscillation interval, and the lower limit of the failure oscillation interval is determined.

[0012] In a second aspect, an embodiment of the present application provides a temperature control method, which comprises:

[0013] When the current chip temperature is lower than an effective temperature starting point, the processor keeps running at the highest frequency point supported by the processor, wherein the effective temperature starting point is a temperature starting point at which an error integral temperature control strategy is effective under the current environmental temperature, the effective temperature starting point is lower than a target temperature, the target temperature is a steady-state temperature corresponding to a target frequency point under the current environmental temperature, and the target frequency point is the highest frequency point among frequency points corresponding to steady-state temperatures lower than a maximum temperature under the current environmental temperature;

[0014] When the current chip temperature reaches the effective temperature starting point, an error integral temperature control strategy is executed based on a failure oscillation target interval to obtain a current frequency point corresponding to the current chip temperature;

[0015] The failure oscillation target interval is obtained based on the failure oscillation interval determination method described above.

[0016] The current frequency point is used as the running frequency point of the processor in the current period.

[0017] In a third aspect, an embodiment of the present application provides a failure oscillation interval determination device, which comprises:

[0018] A first processing unit is configured to, in an i-th test stage, set the width of the failure oscillation interval as an i-th width, acquire the current chip temperature of the processor at a preset period interval, execute an error integral temperature control strategy to obtain a current frequency point corresponding to the current chip temperature if the current chip temperature reaches an effective temperature starting point, and use the current frequency point as the running frequency point of the processor in the current period.

[0019] The effective temperature starting point is a temperature starting point at which an error integral temperature control strategy is effective under the current environmental temperature, the effective temperature starting point is not higher than the lower limit of the failure oscillation interval, the upper limit of the failure oscillation interval is a target temperature, the target temperature is a steady-state temperature corresponding to a target frequency point under the current environmental temperature, the target frequency point is the highest frequency point among frequency points corresponding to steady-state temperatures lower than a maximum temperature under the current environmental temperature, i is greater than or equal to 1, the first width is 0, and the i-th width is less than the (i+1)-th width.

[0020] The first processing unit is further configured to monitor whether the current chip temperature exceeds the target temperature in the ith test stage; if the current chip temperature exceeds the target temperature, setting i = i + 1 and repeating the ith test.

[0021] The second processing unit is configured to determine the target width of the failure oscillation interval as the ith width if the current chip temperature does not exceed the target temperature, and further determine the lower limit of the failure oscillation interval.

[0022] In a fourth aspect, an embodiment of the present application provides a storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described above.

[0023] In a fifth aspect, an embodiment of the present application provides an electronic device, which includes a processor and a memory configured to store one or more programs; when the one or more programs are executed by the processor, the method described above is implemented.

[0024] Compared with the prior art, the method for determining a failure oscillation interval and the temperature control method and related device provided by the embodiment of the present application set the width of the failure oscillation interval as the ith width in the ith test stage, acquire the current chip temperature of the processor at a preset period interval, execute an error integral temperature control strategy if the current chip temperature reaches the effective temperature starting point, to obtain the current frequency point corresponding to the current chip temperature, and set the current frequency point as the running frequency of the processor in the current period; monitor whether the current chip temperature exceeds the target temperature in the ith test stage; if the current chip temperature does not exceed the target temperature, determine the target width of the failure oscillation interval as the ith width, and further determine the lower limit of the failure oscillation interval. The failure oscillation interval when the error integral temperature control strategy is executed is determined, so that the update of the integral error is stopped when the chip temperature is in the failure oscillation interval, the adjustment range of the temperature is changed, and the chip temperature is prevented from oscillating around the target temperature or the oscillation range is reduced.

[0025] In order to make the above objectives, features and advantages of the present application more apparent, the following will describe preferred embodiments in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as a limitation to the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0027] Figure 1 A structural schematic diagram of an electronic device provided by an embodiment of the present application.

[0028] Figure 2 A flowchart of a failure oscillation interval determination method provided by an embodiment of the present application.

[0029] Figure 3 A flowchart of a temperature control method provided by an embodiment of the present application.

[0030] Figure 4 A unit schematic diagram of a failure oscillation interval determination device provided by an embodiment of the present application.

[0031] In the figure: 10-processor; 11-memory; 12-bus; 13-communication interface; 601-first processing unit; 602-second processing unit. DETAILED DESCRIPTION

[0032] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0034] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. Meanwhile, in the description of the present application, the terms “first”, “second” and the like are only used to distinguish description, and cannot be understood as indicating or implying relative importance.

[0035] It should be pointed out that in this article, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitation, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or equipment including the element.

[0036] In the description of the present application, it should be pointed out that the orientation or position relationship indicated by the terms "upper", "lower", "inner", "outer" and the like is based on the orientation or position relationship shown in the drawings, or the orientation or position relationship commonly placed when the product of the application is used, only for the convenience of describing the application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application.

[0037] In the description of the present application, it should be further pointed out that unless otherwise explicitly specified and limited, the terms "arrangement", "connection" should be understood broadly, for example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0038] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following examples and features in the examples can be combined with each other without conflict.

[0039] The electronic device provided by the embodiments of the present application can be a mobile phone device, a tablet computer device, a notebook computer device, a desktop computer device, etc. Please refer to Figure 1 , a structural schematic diagram of the electronic device. The electronic device includes a processor 10, a memory 11, and a bus 12. The processor 10 and the memory 11 are connected through the bus 12, and the processor 10 is used to execute the executable modules stored in the memory 11, such as computer programs.

[0040] The processor 10 can be an integrated circuit chip with signal processing capability. In implementation, the steps of the failure oscillation interval determination method and the temperature control method can be completed by integrated logic circuits of hardware in the processor 10 or instructions in the form of software. The processor 10 described above can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; or can be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0041] The memory 11 can include a high-speed random access memory (RAM), and can also include a non-volatile memory, such as at least one disk memory.

[0042] The bus 12 can be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, etc. Figure 1 Only one bidirectional arrow is used to represent the bus 12, but it does not mean that there is only one bus 12 or only one type of bus 12.

[0043] The memory 11 is used to store programs, such as programs corresponding to the failure oscillation interval determination device and the temperature control device. The failure oscillation interval determination device and the temperature control device include at least one software function module that can be stored in the memory 11 in the form of software or firmware or solidified in an operating system (OS) of the electronic device. After receiving an execution instruction, the processor 10 executes the programs to implement the failure oscillation interval determination method and the temperature control method.

[0044] Possibly, the electronic device provided by the embodiment of the present application further includes a communication interface 13. The communication interface 13 is connected with the processor 10 through the bus.

[0045] It should be understood that, Figure 1The structure shown is only a partial schematic diagram of the electronic device; the electronic device may also include components that are larger than... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown. Figure 1 The components shown can be implemented using hardware, software, or a combination thereof.

[0046] The method for determining the failure oscillation range provided in this embodiment of the invention can be applied to, but is not limited to, [various applications]. Figure 1 For the specific process of the electronic devices shown, please refer to [link / reference]. Figure 2 The methods for determining the failure oscillation range include S10, S20, S30, and S40, which are explained in detail below.

[0047] S10, in the i-th test phase, the width of the failure oscillation interval is set to the i-th width, and the current chip temperature of the processor is obtained according to the preset period interval. If the current chip temperature reaches the effective temperature starting point, the error integral temperature control strategy is executed to obtain the current frequency point corresponding to the current chip temperature, and the current frequency point is used as the operating frequency point of the processor in the current period.

[0048] The effective temperature start point is the temperature start point at which the error integral temperature control strategy takes effect under the current ambient temperature (different ambient temperatures correspond to different effective temperature start points). The effective temperature start point does not exceed the lower limit of the failure oscillation range. The upper limit of the failure oscillation range is the target temperature. The target temperature is the steady-state temperature corresponding to the target frequency point under the current ambient temperature. The target frequency point is the highest frequency point among the frequency points whose corresponding steady-state temperature is lower than the maximum temperature under the current ambient temperature. i is greater than or equal to 1, and the first width is 0. The i-th width is less than the (i+1)-th width. The (i+1)-th width = the preset width difference. The preset width difference can be 1°.

[0049] When the current chip temperature reaches the effective starting temperature, the error integral temperature control strategy is executed. It does not wait until the temperature reaches the target temperature to start the temperature control strategy. This avoids the processor's temperature from exceeding the target temperature significantly due to the lag in temperature regulation caused by the late intervention of temperature control. It ensures that the processor can maintain high power consumption while the temperature is within a safe range, thus ensuring the processor's high performance.

[0050] S20: Monitor whether the current chip temperature exceeds the target temperature during the i-th test phase. If the current chip temperature exceeds the target temperature, proceed to S30; otherwise, proceed to S40.

[0051] S30, let i=i+1.

[0052] After S30, the ith width can be determined, and then the ith test is repeated, that is, in the ith test stage, the width of the invalid oscillation interval is set as the ith width, the current chip temperature of the processor is acquired according to the preset period interval, if the current chip temperature reaches the effective temperature starting point, the error integral temperature control strategy is executed to obtain the current frequency point corresponding to the current chip temperature, and the current frequency point is taken as the running frequency of the processor in the current period.

[0053] In S40, the ith width is determined as the target width of the invalid oscillation interval, and the lower limit of the invalid oscillation interval is determined.

[0054] In the embodiment of the application, the invalid oscillation interval when the error integral temperature control strategy is executed is determined, so that when the chip temperature is in the invalid oscillation interval, the updating of the integral error is stopped, the adjustment range of the temperature is changed, and the chip temperature is prevented from oscillating around the target temperature or the oscillation range is reduced.

[0055] In an optional embodiment, the invalid oscillation interval determination method further includes: in the ith test stage, if the current chip temperature is lower than the effective temperature starting point, the processor keeps running at the highest frequency point supported by the processor.

[0056] On the basis of the foregoing, regarding the content in S10, the embodiment of the application further provides an optional embodiment, please refer to the following. The error integral temperature control strategy is executed to obtain the current frequency point corresponding to the current chip temperature, including S101, S102, S103, S104 and S106, which are specifically described as follows.

[0057] In S101, the current temperature difference and the proportional term factor are determined according to the target temperature and the current chip temperature.

[0058] The current temperature difference = target temperature - current chip temperature, and the proportional term factor = (target temperature - current chip temperature) * proportional parameter.

[0059] Suppose that the proportional parameter is 200, the target temperature is 85 degrees, and the current temperature is 82 degrees, then the proportional term factor is (85-82) * 200 = 600. Then the proportional term matching power consumption after calculation is: (85-82) * 200 = 600 mW.

[0060] In S102, it is determined whether the current chip temperature is in the invalid oscillation interval. If the current chip temperature is in the invalid oscillation interval, S103 is executed; if the current chip temperature is not in the invalid oscillation interval, S104 is executed.

[0061] In S103, the current temperature difference is set as 0.

[0062] In S104, the historical integral error is accumulated according to the current temperature difference to obtain the current integral error.

[0063] Wherein, the history integral error is the integral error obtained at the last temperature measurement, and the first integral error after the current chip temperature reaches the starting point of the current effective temperature is the current temperature difference, i.e. the temperature difference between the target temperature and the current chip temperature at this time.

[0064] The current integral error = the history integral error + the current temperature difference. The history integral error is 0 when the first current integral error is obtained after the current chip temperature reaches the starting point of the current effective temperature.

[0065] After S103, S104 is also executed.

[0066] S106, determining the current frequency point according to the current integral error, the proportional term factor and the target power consumption; wherein, the target power consumption is the matching power consumption corresponding to the target frequency point.

[0067] In an optional embodiment, after the history integral error is accumulated according to the current temperature difference to obtain the current integral error, the error integral temperature control strategy is executed to obtain the current frequency point corresponding to the current chip temperature, which further comprises S105, as follows.

[0068] S105, determining whether the current integral error exceeds the integral error range, if yes, adjusting the current integral error to make it within the integral error range, if not, the current integral error does not need to be adjusted.

[0069] When the current integral error is less than the lower boundary of the integral error range, the lower boundary of the integral error range is taken as the current integral error; when the current integral error is greater than the upper boundary of the integral error range, the upper boundary of the integral error range is taken as the current integral error, so as to make it within the integral error range. If the current integral error is not adjusted, the integral accumulation may be too much, resulting in the situation that the system temperature power consumption is too low and the temperature is controlled too high at once. In the embodiment of the present application, the integral error range control is introduced to prevent the control overshoot problem caused by excessive integral accumulation, reduce the temperature overshoot and reduce the safety risk.

[0070] On the basis of the foregoing, as to the content of S106, the embodiment of the present application further provides an optional embodiment, S106, determining the current frequency point according to the current integral error, the proportional term factor and the target power consumption, comprising S106-1, S106-2 and S106-3, which are specifically described as follows.

[0071] S106-1, obtaining the error matching power consumption corresponding to the current integral error.

[0072] S106-2, obtaining the proportional term matching power consumption corresponding to the proportional term factor.

[0073] S106-3, determining the current frequency point according to the target power consumption, the error matching power consumption and the proportional term matching power consumption.

[0074] Optionally, the target power consumption, the error matching power consumption and the proportional term matching power consumption are obtained as total power consumption, and then the total power consumption is subtracted by the system static power consumption value to obtain dynamic power consumption, and the dynamic power consumption is compared with the corresponding power consumption of each supported frequency point to find a maximum frequency point with power consumption less than the dynamic power consumption as the current frequency point.

[0075] The temperature control method provided by the embodiment of the application can be applied to, but is not limited to, the electronic device shown in the accompanying drawings. Figure 1 The specific flow of the electronic device is shown in the accompanying drawings, and the temperature control method includes S51, S52 and S53, which are specifically described as follows. Figure 3

[0076] S51, when the current chip temperature is lower than the effective temperature starting point, the processor keeps running at the highest frequency point supported by the processor, wherein the effective temperature starting point is a temperature starting point of the error integral temperature control strategy at the current environment temperature, the effective temperature starting point is lower than the target temperature, the target temperature is a steady-state temperature corresponding to the target frequency point at the current environment temperature, and the target frequency point is the highest frequency point in the frequency points corresponding to the steady-state temperature lower than the maximum temperature at the current environment temperature.

[0077] In the low-temperature stage, the highest frequency point is directly run, and performance inhibition does not occur in the temperature rising stage, so that the best power consumption and the best performance are maintained.

[0078] S52, when the current chip temperature reaches the effective temperature starting point, the error integral temperature control strategy is executed based on the invalid oscillation target interval to obtain the current frequency point corresponding to the current chip temperature.

[0079] The invalid oscillation target interval is the invalid oscillation interval obtained based on the invalid oscillation interval determination method.

[0080] S53, the current frequency point is taken as the running frequency point of the processor in the current period.

[0081] Optionally, S52, when the current chip temperature reaches the effective temperature starting point, the error integral temperature control strategy is executed based on the invalid oscillation target interval to obtain the current frequency point corresponding to the current chip temperature, and S521 to S526 are included, which are specifically described as follows.

[0082] S521, the current temperature difference and the proportional term factor are determined according to the target temperature and the current chip temperature.

[0083] The current temperature difference = the target temperature - the current chip temperature, and the proportional term factor = (the target temperature - the current chip temperature) * the proportional parameter.

[0084] ​S522, determining whether the current chip temperature is in the failure oscillation target interval; if the current chip temperature is in the failure oscillation target interval, S523 is executed; if the current chip temperature is not in the failure oscillation target interval, S524 is executed.

[0085] S523, setting the current temperature difference as 0.

[0086] S524, accumulating the historical integral error according to the current temperature difference to obtain a current integral error.

[0087] The historical integral error is the integral error obtained at the last temperature measurement, and the first integral error after the current chip temperature reaches the starting point of the current effective temperature is the current temperature difference at this time, that is, the temperature difference between the target temperature and the current chip temperature at this time.

[0088] The current integral error = the historical integral error + the current temperature difference. The historical integral error when the current integral error is obtained for the first time after the current chip temperature reaches the starting point of the current effective temperature is 0.

[0089] After S523, S524 is also executed.

[0090] S525, determining whether the current integral error exceeds the integral error range; if it exceeds, adjusting the current integral error to be within the integral error range; if it does not exceed, the current integral error does not need to be adjusted.

[0091] S526, determining the current frequency point according to the current integral error, the proportional term factor and the target power consumption; wherein the target power consumption is the matching power consumption corresponding to the target frequency point.

[0092] Please refer to Figure 4 , Figure 4 The failure oscillation interval determination device and the temperature control device provided by the embodiment of the application can be applied to the electronic device described above.

[0093] The failure oscillation interval determination device comprises a first processing unit 601 and a second processing unit 602.

[0094] The first processing unit 601 is configured to set the width of the failure oscillation interval as the i-th width in the i-th test stage, acquire the current chip temperature of the processor at a preset period interval, execute the error integral temperature control strategy if the current chip temperature reaches the starting point of the effective temperature, to obtain the current frequency point corresponding to the current chip temperature, and set the current frequency point as the running frequency point of the processor in the current period.

[0095] Wherein, the effective temperature starting point is a temperature starting point of the error integral temperature control strategy, the effective temperature starting point is not more than the lower limit of the invalid oscillation interval, the upper limit of the invalid oscillation interval is the target temperature, the target temperature is a steady-state temperature corresponding to the target frequency point at the current environment temperature, the target frequency point is the highest frequency point in the frequency point corresponding to the steady-state temperature lower than the maximum temperature at the current environment temperature, i is greater than or equal to 1, and the first width is 0, and the ith width is less than the (i+1)th width.

[0096] The first processing unit 601 is further configured to monitor whether the current chip temperature exceeds the target temperature in the ith test stage; if the current chip temperature exceeds the target temperature, i is set to i+1, and the ith test is repeated.

[0097] The second processing unit 602 is configured to determine the ith width as the target width of the invalid oscillation interval if the current chip temperature does not exceed the target temperature, and further determine the lower limit of the invalid oscillation interval.

[0098] Optionally, the first processing unit 601 can perform other steps in the above method embodiments.

[0099] It should be noted that the invalid oscillation interval determination apparatus provided in the embodiment can perform the method processes shown in the above method process embodiments to achieve the corresponding technical effects. For brevity, the part of the embodiment not mentioned in the above embodiments can be referred to the corresponding content in the above embodiments.

[0100] The embodiment of the present application further provides a storage medium storing computer instructions and programs, which perform the invalid oscillation interval determination method and the temperature control method of the above embodiments when read and run. The storage medium can include memory, flash memory, register or combination thereof.

[0101] The following provides an electronic device, which can be a mobile phone device, a tablet computer device, a notebook computer device, a desktop computer device and the like. The electronic device can implement the invalid oscillation interval determination method and the temperature control method as shown in the above embodiments. Figure 1 Specifically, the electronic device includes a processor 10, a memory 11 and a bus 12. The processor 10 can be a CPU. The memory 11 is configured to store one or more programs, which perform the invalid oscillation interval determination method and the temperature control method of the above embodiments when executed by the processor 10.

[0102] In summary, the method for determining the failure oscillation interval, the temperature control method and the related device provided by the embodiments of the present application set the width of the failure oscillation interval as the ith width in the ith test stage, obtain the current chip temperature of the processor according to the preset period interval, execute the error integral temperature control strategy if the current chip temperature reaches the effective temperature starting point, to obtain the current frequency point corresponding to the current chip temperature, and take the current frequency point as the running frequency of the processor in the current period; monitor whether the current chip temperature exceeds the target temperature in the ith test stage; if the current chip temperature does not exceed the target temperature, determine the ith width as the target width of the failure oscillation interval, and further determine the lower limit of the failure oscillation interval. The failure oscillation interval when the error integral temperature control strategy is executed is determined, so that the integral error is stopped from being updated when the chip temperature is in the failure oscillation interval, so as to change the adjustment range of the temperature, avoid the chip temperature from oscillating around the target temperature, or reduce the oscillation range.

[0103] The preferred embodiments of the present application have been described above with the preferred embodiments, but the present application is not limited to the above description, and various modifications and changes can be made by those skilled in the art without departing from the spirit and principles of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

[0104] It is obvious for those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting, and the scope of the present application is defined by the appended claims rather than the above description, and all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present application. Any reference signs in the claims should not be regarded as limiting the claims.

Claims

1. A method for determining a failure oscillation interval, characterized in that The method comprises: In the ith test stage, the width of the invalid oscillation interval is set as the ith width, the current chip temperature of the processor is obtained according to a preset period interval, if the current chip temperature reaches the effective temperature starting point, an error integral temperature control strategy is executed to obtain a current frequency point corresponding to the current chip temperature, and the current frequency point is taken as the running frequency point of the processor in the current period. The effective temperature starting point is a temperature starting point at which the error integral temperature control strategy is effective under the current environment temperature, the effective temperature starting point is not higher than the lower limit of the invalid oscillation interval, the upper limit of the invalid oscillation interval is a target temperature, the target temperature is a steady-state temperature corresponding to a target frequency point under the current environment temperature, the target frequency point is the highest frequency point in the frequency points corresponding to the steady-state temperature lower than the maximum temperature under the current environment temperature, i is greater than or equal to 1, the first width is 0, and the ith width is less than the (i+1)th width. It is monitored whether the current chip temperature exceeds the target temperature in the ith test stage. If the current chip temperature exceeds the target temperature, i is set as i+1, and the ith test is repeated. If the current chip temperature does not exceed the target temperature, the ith width is determined as the target width of the invalid oscillation interval, and the lower limit of the invalid oscillation interval is determined.

2. The failure oscillation band determination method according to claim 1, wherein The method comprises: In the ith test stage, if the current chip temperature is lower than the effective temperature starting point, the processor keeps running at the highest frequency point supported by the processor.

3. The failure oscillation range determination method according to claim 1, wherein The execution of the error integral temperature control strategy to obtain the current frequency point corresponding to the current chip temperature comprises: A current temperature difference and a proportional term factor are determined according to the target temperature and the current chip temperature. It is determined whether the current chip temperature is in the invalid oscillation interval. If the current chip temperature is in the invalid oscillation interval, the current temperature difference is set as 0. If the current chip temperature is not in the invalid oscillation interval, a historical integral error is accumulated according to the current temperature difference to obtain a current integral error. A current frequency point is determined according to the current integral error, the proportional term factor and a target power consumption, wherein the target power consumption is a matching power consumption corresponding to a target frequency point. The current frequency point is taken as the running frequency point of the processor in the current period.

4. The failure oscillation band determination method according to claim 3, wherein After the historical integral error is accumulated according to the current temperature difference to obtain the current integral error, the execution of the error integral temperature control strategy to obtain the current frequency point corresponding to the current chip temperature further comprises: It is determined whether the current integral error exceeds an integral error range, if yes, the current integral error is adjusted to be in the integral error range, and if no, the current integral error does not need to be adjusted.

5. The failure oscillation band determination method according to claim 3, wherein The determination of the current frequency point according to the current integral error, the proportional term factor and the target power consumption comprises: An error matching power consumption corresponding to the current integral error is obtained. A proportional term matching power consumption corresponding to the proportional term factor is obtained. The current frequency point is determined according to the target power consumption, the error matching power consumption and the proportional term matching power consumption.

6. A temperature control method characterized by, The method comprises: When the current chip temperature is lower than an effective temperature starting point, the processor keeps running at a highest frequency point supported by the processor, wherein the effective temperature starting point is a temperature starting point at which an error integral temperature control strategy is effective at a current environment temperature, the effective temperature starting point is lower than a target temperature, the target temperature is a steady-state temperature corresponding to a target frequency point at the current environment temperature, and the target frequency point is a highest frequency point among frequency points corresponding to steady-state temperatures lower than a maximum temperature at the current environment temperature; When the current chip temperature reaches the effective temperature starting point, an error integral temperature control strategy is executed based on a failure oscillation target interval to obtain a current frequency point corresponding to the current chip temperature; The failure oscillation target interval is determined based on the failure oscillation interval determination method in any one of claims 1-5. The current frequency point is used as a running frequency point of the processor in a current period.

7. A failure oscillation range determination apparatus characterized by comprising: The apparatus comprises: A first processing unit configured to, in an ith test stage, set a width of a failure oscillation interval as an ith width, obtain a current chip temperature of the processor at a preset period interval, and execute an error integral temperature control strategy if the current chip temperature reaches an effective temperature starting point to obtain a current frequency point corresponding to the current chip temperature, and use the current frequency point as a running frequency point of the processor in a current period. The effective temperature starting point is a temperature starting point at which the error integral temperature control strategy is effective at a current environment temperature, the effective temperature starting point is not higher than a lower limit of the failure oscillation interval, an upper limit of the failure oscillation interval is a target temperature, the target temperature is a steady-state temperature corresponding to a target frequency point at the current environment temperature, the target frequency point is a highest frequency point among frequency points corresponding to steady-state temperatures lower than a maximum temperature at the current environment temperature, i is greater than or equal to 1, the first width is 0, and the ith width is less than an (i+1)th width. The first processing unit is further configured to monitor whether the current chip temperature exceeds the target temperature in the ith test stage, and if the current chip temperature exceeds the target temperature, set i=i+1 and repeat the ith test. A second processing unit configured to, if the current chip temperature does not exceed the target temperature, determine the ith width as a target width of the failure oscillation interval, and further determine a lower limit of the failure oscillation interval.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the method in any one of claims 1-6.

9. An electronic device, comprising: The apparatus comprises: A processor and a memory configured to store one or more programs; When the one or more programs are executed by the processor, the method in any one of claims 1-6 is implemented.

Images