Main bare chip and test method
The PTAP-STAP architecture solves the problems of pin resource overhead and design difficulty in chip packaging, achieves efficient test mode compatibility and shortens the test link, thus improving test efficiency.
Patent Information
- Application Number
- CN202410572807.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-09
- Publication Date
- 2025-11-11
Smart Images
Figure CN120929314A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and more particularly to a master die and a testing method. Background Technology
[0002] In design for testability (DFT), the commonly used test interface is the Joint Test Action Group (JTAG). JTAG includes multiple pins such as test clock input (TCK), test mode selection input (TMS), test data input (TDI), test data output (TDO), and test reset input (TRST). During testing, the chip can use JTAG to control the internal test access port (TAP) state machine. The chip can also control the test configuration inputs and test result observations for the memory built-in self-test (MBIST) and intellectual property core (IP).
[0003] However, for chiplets, each die contains a JTAG TAP state machine. If the JTAG pins of each die are routed out of the package, it would incur significant package pin resource overhead. Furthermore, some dies are not directly connected to the external network; the JTAG pins of these dies cannot be directly routed out of the package and must be connected to package pins via other dies, which increases the design complexity of those other dies. Summary of the Invention
[0004] This application provides a master die and a testing method that reduces the number of die packaging pins, shortens the testing chain, reduces testing time, and improves testing efficiency.
[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions.
[0006] In a first aspect, embodiments of this application provide a master die, which includes a main test access port (PTAP), a first auxiliary test access port (STAP), and a second STAP. The first STAP is coupled to a first slave die, and the second STAP is coupled to the second slave die. The PTAP includes an input selection circuit and an output selection circuit. The test data input (TDI) port of the PTAP is coupled to the TDI port of the first STAP. The TDI port of the PTAP is also coupled to a first data input terminal of the input selection circuit. The second data input terminal of the input selection circuit is coupled to a test data output (TDO) port of the first STAP. The output terminal of the input selection circuit is coupled to the TDI port of the second STAP. The TDO port of the first STAP is coupled to the first data input terminal of the output selection circuit. The TDO port of the second STAP is coupled to the second data input terminal of the output selection circuit. The output terminal of the output selection circuit is coupled to the TDO port of the PTAP. The output selection circuit is used to select the output test result of the first STAP or the output test result of the second STAP for output.
[0007] Therefore, the main die provided in this application adopts a PTAP-STAP architecture, which can be connected to the outside only through the pins of the PTAP, reducing the number of package pins of the die. The second STAP can be coupled to the TDI port of the PTAP through an input selection circuit, and the first STAP is coupled to the TDI port of the PTAP. Thus, the input test data of the first STAP and the second STAP can come from the same source. This method can be called broadcast mode. This method does not require clamping logic design, reducing design difficulty. The second STAP can also be coupled to the TDO port of the first STAP through an input selection circuit, that is, the main die is also compatible with non-broadcast mode, improving the applicability of the main die. In addition, the output selection circuit of the PTAP can select one of the output test results of the first STAP and the second STAP for output. Compared with the serial output of the output test results, it can shorten the test link, reduce the test configuration time, and improve the test efficiency.
[0008] In one possible design, the PTAP also includes a first register for storing a first value that indicates whether the master die is configured for broadcast or non-broadcast mode. Thus, by configuring the first register, the master die can be made compatible with both broadcast and non-broadcast modes, improving its applicability.
[0009] In one possible design, the control terminal of the input selection circuit is coupled to the output terminal of the first register. The input selection circuit controls the input test data of the PTAP's TDI port to be transmitted to the TDI port of the second STAP when the main die is configured in broadcast mode, and controls the output test data of the first STAP's TDO port to be transmitted to the TDI port of the second STAP when the main die is configured in non-broadcast mode. Thus, when the main die is configured in broadcast mode, the input test data received by the PTAP's TDI port is transmitted to the TDI port of the second STAP. Consequently, the input test data of the first and second STAPs originate from the same source, eliminating the need for clamping logic design and reducing design complexity.
[0010] In one possible design, the PTAP also includes a first multiplexer circuit, and the output selection circuit includes a second multiplexer and a third multiplexer. The first data input of the first multiplexer is coupled to the TDI port of the PTAP, the second data input of the first multiplexer is coupled to the TDO port of the second STAP, and the output of the first multiplexer is coupled to the first data input of the second multiplexer. The second data input of the second multiplexer is coupled to the TDO port of the first STAP, and the output of the second multiplexer is coupled to the first data input of the third multiplexer. The second data input of the third multiplexer is coupled to the TDO port of the second STAP, and the output of the third multiplexer is coupled to the TDO port of the PTAP. Therefore, by using the first, second, and third multiplexers, multiple output test results can be selected for output, enabling parallel testing of multiple slave dies and improving testing efficiency. Furthermore, when a slave die is not being tested, the test link can be shortened, reducing test time.
[0011] In one possible design, the PTAP also includes a second register, a third register, a first AND gate, and a second AND gate. The first input of the first AND gate is coupled to the output of the first register; the second input of the first AND gate is coupled to the output of the second register; and the output of the first AND gate is coupled to the control terminal of the second multiplexer. The first input of the second AND gate is coupled to the output of the first register; the second input of the second AND gate is coupled to the output of the third register; and the output of the second AND gate is coupled to the control terminal of the third multiplexer.
[0012] In one possible design, the second register stores a second value indicating whether the TDO ports of the first STAP and PTAP are on or off. The third register stores a third value indicating whether the TDO ports of the second STAP and PTAP are on or off. Thus, the second and third registers, the first AND gate, and the second AND gate enable the main die to be compatible with both broadcast and non-broadcast modes, improving the main die's applicability.
[0013] In one possible design, the PTAP also includes a fourth register, a fifth register, and an OR gate. The first input of the OR gate is coupled to the output of the fourth register, the second input of the OR gate is coupled to the output of the fifth register, and the output of the OR gate is coupled to the control terminal of the first multiplexer. The fourth register stores a fourth value, which indicates whether the first STAP is in test or idle state. The fifth register stores a fifth value, which indicates whether the second STAP is in test or idle state. Therefore, the state of the STAP can be configured according to test requirements through the fourth and fifth registers, reducing test time and improving test efficiency.
[0014] Secondly, embodiments of this application also provide a testing method applied to a master die, the master die including a PTAP and at least one STAP, each STAP coupled to a slave die. The method includes: when the master die is configured in broadcast mode, the PTAP sends input test data to the at least one STAP. The at least one STAP sends the received input test data to the slave die. The at least one STAP receives output test data from the slave die, the output test data being derived based on the input test data. A first STAP sends the output test data to the PTAP, and the PTAP selects one output test data from the at least one output test data and outputs it.
[0015] Therefore, the testing method provided in this application adopts a PTAP-STAP architecture, which reduces the number of chip packaging pins. When the main die is configured in broadcast mode, input test data can be sent to each STAP. Thus, the input test data of the STAPs can come from the same source, eliminating the need for clamping logic design and reducing design complexity. In addition, when the die is in the test state, output test data can be sent directly to the PTAP to shorten the test chain and reduce test time.
[0016] In one possible design, the method further includes setting a first value stored in a first register of the master die to a first level, the first level being used to indicate that the master die is configured in broadcast mode.
[0017] In one possible design, at least one STAP includes a first STAP and a second STAP. The method further includes: when the PTAP selects the first STAP to output test data, setting a second value stored in a second register of the main die to a second level, the second level being used to indicate that the TDO port of the first STAP and the TDO port of the PTAP are on. When the PTAP selects the second STAP to output test data, setting a third value stored in a third register of the main die to a third level, the third level being used to indicate that the TDO port of the second STAP and the TDO port of the PTAP are on.
[0018] In one possible design, the method further includes: when testing the slave die corresponding to the first STAP, setting the fourth value stored in the fourth register of the master die to a fourth level, the fourth level being used to indicate that the first STAP is in a test state. When testing the slave die corresponding to the second STAP, setting the fifth value stored in the fifth register of the master die to a fifth level, the fifth level being used to indicate that the second STAP is in a test state.
[0019] Thirdly, embodiments of this application provide a chip packaging structure, which includes a first slave die, a second slave die, an interconnect structure, and a master die in the first aspect. The first slave die is coupled to a first STAP, and the second slave die is coupled to a second STAP.
[0020] Fourthly, embodiments of this application provide an electronic device, which includes a chip packaging structure and a printed circuit board as described in the third aspect, wherein the chip packaging structure is disposed on the printed circuit board.
[0021] Fifthly, embodiments of this application provide a computer-readable storage medium including computer instructions that, when executed on an electronic device, cause the electronic device to perform the test method in any of the possible implementations of the second aspect described above.
[0022] In a sixth aspect, embodiments of this application provide a computer program product that, when run on a computer or processor, causes the computer or processor to execute the test method in any of the possible implementations of the second aspect described above.
[0023] It is understood that any of the main die, chip package structure, electronic device, computer-readable storage medium or computer program product provided above can be applied to the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects in the corresponding methods, and will not be repeated here.
[0024] These or other aspects of this application will become more readily apparent in the following description. Attached Figure Description
[0025] Figure 1 A schematic diagram of the connection of a 2D / 2.5D chip provided in an embodiment of this application;
[0026] Figure 2 A schematic diagram of another 2D / 2.5D chip connection provided for an embodiment of this application;
[0027] Figure 3 This is a schematic diagram of the connection of a 3D chip provided in an embodiment of this application;
[0028] Figure 4 This application provides a schematic diagram of the connection of a core chip in an embodiment.
[0029] Figure 5 A structural diagram of STAP control logic provided in an embodiment of this application;
[0030] Figure 6 A schematic diagram of a PTAP-STAP structure of a main die provided in this application embodiment;
[0031] Figure 7 A test configuration diagram of a core chip provided in an embodiment of this application;
[0032] Figure 8 A test configuration diagram of another core chip provided in an embodiment of this application;
[0033] Figure 9 This is a schematic diagram of the structure of a master die provided in an embodiment of this application;
[0034] Figure 10 This is a schematic diagram of another main die structure provided in an embodiment of this application;
[0035] Figure 11 This is a schematic diagram of another main die provided in an embodiment of this application;
[0036] Figure 12 A test configuration diagram of another core chip provided in an embodiment of this application;
[0037] Figure 13 A flowchart of a testing method provided in an embodiment of this application. Detailed Implementation
[0038] For ease of understanding, the examples provide explanations of some concepts related to the embodiments of this application for reference. As shown below:
[0039] 1. JTAG pin definition in IEEE 1149.1 standard
[0040] (1) TCK provides an independent, basic clock signal for the operation of TAP, which can drive all operations of TAP.
[0041] (2) TMS, which is active on the rising edge of TCK, can be used to control the transitions of the TAP state machine. Specifically, the TMS signal can be used to control the transitions between different states of the TAP.
[0042] (3) TDI, the data input interface. Under the drive of TCK, data can be serially input into a specific register bit by bit through the TDI interface.
[0043] (4) TDO, the data output interface. Under the drive of TCK, data can be serially output bit by bit from a specific register through the TDO interface.
[0044] (5) TRST, also known as TRSTN, is an optional interface in the IEEE 1149.1 standard and can be used to reset (initialize) the TAP controller. Alternatively, the TAP controller can also be reset (initialized) through TMS.
[0045] 2. 2D / 2.5D chip - daisy chain connection method
[0046] For 2D / 2.5D chips, multiple dies can be connected in a daisy-chain configuration. The TCK, TRSTN, and TMS can be designed as a single-drive-multiple-die system within the interconnect structure (e.g., the package substrate or interposer), with the TDI to TDO pathways connected between the dies. For example... Figure 1 As shown, Figure 1 The diagram illustrates a 2D / 2.5D chip, which may include an interconnect structure and two dies (e.g., Die1 and Die2). The 2D / 2.5D chip is externally connected via JTAG pins (e.g., TDI, TMS, TCK, TRSTN, and TDO) of the interconnect structure. Certain JTAG pins (e.g., TMS, TCK, and TRSTN) of the TAP of Die1 and certain JTAG pins (e.g., TMS, TCK, and TRSTN) of the TAP of Die2 are connected to the JTAG pins of the interconnect structure. Furthermore, the TDI pins of the interconnect structure are connected to the TDI pins of the TAP of Die1, the TDO pins of the TAP of Die1 are connected to the TDI pins of the TAP of Die2, and the TDO pins of the TAP of Die2 are connected to the TDO pins of the interconnect structure.
[0047] 3. 2D / 2.5D chip - IEEE1838 connection method
[0048] Besides using a daisy-chain connection, the serial test access ports (STAP) structure in the IEEE 1838 standard can also be used. For example... Figure 2 As shown, that is, the master die (such as...) Figure 2 Die1 in the middle) is controlled by STAP from the bare die (such as Figure 2 The TAPs in Die2 and Die3 are connected externally from a set of JTAGs (e.g., TDI, TMS, TCK, TRSTN, and TDO). Specifically, Die1 includes the primary test access port (PTAP), STAP_2, and STAP_3. PTAP is coupled to STAP_2 and STAP_3 respectively. STAP_2 is coupled to the TAP in Die2 through an interconnect structure, and STAP_3 is coupled to the TAP in Die3 through an interconnect structure.
[0049] In addition, for 3D chips, such as Figure 3 As shown, the test control interface can also adopt the STAP structure of the IEEE 1838 standard. Specifically, the 3D chip can include Die1, Die2, Die3, and Die4, where Die1 and Die2 are stacked in 3D, and Die1 and Die3 are also stacked in 3D. Die1 is the master Die, and Die2, Die3, and Die4 are slave Dies. Die1 includes PTAP, STAP_2, and STAP_3. PTAP is coupled to TAP in Die4, STAP_2 is coupled to PTAP in Die2, and STAP_3 is coupled to PTAP in Die3.
[0050] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; "and / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.
[0051] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this embodiment, unless otherwise stated, "a plurality of" means two or more.
[0052] In describing some embodiments, the terms "coupled" and "connected," and their derived expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Then, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still assist or interact with each other.
[0053] To reduce the number of JTAG pins in the die, the IEEE 1838 standard proposed a die-to-die JTAG TAP connection structure (PTAP-STAP structure). This structure allows the entire die to have only one set of JTAG interface pins, thus improving the pin resource overhead problem.
[0054] like Figure 4 As shown, Figure 4 The die shown includes Die1, Die2, Die3, and Die4. Each die includes PTAP and STAP, where... Figure 4 Only the PTAP and STAP of Die1 are shown; the PTAP and STAP of Die2, Die3, and Die4 are not shown in detail. For Die1, which is the master die, PTAP is the interface connected to external input / output (I / O), and STAP is the interface connected to the next-level die. For Die2, Die3, and Die4, which are slave dies, PTAP is the interface connected to the previous-level die, and STAP is the interface connected to the next-level die.
[0055] Specifically, Die1 may include a PTAP controller, STAP1, STAP2, and STAP3, with each STAP containing STAP control logic. The PTAP controller connects to external I / O via TDI, TMS, TCK, TRSTN, and TDO, and is coupled to STAP1, STAP2, and STAP3 via the above pins respectively. STAP1 is coupled to TDI, TMS, TCK, TRSTN and TDO in Die2 through TDO_S1, TMS_S1, TCK_S1, TRSTN_S1 and TDI_S1 respectively; STAP2 is coupled to TDI, TMS, TCK, TRSTN and TDO in Die3 through TDO_S2, TMS_S2, TCK_S2, TRSTN_S2 and TDI_S2 respectively; and STAP3 is coupled to TDI, TMS, TCK, TRSTN and TDO in Die4 through TDO_S3, TMS_S3, TCK_S3, TRSTN_S3 and TDI_S3 respectively.
[0056] Specifically, the structure diagram of the STAP control logic is as follows: Figure 5 As shown, the STAP control logic is coupled to the PTAP. TCK_Sn, TMS_Sn, and TRST_Sn in the STAP control logic are directly driven by TCK, TMS, and TRSTN in the PTAP. Retiring elements can be added between TDI_Sn and TDO_Sn in the STAP control logic and TDI and TDO in the PTAP to meet timing requirements. Only when the STAP control logic is selected (i.e., Select_Sn = 1) will TMS, TDI, and TDO in the PTAP be connected to the next-level die via a multiplexer (mux).
[0057] Figure 5 The diagram shows mux1, mux2, and mux3. The first data input of mux1 is RTI_or_TLR_Sn, the second data input is TMS, and the control input is Select_Sn. The first data input of mux2 is TDI_Sn, the second data input is TDI_Sn_int, and the control input is Select_Sn. The first data input of mux3 is TDO_Sn_int, the second data input is the output signal from mux2, and the control input is the Enable signal.
[0058] Understandable. Figure 5 The first data input terminal of mux1 is marked with "1", and the second data input terminal is marked with "0". That is, when the signal at the control terminal of mux1 is "1", the first data input terminal and the output terminal of mux1 are connected; when the signal at the control terminal of mux1 is "0", the second data input terminal and the output terminal are connected. The subsequent mux settings are the same as mux1 and will not be repeated.
[0059] Therefore, when Select_Sn = 1, the second data input and output of mux1 are turned on, and TMS is transmitted to PTAP as TMS_Sn. Additionally, when Enable = 1, the second data input and output of mux3 are turned on, and the first data input and output of mux2 are turned on, then TDO is transmitted to TDO_Sn_int.
[0060] In one example, the PTAP-STAP structure of the main die in IEEE 1838 is as follows: Figure 6 As shown, Figure 6 The master die shown can be coupled with two slave dies. Figure 6 The diagram illustrates PTAP, STAP0, and STAP1. PTAP may include an instruction register (IR) and a data register (DR), such as r1, s1, r0, and s0. r1 and s1 control the die coupled to STAP1, while r0 and s0 control the die coupled to STAP0. In one possible example, when s0 is 0, the die coupled to STAP0 is not selected; when s0 is 1, the die coupled to STAP0 is selected. Similarly, when s1 is 0, the die coupled to STAP1 is not selected; when s1 is 1, the die coupled to STAP1 is selected. The data stored in r0 and r1 is used to replace TMS when STAP is not selected, thus controlling the state of the die coupled to STAP. PTAP also includes OR gates, mux1, and flip-flops. Figure 6 (represented by T_1). When no STAP is selected, i.e., s0 = 0 and s1 = 0, the output signal of the OR gate is 0, and TDI and TDO of PTAP are turned on. The signal received through TDI is transmitted to T_1.
[0061] Specifically, the TDI port of STAP0 can be represented as TDI_S0_int, the TDO port of STAP0 can be represented as TDO_S0_int, the TMS port of STAP0 can be represented as TMS_S0_int, the status port of STAP0 can be represented as RTI_or_TLR_S0, and the enable port of STAP0 can be represented as Select_S0. The ports connecting STAP0 to the die can be represented as TDO_S0, TDI_S0, and TMS_S0.
[0062] The STAP1 TDI port can be represented as TDI_S1_int, the STAP1 TDO port can be represented as TDO_S1_int, the STAP1 TMS port can be represented as TMS_S1_int, the STAP1 status port can be represented as RTI_or_TLR_S1, and the STAP1 enable port can be represented as Select_S1. The ports connecting STAP1 to the die can be represented as TDO_S1, TDI_S1, and TMS_S1.
[0063] Additionally, STAP0 can include two triggers ( Figure 6 The test data for STAP1 is transmitted to subsequent dies via T_2 and T_3 (represented by T_2 and T_3 respectively), mux2, and mux3. The control terminals of mux2 and mux3 are coupled to the output of data register s0. When s0 = 0, i.e., the die coupled to STAP0 is not selected, the input of T_3 is turned on via mux2 and TDI, and the input test data for TDI is transmitted to STAP1 via T_3. At this time, the data stored in data register r0 is transmitted to subsequent dies via mux3; that is, the data stored in r0 replaces TMS to control the state of the die coupled to STAP0. When s0 = 1, i.e., the die coupled to STAP0 is selected, the output test data received by STAP0 is transmitted to T_3 via mux2. At this time, TMS is transmitted to subsequent dies via mux3 to control the state of the die coupled to STAP0.
[0064] STAP1 can include two triggers ( Figure 6The test data for TDI is transmitted to subsequent dies via T_4 (represented by T_4 and T_5, respectively), mux4, and mux5. The control terminals of mux4 and mux5 are coupled to the output of data register s1. When s1 = 0, i.e., the die coupled to STAP1 is not selected, the input of T_5 is turned on via mux4 and TDI, and the input test data for TDI is transmitted to PTAP via T_5. At this time, the data stored in data register r1 is transmitted to subsequent dies via mux5; that is, the data stored in r1 replaces TMS to control the state of the die coupled to STAP1. When s1 = 1, i.e., the die coupled to STAP1 is selected, the output test data received by STAP1 is transmitted to T_5 via mux4. At this time, TMS is transmitted to subsequent dies via mux5 to control the state of the die coupled to STAP1.
[0065] As can be seen, the TAPs of each die in the PTAP-STAP structure are connected serially. When testing the die, the multiplexer in the STAP can be controlled by configuring the three-dimensional configuration register (3DCR). This allows the die that needs to be controlled for the test item to be configured with JTAG, while the die that does not need to be configured can be bypassed in the STAP, thus shortening the configuration link.
[0066] exist Figure 4 Based on the core particles shown in the figure, such as Figure 7 As shown, assuming the Die to be controlled is Die4, JTAG configuration can be performed on Die4, while Die2 and Die3 are bypassed in STAP. Specifically, the data flow for JTAG configuration is as follows: The PTAP controller in Die1 receives the input test data and transmits it to STAP3. STAP3 then transmits the input test data to Die4 via the JTAG pin. Die4 transmits the output test data obtained based on the input test data to TDI_S3 in STAP3 via the TDO interface. STAP3 then transmits the output test data sequentially to the STAP control logic in STAP2 and STAP control logic in STAP3, and finally to the PTAP controller, which transmits it outwards via the TDO interface. This completes the testing of Die4, and the bypassing of Die2 and Die3 shortens the configuration link.
[0067] However, if multiple Die test configurations need to be started simultaneously during testing, such as Figure 8As shown, assuming Die2, Die3, and Die4 need to be tested simultaneously, the data flow in the JTAG configuration can be: PTAP controller -> STAP3 -> Die4 -> STAP3 -> STAP2 -> Die3 -> STAP2 -> STAP1 -> Die2 -> STAP1 -> PTAP controller. It can be seen that when multiple dies need to be tested simultaneously, there is a problem of excessively long test chains, reducing testing efficiency.
[0068] Therefore, this application provides a master die, which includes a PTAP, a first STAP, and a second STAP. The master die adopts a PTAP-STAP architecture, allowing external connections via only the pins of the PTAP, reducing the number of package pins. The second STAP can be coupled to the TDI port of the PTAP via an input selection circuit, and the first STAP is also coupled to the TDI port of the PTAP. Thus, the input test data of the first and second STAPs can come from the same source; this method can be called broadcast mode. This method eliminates the need for clamping logic design, reducing design complexity. The second STAP can also be coupled to the TDO port of the first STAP via an input selection circuit, meaning the master die is also compatible with non-broadcast modes, improving its applicability. Furthermore, the PTAP's output selection circuit can selectively output either the test results from the first or second STAP. Compared to serial output of test results, this shortens the test link, reduces test configuration time, and improves test efficiency.
[0069] In the above scenario, the chip packaging structure including the main die provided in this application embodiment can be applied to electronic devices, such as mobile phones, tablets, desktops, laptops, handheld computers, notebook computers, ultra-mobile personal computers (UMPCs), netbooks, as well as cellular phones, personal digital assistants (PDAs), augmented reality (AR) / virtual reality (VR) devices, etc. This application embodiment does not impose any special restrictions on the specific form of the electronic device.
[0070] The chip packaging structure (also known as the Chiplet system) includes multiple bare dies with specific functions that can be modularly assembled. These dies can perform functions such as data storage, computation, signal processing, and data flow management. Based on a rich reserve of intellectual property cores (IP), the Chiplet system proposes the concept of IP as a Chiplet (IaaC), aiming to achieve "plug-and-play" functionality for specialized IPs using bare dies. For example, for some core processor IPs, the bare die can be a Graphics Processing Unit (GPU) IP, a Neural-network Unit (NPU) IP, a Video Processing Unit (VPU) IP, a Digital Signal Processor (DSP) IP, an Image Signal Processor (ISP) IP, and a Display Processor IP. Furthermore, the bare die can also be mixed-signal IP and radio frequency (RF) IP.
[0071] The Chiplet system in this application can also be referred to as a chiplet system or a die system. That is, a bare die can also be referred to as a chiplet or a die.
[0072] For example, this Chiplet system can also be applied to a System-on-a-Chip (SoC), where multiple functional dies are integrated. Taking a Chiplet system comprising a first die and a second die as an example, the first die can transmit service data / application data with the second die via a serial interface. The first die can also transmit control signals with the second die via a sideband control channel.
[0073] The main wafer provided in the embodiments of this application is described below.
[0074] This application provides a master die, such as Figure 9 As shown, the master die includes PTAP, first STAP and second STAP, the first STAP is coupled to the first slave die, and the second STAP is coupled to the second slave die.
[0075] For example, each slave die may include a PTAP and a STAP, a first STAP and a PTAP connection of a first slave die, and a second STAP and a PTAP connection of a second slave die. A slave die's STAP may be connected to the PTAP connections of other slave dies.
[0076] For example, the master die can send input test data to the first slave die via the first STAP and receive output test data from the first slave die via the first STAP to complete the testing of the first slave die. Similarly, the master die can send input test data to the second slave die via the second STAP and receive output test data from the second slave die via the second STAP to complete the testing of the second slave die.
[0077] The PTAP includes an input selection circuit and an output selection circuit. The TDI port of the PTAP is coupled to the TDI port of the first STAP. The TDI port of the PTAP is also coupled to the first data input terminal of the input selection circuit. Figure 9 The second data input terminal of the input selection circuit is coupled to the input terminal a) (represented by input terminal a). Figure 9 The input terminal (represented by input b) is coupled to the TDO port of the first STAP, and the output terminal of the input selection circuit ( Figure 9 The second STAP (represented by output terminal c) is coupled to the TDI port. The first STAP's TDO port is coupled to the first data input terminal of the output selection circuit. Figure 9 The second STAP's TDO port and the output selection circuit's second data input terminal (represented by input terminal d) are coupled together. Figure 9 The input terminal (e) is used for coupling, and the output terminal of the output selection circuit ( Figure 9 (represented by the output terminal f) is coupled to the TDO port of the PTAP.
[0078] The output selection circuit is used to select the output test result of the first STAP or the output test result of the second STAP.
[0079] For example, when the first data input and output terminals of the input selection circuit are turned on, the TDI ports of both the first STAP and the second STAP are connected to the TDI port of the PTAP. This means the input test data for the first and second STAPs comes from the same source. This method can be called broadcast mode, where the PTAP broadcasts the received input test data to each STAP. In this case, no clamping logic design is needed in the chip, reducing design complexity.
[0080] For example, when the first data input and output terminals of the input selection circuit are turned on, the TDO port of the first STAP and the TDI port of the second STAP are also turned on. This means the input test data for the second STAP comes from the first STAP, and the first and second STAPs are connected serially. This method can be called non-broadcast mode. Therefore, by selecting the input test data through the input selection circuit, the main die can be compatible with both broadcast and non-broadcast modes, improving the chip's applicability.
[0081] For example, when the first data input and output terminals of the output selection circuit are connected, the output selection circuit selects the output test result of the first STAP to output. When the second data input and output terminals of the output selection circuit are connected, the output selection circuit outputs the output test result of the second STAP. In other words, the output selection circuit can choose either the output test result of the first STAP or the second STAP to output. Compared with the serial output of test results, this can shorten the test link, reduce test configuration time, and save test costs.
[0082] Understandably, the master die, the first slave die, and the second slave die may also include other external pins. Figure 9 The embodiments of this application do not limit this.
[0083] Optional, such as Figure 10 As shown, the master die can also include more STAPs, for example... Figure 10 The diagram shows a first STAP, a second STAP, and STAP_N, where N is an integer greater than 2. Each STAP is coupled to a slave die, i.e., STAP_N is coupled to the Nth slave die. The PTAP may include an output selection circuit and N-1 input selection circuits, which may include input selection circuits_1 to_N-1. The first data input terminal of input selection circuit_N-1 is coupled to the TDI port of the PTAP, and the second data input terminal of input selection circuit_N-1 is coupled to STAP_N-1 (…). Figure 10 The TDO port is coupled (not shown in the image).
[0084] In one possible implementation, the output selection circuit may include N data input terminals to select one of the N STAP output test results for output. In another possible implementation, the output selection circuit may also include N-1 cascaded multiplexers, where the output terminal of the previous stage multiplexer is coupled to the data input terminal of the current stage multiplexer. It is understood that the structure of the output selection circuit can also take other forms, and the embodiments of this application are not limited thereto.
[0085] Optional, such as Figure 11 As shown, PTAP may also include a first register, which stores a first value indicating whether the master die is configured in broadcast mode or non-broadcast mode. That is, the first register can be a broadcast mode enable (broadcast_enable, bc) register. Figure 11 In this context, "bc" represents the first register.
[0086] For example, the first value can be "0" or "1", which can also be understood as a low level or a high level. In one possible implementation, when the first value is "0", the main die is configured in broadcast mode; when the first value is "1", the main die is configured in non-broadcast mode. In another possible implementation, when the first value is "0", the main die is configured in non-broadcast mode; when the first value is "1", the main die is configured in broadcast mode. This application does not limit the scope of the embodiments.
[0087] For example, broadcast mode such as Figure 12 As shown, Figure 12 The diagram shows Die1, Die2, Die3, and Die4. Input test data received by the TDI port in Die1 can be simultaneously broadcast to Die2, Die3, or Die4. This allows the die to broadcast and distribute test configurations from multiple dies, significantly improving the parallel measurement capability of dies and increasing test efficiency.
[0088] For example, the non-broadcast mode can be referred to Figure 7 or Figure 8 The test mode shown is the serial configuration mode that conforms to the IEEE 1838 standard. It is understood that other test modes are also possible in the non-broadcast mode, and this application embodiment does not limit this to any particular mode.
[0089] Optional, please continue reading Figure 11 Input selection circuit ( Figure 11 The control terminal (represented by mux1 in Chinese) Figure 11 The output selection circuit is coupled to the output terminal of the first register (represented by the coupling terminal g). When the master die is configured in broadcast mode, the output selection circuit controls the input test data of the PTAP's TDI port to the TDI port of the second STAP; and when the master die is configured in non-broadcast mode, the output test data of the first STAP's TDO port to the TDI port of the second STAP.
[0090] For example, the input selection circuit can be a 2-to-1 multiplexer, with the first data input terminal of mux1 ( Figure 11 (represented by input terminal a) is the first data input terminal of the input selection circuit, and the second data input terminal of mux1. Figure 11 (represented by input terminal b) is the second data input terminal of the input selection circuit, and the output terminal of mux1. Figure 11 (The output terminal is represented by c) which is the output terminal of the input selection circuit.
[0091] Taking the first value of "1" for broadcast mode and "0" for non-broadcast mode as examples, when the main die is configured in non-broadcast mode, the first value stored in the first register is set to "0". At this time, the value input to the control terminal of the input selection circuit is "0", and the second data input terminal and output terminal of the input selection circuit are connected, that is, the TDO port of the first STAP and the TDI port of the second STAP are connected, and the input test data of the TDO port of the first STAP is transmitted to the TDI port of the second STAP. When the main die is configured in broadcast mode, the first value stored in the first register is set to "1". At this time, the value input to the control terminal of the input selection circuit is "1", and the first data input terminal and output terminal of the input selection circuit are connected, that is, the TDI port of the PTAP and the TDI port of the second STAP are connected, and the input test data of the TDI port of the PTAP is transmitted to the TDI port of the second STAP.
[0092] Optional, please continue reading Figure 11 PTAP also includes a first multiplexer ( Figure 11 (referred to as mux2 in Chinese), the output selection circuit includes a second multiplexer ( Figure 11 (represented by mux3 in Chinese) and the third multiplexer ( Figure 11 (referred to as mux4 in Chinese). The first, second, and third multiplexers in the embodiments of this application can be two-to-one multiplexers.
[0093] Among them, the first data input terminal of the first multiplexer ( Figure 11 The input terminal (represented by h) is coupled to the TDI port of the PTAP, and the second data input terminal of the first multiplexer ( Figure 11 The input terminal (represented by i) is coupled to the TDO port of the second STAP, and the output terminal of the first multiplexer ( Figure 11 The output terminal j is used to represent the first data input terminal of the second multiplexer. Figure 11 The second data input of the second multiplexer (represented by input terminal k) is coupled. Figure 11 The input terminal (represented by d) is coupled to the TDO port of the first STAP, and the output terminal of the second multiplexer ( Figure 11 The output terminal (l) and the first data input terminal of the third multiplexer ( Figure 11 The second data input of the third multiplexer (represented by input terminal m) is coupled. Figure 11 The input terminal (represented by e) is coupled to the TDO port of the second STAP, and the output terminal of the third multiplexer ( Figure 11 The output terminal (represented by f) is coupled to the TDO port of the PTAP.
[0094] Understandably, the second data input terminal of the second multiplexer is the first data input terminal of the output selection circuit, the second data input terminal of the third multiplexer is the second data input terminal of the output selection circuit, and the output terminal of the third multiplexer is the output terminal of the output selection circuit.
[0095] Understandably, PTAP can also include a first trigger ( Figure 11 (represented by T_1), the first STAP includes the second flip-flop ( Figure 11 (represented by T_2) and the third flip-flop ( Figure 11 (represented by T_3), and the second STAP includes the fourth trigger ( Figure 11 (represented by T_4) and the fifth trigger ( Figure 11 (Represented by T_5 in the original text), the trigger can meet the timing requirements between the TDI port and the TDO port. In addition, the first STAP can also include mux5 and mux6, and the second STAP can also include mux7 and mux8.
[0096] Additionally, the port settings for the first and second STAPs and Figure 6 STAP0 and STAP1 are the same, so we will not repeat them here.
[0097] Optional, please continue reading Figure 11 PTAP also includes a second register ( Figure 11 (represented by t0), the third register ( Figure 11 (represented by t1), first AND gate ( Figure 11 (represented by A0) and the second AND gate ( Figure 11 (represented by A1 in Chinese).
[0098] Among them, the first input terminal of the first AND gate ( Figure 11 The input terminal (represented by n) is coupled to the output terminal of the first register, and the second input terminal of the first AND gate ( Figure 11 The input terminal (represented by o) is coupled to the output terminal of the second register, and the output terminal of the first AND gate ( Figure 11 The output terminal (p) and the control terminal of the second multiplexer (represented by the output terminal p) Figure 11 The first input terminal (represented by q) of the second AND gate is coupled. Figure 11 The input terminal (represented by r) is coupled to the output terminal of the first register, and the second input terminal of the first AND gate ( Figure 11 The input terminal (represented by s) is coupled to the output terminal of the third register, and the output terminal of the second AND gate ( Figure 11 (represented by the output terminal t) and the control terminal of the third multiplexer ( Figure 11 (The input terminal u is used to represent the coupling).
[0099] The second register is used to store a second value, which indicates whether the TDO port of the first STAP and the TDO port of the PTAP are on or off.
[0100] For example, the second value can be "0" or "1", which can also be understood as a low level or a high level. In one possible implementation, when the second value is "0", the TDO port of the first STAP and the TDO port of the PTAP are connected; when the second value is "1", the TDO port of the first STAP and the TDO port of the PTAP are not connected. In another possible implementation, when the second value is "1", the TDO port of the first STAP and the TDO port of the PTAP are connected; when the second value is "0", the TDO port of the first STAP and the TDO port of the PTAP are not connected. This application does not limit the scope of the embodiments.
[0101] The third register is used to store a third value, which indicates whether the TDO port of the second STAP and the TDO port of the PTAP are on or off.
[0102] For example, the third value can be "0" or "1", which can also be understood as a low level or a high level. In one possible implementation, when the third value is "0", the TDO port of the second STAP and the TDO port of the PTAP are connected; when the third value is "1", the TDO port of the second STAP and the TDO port of the PTAP are not connected. In another possible implementation, when the third value is "1", the TDO port of the second STAP and the TDO port of the PTAP are connected; when the third value is "0", the TDO port of the second STAP and the TDO port of the PTAP are not connected. This application does not limit the scope of the embodiments.
[0103] Taking the master die configured in broadcast mode as an example, when the first value stored in the first register is "1", if the second value stored in the second register is "1", the first AND gate outputs "1"; if the second value stored in the second register is "0", the first AND gate outputs "0". If the third value stored in the third register is "1", the second AND gate outputs "1"; if the third value stored in the third register is "0", the second AND gate outputs "1".
[0104] by Figure 11Taking the configuration of mux3 and mux4 as an example, when the master die is configured in broadcast mode and the input selection circuit selects the output test result of the first STAP, then t0 = 1 and t1 = 0. The first AND gate outputs "1" and the second AND gate outputs "0". That is, the control terminal of mux3 is "1", at which point the second data input and output terminals of mux3 are connected, and the output test result of the first STAP is transmitted to mux4. Since the control terminal of mux4 is "0", the first data input and output terminals of mux4 are connected, and mux4 transmits the output test result of the first STAP to T_1 for external transmission through the TDO port of the PTAP.
[0105] When the main die is configured in broadcast mode and the input selection circuit selects the output test result of the second STAP, t0 = 0 and t1 = 1. Therefore, the first AND gate outputs "0" and the second AND gate outputs "1". In other words, the control terminal of mux4 is "1", the second data input and output terminals of mux4 are connected, and the output test result of the second STAP is transmitted to T_1 for external transmission through the TDO port of PTAP.
[0106] Optional, please continue reading Figure 11 PTAP also includes a fourth register ( Figure 11 (represented by s0), fifth register ( Figure 11 (s1 represents) and OR gates. The fourth and fifth registers can be used to control the output test results of the first STAP or the second STAP in broadcast mode; therefore, the fourth and fifth registers can be called output selection registers, and can be represented by tdo_sel. Additionally, PTAP may also include a sixth register ( Figure 11 (represented by r0) and the seventh register ( Figure 11 (represented by r1 in the text), and the values stored in r0 and r1 are usually "0".
[0107] Among them, the first input terminal of the OR gate ( Figure 11 The input terminal (represented by v) is coupled to the output terminal of the fourth register, and the second input terminal of the OR gate ( Figure 11 The input terminal (represented by w) is coupled to the output terminal of the fifth register, and the output terminal of the OR gate ( Figure 11 (represented by output terminal x) and the control terminal of the first multiplexer ( Figure 11 (The input terminal y is used to represent the coupling).
[0108] The fourth register is used to store a fourth value, which indicates whether the first STAP is in test or idle state.
[0109] For example, the fourth value can be "0" or "1", which can also be understood as a low level or a high level. In one possible implementation, when the fourth value is "0", the first STAP is in a test state; when the fourth value is "1", the first STAP is in an idle state. In another possible implementation, when the fourth value is "1", the first STAP is in a test state; when the fourth value is "0", the first STAP is in an idle state. This application does not limit the scope of the embodiments.
[0110] The fifth register is used to store the fifth value, which indicates whether the second STAP is in test or idle state.
[0111] For example, the fifth value can be "0" or "1", which can also be understood as a low level or a high level. In one possible implementation, when the fifth value is "0", the second STAP is in a test state; when the fifth value is "1", the second STAP is in an idle state. In another possible implementation, when the fifth value is "1", the second STAP is in a test state; when the fifth value is "0", the second STAP is in an idle state. This application does not limit the scope of the embodiments.
[0112] Taking the first STAP as an example, when s0 = 1, the control terminal signal Select_S0 of mux5 and mux6 is 1, TDI_S0 is turned on through mux5 and T_3, and TMS_S0_int is turned on through mux6 and TMS_S0. That is, when the first STAP is in test mode, the input test data received by TDI_S0_int is transmitted to the first slave die through T_2 and TDO_S0, and the output test data sent by the first slave die is transmitted to T_3 through TDI_S0 and mux5. Conversely, when s0 = 0, the control terminal signal Select_S0 of mux5 and mux6 is 0, TDI_S0_int is turned on through mux5 and T_3, and RTI_or_TLR_S0 is turned on through mux6 and TMS_S0. In other words, when the first STAP is idle, the input test data received by TDI_S0_int is transmitted to subsequent slave dies via mux5 and T_3. RTI_or_TLR_S0 replaces TMS_S0_int to control the state of the first slave die. The configuration method of the second STAP is similar to that of the first STAP, and will not be repeated here. It can be understood that the configuration of the fourth and fifth registers of the master die can be understood as the 3DCR configuration mentioned earlier. It can control the multiplexer in the STAP, allowing slave dies that need to be controlled for this test item to undergo JTAG configuration, while slave dies that do not need configuration can be bypassed directly in the STAP to shorten the configuration link. The number of registers in the 3DCR can be determined based on the number of slave dies.
[0113] Understandably, taking the second and fourth registers as examples, users should refer to the configuration of the fourth register when configuring the second register. In one possible example, when the first STAP controlled by the fourth register is in an idle state, the second value stored in the second register should not be configured to indicate that the TDO port of the first STAP and the TDO port of the PTAP are turned on.
[0114] Applied to Figure 11 In the master die, when the master die tests multiple slave dies simultaneously, the master die performs parallel write operations. The master die can set the first register bc to 1. The master die also sets the registers corresponding to the STAPs in the test state to 1 through 3DCR, i.e., s* = 1, where "*" can be replaced by a number, and sets the registers corresponding to the STAPs not in the test state to 0, i.e., s* = 0, and all r* = 0.
[0115] Correspondingly, when the master die performs a read operation, it can set the first register bc to 1. The master die can also select the STAP to be read via tdo_sel. For the STAP to be read, the master die sets the corresponding s* in 3DCR to 1, and r* can be set to 0. For other STAPs not being read, if the corresponding s* in 3DCR is 1, the TAP in the STAP performs the same operation as the TAP of the STAP being read; if the corresponding s* in 3DCR is 0 and r* is 0, then its TAP is in an idle state. Users can determine the configuration method according to their needs.
[0116] The testing methods provided in the embodiments of this application are described below.
[0117] This application provides a testing method, such as... Figure 13 As shown, this test method is applied to a master die, which includes a PTAP and at least one STAP, each STAP being coupled to a slave die. The method includes the following procedure.
[0118] In one possible implementation, when the master die is configured in broadcast mode, PTAP sends input test data to at least one STAP.
[0119] For example, suppose that a first value stored in the first register is "1" to indicate broadcast mode, and a first value stored is "0" to indicate non-broadcast mode. When multiple slave dies need to be tested simultaneously, in order to shorten the test chain and improve test efficiency, the master die can be configured to broadcast mode. Specifically, the master die sets the first value stored in the first register to "1", thereby allowing the PTAP to broadcast input test data to each STAP through the TDI port. In another possible implementation, at least one STAP sends the received input test data to the slave die. In yet another possible implementation, at least one STAP receives output test data from the slave die, and the output test data is obtained based on the input test data.
[0120] For example, the master die can configure the state of each slave die via a 3DCR configuration register. Assume that when the value stored in the master die's register is "1", the slave die performs a write or read operation; when the value stored in the master die's register is "0", the slave die does not perform a write or read operation, i.e., the slave die is in an idle state. Thus, the user can determine the configuration method according to their needs to send input test data to the STAP connected to the slave die that needs to be written to, and receive output test data from the STAP connected to the slave die that needs to be read from. In another possible implementation, at least one STAP sends output test data to the PTAP.
[0121] In yet another possible implementation, PTAP selects one output test data from at least one output test data and outputs it.
[0122] For example, after receiving the output test data, STAP sends the output test data to PTAP. PTAP can select one output test data from at least one set of output test data for output by configuring registers. In a possible example, suppose that when the value stored in the register is "1", the output test result is selected for output; when the value stored in the register is "0", the output test result is not selected for output. Thus, the user can determine the register configuration according to their needs, setting the value in the register corresponding to the required output test result to "1" to output the desired output test result.
[0123] Therefore, since the master die adopts a PTAP-STAP architecture, it can be connected to the outside via only PTAP pins, reducing the number of package pins for the die. At least one STAP input test data comes from the same source, eliminating the need for clamping logic design and reducing design complexity. Furthermore, the PTAP output selection circuit can randomly select one of multiple output test results for output. Compared to serial output of test results, this shortens the test chain, reduces test configuration time, and lowers test costs. Because the master die can use a broadcast mode, the test parallelism of multiple slave dies can be improved, significantly reducing test configuration time and saving test costs.
[0124] Optionally, the test method may further include setting a first value stored in the first register of the master die to a first level, the first level being used to indicate that the master die is configured in broadcast mode.
[0125] For example, the first level can be a high level, which can be represented by "1". When the first value is "1", the main die is configured in broadcast mode. The first level can also be a low level, which can be represented by "0". When the first value is "0", the main die is configured in broadcast mode. Thus, by configuring the first register, the main die can be made compatible with both broadcast and non-broadcast modes, improving the applicability of the main die.
[0126] Optionally, at least one STAP includes a first STAP and a second STAP. The test method further includes: when the PTAP selects the output test data of the first STAP, setting the second value stored in the second register of the main die to a second level, the second level being used to indicate that the TDO port of the first STAP and the TDO port of the PTAP are turned on.
[0127] For example, the second level can be a high level, which can be represented by "1". When the second value is "1", the TDO port of the first STAP and the TDO port of the PTAP are turned on, and the PTAP selects the output test data of the first STAP for output. The second level can also be a low level, which can be represented by "0". When the second value is "0", the TDO port of the first STAP and the TDO port of the PTAP are turned on, and the PTAP selects the output test data of the first STAP for output. Thus, by configuring the second register, the main die can be made compatible with both broadcast and non-broadcast modes, improving the applicability of the main die.
[0128] Optionally, the test method also includes: when PTAP selects the output test data of the second STAP, setting the third value stored in the third register of the main die to the third level, the third level is used to indicate that the TDO port of the second STAP and the TDO port of PTAP are turned on.
[0129] For example, the third level can be a high level, represented by "1". When the third value is "1", the TDO ports of the second STAP and PTAP are connected, and PTAP selects the output test data of the second STAP. The third level can also be a low level, represented by "0". When the third value is "0", the TDO ports of the second STAP and PTAP are connected, and PTAP selects the output test data of the second STAP. Therefore, by configuring the third register, the main die can be made compatible with both broadcast and non-broadcast modes, improving the applicability of the main die.
[0130] Optionally, the test method further includes: when it is necessary to test the slave die corresponding to the first STAP, setting the fourth value stored in the fourth register of the master die to the fourth level, the fourth level being used to indicate that the first STAP is in the test state.
[0131] For example, the fourth level can be a high level, which can be represented by "1". When the fourth level is "1", the first STAP is in test mode. The fourth level can also be a low level, which can be represented by "0". When the fourth level is "0", the first STAP is in test mode. Therefore, the main die can configure the STAP state according to test requirements through the fourth register, reducing test time and improving test efficiency.
[0132] Optionally, the test method also includes: when it is necessary to test the slave die corresponding to the second STAP, setting the fifth value stored in the fifth register of the master die to the fifth level, the fifth level being used to indicate that the second STAP is in the test state.
[0133] For example, the fifth level can be a high level, which can be represented by "1". When the fifth level is "1", the second STAP is in test mode. The fifth level can also be a low level, which can be represented by "0". When the fifth level is "0", the second STAP is in test mode. Therefore, the main die can configure the STAP state according to test requirements through the fifth register, reducing test time and improving test efficiency.
[0134] This application also provides a chip packaging structure, which includes a first slave die, a second slave die, an interconnect structure, and a main die as described above. The first slave die is coupled to a first STAP, and the second slave die is coupled to a second STAP.
[0135] This application also provides an electronic device, which includes a chip package structure and a printed circuit board, wherein the chip package structure is disposed on the printed circuit board.
[0136] It is understood that, in order to achieve the above functions, the electronic device includes hardware and / or software modules that perform the respective functions. Based on the algorithmic steps of the examples described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is implemented in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in conjunction with the embodiments, but such implementation should not be considered beyond the scope of this application.
[0137] Embodiments of this application also provide a computer storage medium storing computer instructions. When the computer instructions are executed on an electronic device, the electronic device performs the aforementioned related method steps to implement the testing method in the above embodiments.
[0138] Embodiments of this application also provide a computer program product that, when run on a computer, causes the computer to perform the aforementioned related steps to implement the testing method executed by the electronic device in the above embodiments.
[0139] In addition, embodiments of this application also provide an apparatus, which may specifically be a chip, component, or module. The apparatus may include a connected processor and a memory; wherein the memory is used to store computer execution instructions, and when the apparatus is running, the processor may execute the computer execution instructions stored in the memory to cause the chip to execute the test methods executed by the electronic devices in the above-described method embodiments.
[0140] In this embodiment, the main die, chip package structure, electronic device, computer storage medium, computer program product or chip are all used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects in the corresponding methods provided above, and will not be repeated here.
[0141] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.
[0142] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.
[0143] The units described as separate components may or may not be physically separate. A component shown as a unit can be one or more physical units; that is, it can be located in one place or distributed in multiple different locations. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0144] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0145] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solutions of the embodiments of this application, essentially, or the parts that contribute to the prior art, or all or part of the technical solutions, can be embodied in the form of a software product. This software product is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0146] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A master die, characterized in that, include: The main test access port PTAP, the first auxiliary test access port STAP and the second STAP, the first STAP and the first slave die are coupled, and the second STAP and the second slave die are coupled. The PTAP includes: an input selection circuit and an output selection circuit; The PTAP's test data input TDI port is coupled to the first STAP's TDI port. The PTAP's TDI port is also coupled to the first data input terminal of the input selection circuit. The second data input terminal of the input selection circuit is coupled to the first STAP's test data output TDO port. The output terminal of the input selection circuit is coupled to the second STAP's TDI port. The TDO port of the first STAP is coupled to the first data input terminal of the output selection circuit, the TDO port of the second STAP is coupled to the second data input terminal of the output selection circuit, and the output terminal of the output selection circuit is coupled to the TDO port of the PTAP. The output selection circuit is used to select the output test result of the first STAP or the output test result of the second STAP.
2. The master die according to claim 1, characterized in that, The PTAP also includes a first register; The first register is used to store a first value, which is used to indicate whether the master die is configured in broadcast mode or non-broadcast mode.
3. The master die according to claim 2, characterized in that, The control terminal of the input selection circuit is coupled to the output terminal of the first register; The input selection circuit is used to control the input test data of the TDI port of the PTAP to be transmitted to the TDI port of the second STAP when the main die is configured in broadcast mode, and to control the output test data of the TDO port of the first STAP to be transmitted to the TDI port of the second STAP when the main die is configured in non-broadcast mode.
4. The master die according to any one of claims 1-3, characterized in that, The PTAP further includes a first multiplexing circuit, and the output selection circuit includes a second multiplexer and a third multiplexer; The first data input terminal of the first multiplexer is coupled to the TDI port of the PTAP, the second data input terminal of the first multiplexer is coupled to the TDO port of the second STAP, and the output terminal of the first multiplexer is coupled to the first data input terminal of the second multiplexer. The second data input terminal of the second multiplexer is coupled to the TDO port of the first STAP, and the output terminal of the second multiplexer is coupled to the first data input terminal of the third multiplexer. The second data input terminal of the third multiplexer is coupled to the TDO port of the second STAP, and the output terminal of the third multiplexer is coupled to the TDO port of the PTAP.
5. The master die according to claim 4, characterized in that, The PTAP also includes a second register, a third register, a first AND gate, and a second AND gate; The first input terminal of the first AND gate is coupled to the output terminal of the first register, the second input terminal of the first AND gate is coupled to the output terminal of the second register, and the output terminal of the first AND gate is coupled to the control terminal of the second multiplexer. The first input of the second AND gate is coupled to the output of the first register, the second input of the second AND gate is coupled to the output of the third register, and the output of the second AND gate is coupled to the control terminal of the third multiplexer.
6. The master die according to claim 5, characterized in that, The second register is used to store a second value, which is used to indicate whether the TDO port of the first STAP and the TDO port of the PTAP are turned on or off. The third register is used to store a third value, which is used to indicate whether the TDO port of the second STAP and the TDO port of the PTAP are on or off.
7. The master die according to any one of claims 4-6, characterized in that, The PTAP also includes a fourth register, a fifth register, and an OR gate; The first input terminal of the OR gate is coupled to the output terminal of the fourth register, the second input terminal of the OR gate is coupled to the output terminal of the fifth register, and the output terminal of the OR gate is coupled to the control terminal of the first multiplexer; The fourth register is used to store a fourth value, which is used to indicate whether the first STAP is in a test state or an idle state. The fifth register is used to store a fifth value, which is used to indicate whether the second STAP is in a test state or an idle state.
8. A testing method, characterized in that, The test method is applied to a master die, the master die including a PTAP and at least one STAP, each STAP being coupled to a slave die, the method comprising: When the master die is configured in broadcast mode, the PTAP sends input test data to the at least one STAP; The at least one STAP will send the received input test data to the die; The at least one STAP receives output test data from the die, the output test data being obtained based on the input test data; The at least one STAP sends the output test data to the PTAP; The PTAP selects one output test data from at least one output test data and outputs it.
9. The method according to claim 8, characterized in that, The method further includes: The first value stored in the first register of the master die is set to a first level, which is used to indicate that the master die is configured to broadcast mode.
10. The method according to claim 8 or 9, characterized in that, The at least one STAP includes a first STAP and a second STAP, and the method further includes: When the PTAP selects the output test data of the first STAP, the second value stored in the second register of the main die is set to the second level. The second level is used to indicate that the TDO port of the first STAP and the TDO port of the PTAP are turned on. When the PTAP selects the output test data of the second STAP, the third value stored in the third register of the main die is set to the third level. The third level is used to indicate that the TDO port of the second STAP and the TDO port of the PTAP are turned on.
11. The method according to claim 10, characterized in that, The method further includes: When it is necessary to test the slave die corresponding to the first STAP, the fourth value stored in the fourth register of the master die is set to the fourth level, which is used to indicate that the first STAP is in the test state. When it is necessary to test the slave die corresponding to the second STAP, the fifth value stored in the fifth register of the master die is set to the fifth level, which is used to indicate that the second STAP is in the test state.
12. A chip packaging structure, characterized in that, Includes a first slave die, a second slave die, an interconnect structure, and a master die as described in any one of claims 1-7; The first die is coupled to the first STAP, and the second die is coupled to the second STAP.
13. An electronic device, characterized in that, Includes the chip packaging structure and printed circuit board as described in claim 12; The chip packaging structure is disposed on the printed circuit board.