Concurrency control method and device, electronic equipment, storage medium and product

Abstract

The invention discloses a concurrency control method and device, electronic equipment, a storage medium and a product. The method is applied to a concurrency control system comprising a processor and a bus controller, and comprises the steps that the processor responds to an atomic operation request of a target thread and sequentially sends a storage area switching instruction and a register operation instruction to the bus controller; the bus controller responds to the storage area switching instruction and the register operation instruction, executes storage area switching operation, generates a bus occupation maintaining signal and continuously executes register read-write operation in a target storage area; the processor sends a scheduling request to an operating system, so that the operating system improves the priority of the target thread to be a first priority; and the bus controller generates a bus release signal after the atomic operation of the target thread is finished. According to the scheme, through cooperation of the processor and the bus controller, atomized execution of thread Bank switching and register reading and writing is achieved, and the concurrency performance is improved while the reliability and consistency of data are ensured.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a concurrent control method, apparatus, electronic device, storage medium, and product. Background Technology

[0002] An Inter-Integrated Circuit (I2C) is a bidirectional two-wire synchronous serial bus that transmits information between devices via a clock line (Serial Clock, SCL) and a data line (Serial Data, SDA). When an I2C device operates on a register, it needs to send at least two instructions. For example, it must first send a bank switching instruction to switch to the corresponding memory bank, then release the I2C bus, and only then can it perform register read / write operations.

[0003] However, in scenarios where multiple threads / processes concurrently access I2C bus devices, after thread A completes the bank switch and releases the I2C bus, a higher-priority thread B may preempt the I2C bus and switch to another bank before thread A can perform register read / write operations. Consequently, when thread A resumes execution, it may access the wrong bank, resulting in the accessed register not being in the expected bank and causing a functional error. Summary of the Invention

[0004] This invention provides a concurrency control method, apparatus, electronic device, storage medium, and product to solve the problem of concurrent access conflicts in related technologies.

[0005] According to one aspect of the present invention, a concurrent control method is provided, applied to a concurrent control system including a processor and a bus controller, the method comprising:

[0006] In response to the atomic operation request from the target thread, the processor sequentially sends memory area switching instructions and register operation instructions to the bus controller;

[0007] The bus controller responds to memory area switching instructions and register operation instructions, performs memory area switching operations and generates a bus occupancy sustain signal, and continuously performs register read and write operations in the target memory area;

[0008] The processor sends a scheduling request to the operating system so that the operating system can raise the priority of the target thread to the first priority;

[0009] The bus controller generates a bus release signal after the atomic operation of the target thread is completed.

[0010] According to another aspect of the present invention, a concurrent control device is provided, applied to a concurrent control system including a bus controller and a processor, the device comprising:

[0011] The instruction sending module, configured in the processor, is used to send memory area switching instructions and register operation instructions to the bus controller in response to the atomic operation request of the target thread.

[0012] The bus control module, configured in the bus controller, is used to respond to memory area switching instructions and register operation instructions, perform memory area switching operations and generate bus occupancy maintenance signals, and continuously perform register read and write operations in the target memory area;

[0013] The scheduling request module, configured in the processor, is used to send scheduling requests to the operating system so that the operating system can raise the priority of the target thread to the first priority.

[0014] The bus release module, configured on the bus controller, is used to generate a bus release signal after the atomic operation of the target thread has completed.

[0015] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0016] At least one processor;

[0017] Bus controller, communicatively connected to the processor; and

[0018] A memory communicatively connected to the at least one processor; wherein,

[0019] The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the concurrency control method described in any embodiment of the present invention.

[0020] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the concurrency control method described in any embodiment of the present invention.

[0021] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the concurrency control method described in any embodiment of the present invention.

[0022] The technical solution of this invention is applied to a concurrent control system including a processor and a bus controller. The processor, in response to an atomic operation request from a target thread, sequentially sends a memory area switching instruction and a register operation instruction to the bus controller. The bus controller, in response to the memory area switching instruction and the register operation instruction, executes the memory area switching operation and generates a bus occupancy maintenance signal, and continuously executes register read / write operations within the target memory area. The processor sends a scheduling request to the operating system to raise the priority of the target thread to the first priority. The bus controller generates a bus release signal after the atomic operation of the target thread is completed. This technical solution binds memory area switching and register read / write operations into an atomic operation by generating a bus occupancy maintenance signal through the bus controller. Simultaneously, the processor triggers the operating system to raise the target thread to the first priority, preventing high-priority threads from preempting the bus. Furthermore, the solution employs a lock-free design, improving system concurrency performance while ensuring the reliability and consistency of data transmission.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a concurrent control system provided according to Embodiment 1 of the present invention;

[0026] Figure 2 This is a flowchart of a concurrency control method provided in Embodiment 1 of the present invention;

[0027] Figure 3 This is a flowchart of a concurrency control method provided in Embodiment 2 of the present invention;

[0028] Figure 4 This is a schematic diagram of an I2C timing read / write operation according to Embodiment 2 of the present invention;

[0029] Figure 5 This is a schematic diagram of thread scheduling according to Embodiment 2 of the present invention;

[0030] Figure 6 This is a schematic diagram of another I2C timing read / write operation provided according to Embodiment 2 of the present invention;

[0031] Figure 7 This is a schematic diagram of another thread scheduling method provided according to Embodiment 2 of the present invention;

[0032] Figure 8 This is a schematic diagram of the structure of a concurrent control device according to Embodiment 3 of the present invention;

[0033] Figure 9 This is a schematic diagram of the structure of an electronic device that implements the concurrent control method of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] Example 1

[0037] Figure 1 This is a schematic diagram of a concurrent control system provided in Embodiment 1 of the present invention, as shown below. Figure 1 As shown, the concurrent access control system includes a processor 11 and a bus controller 12. The specific functions of the processor 11 and the bus controller 12 are described below.

[0038] The processor 11, which is connected to the bus controller 12 via a bus (such as I2C), is configured to: ① send memory area switching instructions and register operation instructions to the bus controller 12 in sequence in response to the atomic operation request of the target thread; ② monitor the bus occupancy status and send a scheduling request to the operating system to increase the priority of the target thread.

[0039] Bus controller 12 is configured to: ① generate a bus occupancy maintenance signal to maintain bus occupancy after performing a memory area switching operation; ② continuously perform register read and write operations in the target memory area; ③ generate a bus release signal to release the bus after completing the atomic operation of the target thread.

[0040] The concurrent control system proposed in this embodiment of the invention achieves atomic execution of target thread's bank switching and register read / write through the coordinated cooperation of processor 11 and bus controller 12, ensuring that it is not interrupted by other threads during bus occupancy, thereby guaranteeing the integrity and consistency of data transmission and improving the system's concurrent performance.

[0041] Based on the above concurrent control system, Figure 2 This is a flowchart of a concurrency control method provided in Embodiment 1 of the present invention. This embodiment is applicable to resolving the problem of concurrent access conflicts by combining memory bank switching and register read / write operations into an atomic operation through a bus occupancy sustaining signal. This method can be executed by a concurrency control device, which can be implemented in hardware and / or software. This concurrency control device can be configured in electronic devices, such as I2C devices containing multiple banks. Figure 2 As shown in the figure, the concurrency control method provided in this embodiment includes the following steps:

[0042] S110. In response to the atomic operation request of the target thread, the processor sequentially sends a memory area switching instruction and a register operation instruction to the bus controller.

[0043] The target thread can represent a software execution unit that requests an atomic operation, such as a diagnostic thread, a query thread, or other business thread.

[0044] An atomic operation request can be a continuous operation (bank switching + register read / write) request sent by the target thread that requires the processor to guarantee indivisible execution. This request may include parameter information such as device selection (e.g., device identifier, device address), memory location (e.g., bank identifier), and register operation (e.g., read operation, write operation).

[0045] A bank switching instruction refers to an instruction used to switch banks within a device. This instruction may include parameters such as device identifier and bank identifier. A bank is a logical partition within a chip that divides physical registers according to function or address range. Each bank contains a set of registers with specific functions and is identified by a unique Bank ID. To access registers, you must first switch to the target bank before you can read or write to its internal registers.

[0046] Register operation instructions refer to instructions used to perform read / write operations on a specified register. These instructions may include parameter information such as the target register address, operation type, and operation data.

[0047] In this embodiment of the invention, after receiving an atomic operation request from a target thread, the processor parses information such as the target device identifier, target bank identifier, target register address, and operation data from the request. Then, it verifies the legality of the atomic operation request, for example, by checking whether the target device identifier is in the bus mounted device list, and verifying whether the target bank identifier and target register address are within the device address mapping range. If the request is verified, the processor generates corresponding memory area switching instructions and register operation instructions based on the information parsed from the atomic operation request, and sends the instructions to the bus controller for atomic operation execution.

[0048] S120: The bus controller responds to memory area switching instructions and register operation instructions, performs memory area switching operations and generates a bus occupancy maintenance signal, and continuously performs register read and write operations in the target memory area.

[0049] The bus occupancy sustaining signal can refer to a signal used to maintain the occupancy state of the bus, preventing other devices from preempting the bus. By utilizing this bus occupancy sustaining signal, bank switching and several sets of register read / write operations can be performed continuously without interruption, thereby ensuring the integrity and consistency of data transmission. For example, the bus occupancy sustaining signal can include at least the repeat start signal (Sr) in the I2C protocol.

[0050] In this embodiment of the invention, the bus controller can sequentially receive the memory area switching instruction and the register operation instruction sent by the processor, and then execute the corresponding Bank switching operation according to the memory area switching instruction, and generate a bus occupancy maintenance signal to prevent the bus from being preempted by other devices after the Bank switching is completed, which would cause errors in subsequent register read and write operations; then, during the effective period of the bus occupancy maintenance signal, the corresponding register read and write operation is executed according to the register operation instruction until the entire atomic operation is completed.

[0051] Understandably, when there are multiple consecutive register operation instructions, a bus occupancy hold signal is generated after each instruction is completed and an acknowledgement (ACK) signal is received, until the last instruction completes. Specifically, in practical applications, the number of times the bus occupancy hold signal is generated can be dynamically adjusted according to the operation complexity. For example, when a single atomic operation requires performing multiple sets of consecutive actions (such as switching a bank → writing to register A → reading from register B → writing to register C), multiple bus occupancy hold signals can be generated to connect the various sets of operations.

[0052] S130. The processor sends a scheduling request to the operating system so that the operating system can raise the priority of the target thread to the first priority.

[0053] A scheduling request can be a processor-triggered request to adjust the priority of a specified thread. This request may include parameters such as thread identifier and target priority. The first priority can be understood as the highest priority level preset in the operating system (such as real-time priority), ensuring that the target thread can quickly obtain CPU resources.

[0054] In this embodiment of the invention, the processor can determine whether the bus is occupied (i.e., whether the bus controller has generated a bus occupancy sustain signal) by reading the status register of the bus controller. If the bus is detected to be occupied, the processor will send a scheduling request to the operating system to raise the priority of the target thread to the first priority, thereby blocking other threads in the system.

[0055] It's important to understand that in the S120, the bus controller maintains physical bus occupancy through a generated bus occupancy maintenance signal, ensuring that the operation sequence is not interrupted by other bus accesses. However, if the target thread is preempted by a higher-priority thread during operation, the target thread will pause execution, resulting in continuous bus occupancy without subsequent operations, potentially leading to a system deadlock. To address this issue, this solution, while maintaining physical bus occupancy, also ensures the target thread has exclusive access to the CPU by increasing its priority until the atomic operation is completed, thus preventing preemption by other higher-priority threads and improving system reliability.

[0056] S140. The bus controller generates a bus release signal after the atomic operation of the target thread is completed.

[0057] The bus release signal can refer to a signal used to release control of the bus. For example, the bus release signal can include at least the stop signal (P) in the I2C protocol.

[0058] In this embodiment of the invention, the bus controller can continuously monitor whether all atomic operations of the target thread have been completed. For example, it can determine whether all atomic operations have been completed by reading a specific flag bit of the status register. If all are completed, the bus controller will generate a bus release signal to release control of the bus, and can also update the bus status flag bit of the status register to be idle.

[0059] The technical solution of this invention is applied to a concurrent control system including a processor and a bus controller. The processor, in response to an atomic operation request from a target thread, sequentially sends a memory area switching instruction and a register operation instruction to the bus controller. The bus controller, in response to the memory area switching instruction and the register operation instruction, executes the memory area switching operation and generates a bus occupancy maintenance signal, and continuously executes register read / write operations within the target memory area. The processor sends a scheduling request to the operating system to raise the priority of the target thread to the first priority. The bus controller generates a bus release signal after the atomic operation of the target thread is completed. This technical solution binds memory area switching and register read / write operations into an atomic operation by generating a bus occupancy maintenance signal through the bus controller. Simultaneously, the processor triggers the operating system to raise the target thread to the first priority, preventing high-priority threads from preempting the bus. Furthermore, the solution employs a lock-free design, improving system concurrency performance while ensuring the reliability and consistency of data transmission.

[0060] Example 2

[0061] Figure 3 This is a flowchart of a concurrency control method provided in Embodiment 2 of the present invention. It is further optimized and extended based on the above embodiments and can be combined with various optional technical solutions in the above embodiments. For example... Figure 3 As shown in the figure, the concurrency control method provided in this embodiment includes the following steps:

[0062] S210: The processor receives and parses the atomic operation request, and verifies the validity of the atomic operation request.

[0063] In this embodiment of the invention, when the target thread needs to perform an atomic operation (bank switching + register read / write), it can submit an atomic operation request by calling the system interface. After receiving the atomic operation request from the target thread, the processor will parse information such as the target device identifier, target bank identifier, target register address, and operation data from the request, and verify the legality of the request based on the above parsed information, such as checking whether the target device identifier is in the bus mounted device list, and verifying whether the target bank identifier and target register address are within the device address mapping range.

[0064] S220. When the processor determines that the atomic operation request is valid, it writes the generated memory area switching instructions and register operation instructions into the preset instruction queue of the bus controller.

[0065] The preset instruction queue can refer to a queue (hardware FIFO buffer) set up inside the bus controller to temporarily store instructions to be executed. The instructions in the queue are processed in a first-in-first-out (FIFO) order.

[0066] In this embodiment of the invention, after verifying the legality of the atomic operation request of the target thread, the processor generates a corresponding memory area switching instruction based on the target device identifier and target memory area identifier parsed from the atomic operation request, and generates a corresponding register operation instruction based on the target register address and operation data. Then, the processor obtains the write pointer of the preset instruction queue of the bus controller, and writes the generated memory area switching instruction and register operation instruction into the preset instruction queue in a first-in-first-out (FIFO) order, and updates the write pointer of the queue. Subsequently, the bus controller will extract instructions from the queue and execute them.

[0067] Furthermore, if the atomic operation request of the target thread is found to be invalid, the processor will return an error code to the target thread and terminate the operation process.

[0068] S230, the bus controller extracts memory area switching instructions and register operation instructions from the preset instruction queue; the memory area switching instructions include the target device identifier and the target memory area identifier, and the register operation instructions include the target register address and operation data.

[0069] In this embodiment of the invention, the bus controller can continuously monitor the fill status of the preset instruction queue. When the queue is not empty, it will extract the memory area switching instruction and the register operation instruction from the queue, and parse the target device identifier and the target bank identifier from the memory area switching instruction, and parse the target register address and operation data from the register operation instruction.

[0070] S240, the bus controller performs a storage area switching operation according to the target device identifier and the target storage area identifier.

[0071] In this embodiment of the invention, the bus controller can query a preset address mapping table according to the parsed target device identifier, obtain the physical address of the control register of the target device, write the target bank identifier into the bank switching register of the target device, and then wait for the target device to return an acknowledgment signal (ACK).

[0072] S250: After receiving the response signal from the target device, the bus controller generates a repeat start signal as a bus occupancy maintenance signal.

[0073] In this embodiment of the invention, if the bus controller receives an acknowledgment signal (ACK) from the target device, it will control the SDA data line to switch from low to high to low when the SCL clock line is high, so as to generate a repeat start signal (Sr) and use the repeat start signal (Sr) as the bus occupancy sustain signal.

[0074] S260, the bus controller, continuously executes register read and write operations in the target memory area according to the target register address and operation data.

[0075] In this embodiment of the invention, after generating the repeat start signal (Sr), the bus controller can perform the corresponding register read and write operations according to the target register address and operation data. If there are multiple consecutive register operation instructions, the bus controller will execute them sequentially according to the instruction queue order.

[0076] S270. When the processor detects that the bus is occupied, it sends a scheduling request to the operating system through a preset interrupt signal line, so that the operating system responds to the scheduling request and adjusts the priority of the target thread to the highest level in the preset priority category by calling the preset thread scheduling interface.

[0077] The preset interrupt signal line can refer to a dedicated communication line between the processor and the operating system, used to transmit scheduling request interrupt signals. The preset thread scheduling interface can refer to the system call API (Application Programming Interface) provided by the operating system, used to dynamically modify thread priorities. For example, the preset thread scheduling interface may include, but is not limited to, the `sched_setparam` interface and the `sched_setscheduler` interface. The preset priority classification can refer to a priority hierarchy predefined by the operating system, such as 0-99 for real-time priority and 100-139 for normal priority.

[0078] In this embodiment of the invention, S270 specifically includes the following steps:

[0079] S2701. The processor obtains the bus occupancy status by reading the status register of the bus controller;

[0080] S2702. When the processor determines that the bus is busy, it generates a scheduling request and sends the scheduling request to the operating system through a preset interrupt signal line.

[0081] Specifically, the processor can read the bus status flags (such as the BUSY bit) in the bus controller's status register to detect whether the bus is occupied. If it determines that the bus is occupied (e.g., BUSY = 1), it will send a scheduling request to the operating system through a preset interrupt signal line. This request may include parameters such as the target thread identifier and target priority. Then, the interrupt service routine on the operating system side, after capturing the interrupt signal, parses the scheduling request and calls the preset thread scheduling interface to adjust the priority of the target thread to the highest level in the preset priority category. Furthermore, it can immediately trigger a context switch to ensure that the target thread obtains CPU execution rights.

[0082] S280, the bus controller detects whether register read / write operations in the target memory area are completed.

[0083] In this embodiment of the invention, the bus controller can preload an instruction counter, with an initial value of the number of instructions included in the atomic operation (such as 1 Bank switch + N register operations). The counter is decremented by 1 after each instruction is completed (such as after sending a Bank switch command). When the counter reaches zero and there is no error flag, the atomic operation is determined to be completed.

[0084] S290. When the bus controller determines that the register operation is complete, it generates a stop signal as a bus release signal and clears the bus occupancy status flag.

[0085] In this embodiment of the invention, after the bus controller detects that all register operations have been completed, it can control the SDA data line to switch from low level to high level, thereby generating a stop signal (P) to release the bus. At the same time, it can update the bus status flag bit (such as the BUSY bit) in the status register to indicate that the bus is in an idle state.

[0086] Furthermore, based on the above embodiments of the invention, the concurrency control method provided by the embodiments of the present invention further includes:

[0087] The bus controller resets the watchdog timer and configures its timeout period each time a bus occupancy hold signal is generated.

[0088] When the bus controller detects that the watchdog timer has timed out, it forces the generation of a bus release signal.

[0089] The watchdog timer can refer to the hardware timing circuit configured in the bus controller. In this solution, it is used to prevent system deadlock caused by thread crashes / abnormalities.

[0090] In this embodiment of the invention, the bus controller triggers a watchdog timer reset (i.e., clears it to zero) every time it generates a bus occupancy sustain signal (such as the Sr signal). At the same time, it can read a preset timeout period (such as 10ms) from the preset configuration register and write it to the watchdog timeout register. When the bus controller detects that the watchdog timer count exceeds the preset timeout period, it immediately generates a bus release signal and updates the bus status flag in the status register.

[0091] This embodiment improves the system's functional safety level by setting a watchdog timer to ensure the guaranteed release of bus resources in abnormal scenarios.

[0092] To facilitate a better understanding of this solution by those skilled in the art, the concurrency control method proposed in the embodiments of the present invention will be described below through specific examples.

[0093] like Figure 4As shown, taking the SONY deserializer as an example, it needs to send at least two consecutive I2C timing instructions to complete the read / write operation relative to the register. However, after sending the first Bank switching instruction, the I2C bus is released, and other high-priority threads may then preempt the I2C bus to perform other operations.

[0094] For example, such as Figure 5 As shown, after the diagnostic thread of process A completes the Bank1 switch, it releases the I2C bus. However, at this time, the hot-plug detection thread of process A and the query thread of process B, due to their higher priority, will preempt the I2C bus and execute before the register read / write operations of the diagnostic thread. After the hot-plug detection thread and the query thread have finished executing, the Bank (e.g., ...) will be released. Figure 5 The Bank3 register in the diagnostic thread might not be the Bank1 it expects; that is, it might be reading from or writing to the Bank3 register, which is inconsistent with its actual purpose and can lead to functional abnormalities. Simultaneously, the constant contention for the I2C bus between threads results in low operational efficiency.

[0095] To address the aforementioned issues, this solution proposes using a repeating start signal (Sr) to connect multiple operations, combining a bank switch and register read / write into an atomic operation. Simultaneously, during the execution of this atomic operation, the target thread's priority is temporarily adjusted to the highest priority to prevent other high-priority threads from preempting the I2C bus and CPU, ensuring the reliability and consistency of data transmission. Figure 6 As shown, when reading or writing to the registers of the SONY deserializer, the I2C bus is not released after switching banks. Instead, an Sr signal is sent before subsequent register read / write operations are connected. This way, it will not be interrupted by other threads or processes.

[0096] For example, such as Figure 7 As shown, after preempting the I2C bus, the diagnostic thread of process A will maintain its hold on the bus (without directly sending a Stop signal, but using the Sr signal for bus preemption) until it completes all register operations, at which point it will release the bus. Meanwhile, the hot-plug detection thread of process A will be blocked while the diagnostic thread is operating on the registers, until the I2C bus is released, at which point the system will switch to the hot-plug detection thread to continue execution. Similarly, the polling thread of process B will also be blocked while the diagnostic thread of process A is operating on the registers, until the diagnostic thread of process A completes its operations, releases the I2C bus, and waits for system scheduling.

[0097] The technical solution of this invention binds memory area switching and register read / write into an atomic operation by generating a bus occupancy maintenance signal through the bus controller. At the same time, the processor triggers the operating system to promote the target thread to the first priority, avoiding other threads from preempting the bus and avoiding bus conflicts in multi-threaded or multi-process environments. This improves the continuity and consistency of operations and ensures data integrity and reliability. By adopting a lock-free design, the risk of deadlock is avoided, and the system concurrency performance is improved. It can effectively solve the resource contention problem in multi-threaded and multi-process environments, can be optimized according to system requirements, and has high flexibility and scalability.

[0098] Example 3

[0099] Figure 8 This is a schematic diagram of a concurrent control device provided in Embodiment 3 of the present invention. Figure 8 As shown, this device is applied to a concurrent control system that includes a bus controller and a processor, and includes:

[0100] The instruction sending module 31, configured in the processor, is used to send memory area switching instructions and register operation instructions to the bus controller in sequence in response to the atomic operation request of the target thread.

[0101] The bus control module 32, configured in the bus controller, is used to respond to memory area switching instructions and register operation instructions, perform memory area switching operations and generate bus occupancy maintenance signals, and continuously perform register read and write operations in the target memory area;

[0102] The scheduling request module 33, configured in the processor, is used to send a scheduling request to the operating system so that the operating system can raise the priority of the target thread to the first priority.

[0103] The bus release module 34, configured in the bus controller, is used to generate a bus release signal after the atomic operation of the target thread is completed.

[0104] Furthermore, based on the above embodiments of the invention, the instruction sending module 31 includes:

[0105] The request parsing unit is used to receive and parse atomic operation requests, and to verify the validity of atomic operation requests;

[0106] The instruction generation and writing unit is used to write the generated memory area switching instructions and register operation instructions into the preset instruction queue of the bus controller when the atomic operation request is determined to be valid.

[0107] Furthermore, based on the above embodiments of the invention, the bus control module 32 includes:

[0108] The instruction extraction unit is used to extract memory area switching instructions and register operation instructions from a preset instruction queue. The memory area switching instructions include the target device identifier and the target memory area identifier, and the register operation instructions include the target register address and the operation data.

[0109] The storage area switching unit is used to perform a storage area switching operation according to the target device identifier and the target storage area identifier;

[0110] The signal generation unit is used to generate a repeating start signal as a bus occupancy sustaining signal after receiving the response signal from the target device.

[0111] The register operation unit is used to continuously perform register read and write operations in the target memory area according to the target register address and operation data.

[0112] Furthermore, based on the above embodiments of the invention, the scheduling request module 33 includes:

[0113] The scheduling request unit is used to send a scheduling request to the operating system through a preset interrupt signal line when the bus is detected to be occupied, so that the operating system responds to the scheduling request and adjusts the priority of the target thread to the highest level in the preset priority category by calling the preset thread scheduling interface.

[0114] Furthermore, based on the above embodiments of the invention, the scheduling request unit is specifically used for:

[0115] The bus occupancy status can be obtained by reading the status register of the bus controller;

[0116] When the bus is determined to be busy, a scheduling request is generated and sent to the operating system via a preset interrupt signal line.

[0117] Furthermore, based on the above embodiments of the invention, the bus release module 34 includes:

[0118] An operation detection unit is used to detect whether register read / write operations in the target memory area have been completed.

[0119] The bus release unit is used to generate a stop signal as a bus release signal and clear the bus occupancy status flag when the register operation is completed.

[0120] Furthermore, based on the above embodiments of the invention, the concurrency control device further includes:

[0121] The watchdog timer configuration module, located on the bus controller, is used to reset the watchdog timer and configure its timeout period each time a bus occupancy sustain signal is generated.

[0122] The bus forced release module, configured on the bus controller, is used to forcibly generate a bus release signal when the watchdog timer times out.

[0123] The concurrency control device provided in the embodiments of the present invention can execute the concurrency control method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0124] Example 4

[0125] Figure 9 A schematic diagram of an electronic device 40 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0126] like Figure 9 As shown, the electronic device 40 includes at least one processor 41 and a memory, such as a read-only memory (ROM) 42 or a random access memory (RAM) 43, communicatively connected to the at least one processor 41. The memory stores computer programs executable by the at least one processor. The processor 41 can perform various appropriate actions and processes based on the computer program stored in the ROM 42 or loaded into the RAM 43 from storage unit 48. The RAM 43 may also store various programs and data required for the operation of the electronic device 40. The processor 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0127] Multiple components in electronic device 40 are connected to I / O interface 45, including: input unit 46, such as keyboard, mouse, etc.; output unit 47, such as various types of monitors, speakers, etc.; storage unit 48, such as disk, optical disk, etc.; and communication unit 49, such as network card, modem, wireless transceiver, etc. Communication unit 49 allows electronic device 40 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0128] Processor 41 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 41 performs the various methods and processes described above, such as concurrent control methods.

[0129] In some embodiments, the concurrency control method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or mounted on electronic device 40 via ROM 42 and / or communication unit 49. When the computer program is loaded into RAM 43 and executed by processor 41, one or more steps of the concurrency control method described above may be performed. Alternatively, in other embodiments, processor 41 may be configured to execute the concurrency control method by any other suitable means (e.g., by means of firmware).

[0130] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0131] In some embodiments, the concurrency control method may be implemented as a computer program, which is implicitly included in a computer program product. When executed by a processor, the computer program implements the concurrency control method of the present invention. The computer program product can be understood as a software product that primarily implements its solution through a computer program. The computer program used to implement the method of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer program causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer program may be executed entirely on a machine, partially on a machine, partially on a remote machine as a standalone software package, or entirely on a remote machine or server.

[0132] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0133] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0134] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0135] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0136] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0137] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A concurrency control method, characterized in that, The method, applied to a concurrent control system including a processor and a bus controller, comprises: In response to the atomic operation request of the target thread, the processor sequentially sends a memory area switching instruction and a register operation instruction to the bus controller. The bus controller responds to the memory area switching instruction and the register operation instruction by performing a memory area switching operation and generating a bus occupancy maintenance signal, and continuously performing register read and write operations in the target memory area; The processor sends a scheduling request to the operating system, so that the operating system can raise the priority of the target thread to the first priority; The bus controller generates a bus release signal after the atomic operation of the target thread is completed.

2. The method according to claim 1, characterized in that, In response to the atomic operation request of the target thread, the processor sequentially sends a memory area switching instruction and a register operation instruction to the bus controller, including: The processor receives and parses the atomic operation request, and verifies the legality of the atomic operation request; When the processor determines that the atomic operation request is valid, it writes the generated memory area switching instruction and the register operation instruction into the preset instruction queue of the bus controller.

3. The method according to claim 1, characterized in that, The bus controller, in response to the memory area switching instruction and the register operation instruction, performs a memory area switching operation and generates a bus occupancy sustaining signal, and continuously performs register read / write operations within the target memory area, including: The bus controller extracts the memory area switching instruction and the register operation instruction from a preset instruction queue; the memory area switching instruction includes a target device identifier and a target memory area identifier, and the register operation instruction includes a target register address and operation data. The bus controller performs a storage area switching operation according to the target device identifier and the target storage area identifier; After receiving the response signal from the target device, the bus controller generates a repeat start signal as the bus occupancy maintenance signal. The bus controller continuously executes register read and write operations in the target memory area according to the target register address and the operation data.

4. The method according to claim 1, characterized in that, The processor sends a scheduling request to the operating system to cause the operating system to raise the priority of the target thread to the first priority, including: When the processor detects that the bus is occupied, it sends the scheduling request to the operating system through a preset interrupt signal line, so that the operating system responds to the scheduling request and adjusts the priority of the target thread to the highest level in the preset priority category by calling a preset thread scheduling interface.

5. The method according to claim 4, characterized in that, When the processor detects that the bus is occupied, it sends the scheduling request to the operating system via a preset interrupt signal line, including: The processor obtains the bus occupancy status by reading the status register of the bus controller; When the processor determines that the occupancy status is bus busy, it generates the scheduling request and sends the scheduling request to the operating system through the preset interrupt signal line.

6. The method according to claim 1, characterized in that, The bus controller generates a bus release signal after the atomic operation of the target thread is completed, including: The bus controller detects whether register read / write operations in the target memory area are completed; When the bus controller determines that the register operation is complete, it generates a stop signal as a bus release signal and clears the bus occupancy status flag.

7. The method according to claim 1, characterized in that, The method further includes: The bus controller resets the watchdog timer and configures the timeout period of the watchdog timer each time it generates the bus occupancy sustain signal. When the bus controller detects that the watchdog timer has timed out, it forcibly generates the bus release signal.

8. A concurrent control device, characterized in that, An apparatus for use in a concurrent control system comprising a bus controller and a processor, the apparatus comprising: An instruction sending module, configured in the processor, is used to send memory area switching instructions and register operation instructions sequentially to the bus controller in response to an atomic operation request from a target thread. A bus control module, configured in the bus controller, is used to respond to the memory area switching instruction and the register operation instruction, perform memory area switching operation and generate a bus occupancy maintenance signal, and continuously perform register read and write operations in the target memory area; A scheduling request module, configured in the processor, is used to send a scheduling request to the operating system so that the operating system can raise the priority of the target thread to the first priority; A bus release module, configured in the bus controller, is used to generate a bus release signal after the atomic operation of the target thread is completed.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; Bus controller, communicatively connected to the processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor to enable the at least one processor to perform the concurrency control method according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the concurrency control method according to any one of claims 1-7.

11. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the concurrency control method as described in any one of claims 1-7.

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