Multi-platform hybrid power model simulation method, system and computer device

Abstract

The application relates to a multi-platform mixed power model simulation method, system and computer equipment. The method comprises the following steps: determining a next time synchronization point of a power model and writing a state signal and the time synchronization point into a first shared memory, providing an accurate benchmark for discrete system simulation; triggering the discrete system to advance according to the time synchronization point and updating a second shared memory, guaranteeing simulation timing and data synchronization; reading the updated target simulation signal in the second shared memory to continue power model simulation, ensuring a circulating dynamic updating process of "benchmark setting-simulation advancing-data feedback", realizing collaborative simulation under non-real-time multi-platform mixing, and improving overall simulation synchronization and accuracy.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power system analysis, in particular to a multi-platform hybrid power model simulation method and system and a computer device. BACKGROUND

[0002] With the sweeping tide of digitalization and intelligentization, the traditional power system is accelerating the transformation to a smart grid, and its landmark feature is the deep integration of the power system and the network communication system, which interweave to form a complex power information physical system (CPS). To cope with the problems arising in operation control, information interaction and other aspects, new and stringent requirements are put forward for simulation technology. If a joint simulation platform of the power system and the network communication system is to be built, the problem of time synchronization needs to be solved.

[0003] Currently, real-time hybrid digital simulation of the power CPS is usually used to achieve the same time axis synchronization, but this requires high computational performance of the simulation hardware, high cost of a single node, limited system scale that can be simulated, and low efficiency in large time scale simulation due to the real-time nature of the simulation time. SUMMARY

[0004] Therefore, the present application aims to drive the time synchronization and the simulation progress uniformly to jointly complete the construction of a non-real-time hybrid simulation system of the power CPS, so as to eliminate the inherent time delay introduced by the network communication equipment and break through the scale limitation of real-time simulation.

[0005] In a first aspect, the present application provides a multi-platform hybrid power model simulation method. The multi-platform includes a continuous system and a discrete system, and the method is applied to the continuous system and includes the following steps.

[0006] determining a next time synchronization point at the current simulation time of the power model, and writing a state signal associated with the power model and the time synchronization point into a first shared memory;

[0007] triggering the discrete system to proceed with simulation according to the time synchronization point, and updating a second shared memory according to a target digital signal read from the first shared memory;

[0008] reading a target analog signal from the second shared memory associated with the discrete system, and continuing the simulation of the power model according to the target analog signal.

[0009] In one embodiment, the multi-platform further comprises a coordination controller; the method further comprises: sending a semaphore of communication between processes to the coordination controller; when the discrete system monitors occurrence of the semaphore, triggering the discrete system to simulate and advance according to the time synchronization point, and sending a confirmation signal to the coordination controller; when receiving the confirmation signal fed back by the coordination controller, reading the target analog signal from the second shared memory.

[0010] In one embodiment, after sending the semaphore of communication between processes to the coordination controller, the execution process of the coordination controller comprises: non-blocking detection through the semaphore, issuing a time advance instruction to the discrete system when the first shared memory is in an idle state; determining the confirmation signal fed back by the discrete system based on a preset waiting mechanism.

[0011] In one embodiment, determining the confirmation signal fed back by the discrete system based on the preset waiting mechanism comprises: starting a high-precision timer and determining an absolute time point; non-blocking polling monitoring according to the absolute time point to determine an average delay when the feedback of the discrete system is acquired; dynamically adjusting a waiting duration according to the average delay to determine the confirmation signal fed back by the discrete system according to the waiting duration.

[0012] In one embodiment, triggering the discrete system to simulate and advance according to the time synchronization point, and updating the second shared memory according to the target digital signal read from the first shared memory comprises: pausing current event processing of the discrete system, and determining a target event corresponding to the time synchronization point; reading a target digital signal associated with the target event from the first shared memory, and triggering the discrete system to execute the target event to obtain an execution result; updating the second shared memory associated with the discrete system according to the execution result.

[0013] In one embodiment, scheduling of the first shared memory and the second shared memory is implemented through a memory manager; the first shared memory represents a shared memory in which an analog signal is written after analog-digital conversion according to a mapping file configuration, realizing writing of the analog signal of the continuous system and reading of the digital signal of the discrete system; the second shared memory represents a shared memory in which a digital signal is written after digital-analog conversion according to a mapping file configuration, realizing writing of the digital signal of the discrete system and reading of the analog signal of the continuous system.

[0014] In a second aspect, the application further provides a multi-platform hybrid power model simulation system. The system comprises a continuous system, a discrete system, a first shared memory and a second shared memory, wherein:

[0015] The continuous system is configured to determine a next time synchronization point of current simulation of the power model, and write a state signal associated with the power model and the time synchronization point into the first shared memory.

[0016] a discrete system configured to simulate the advancement according to the time synchronization point and update the second shared memory according to the target digital signal read from the first shared memory;

[0017] a continuous system further configured to read the target analog signal from the second shared memory associated with the discrete system and continue the simulation of the power model according to the target analog signal.

[0018] In one embodiment, the system further comprises a protocol application module, a protocol stack, a virtual network, a smart device and a protocol processing module, wherein: the protocol application module and the protocol stack are configured to convert the target analog signal into a data set and a protocol message respectively and send them to the virtual network; the smart device is configured to implement the interaction with the virtual network and complete the data sampling and structure conversion; and the protocol processing module is configured to analyze the data set and trigger the simulation process update of the power model.

[0019] In a third aspect, the present application further provides a computer device. The computer device comprises a memory and a processor, the memory stores a computer program, and the processor implements the steps of the above multi-platform mixed power model simulation method when executing the computer program.

[0020] In a fourth aspect, the present application further provides a computer readable storage medium. The computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the above multi-platform mixed power model simulation method.

[0021] The above multi-platform mixed power model simulation method, system, computer device and storage medium first determine the next time synchronization point of the power model and write the state signal and the time synchronization point into the first shared memory to provide a precise benchmark for the discrete system simulation; then trigger the discrete system to advance according to the time synchronization point and update the second shared memory to ensure the simulation timing and data synchronization; finally, read the updated target analog signal in the second shared memory to continue the power model simulation, ensuring the dynamic update process of "benchmark setting-simulation advancement-data feedback", realizing the collaborative simulation under the non-real-time multi-platform mixed mode, and improving the overall simulation synchronization and accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 Flowchart of the implementation method of the CPS non-real-time mixed simulation system in one embodiment;

[0023] Figure 2 Flowchart of the multi-platform mixed power model simulation method in one embodiment;

[0024] Figure 3 Time and data synchronization flowchart of the continuous system in one embodiment;

[0025] Figure 4 Flowchart for a process performed by a coordination controller in one embodiment;

[0026] Figure 5 Flowchart for time and data synchronization of a discrete system in one embodiment;

[0027] Figure 6 Schematic diagram of a multi-platform hybrid power model simulation system in one embodiment;

[0028] Figure 7 Internal structure diagram of a computer device in one embodiment. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0030] The present application designs a multi-platform hybrid power model simulation system, which comprises a continuous system, a discrete system, a first shared memory and a second shared memory, wherein: the continuous system is configured to determine a next time synchronization point in the current simulation of the power model, and write a state signal associated with the power model and the time synchronization point into the first shared memory; the discrete system is configured to perform simulation promotion according to the time synchronization point, and update the second shared memory according to a target digital signal read from the first shared memory; and the continuous system is further configured to read a target analog signal from the second shared memory associated with the discrete system, and continue the simulation of the power model according to the target analog signal.

[0031] Among them, the power system in the power information physical system is usually a continuous system, and its mathematical model is described by a system of differential equations. In the simulation process, the system of differential equations is usually discretized into a system of difference equations, and a recursive formula is used for solving. The solver sequentially arranges the system state solved at each time step to obtain a trajectory representing the dynamic change process of the system. The network communication system in the power information physical system is usually a discrete system. For a discrete event system, its model is more described in the form of a logic equation, a state machine and other forms suitable for computer numerical solution. Unlike the time axis of the continuous system, the time axis of the discrete time system is a coordinate of a plurality of events, and is also called an event axis. Some of these events occur at fixed time points and are predetermined, but more of them are random events, and their occurrence time cannot be determined before the simulation is performed.

[0032] Specifically, as shown in Figure 1 , the continuous system comprises a continuous system simulation module 101, a time synchronization module 102 and a shared memory module 103. The continuous system simulation module 101 is configured to determine a next time synchronization point in the current simulation of the power model, and write a state signal associated with the power model and the time synchronization point into the first shared memory. The time synchronization module 102 is configured to read a target analog signal from the second shared memory associated with the discrete system, and continue the simulation of the power model according to the target analog signal. The shared memory module 103 is configured to write the state signal associated with the power model and the time synchronization point into the first shared memory, and read the target digital signal from the first shared memory. Figure 1A flow chart of an implementation method of a power cyber physical system (CPS) non-real-time hybrid simulation system. A power system, i.e., a continuous system, is built by, for example, Simulink (a visual simulation platform) of Matlab; a network communication system, i.e., a discrete system, is built by, for example, an OMNet++ platform (a multi-protocol network simulation platform) and an INET standard protocol model library. The continuous system built based on the visual simulation platform can realize multi-domain simulation and model-based design; support system design, simulation, automatic code generation, and continuous testing and verification of embedded systems; and provide a graphical editor, a customizable module library, and a solver, enabling dynamic system modeling and simulation. The discrete system built based on the multi-protocol network simulation platform has a perfect graphical interface and an embeddable simulation kernel, and can be used for simulation of distributed systems and communication networks.

[0033] In one embodiment, as shown in Figure 2 , a multi-platform hybrid power model simulation method is provided, which is described below by taking the continuous system in Figure 1 as an example and including the following steps:

[0034] Step 202: Determine the next time synchronization point of the current simulation of the power model, and write the state signals associated with the power model and the time synchronization point into the first shared memory.

[0035] The power model represents a to-be-simulated model built for, for example, smart grid security attack and defense drills, new energy station grid connection communication verification, and distribution network self-healing control strategy testing.

[0036] Specifically, as shown in Figure 3 , Figure 3 is a time and data synchronization flow chart of the continuous system. The Simulink S-Function (system function module) in the continuous system obtains the current time t before the start of each simulation step, calculates the next time synchronization point , where is the simulation step length of the power system. Then, the time synchronization point and the state signals to be collected and sent by the intelligent electronic device are written into the first shared memory.

[0037] In one embodiment, the scheduling of the first shared memory and the second shared memory is realized by a memory manager; the first shared memory represents a shared memory into which analog signals are written after analog-digital conversion according to a mapping file configuration, realizing writing of analog signals of the continuous system and reading of digital signals of the discrete system; and the second shared memory represents a shared memory into which digital signals are written after digital-analog conversion according to a mapping file configuration, realizing writing of digital signals of the discrete system and reading of analog signals of the continuous system.

[0038] In particular, referring to Figure 1 As shown in the figure, the first shared memory is a kind of analog-digital conversion shared memory, which is implemented by an analog-digital conversion module. The analog-digital conversion module developed in Simulink completes the sampling and quantization of analog signals in the power system. Since the differential equation model describing the continuous system is often discretized into difference equations for solving, the system state is calculated by advancing in steps, which means that at the end of each step, the sampling and quantization of the discretized state of the power system have been completed. The analog-digital conversion module only needs to write the state signal to be sent according to the configuration of the mapping file into the named first shared memory. That is, the first shared memory corresponding to the analog-digital conversion module of the secondary side intelligent electronic device of the power system is written by the power system on the Simulink side, and the network communication system on the OMNet++ side is responsible for reading.

[0039] Similarly, the second shared memory is a kind of digital-analog conversion shared memory, which is implemented by a digital-analog conversion module. Since the network communication system itself is a discrete system, the signal received by the intelligent electronic device (IED device) through the network communication system is a discrete digital signal, which can be written into the named second shared memory corresponding to the digital-analog conversion module. Before each simulation step of the power system simulated by Simulink, the value in the second shared memory corresponding to the digital-analog conversion module is read as the state signal to be input by the intelligent electronic device in the current simulation step. That is, the second shared memory corresponding to the digital-analog conversion module of the secondary side intelligent electronic device of the power system is written by the network communication system on the OMNet++ side, and the power system on the Simulink side is responsible for reading.

[0040] In one embodiment, the shared memory is implemented by inter-process communication technology, which can achieve a delay of <1μs.

[0041] In step 204, the discrete system is triggered to simulate and advance according to the time synchronization point, and the second shared memory is updated according to the target digital signal read from the first shared memory.

[0042] In particular, referring to Figure 3 As shown in the figure, the continuous system triggers the discrete system to perform event jumping by publishing a semaphore for inter-process communication, so that the discrete system simulates and advances according to the time synchronization point and the target digital signal read from the first shared memory, and finally updates the second shared memory according to the execution result. At this time, the continuous system also synchronously advances the simulation process of the power model, and blocks and waits for the confirmation signal fed back by the discrete system.

[0043] In step 206, the target analog signal is read from the second shared memory associated with the discrete system, and the simulation of the power model is continued according to the target analog signal.

[0044] In particular, referring toFigure 3 As shown, the update writing of the digital signal in the second shared memory has been completed by the discrete system, and the system function module in the continuous system continues to read the second shared memory maintained by the digital-analog conversion module of the intelligent electronic device, reads the target analog signal converted therefrom, continuously maintains and updates the first shared memory, and serves as a new input signal of the continuous system, thereby realizing the update and continuous simulation of the power model.

[0045] In one embodiment, with reference to Figure 1 As shown, the update writing of the digital signal in the second shared memory has been completed by the discrete system, and the system function module in the continuous system continues to read the second shared memory maintained by the digital-analog conversion module of the intelligent electronic device, reads the target analog signal converted therefrom, continuously maintains and updates the first shared memory, and serves as a new input signal of the continuous system, thereby realizing the update and continuous simulation of the power model.

[0046] In the above multi-platform hybrid power model simulation method, the next time synchronization point of the power model is determined and written into the first shared memory together with the state signal and the time synchronization point, thereby providing a precise reference for the discrete system simulation; then the discrete system is triggered to advance according to the time synchronization point and update the second shared memory, thereby ensuring the synchronization of the simulation time sequence and data; finally, the updated target analog signal in the second shared memory is read to continue the simulation of the power model, thereby ensuring the dynamic update process of "reference setting-simulation advancement-data feedback", realizing the collaborative simulation under the non-real-time multi-platform hybrid, and improving the overall simulation synchronization and accuracy.

[0047] In one embodiment, the multi-platform further includes a coordination controller. The above method further includes: sending the semaphore of the communication between the processes to the coordination controller; when the discrete system monitors the occurrence of the semaphore, triggering the discrete system to advance the simulation according to the time synchronization point, and sending an acknowledgement signal to the coordination controller; and when receiving the acknowledgement signal fed back by the coordination controller, reading the target analog signal from the second shared memory.

[0048] In detail, with reference to Figure 3As shown, the continuous system sends the semaphore of communication between processes to the coordination controller after triggering the memory manager. The discrete system on the OMNet++ side monitors the semaphore and waits for the semaphore to occur, and then advances the discrete system simulation time to the time synchronization point. After the discrete system simulates and executes according to the time synchronization point and the target digital signal read from the first shared memory, an acknowledgement signal is sent to the coordination controller. When the acknowledgement signal fed back by the coordination controller is received, the target analog signal is read from the second shared memory maintained by the digital-analog conversion module of the intelligent electronic device.

[0049] In this embodiment, the communication semaphore of each process is sent to the coordination controller, so that the centralized delivery of the running state and interaction demand of the discrete process is realized. When the discrete system monitors the semaphore and triggers the simulation according to the time synchronization point, the timing accuracy of the simulation process is ensured. The synchronous sending of the acknowledgement signal by the discrete system to the coordination controller enables the coordination center to grasp the simulation progress in real time. After the process receives the acknowledgement signal fed back by the coordination controller, the target analog signal is read from the second shared memory, so that the reliability of subsequent data reading is ensured.

[0050] In one embodiment, after the semaphore of communication between processes is sent to the coordination controller, the execution process of the coordination controller includes: non-blocking detection through the semaphore, issuing a time advance instruction to the discrete system when the first shared memory is in an idle state; and determining the acknowledgement signal fed back by the discrete system based on a preset waiting mechanism.

[0051] The coordination controller is the central decision system between the continuous system on the Simulink side and the discrete system on the OMNeT++ side, and undertakes the following functions: time synchronization arbitration, ensuring that the simulation clocks of the power system (continuous time) and the communication system (discrete event) are strictly aligned; data exchange management, controlling the read-write permission and transmission timing of the shared memory; and abnormal state processing, detecting and recovering the synchronization failure scene.

[0052] Specifically, as shown in FIG. 2, the execution process of the coordination controller includes the following steps. Figure 4 Figure 4 FIG. 3 is a flowchart of the execution process of the coordination controller. When the power system starts a new simulation step, non-blocking detection of the shared memory is performed through the semaphore, for example, the first shared memory (BufferA) is idle, indicating that data needs to be written, and the second shared memory (BufferB) has data, indicating that data needs to be read. When the buffer state of the shared memory is idle, the state signal associated with the power model needs to be written. At this time, the continuous system issues a time advance instruction to the discrete system through ZMQ (a high-performance asynchronous message communication library), that is, issues the timestamp of the time synchronization point to the discrete system, so that the discrete system determines the acknowledgement signal fed back by the discrete system based on a preset waiting mechanism.

[0053] ​In the embodiment, the non-blocking detection by the semaphore can realize real-time sensing of the state of the shared memory without interrupting other operations of the system, avoiding the efficiency loss caused by the blocking detection due to continuous occupation of resources. The time advance instruction is sent to the discrete system, which can ensure the timeliness and accuracy of the instruction sending. The confirmation signal fed back by the discrete system is determined based on the preset waiting mechanism, which can standardize the waiting process of the signal feedback and avoid the system response confusion caused by irregular waiting.

[0054] In one embodiment, the data interaction between the digital signal and the analog signal is realized based on the TCP / IP socket mode, and a socket client module is developed in the continuous system on the Simulink side, and the discrete system on the OMNeT++ side is constructed into a socket server.

[0055] In one embodiment, the confirmation signal fed back by the discrete system is determined based on the preset waiting mechanism, including starting a high-precision timer and determining an absolute time point, non-blocking polling monitoring according to the absolute time point to determine the average delay when the feedback of the discrete system is obtained, and dynamically adjusting the waiting time according to the average delay to determine the confirmation signal fed back by the discrete system according to the waiting time.

[0056] Specifically, the continuous system starts a high-precision timer to determine the wake-up at the next absolute time point in each cycle, ensuring that the control / sending period is strictly fixed. By listening to the ZMQ ACK channel (non-blocking polling monitoring mode), it is determined whether the confirmation signal ACK fed back by the discrete system is received, and if so, the time of receiving is recorded and the average delay is updated. The timeout threshold of waiting is dynamically adjusted in the following manner to obtain the waiting time length timeout = max (1.5 x average delay, 200 μs). If the timeout is triggered, the exception handling is triggered, and if the confirmation signal fed back by the discrete system is received, the target analog signal is read from the second shared memory associated with the network communication system.

[0057] In the embodiment, the high-precision timer is started to determine the absolute time point, providing an accurate reference for delay monitoring. Non-blocking polling is performed to accurately calculate the average delay of the feedback of the discrete system. The waiting time is dynamically adjusted according to the actual feedback speed, which can prevent false positives and waste, and finally accurately determine the confirmation signal to ensure accurate and efficient interaction.

[0058] In one embodiment, the trigger discrete system simulates the advancement according to the time synchronization point, and updates the second shared memory according to the target digital signal read from the first shared memory, comprising: suspending the current event processing of the discrete system, and determining the target event corresponding to the time synchronization point; reading the target digital signal associated with the target event from the first shared memory, and triggering the discrete system to execute the target event, obtaining the execution result; updating the second shared memory associated with the discrete system according to the execution result.

[0059] Specifically, as shown in Figure 5 , Figure 5 is a time and data synchronization flowchart of the discrete system. When determining the target time of event processing, that is, the time synchronization point, the OMNet++ simulation kernel in the discrete system reads the target digital signal from the first shared memory maintained by the analog-digital conversion module. Then the discrete system starts the current event processing, quickly advances the simulation clock to the time synchronization point, and processes all target events corresponding to the time synchronization point, obtaining the execution result. When waiting for external time advancement, high-precision waiting can also be performed according to the 100 μs polling interval to avoid busy waiting. Finally, the discrete system updates the second shared memory maintained by the digital-analog conversion module according to the execution result, and feeds back the confirmation signal to the coordination controller.

[0060] In this embodiment, the current event processing of the discrete system is first suspended and the target event of the time synchronization point is locked to avoid event conflict interference; then the digital signal of the target event in the first shared memory is read to ensure accurate execution; and after the result of triggering the execution of the target event is obtained, the second shared memory is updated to realize event processing focusing and data synchronization, and to guarantee the execution accuracy of the discrete system and the data timeliness.

[0061] In one embodiment, the discrete system can use a fixed time step (such as 10 ms) to poll the signals.

[0062] In one embodiment, the system further comprises a protocol application module, a protocol stack, a virtual network, an intelligent device, and a protocol processing module, wherein: the protocol application module and the protocol stack are used to convert the target analog signal into a data set and a protocol message respectively, and send them to the virtual network; the intelligent device is used to realize interaction with the virtual network and complete data sampling and structure conversion; and the protocol processing module is used to analyze the data set and trigger the simulation process update of the power model.

[0063] The structure of the analog-digital conversion shared memory can include a timestamp, three-phase voltage, three-phase current, circuit breaker state, data quality flag, check code, etc. The structure of the digital-analog conversion shared memory can include a command type (0: no 1: open 2: close), device identification, validity period, maximum 10 concurrent commands, etc. Through the analog-digital conversion shared memory, the digital-analog conversion shared memory, and the participation of the coordination controller, combined with, for example, the GOOSE protocol under the IEC61850 standard, data interaction during offline non-real-time hybrid simulation of the power system and the network communication system can be completed.

[0064] Specifically, as shown in Figure 6 , Figure 6 is a schematic diagram of a multi-platform hybrid power model simulation system. The network communication system will first be initialized, including connecting the shared memory, loading the device mapping configuration based on the mapping rule of the XML configuration, creating the GOOSE publisher and registering the subscription callback, etc. When reading, for example, the state signal of the power model from the analog-digital conversion shared memory, the protocol application module and the protocol stack are used to convert the target analog signal into a GOOSE data set and a GOOSE protocol message, respectively, and send them to the virtual network and set the next synchronization. The protocol message structure generation process includes creating a GOOSE message that conforms to IEC61850-8-1, setting the protocol header, adding the data set, and setting the time parameter. That is, the custom of the GOOSE message structure and the support of multiple protocol parallel processing are realized.

[0065] Then the data mapping between the network communication system and the power system is completed, and the time synchronization is completed. The specific process includes obtaining the time synchronization point and executing the event jump by monitoring the semaphore sent by the coordination controller to process the execution of all target events corresponding to the time synchronization point. The protocol processing module will be used to parse the data set and trigger the simulation process update of the power model by writing to the digital-analog conversion shared memory and triggering the control instruction during the execution process of the target event.

[0066] In this embodiment, the protocol application module and the protocol stack convert the target analog signal into a data set and a protocol message and send them to the virtual network, ensuring subsequent data transmission; the intelligent device interacts with the virtual network to complete data sampling and structure conversion, ensuring data adaptability; the protocol processing module parses the data set to trigger the power model simulation update, ensuring the accuracy of the power model simulation data and the real-time of the process.

[0067] In summary, the application provides an implementation method of a power information physical system non-real-time hybrid simulation system based on time synchronization, which is driven by time synchronization and simulation progress to jointly complete the construction of the power CPS non-real-time hybrid simulation system, so as to eliminate the inherent time delay introduced by the network communication equipment, break through the scale limitation of real-time simulation (support > 500 nodes), and realize the microsecond-level synchronization of continuous systems (power systems) and discrete systems (network communication systems). The microsecond-level synchronization mechanism ensures the asynchronous advancement driven by the timestamp (jump of OMNet++ event execution) and eliminates the read-write conflict of double-buffer shared memory. The application also realizes transparent device mapping based on the dynamic binding between power and communication equipment, supports 1:N complex mapping relationship, and realizes transparent device mapping.

[0068] Therefore, the technical scheme of the application is suitable for power companies, energy management agencies, smart grid operators, and scientific research institutions engaged in power system design, testing and optimization, and can realize smart grid security attack and defense drills, new energy station grid-connected communication verification, distribution network self-healing control strategy testing, power Internet of Things protocol compatibility testing, substation automation system reliability evaluation, etc. It can support one-year power grid operation scenarios to be completed in 24 hours; the hardware cost is reduced by 85% (2 million to 300,000 general servers); the development cycle is shortened by 70% (from 12 months to 3.5 months). The application value can compress the new energy station testing period by 83% (3 months to 2 weeks) and reduce the cost of power grid attack and defense drills to 10% of the traditional scheme.

[0069] It should be understood that, although each step in the flowchart involved in each of the above embodiments is shown in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart involved in each of the above embodiments can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0070] Based on the same inventive concept, the application embodiments also provide a multi-platform hybrid power model simulation device for implementing the above-mentioned multi-platform hybrid power model simulation method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more multi-platform hybrid power model simulation device embodiments provided below can refer to the limitations of the multi-platform hybrid power model simulation method in the above text, which will not be repeated here.

[0071] In one embodiment, a multi-platform hybrid power model simulation device is provided, comprising: a first shared memory writing module, a second shared memory updating module, and a power model simulation module, wherein:

[0072] The first shared memory writing module is configured to determine a next time synchronization point in a current simulation of the power model, and write a state signal associated with the power model and the time synchronization point into the first shared memory.

[0073] The second shared memory updating module is configured to trigger the discrete system to simulate and advance according to the time synchronization point, and update the second shared memory according to the target digital signal read from the first shared memory.

[0074] The power model simulation module is configured to read the target analog signal from the second shared memory associated with the discrete system, and continue the simulation of the power model according to the target analog signal.

[0075] The above-mentioned modules in the multi-platform hybrid power model simulation can be realized by software, hardware, or a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to the above-mentioned modules.

[0076] In one embodiment, a computer device is provided, which can be a server, and the internal structure diagram thereof can be as shown in Figure 7 The computer device comprises a processor, a memory, an input / output interface (I / O), and a communication interface. The processor, the memory, and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The database of the computer device is configured to store digital signals and analog signals. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to communicate with external terminals through a network connection. The computer program is executed by the processor to implement a multi-platform hybrid power model simulation method.

[0077] Those skilled in the art can understand that, Figure 7The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0078] In an embodiment, a computer device is also provided, including a memory and a processor. The memory stores a computer program. The processor executes the computer program to implement the steps in the above method embodiments.

[0079] In an embodiment, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the steps in the above method embodiments.

[0080] In an embodiment, a computer program product or computer program is provided, which includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium. The processor executes the computer instructions to cause the computer device to perform the steps in the above method embodiments.

[0081] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magnetic random access memory (MRAM), ferroelectric memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0082] Any combination of the technical features of the above embodiments can be made. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0083] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A multi-platform hybrid power model simulation method, characterized in that, The multi-platform approach includes continuous and discrete systems, and the method is applied to continuous systems, including: Determine the next time synchronization point during the current simulation of the power model, and write the state signal associated with the power model and the time synchronization point into the first shared memory; The discrete system is triggered to perform simulation progress according to the time synchronization point, and the second shared memory is updated according to the target digital signal read from the first shared memory; The target analog signal is read from the second shared memory associated with the discrete system, and the simulation of the power model is continued based on the target analog signal; The scheduling of the first shared memory and the second shared memory is implemented through a memory manager; The first shared memory represents the shared memory that the analog signal is written to according to the mapping file configuration after analog-to-digital conversion, realizing the writing of analog signals in continuous systems and the reading of digital signals in discrete systems; The second shared memory represents the shared memory that is written to after digital signals are converted from digital to analog according to the mapping file configuration, enabling the writing of digital signals to discrete systems and the reading of analog signals to continuous systems.

2. The method according to claim 1, characterized in that, The multi-platform also includes a coordination controller; the method further includes: Send semaphores for inter-process communication to the coordination controller; When the discrete system detects the occurrence of the signal, it triggers the discrete system to perform simulation progress according to the time synchronization point and sends an acknowledgment signal to the coordinating controller. When an acknowledgment signal is received from the coordinating controller, the target analog signal is read from the second shared memory.

3. The method according to claim 2, characterized in that, After sending semaphores for inter-process communication to the coordination controller, the execution process of the coordination controller includes: Non-blocking detection is performed using the semaphore. When the first shared memory is in an idle state, a time advance instruction is issued to the discrete system. Based on a preset waiting mechanism, the confirmation signal of the discrete system feedback is determined.

4. The method according to claim 3, characterized in that, The determination of the acknowledgment signal fed back by the discrete system based on the preset waiting mechanism includes: Start the high-precision timer and determine the absolute time point; Non-blocking polling monitoring is performed based on the absolute time point to determine the average delay when the feedback from the discrete system is obtained. The waiting time is dynamically adjusted based on the average delay to determine the confirmation signal fed back by the discrete system based on the waiting time.

5. The method according to any one of claims 1 to 4, characterized in that, Triggering the discrete system to perform simulation progression according to the stated time synchronization point, and updating the second shared memory based on the target digital signal read from the first shared memory, including: Pause the current event processing of the discrete system and determine the target event corresponding to the time synchronization point; Read the target digital signal associated with the target event from the first shared memory, and trigger the discrete system to execute the target event to obtain the execution result; Update the second shared memory associated with the discrete system based on the execution result.

6. A multi-platform hybrid power model simulation system, characterized in that, For implementing the method of any one of claims 1 to 5, the system comprises a continuous system, a discrete system, a first shared memory, and a second shared memory, wherein: A continuous system is used to determine the next time synchronization point during the current simulation of the power model, and writes the state signal associated with the power model and the time synchronization point into the first shared memory; A discrete system for performing simulation progression according to the time synchronization point and updating the second shared memory based on the target digital signal read from the first shared memory; The continuous system is also used to read the target analog signal from the second shared memory associated with the discrete system and to continue the simulation of the power model based on the target analog signal.

7. The system according to claim 6, characterized in that, The system also includes a protocol application module, a protocol stack, a virtual network, smart devices, and a protocol processing module, wherein: The protocol application module and protocol stack are used to convert the target analog signal into a dataset and protocol messages, respectively, and send them to the virtual network; The intelligent device is used to interact with the virtual network and perform data sampling and structure transformation; The protocol processing module is used to parse the dataset and trigger the simulation process update of the power model.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

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