Wiring path determination method and device based on AI constraint solution

Abstract

The invention discloses a wiring path determination method and device based on AI constraint solution, and the method comprises the steps: carrying out the global design rule violation detection of an initial wiring path corresponding to each to-be-wired network, and obtaining the wiring path of each to-be-wired network based on the global design rule violation detection result and the use condition of wiring resources; constructing a selectable wiring path in a directed acyclic graph form or a selectable wiring path in a wiring tree form; and generating a corresponding conflict constraint and a communication constraint for each selectable wiring path, solving the conflict constraint and the communication constraint by using a preset solver, and determining the selectable wiring path corresponding to a successful solving result as a target wiring path corresponding to the network to be wired. According to the wiring path determination method based on AI constraint solution, the wiring problem is converted into the logic solution problem of the solver, the method does not depend on specific network arrangement, the parameter adjustment process is avoided, the key wiring resource allocation problem is effectively solved, and the wiring process is more efficient.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, specifically to a routing path determination method based on AI constraint solving. This application also relates to a routing path determination device, electronic device, and computer-readable storage medium based on AI constraint solving. Background Technology

[0002] Very Large Scale Integration (VLSI) is a technology that integrates millions of electronic components (transistors, capacitors, resistors, etc.) onto a single chip. VLSI physical design is the process of translating the logic design of a circuit into its actual geometric layout, enabling a factory to manufacture it on a semiconductor wafer. The VLSI physical design process is divided into several sub-steps, including placement, clock network design, timing optimization, and routing.

[0003] In the field of cabling, during the cabling process, all pins in each net must be connected by wires. Wires between different nets cannot be short-circuited or open-circuited. At the same time, multiple objectives need to be optimized while meeting many complex physical design rules. Optimization objectives include total wire length, number of vias, timing critical path length, etc.

[0004] Existing routing methods all suffer from the Design Rule Violation Cleanup Challenge, specifically as follows: Some methods rely on a fixed order of all networks to be routed and perform routing according to this fixed order. This method makes it easier for networks that are routed first to obtain critical routing resources, thus making it easier for networks that are routed later to become congested, leading to an unsolvable global routing problem. Some methods use heuristic algorithms (such as simulated annealing, genetic algorithms, etc.) during the routing process. This method may block the necessary paths of other networks while providing routing resources for one network. Some methods rely on the transformation parameter (cost parameter) from Design Rule Violation (DRV) to path cost. This parameter largely determines the effectiveness of the algorithm, and the applicable cost parameter may be inconsistent for different layout designs. Summary of the Invention

[0005] This invention provides a routing path determination method based on AI constraint solving, a routing path determination device based on AI constraint solving, an electronic device, and a computer-readable storage medium, to solve the problem that existing routing methods cannot effectively solve the problem of clearing design rule violations.

[0006] To solve or partially solve the above-mentioned technical problems, according to one aspect of the present invention, a wiring path determination method based on AI constraint solving is provided, comprising:

[0007] Global design rule violation detection is performed on the initial routing paths corresponding to each network to be routed. Based on the results of the global design rule violation detection and the usage of routing resources, optional routing paths in the form of directed acyclic graphs or optional routing paths in the form of routing trees are constructed. In any of the optional routing paths, all pins of the network to be routed are connected and violation information is avoided.

[0008] For each of the optional routing paths, corresponding conflict constraints and connectivity constraints are generated, and the conflict constraints and connectivity constraints are solved using a preset solver. The optional routing path corresponding to the successfully solved result is determined as the target routing path for the network to be routed.

[0009] In one implementation, the step of constructing optional routing paths in the form of a directed acyclic graph or a routing tree based on the results of global design rule violation detection and the usage of routing resources includes:

[0010] If the network to be wired meets one of the following conditions, then an optional wiring path in the form of a wiring tree should be constructed, and during the construction process, it must be ensured that a wiring tree connects all nodes of the same network to be wired:

[0011] The network to be cabled contains only one DRC violation identifier;

[0012] Although the network to be cabled contains multiple DRC violation identifiers, the number of optional cabling paths that can be transformed and combined based on these multiple DRC violation identifiers is less than the maximum number of cabling trees;

[0013] The network to be wired is on a time-critical path;

[0014] When the network to be wired does not meet all of the above conditions, an optional wiring path in the form of a directed acyclic graph is constructed. The constructed DAG must ensure that the DAG connects all nodes of the same network to be wired.

[0015] In one implementation, the method further includes: generating an initial wiring path for the network to be wired in response to the network being divided into a partially connected state or an unwired state.

[0016] In one implementation, obtaining the initial wiring path corresponding to each network to be wired includes: in response to the network to be wired being in a fully connected state, correcting the fully connected network to be wired to obtain the initial wiring path.

[0017] In one implementation, the method further includes: generating corresponding conflict constraints and connectivity constraints for the initial routing path in response to the initial routing path not containing violation information.

[0018] In one implementation, before generating conflict constraints and connectivity constraints for the optional routing paths, the method further includes filtering the optional routing paths.

[0019] In one implementation, the method further includes converting the conflict constraints and connectivity constraints into an input form corresponding to the objective solver.

[0020] In one implementation, after solving the conflict constraints and connectivity constraints using a preset solver, if the solution fails, the initial routing paths between all networks to be routed are detected.

[0021] According to another aspect of the present invention, a wiring path determination apparatus based on AI constraint solving is provided, the apparatus comprising:

[0022] The optional routing path acquisition unit is used to perform global design rule violation detection on the initial routing path corresponding to each network to be routed, and construct optional routing paths in the form of a directed acyclic graph or in the form of a routing tree based on the results of the global design rule violation detection and the usage of routing resources. In any of the optional routing paths, all pins of the network to be routed are connected and violation information is avoided.

[0023] The target routing path determination unit is used to generate corresponding conflict constraints and connectivity constraints for each of the optional routing paths, and to solve the conflict constraints and connectivity constraints using a preset solver, and to determine the optional routing path corresponding to the successfully solved result as the target routing path of the network to be routed.

[0024] According to another aspect of the present invention, an electronic device is also provided, including a processor and a memory; wherein the memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the above-described method.

[0025] According to another aspect of the present invention, a computer-readable storage medium is also provided, on which one or more computer instructions are stored, which are executed by a processor to implement the above-described method.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] The routing path determination method based on AI constraint solving provided by this invention includes: performing global design rule violation detection on the initial routing paths corresponding to each network to be routed; and constructing optional routing paths in the form of a directed acyclic graph or a routing tree based on the results of the global design rule violation detection and the usage of routing resources, wherein any optional routing path connects all pins of the network to be routed and avoids violation information; generating corresponding conflict constraints and connectivity constraints for each optional routing path; solving the conflict constraints and connectivity constraints using a preset solver; and determining the optional routing path corresponding to the successfully solved result as the target routing path for the network to be routed. This method avoids the potential "combinatorial explosion" problem in cabling and transforms the cabling problem into a logical problem. Specifically, after performing global design rule violation detection on the initial cabling paths corresponding to each network to be cabled, the constructed alternative cabling paths can fully consider the usage of cabling resources while avoiding conflicts, making the form and number of selected alternative cabling paths more scientific and reasonable, thus avoiding the "combinatorial explosion" problem. Furthermore, constraints representing the logical reasoning problem are constructed using the aforementioned alternative cabling paths in the form of directed acyclic graphs or cabling trees. These constraints are then solved using logical reasoning methods by a solver, and the target cabling path for the network to be cabled is determined based on the successful solution. This method transforms the cabling problem into a logical problem for the solver, comprehensively considering the cabling issues through logical solving, without relying on specific network layouts or parameter tuning processes. It effectively solves the allocation problem of critical cabling resources and makes the cabling process more efficient. Attached Figure Description

[0028] Figure 1 This is a flowchart of a wiring path determination method based on AI constraint solving provided in an embodiment of this application;

[0029] Figure 2 This is a unit block diagram of a wiring path determination device based on AI constraint solving provided in an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of the logical structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0031] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0032] To address the need to avoid design rule violations during cabling, this application provides a cabling path determination method based on AI constraint solving, a corresponding AI constraint solving-based cabling path determination device, electronic device, and computer-readable storage medium. The following embodiments provide a detailed description of the above method, device, electronic device, and computer-readable storage medium.

[0033] The first embodiment of this application provides a wiring path determination method based on AI constraint solving. The main application of this method can be a computing device used for wiring. Figure 1 This is a flowchart of the routing path determination method based on AI constraint solving provided in the first embodiment of this application, which is described below in conjunction with... Figure 1 The method provided in this embodiment will be described in detail. The embodiments described below are used to explain the principle of the method and are not intended to limit actual use.

[0034] like Figure 1 As shown, the routing path determination method based on AI constraint solving provided in this embodiment includes the following steps:

[0035] S101, perform global design rule violation detection on the initial cabling path corresponding to each network to be cabled, and construct optional cabling paths in the form of a directed acyclic graph or in the form of a cabling tree based on the results of the global design rule violation detection and the usage of cabling resources.

[0036] This step is used to perform global design rule violation detection on the initial routing paths corresponding to each network to be routed. Based on the results of the global design rule violation detection and the usage of routing resources, optional routing paths in the form of a directed acyclic graph or a routing tree are constructed. That is, global DRC is detected for each initial routing path, and the DRC violation identifier is associated with the corresponding initial routing path. Based on the resource usage, multiple optional routing paths in the form of a directed acyclic graph or a routing tree are generated for each initial routing path with a DRC violation identifier. Each optional routing path connects all pins of the network to be routed and avoids violation information.

[0037] In this embodiment, the initial cabling path corresponding to each network to be cabled is obtained in the following way:

[0038] When the network to be routed is divided into a partially connected state or an unrouted state, an initial routing path is generated for the network to be routed. When the network to be routed is fully connected, the network to be routed in the fully connected state is modified. For example, the routing tree of the network to be routed is pruned and optimized to ensure that there are no loops, multiple edges, useless points, and useless edges in the routing tree, so as to minimize the use of routing resources in the connected state. The modified routing tree is then determined as the initial routing path.

[0039] In this embodiment, when the network to be routed is divided into a partially connected state or an unrouted state, the initial routing path can be generated for the network to be routed in the following way: First, a Rectilinear Steiner Minimal Tree (RSMT) is constructed for the network to be routed. For example, the RC aware tree algorithm is used to construct the RSMT for the network to be routed, so as to minimize the network bus length while ensuring that the path delay from source to sink does not violate timing rules (e.g., setup timing rules and hold timing rules); Second, path search is performed under the guidance of the RSMT (e.g., using Dijkstra's algorithm or A* algorithm for path search) to achieve network connectivity. The path search process needs to avoid the same network design rules, including limiting the minimum connected path length of a layer to avoid minimum area DRC, limiting the path in the same direction before turning during the pathfinding process to not be too short to avoid minimum step DRC, and selecting vias that conform to the rules for metal wires of different widths to avoid minimum cut DRC. DRC, or Geometric Design Rule Check, is a series of constraints and inspection rules established during the integrated circuit design process to ensure the feasibility of the manufacturing process and the reliability of the circuit, regarding the size, shape, spacing, overlap, and other aspects of geometric figures.

[0040] In this embodiment, the common rules for DRC detection include the following:

[0041] Minimum linewidth rules are used to specify the minimum width of traces such as metal lines and polysilicon lines. For example, in a certain integrated circuit process, the minimum linewidth is 0.1μm. Therefore, the width of all lines in the design must not be less than this value. Otherwise, problems such as line breakage may occur during the manufacturing process.

[0042] Minimum spacing rules are used to define the minimum distance between patterns in the same or different layers. For example, the spacing between two adjacent metal lines must not be less than a specified value to prevent short circuits or signal crosstalk.

[0043] Minimum via size rules are used to specify the minimum diameter, ring width, and other dimensions of vias. In integrated circuits, vias are used to connect different metal layers. If the via size is too small, it may lead to problems such as unreliable connections or excessive resistance.

[0044] This embodiment uses a scan-line algorithm to detect global design rule violations. Specifically, the following algorithm is executed for each metal layer:

[0045] Calculate the maximum rectangle for each orthogonal metal polygon, that is, find the inscribed rectangle with the largest area among all orthogonal metal polygons. The coordinates of the four vertices of the maximum rectangle are represented as Xmin, Ymin, Xmax, and Ymax.

[0046] Perform a topological sort on each largest rectangle, sorting in ascending order according to the values ​​of its corresponding coordinates (Xmin, Ymin, Xmax, Ymax).

[0047] Calculate the maximum violation spacing (max drc Spacing) corresponding to the current metal layer. The maximum violation spacing represents the maximum spacing that can generate DRC. That is, if the spacing exceeds this, DRC is impossible to generate.

[0048] Use an interval tree to maintain the valid region; only the largest rectangle within the valid region can generate a DRC.

[0049] Traverse all sorted largest rectangles and dynamically detect DRC based on this: Expand the interval corresponding to the current largest rectangle in the Y direction to the maximum violation spacing to obtain the coordinate interval that may generate DRC with the current largest rectangle. Based on this coordinate interval, search for a set of rectangles that may generate DRC with the current largest rectangle in the valid area, and determine the DRC with the current largest rectangle based on the following conditions: Check whether the x and y coordinate intervals of each largest rectangle in the rectangle set overlap with the current largest rectangle. If there is overlap in both x and y dimensions, the design rule is determined to be violated. Calculate the required spacing based on the surrounding environment of the two largest rectangles and the preset spacing design rule. If the Euler distance between the two largest rectangles is less than the spacing, the design rule is determined to be violated. Filter and delete the largest rectangles in the valid area that do not meet the preset conditions (e.g., the corresponding Xmax≤Xmin-maxdrcSpacing) using the dynamic range constraint parameter (Xmin-maxdrcSpacing) of the current largest rectangle, and add the current largest rectangle to the valid area.

[0050] The above-mentioned construction of optional routing paths in the form of directed acyclic graphs or routing trees, based on the results of global design rule violation detection and the usage of routing resources, means that for each network to be routed, based on the DRC violations determined by the above global detection and the usage of routing resources, a heuristic strategy is used to transform the initial routing path of each network to be routed into multiple optional routing paths of different forms. The transformation process must ensure that any optional routing path of any form connects all pins of the network to be routed and avoids DRC violations.

[0051] In this embodiment, since an initial routing path may have multiple edges with DRC violations, the process of transforming the initial routing path into multiple optional routing paths may lead to a "combination explosion" problem. Therefore, in order to avoid the "combination explosion" problem that may occur during routing, this embodiment can select to construct different forms of optional routing paths according to the usage of routing resources. Specifically, optional routing paths in the form of a Directed Acyclic Graph (DAG) or optional routing tree can be constructed according to the usage of routing resources. For example, if multiple edges in the initial cabling path have DRC violations, directly modeling the complete path search problem as a logical reasoning problem solved by a solver would result in too many constraints and an inability to model multi-source, multi-sink path searches. Therefore, this embodiment analyzes the cabling resources occupied by the network to be cabled based on the above transformation, constructs a relatively sparse directed acyclic graph (DAG), and restricts the path search problem to this DAG. This reduces the number of nodes and edges while ensuring that the constraints constructed subsequently have a linear or near-linear relationship with the number of nodes and edges. Since a single point in geometry can correspond to multiple points in the DAG, multiple turning paths are still allowed. For example, a first-layer DAG can be constructed by mimicking a monotonic route, then the monotonic direction can be changed, and the relevant modifications can be superimposed to form a second-layer DAG. There is no theoretical limit to the number of layers.

[0052] In this embodiment, the aforementioned construction of optional routing paths in the form of a Directed Acyclic Graph (DAG) or a routing tree based on global detection results and routing resource usage can specifically refer to:

[0053] If the network to be wired meets one of the following conditions, then an optional wiring path in the form of a wiring tree should be constructed, and during the construction process, it must be ensured that a wiring tree connects all nodes of the same network to be wired:

[0054] The network to be cabled contains only one DRC violation mark;

[0055] Although the network to be routed contains multiple DRC violation identifiers, the number of optional routing paths that can be transformed and combined based on these multiple DRC violation identifiers is less than the maximum number of routing trees (Max_Routing_Tree_count), where Max_Routing_Tree_count is an adjustable hyperparameter;

[0056] If the network to be routed is on a timing critical path, in this case, although the number of alternative routing paths generated by combining multiple DRC violation identifiers exceeds the maximum number of routing trees (Max_Routing_Tree_count), the generation of new alternative routing paths can be stopped when the number of alternative routing paths generated by the combination reaches Max_Routing_Tree_count.

[0057] If the network to be routed does not meet all the above conditions, then an optional routing path in the form of a directed acyclic graph (DAG) is constructed. For the constructed DAG, it must also be ensured that the DAG connects all nodes of the same network to be routed.

[0058] It should be noted that the initial routing paths for different networks to be routed can correspond to different forms. That is, the initial routing paths for some networks to be routed can be in the form of a routing tree, while the initial routing paths for other networks to be routed can be in the form of a directed acyclic graph.

[0059] Additionally, it should be noted that in this embodiment, after determining that the initial routing path is in the form of a routing tree or a directed acyclic graph, the initial routing path can be transformed into multiple optional routing paths in the following way:

[0060] First, construct an undirected graph G = (V, E) for the initial routing path, where E is the set of edges corresponding to all wires and vias of the initial routing path, and V is the set of nodes corresponding to the connection relationships between all wires and vias of the initial routing path. The constructed undirected graph G satisfies connectivity (i.e., for any two nodes u, v ∈ V, there exists a path connecting u and v) and acyclicity (there is no node sequence v1, v2, ..., vk (k > 2 and v1 = vk) such that the nodes in the sequence are connected sequentially to form a cycle). Furthermore, DRC violations can be regarded as binary relations on the edges of different initial routing paths (Net1 and Net2): DRC = (e1, e2), e1 ∈ {G1 | G1 ∈ Net1}, e2 ∈ {G2 | G2 ∈ Net2}.

[0061] Secondly, in order to generate alternative routing paths, the following transformation is performed based on each DRC violation in the initial routing path:

[0062] If the edge that generates a DRC violation mark in the initial wiring path represents a via (i.e., the connecting edge is perpendicular to different metal layers), then the initial wiring path is replaced with a different via to avoid the DRC violation (i.e., change via).

[0063] If the edge that generates a DRC violation mark in the initial routing path represents a via, the via can be moved in the opposite direction to the other connecting edge associated with the DRC violation mark to a position where no more DRC violations will occur (i.e., jump via). This process of moving the via may cause path breaks, so connecting edges need to be added to the broken parts to reconnect the broken parts of the alternative routing path obtained after the transformation.

[0064] If the edge that generates a DRC violation mark in the initial routing path represents a wire, the wire can be shifted in the opposite direction to the other edge associated with the DRC violation mark to a position where no DRC violation will occur (i.e., Jump loc). The process of moving the wire edge may cause a break in the connection, and an additional edge needs to be added to make the broken part connected.

[0065] If the edge that generates a DRC violation mark in the initial wiring path represents a wire, the wire can be moved to another metal layer (i.e., a jump layer), and the broken part can be supplemented with an edge to ensure that the broken part is connected.

[0066] If the edge that generates a DRC violation mark in the initial routing path represents a wire, the wire edge can be split into multiple short wire edges (i.e., break edges) to ensure that only one shorter wire edge generates a DRC violation mark. Then, the above transformation (e.g., Jump loc or Jump layer) is performed on the shorter wire.

[0067] If the above routing tree violates the design rules or timing rules of the same network, the routing tree can be filtered out or these violations can be corrected through subsequent processing.

[0068] S102, generate corresponding conflict constraints and connectivity constraints for each optional routing path, and use a preset solver to solve the conflict constraints and connectivity constraints, and determine the optional routing path corresponding to the successfully solved result as the target routing path of the network to be routed.

[0069] After the above steps, based on the results of global design rule violation detection and the transformation of the initial routing path into multiple optional routing paths for the network to be routed, this step is used to generate corresponding conflict constraints and connectivity constraints for each optional routing path, and to solve the conflict constraints and connectivity constraints using a preset solver. The optional routing path corresponding to the successfully solved result is determined as the target routing path for the network to be routed, and the initial routing path is replaced by the target routing path.

[0070] When constructing constraints, a wiring tree is considered a variable. For example, based on the constructed optional wiring paths, the solver can model the conflict constraints and connectivity constraints corresponding to solving logical reasoning problems in the following way:

[0071] In modeling, for conflict constraints, conflict constraints are generated for optional routing paths (i.e., DiffNet DRC) where DRC violations exist between different networks. For each different network corresponding to a DRC violation, only one optional routing path can be selected for the different networks associated with that DRC violation (they cannot exist simultaneously). Specifically, this includes the following three cases: routing tree to routing tree, routing tree to DAG, and DAG to DAG. For connectivity constraints, it is necessary to ensure that each network has at least one optional routing path selected. That is, for each Net, at least one routing tree or the source and all sinks of the DAG must be selected. If the source and all sinks of the DAG are selected, then it is guaranteed that for each selected point except the source, at least one incoming edge must be selected; for each selected edge, its starting point must be selected.

[0072] In this step, when solving the constraints generated above using a solver, selectable solvers include satsolver (Boolean satisfiability solver), max-sat solver, csp solver, ILP solver (integer linear programming solver), etc. After solving the conflict constraints and connectivity constraints using the above-mentioned preset solvers, if the solution is unsuccessful, the initial routing paths between all networks to be routed are checked. Taking the sat solver as an example, the above constraints are first constructed into a CNF file corresponding to the sat solver. After the sat solver reads the CNF file and solves it, the output of the sat solver is obtained. If the result is satisfiable, the sat solver returns a set of solutions that satisfy the constraints; if the result is unsatisfiable, it means that the current constraint is unsatisfiable, and the iteration process needs to be entered to generate more potential alternative routing paths.

[0073] In another implementation, when the initial wiring path does not contain DRC violations, corresponding conflict constraints and connectivity constraints can be generated for the initial wiring path.

[0074] In this embodiment, before generating conflict constraints and connectivity constraints for the optional routing paths, the optional routing paths can be filtered to remove those that consume excessive routing resources. For a DAG, the filtering object is the edge on the DAG, and the filtering methods can be: filtering optional routing paths that have DRC violations within the same network; filtering optional routing paths that have DRC violations with more than a predetermined number of other optional routing paths; filtering optional routing paths that consume excessive routing resources (option routing paths with excessive detours), etc.

[0075] In this embodiment, before using a preset solver to solve conflict constraints and connectivity constraints, it is necessary to convert the conflict constraints and connectivity constraints into an input form corresponding to the target solver.

[0076] The routing path determination method based on AI constraint solving provided in this embodiment first performs global design rule violation detection on the initial routing paths corresponding to each network to be routed. Based on the results of the global design rule violation detection and the usage of routing resources, optional routing paths in the form of directed acyclic graphs or routing trees are constructed. Each optional routing path connects all pins of the network to be routed and avoids violation information. Corresponding conflict constraints and connectivity constraints are generated for each optional routing path, and a preset solver is used to solve the conflict constraints and connectivity constraints. The optional routing path corresponding to the successfully solved result is determined as the target routing path for the network to be routed. By using this method, the "combinatorial explosion" problem that may occur in cabling can be avoided, and the cabling problem can be transformed into a logic problem. Specifically, after performing global design rule violation detection on the initial cabling paths corresponding to each network to be cabled, the constructed optional cabling paths can fully combine the use of cabling resources while avoiding conflicts, making the form and number of the selected optional cabling paths more scientific and reasonable, and avoiding the "combinatorial explosion" problem. Furthermore, the optional cabling paths in the form of the above-mentioned directed acyclic graph or cabling tree are used to construct constraints representing the logical reasoning problem, and the constraints are solved by the solver using logical reasoning methods. Based on the successful solution, the target cabling path of the network to be cabled is determined.

[0077] Furthermore, this AI-constrained routing path determination method transforms the routing problem into a logical problem for the solver. By comprehensively considering the routing issues through logical solutions, it avoids dependence on specific network layouts and parameter tuning processes, effectively resolving the allocation of critical routing resources and making the routing process more efficient. For example, this method does not rely on specific network ordering, overcoming the dependency on network ordering in sequence-based AI-constrained routing path determination methods. This method does not rely on a large number of cost hyperparameters, avoiding parameter tuning processes, and is applicable to all layout designs. Unlike existing greedy heuristic methods, the AI-constrained routing path determination method provided in this embodiment effectively considers global conflicts, effectively solving the problem of unreasonable allocation of critical routing resources. Moreover, compared to track grid point-based modeling, the AI-constrained routing path determination method provided in this embodiment significantly reduces the number of variables and constraints during the solution process, making the solution process more efficient.

[0078] The above embodiments provide a routing path determination method based on AI constraint solving. Correspondingly, another embodiment of this application also provides a routing path determination device based on AI constraint solving. Since the device embodiment is basically similar to the method embodiment, it is described in a relatively simple way. For details of the relevant technical features, please refer to the corresponding description of the method embodiment provided above. The following description of the device embodiment is only illustrative.

[0079] Please refer to Figure 2 Understanding this embodiment, Figure 2 This is a unit block diagram of the wiring path determination device based on AI constraint solving provided in this embodiment, such as... Figure 2 As shown, the wiring path determination device based on AI constraint solving provided in this embodiment includes:

[0080] The optional routing path acquisition unit 201 is used to perform global design rule violation detection on the initial routing path corresponding to each network to be routed, and construct optional routing paths in the form of a directed acyclic graph or in the form of a routing tree based on the results of the global design rule violation detection and the usage of routing resources. In any of the optional routing paths, all pins of the network to be routed are connected and violation information is avoided.

[0081] The target routing path determination unit 202 is used to generate corresponding conflict constraints and connectivity constraints for each of the optional routing paths, and to solve the conflict constraints and connectivity constraints using a preset solver, and to determine the optional routing path corresponding to the successfully solved result as the target routing path of the network to be routed.

[0082] In one implementation, the construction of multiple optional routing paths in the form of a directed acyclic graph or a routing tree, based on the results of global design rule violation detection and the usage of routing resources, includes:

[0083] If the network to be wired meets one of the following conditions, then an optional wiring path in the form of a wiring tree should be constructed, and during the construction process, it must be ensured that a wiring tree connects all nodes of the same network to be wired:

[0084] The network to be cabled contains only one DRC violation identifier;

[0085] Although the network to be cabled contains multiple DRC violation identifiers, the number of optional cabling paths that can be transformed and combined based on these multiple DRC violation identifiers is less than the maximum number of cabling trees;

[0086] The network to be wired is on a time-critical path;

[0087] When the network to be wired does not meet all of the above conditions, an optional wiring path in the form of a directed acyclic graph is constructed. The constructed DAG must ensure that the DAG connects all nodes of the same network to be wired.

[0088] In one implementation, the method further includes: generating an initial wiring path for the network to be wired in response to the network being divided into a partially connected state or an unwired state.

[0089] In one implementation, obtaining the initial wiring path corresponding to each network to be wired includes: in response to the network to be wired being in a fully connected state, correcting the fully connected network to be wired to obtain the initial wiring path.

[0090] In one implementation, the method further includes: generating corresponding conflict constraints and connectivity constraints for the initial routing path in response to the initial routing path not containing violation information.

[0091] In one implementation, before generating conflict constraints and connectivity constraints for the optional routing paths, the method further includes filtering the optional routing paths.

[0092] In one implementation, the method further includes converting the conflict constraints and connectivity constraints into an input form corresponding to the objective solver.

[0093] In one implementation, after solving the conflict constraints and connectivity constraints using a preset solver, if the solution fails, the initial routing paths between all networks to be routed are detected.

[0094] In the above embodiments, a wiring path determination method and a wiring path determination device based on AI constraint solving are provided. Furthermore, another embodiment of this application also provides an electronic device. Since the electronic device embodiment is basically similar to the method embodiment, it is described relatively simply. For details of the relevant technical features, please refer to the corresponding descriptions of the above-provided method embodiments. The following description of the electronic device embodiment is merely illustrative. The electronic device embodiment is as follows:

[0095] Please refer to Figure 3 To understand this embodiment, Figure 3 This is a schematic diagram of the electronic device provided in this embodiment.

[0096] like Figure 3 As shown, the electronic device provided in this embodiment includes: a processor 301 and a memory 302;

[0097] The memory 302 is used to store computer instructions for data processing. When these computer instructions are read and executed by the processor 301, they perform the following operations:

[0098] Global design rule violation detection is performed on the initial routing paths corresponding to each network to be routed. Based on the results of the global design rule violation detection and the usage of routing resources, optional routing paths in the form of directed acyclic graphs or optional routing paths in the form of routing trees are constructed. In any of the optional routing paths, all pins of the network to be routed are connected and violation information is avoided.

[0099] For each of the optional routing paths, corresponding conflict constraints and connectivity constraints are generated, and the conflict constraints and connectivity constraints are solved using a preset solver. The optional routing path corresponding to the successfully solved result is determined as the target routing path for the network to be routed.

[0100] In one implementation, the construction of multiple optional routing paths in the form of a directed acyclic graph or a routing tree, based on the results of global design rule violation detection and the usage of routing resources, includes:

[0101] If the network to be wired meets one of the following conditions, then an optional wiring path in the form of a wiring tree should be constructed, and during the construction process, it must be ensured that a wiring tree connects all nodes of the same network to be wired:

[0102] The network to be cabled contains only one DRC violation identifier;

[0103] Although the network to be cabled contains multiple DRC violation identifiers, the number of optional cabling paths that can be transformed and combined based on these multiple DRC violation identifiers is less than the maximum number of cabling trees;

[0104] The network to be wired is on a time-critical path;

[0105] When the network to be wired does not meet all of the above conditions, an optional wiring path in the form of a directed acyclic graph is constructed. The constructed DAG must ensure that the DAG connects all nodes of the same network to be wired.

[0106] In one implementation, the method further includes: generating an initial wiring path for the network to be wired in response to the network being divided into a partially connected state or an unwired state.

[0107] In one implementation, obtaining the initial wiring path corresponding to each network to be wired includes: in response to the network to be wired being in a fully connected state, correcting the fully connected network to be wired to obtain the initial wiring path.

[0108] In one implementation, the method further includes: generating corresponding conflict constraints and connectivity constraints for the initial routing path in response to the initial routing path not containing violation information.

[0109] In one implementation, before generating conflict constraints and connectivity constraints for the optional routing paths, the method further includes filtering the optional routing paths.

[0110] In one implementation, the method further includes converting the conflict constraints and connectivity constraints into an input form corresponding to the objective solver.

[0111] In one implementation, after solving the conflict constraints and connectivity constraints using a preset solver, if the solution fails, the initial routing paths between all networks to be routed are detected.

[0112] In the above embodiments, a routing path determination method based on AI constraint solving, a routing path determination device based on AI constraint solving, and an electronic device are provided. Furthermore, another embodiment of this application provides a computer-readable storage medium for implementing the above-described routing path determination method based on AI constraint solving. The computer-readable storage medium embodiments provided in this application are described relatively simply; relevant parts can be found in the corresponding descriptions of the above method embodiments.

[0113] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0114] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0115] 1. Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can store information by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include non-transitory computer-readable media, such as modulated data signals and carrier waves.

[0116] 2. Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0117] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. A wiring path determination method based on AI constraint solving, characterized in that, The method includes: Global design rule violation detection is performed on the initial routing paths corresponding to each network to be routed. Based on the results of the global design rule violation detection and the usage of routing resources, optional routing paths in the form of directed acyclic graphs or optional routing paths in the form of routing trees are constructed. In any of the optional routing paths, all pins of the network to be routed are connected and violation information is avoided. For each of the optional routing paths, corresponding conflict constraints and connectivity constraints are generated, and the conflict constraints and connectivity constraints are solved using a preset solver. The optional routing path corresponding to the successfully solved result is determined as the target routing path for the network to be routed.

2. The method according to claim 1, characterized in that, Based on the results of global design rule violation detection and the usage of cabling resources, the system constructs optional cabling paths in the form of a directed acyclic graph or a cabling tree, including: If the network to be wired meets one of the following conditions, then an optional wiring path in the form of a wiring tree should be constructed, and during the construction process, it must be ensured that a wiring tree connects all nodes of the same network to be wired: The network to be cabled contains only one DRC violation identifier; Although the network to be cabled contains multiple DRC violation identifiers, the number of optional cabling paths that can be transformed and combined based on these multiple DRC violation identifiers is less than the maximum number of cabling trees; The network to be wired is on a time-critical path; Alternatively, when the network to be wired does not meet all of the above conditions, construct optional wiring paths in the form of a directed acyclic graph. The constructed optional wiring paths in the form of a directed acyclic graph must connect all nodes of the same network to be wired.

3. The method according to claim 1, characterized in that, Also includes: In response to the network to be wired being divided into a partially connected state or an unwired state, an initial wiring path is generated for the network to be wired.

4. The method according to claim 1, characterized in that, The step of obtaining the initial wiring path corresponding to each network to be wired includes: in response to the network to be wired being in a fully connected state, correcting the fully connected network to be wired to obtain the initial wiring path.

5. The method according to claim 1, characterized in that, Also includes: In response to the initial routing path not containing violation information, corresponding conflict constraints and connectivity constraints are generated for the initial routing path.

6. The method according to claim 1, characterized in that, Before generating conflict constraints and connectivity constraints for the optional routing paths, the method further includes filtering the optional routing paths.

7. The method according to claim 1, characterized in that, The method further includes converting the conflict constraints and connectivity constraints into an input form corresponding to the objective solver.

8. The method according to claim 1, characterized in that, After solving the conflict constraints and connectivity constraints using the preset solver, if the solution fails, the initial routing paths between all networks to be routed are checked.

9. A wiring path determination device based on AI constraint solving, characterized in that, The device includes: The optional routing path acquisition unit is used to perform global design rule violation detection on the initial routing path corresponding to each network to be routed, and construct optional routing paths in the form of a directed acyclic graph or in the form of a routing tree based on the results of the global design rule violation detection and the usage of routing resources. In any of the optional routing paths, all pins of the network to be routed are connected and violation information is avoided. The target routing path determination unit is used to generate corresponding conflict constraints and connectivity constraints for each of the optional routing paths, and to solve the conflict constraints and connectivity constraints using a preset solver, and to determine the optional routing path corresponding to the successfully solved result as the target routing path of the network to be routed.

10. An electronic device, characterized in that, Includes processor and memory; among which, The memory is used to store one or more computer instructions, wherein the one or more computer instructions are executed by the processor to implement the method as described in any one of claims 1-8.

11. A computer-readable storage medium storing one or more computer instructions thereon, characterized in that, The instruction is executed by the processor to implement the method as described in any one of claims 1-8.

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