Substrate layer of double-interface intelligent card and double-interface intelligent card

Abstract

The embodiment of the invention provides a double-interface intelligent card substrate layer and a double-interface intelligent card. The double-interface intelligent card substrate layer comprises a bearing layer, a first connecting structure, an antenna and a chip module, the first connecting structure, the antenna and the chip module are all borne by the bearing layer, and the first connecting structure and the antenna are electrically connected with the chip module; the first connecting structure and the antenna are in an enameled conductor wire winding mode, and the first connecting structure and the antenna are located in different sub-substrate layers respectively; for the first connecting structure and the antenna, a conductive metal foil etching wiring mode is adopted, and at least one of an inner lead of the first connecting structure, an inner lead connecting line, an antenna winding and an antenna lead in the antenna and the other three are located on different planes. The orthographic projection areas of the projection areas of the chip module and the strip module of the bearing layer on the target surface of the bearing layer are not overlapped; wherein the target surface of the bearing layer is one of the largest-area surfaces of the bearing layer; the mechanical reliability of the chip can be improved, and the cost is reduced.

Description

Technical Field

[0001] This invention relates to the field of chip devices, and more specifically, to chip devices comprising contact or contactless communication interfaces. Background Technology

[0002] Dual-interface smart cards are multifunctional cards that combine both contact and contactless communication interfaces. Because they combine the ease of use of contactless IC cards with the security and reliability of contact IC cards, dual-interface smart cards have been widely used in urban public transportation, highway toll collection, e-wallets, financial services, e-commerce and other fields.

[0003] Existing dual-interface smart cards assemble the smart card module, antenna, and card body together through lamination, milling, spot welding, and hot pressing. The functional circuits of the dual-interface module are concentrated in the module packaging position, which causes the chip to be subjected to excessive heat, pressure, and deformation during the card sealing process. At the same time, the mechanical reliability of the chip is insufficient, and the cost is too high. Summary of the Invention

[0004] To address the above problems, this invention proposes a dual-interface smart card substrate layer and a dual-interface smart card. Attached Figure Description

[0005] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0006] Figure 1 This is one of the top view schematic diagrams of the dual-interface smart card substrate layer structure in a specific embodiment of the present invention.

[0007] Figure 1A This is one of the schematic diagrams of the strip module projection area structure of the dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0008] Figure 1B This is a schematic diagram of the strip module structure of the dual-interface smart card according to a specific embodiment of the present invention.

[0009] Figure 1C This is the second schematic diagram of the projection area structure of the strip module of the dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0010] Figure 1D This is one of the schematic diagrams of the chip module structure of the dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0011] Figure 1EThis is the second schematic diagram of the chip module structure of the dual-interface smart card substrate layer in a specific embodiment of the present invention.

[0012] Figure 1F yes Figure 1D One of the schematic diagrams of the cross-sectional structure along the AA direction.

[0013] Figure 1G yes Figure 1E A schematic diagram of the cross-sectional structure along the AA direction.

[0014] Figure 1H This is a schematic diagram of a card insertion bending test according to a specific implementation of the present invention.

[0015] Figure 1I This is a schematic diagram of the conductive channel layer relationship in the same-layer winding and etching method of the present invention.

[0016] Figure 1J This is a schematic diagram of the conductive channel layer relationship of different winding and etching methods of the present invention.

[0017] Figure 2 This is a schematic diagram of the preferred positions of the substrate layer chip modules corresponding to the antenna full-wrap of different / same layers in the dual-interface smart card of the present invention.

[0018] Figure 2A This is a schematic diagram of the preferred positions of the antenna 2 / 3 or 3 / 4 around the corresponding substrate layer chip module in a specific embodiment of the dual-interface smart card of the present invention.

[0019] Figure 2B This is a schematic diagram showing the preferred positions of the substrate layer chip modules corresponding to the different layers of the dual-interface smart card and the antenna full-wrap in a specific embodiment of the present invention.

[0020] Figure 3 This is one of the schematic diagrams of the substrate layer structure corresponding to the co-layer antenna half-wrap of the dual-interface smart card in a specific embodiment of the present invention.

[0021] Figure 3A This is a schematic diagram of the preferred position of the substrate layer chip module corresponding to the antenna half-wrap in the same layer of the dual-interface smart card in a specific embodiment of the present invention.

[0022] Figure 3B This is the second schematic diagram of the substrate layer structure corresponding to the half-wrap antenna of the dual-interface smart card in a specific embodiment of the present invention.

[0023] Figure 3C This is the third schematic diagram of the substrate layer structure corresponding to the same layer of the dual-interface smart card and the antenna half-wrap in a specific implementation of the present invention.

[0024] Figure 4 This is one of the schematic diagrams of the substrate layer structure corresponding to the antenna half-wrap of different layers in the dual-interface smart card of the present invention.

[0025] Figure 4A This is one of the preferred positions of the substrate layer chip module corresponding to the antenna half-wrap of different layers in the dual-interface smart card of the present invention.

[0026] Figure 4B This is the second schematic diagram of the substrate layer structure corresponding to the antenna half-wrap of different layers in the dual-interface smart card of this invention.

[0027] Figure 4C This is the second schematic diagram of the preferred positions of the substrate layer chip modules corresponding to the antenna half-wrap of different layers in the dual-interface smart card of the present invention.

[0028] Figure 4D This is the third schematic diagram of the substrate layer structure corresponding to the antenna half-wrap of different layers in the dual-interface smart card of this invention.

[0029] Figure 4E This is the fourth schematic diagram of the substrate layer structure corresponding to the antenna half-wrap of different layers in the dual-interface smart card of this invention.

[0030] Figure 4F This is one of the top views of the dual-interface smart card of this invention.

[0031] Figure 5 yes Figure 1 One embodiment of a COB chip module mounted in the case of a cross-sectional view along the AA direction with the winding configuration.

[0032] Figure 5A yes Figure 1 Example 2 of COB chip module upright mounting in the case of winding in the cross-sectional view along the AA direction.

[0033] Figure 5B yes Figure 1 Example 3 of COB chip module upright mounting in the case of winding in the cross-sectional view along the AA direction.

[0034] Figure 5C yes Figure 1 Example 4 of COB chip module upright mounting in the case of winding in the cross-sectional view along the AA direction.

[0035] Figure 5D yes Figure 1 Fifth embodiment of the COB chip module in the case of winding in the cross-sectional view along the AA direction.

[0036] Figure 5E yes Figure 1 Example 6 of COB chip module upright mounting in the case of winding in the cross-sectional view along the AA direction.

[0037] Figure 5F yes Figure 1 Example 7 of COB chip module upright mounting in the case of winding in the cross-sectional view along the AA direction.

[0038] Figure 5G yes Figure 1 Example 8 of a COB chip module mounted in the case of a cross-sectional view along the AA direction with winding.

[0039] Figure 5H yes Figure 1 Example 9 of COB chip module upright mounting in the case of winding in the cross-sectional view along the AA direction.

[0040] Figure 5I yes Figure 1 One embodiment of a flip-chip module in the case of a cross-sectional view along the AA direction with winding.

[0041] Figure 5J yes Figure 1 Example 2 of COB chip module flip-chip configuration in the case of wire winding in the cross-sectional view along the AA direction.

[0042] Figure 5K yes Figure 4F One of the schematic diagrams of an embodiment of a COB chip module mounted in the case of a cross-sectional view along the AA direction with the winding configuration.

[0043] Figure 5L yes Figure 4F One of the schematic diagrams of an embodiment of a flip-chip module in the case of a cross-sectional view along the AA direction with winding.

[0044] Figure 5M yes Figure 1 Example 10 of COB chip module upright mounting in the case of winding in the cross-sectional view along the AA direction.

[0045] Figure 5N yes Figure 1 Example eleven of a COB chip module mounted in the case of a cross-sectional view along the AA direction with winding.

[0046] Figure 5O yes Figure 1 Example 12 of a COB chip module mounted in the case of a cross-sectional view along the AA direction with the winding configuration.

[0047] Figure 5P yes Figure 1 Example 13 of a COB chip module mounted in the case of a cross-sectional view along the AA direction with winding.

[0048] Figure 5Q yes Figure 2B or Figure 4One embodiment of a COB chip module mounted in the case of a cross-sectional view along the AA direction with the winding configuration.

[0049] Figure 6 yes Figure 1 One embodiment of a WLCSP chip module mounted in the form of an etched cross-section along the AA direction.

[0050] Figure 6A yes Figure 1 Example 2 of WLCSP chip module mounted upright under etching conditions in cross-sectional view along the AA direction.

[0051] Figure 6B yes Figure 1 One embodiment of flip-chip WLCSP module under etching conditions in a cross-sectional view along the AA direction.

[0052] Figure 6C yes Figure 1 One embodiment of a COB chip module mounted in the form of an etched cross-section along the AA direction.

[0053] Figure 6D yes Figure 1 One embodiment of COB chip module flip-chip etching under cross-sectional view along the AA direction.

[0054] Figure 6E yes Figure 1 Example 3 of WLCSP chip module upright mounting under the etching condition of cross-sectional view along the AA direction.

[0055] Figure 6F yes Figure 1 Example 4 of WLCSP chip module upright mounting under the etching condition of cross-sectional view along the AA direction.

[0056] Figure 6G yes Figure 1 Example 2 of a flip-chip WLCSP module under etch conditions in a cross-sectional view along the AA direction.

[0057] Figure 6H yes Figure 1 Example 2 of COB chip module upright mounting under the etching condition of cross section along the AA direction.

[0058] Figure 6I yes Figure 1 Example 2 of COB chip module flip-chip etching under cross-sectional view along the AA direction.

[0059] Figure 6J yes Figure 1 Example 3 of COB chip module upright mounting under the etching condition of cross-sectional view along the AA direction.

[0060] Figure 6K yes Figure 1 Example 3 of COB chip module flip-chip etching under cross-sectional view along the AA direction.

[0061] Figure 6L yes Figure 2B or Figure 4 One embodiment of a WLCSP chip module mounted in the form of an etched cross-section along the AA direction.

[0062] Figure 6M yes Figure 1 Example 4 of COB chip module upright mounting under the etching condition of cross-sectional view along the AA direction.

[0063] Figure 6N yes Figure 1 Example 4 of COB chip module flip-chip etching under cross-sectional view along the AA direction.

[0064] Figure 6O yes Figure 1 Fifth embodiment of COB chip module upright mounting under the etching condition of cross-sectional view along the AA direction.

[0065] Figure 6P yes Figure 1 Example 3 of flip-chip WLCSP module under etch conditions in cross-sectional view along AA direction.

[0066] Figure 6Q yes Figure 1 Fifth embodiment of WLCSP chip module upright mounting under the etching condition of cross-sectional view along the AA direction.

[0067] Figure 6R yes Figure 1 Example 6 of COB chip module upright mounting under the etching condition of cross-sectional view along the AA direction.

[0068] Figure 6S yes Figure 1 Example 6 of WLCSP chip module upright mounting under the etching condition of cross-sectional view along the AA direction.

[0069] Figure 6T Yes, yes Figure 1 Fifth embodiment of COB chip module flip-chip etching under cross-sectional view along the AA direction.

[0070] Figure 6U yes Figure 1 Example 7 of WLCSP chip module upright mounting under the etching condition of cross-sectional view along the AA direction.

[0071] Figure 6V yes Figure 4FOne of the schematic diagrams of an embodiment of a flip-chip module in the case of etching along the AA direction.

[0072] Figure 6W yes Figure 4F One of the schematic diagrams of an embodiment of a flip-chip WLCSP module under etch conditions in a cross-sectional view along the AA direction.

[0073] Figure 6X yes Figure 4F One of the schematic diagrams of an embodiment of a COB chip module mounted in the form of an etched cross-section along the AA direction.

[0074] Figure 6Y yes Figure 4F One of the schematic diagrams of an embodiment of a WLCSP chip module mounted in the form of an etched cross-section along the AA direction. Detailed Implementation

[0075] In the following description, numerous specific details are set forth in order to provide a thorough understanding of various illustrative embodiments of the invention. However, those skilled in the art will understand that embodiments of the invention can be practiced without some or all of these specific details. It should be understood that the terminology used herein is for descriptive purposes only and is not intended to limit the scope of the invention. In the drawings, the same reference numerals refer to the same or similar functions or features in several figures.

[0076] It should be understood that the terms "comprising," "including," and "having" are intended to be open-ended, meaning that there may be additional elements besides those listed. The use of reference numerals such as first, second, third, and fourth should not be construed as imposing any order of position or time among the multiple definitions. Furthermore, terms such as "top," "bottom," "side," "below," and "vertical" used herein are merely for descriptive convenience and refer to the orientation of the components as shown in the figures. It should be understood that any orientation of the components described herein is within the scope of this invention.

[0077] General Introduction to Separation:

[0078] Existing dual-interface smart cards concentrate the dual-interface module's functional circuitry at the module packaging location. This integration method, where the stripe module and chip are in the same area, exposes the chip to excessive heat, pressure, and deformation during card sealing and use. Furthermore, the chip's mechanical reliability is insufficient, and the cost is too high. To address this issue, this invention proposes a dual-interface smart card comprising a substrate layer, a stripe module, and a supplementary support layer. The substrate layer includes a carrier layer, a first connection structure, an antenna, and a chip module. The first connection structure, antenna, and chip module are all carried by the carrier layer, and the first connection structure and the antenna are electrically connected to the chip module.

[0079] The projection area of ​​the chip module on the target surface of the carrier layer and the projection area of ​​the strip module of the carrier layer do not overlap. The projection area of ​​the strip module of the carrier layer is the projection area of ​​the strip module of the dual-interface smart card on the target surface of the carrier layer after the strip module is installed. The position of the projection area of ​​the strip module conforms to the industry standard for dual-interface smart cards.

[0080] The target surface of the bearing layer is one of the surfaces with the largest area of ​​the bearing layer.

[0081] See Figure 1 This is one of the top-view schematic diagrams of the dual-interface smart card substrate layer structure according to a specific embodiment of the present invention. The substrate layer 100 of this embodiment includes a carrier layer, a strip module projection area 110, a chip module 120, an antenna 130, and a first connection structure. The carrier layer is a single-layer or multi-layer film structure. The film layer structure constituting the carrier layer is called a sub-substrate layer, used to support other structures of the substrate layer. The first connection structure and the antenna are collectively referred to as a conductive channel. The first connection structure is a connection line between the strip module projection area 110 and the chip module 120, used to realize the electrical connection between the strip module and the chip. The first connection structure includes an inner lead and an inner lead connecting line. The inner lead is electrically connected to the chip module and the inner lead connecting line, respectively. The inner lead connecting line is used to realize the electrical connection with the strip module after installation (see [reference]). Figure 1I and Figure 1J The antenna 130 includes antenna windings (i.e., Figure 1 (intermediate coil) and antenna leads (i.e.) Figure 1The antenna leads are the connection lines between the antenna 130 and the chip module 120. The antenna and the first connection structure can be generated by methods including, but not limited to, winding or etching. For the winding method, both the first connection structure and the antenna are enameled conductive wires. The inner leads and inner lead connecting lines of the first connection structure are integrally formed, and the antenna winding and antenna leads are integrally formed. For the etching method, both the first connection structure and the antenna are conductive metal foils. The inner leads and inner lead connecting lines of the first connection structure can be integrally formed or separately set, and the antenna winding and antenna leads are separately set. In this embodiment, the enameled conductive wire is preferably made of copper, and the conductive metal foil is preferably made of aluminum or copper. However, it is worth noting that other suitable materials can also be used for the enameled conductive wire and conductive metal foil, and this embodiment does not specifically limit this. It should be noted that antenna winding refers to a coil set up to form resonance, and does not limit the material of the antenna. That is, antennas using either the winding method or the etching method have an antenna winding structure, and the same applies to antenna leads. Figure 1 The diagram illustrates a wire routing method for illustrative purposes only. It is understood that the same principle applies to etching routing methods, and this should not be taken as a definitive representation. Figure 1 The wiring method shown is defined.

[0082] Based on the positional relationship between the antenna and the first connection structure, the following two scenarios can be identified:

[0083] Same layer: For the method of winding enameled conductive wire, the first connection structure and the antenna are embedded in the same sub-substrate layer; for the method of etching and wiring conductive metal foil, the first connection structure and the antenna are located in the same plane. Figure 1I (A) and (B) respectively illustrate one of the winding and etching methods in the same layer of the present invention.

[0084] Different layers: For the winding method of enameled conductive wire, the first connection structure and the antenna are located in different sub-substrate layers; for the etching and wiring method of conductive metal foil, at least one of the inner lead and inner lead connection line of the first connection structure, the antenna winding and antenna lead in the antenna is located in a different plane from the other three. Figure 1J (A) and (B) respectively illustrate one of the winding and etching methods for different layers in the embodiments of the present invention.

[0085] The carrier layer is a single-layer or multi-layer film structure, that is, it contains one or more sub-substrate layers, preferably flexible films such as PVC, PC, or PET. Based on the positional relationship between the conductive channels and the sub-substrate layers, the sub-substrate layers can be divided into at least two categories: target sub-substrate layers and additional sub-substrate layers; wherein, the target sub-substrate layer is a sub-substrate layer containing conductive channels. Specifically, when the conductive channels are wire-wound, the conductive channels are embedded in the target sub-substrate layer (see...). Figure 1I (A), Figure 1J (A)) When the conductive channel is etched, the conductive channel is attached to the surface of the target sub-substrate layer (see [reference]). Figure 1I (B), Figure 1J (B) The additional sub-substrate layer is a sub-substrate layer that does not contain conductive channels. Specifically, when the conductive channel is wire-wound, even if the conductive channel in the additional sub-substrate layer is in physical contact with the conductive channel in the target sub-substrate layer after the target sub-substrate layer and the additional sub-substrate layer are pressed together, the additional sub-substrate layer is not considered to contain conductive channels. This is because the wire-wound process will inevitably embed the conductive channel into a sub-substrate layer. When the conductive channel is etched, the additional sub-substrate layer and the conductive channel do not have physical contact. In the case of wire-wound in the same layer, the target sub-substrate layer is one layer. In the case of etching in the same layer, the target sub-substrate layer is at least one layer and at most two layers. In the case of wire-wound in different layers, the target sub-substrate layer is two layers. In the case of etching in different layers, the target sub-substrate layer is at least one layer and at most three layers. Regardless of any combination of wire-wound or etching, same layer or different layers, the additional sub-substrate layer is not necessary. However, when an additional sub-substrate layer exists, it can be one or more layers.

[0086] Based on this, under different etching conditions, when the antenna leads and antenna windings are located on different planes, vias are set in the target sub-substrate layer and filled with conductive filler to achieve electrical connection between the antenna leads and antenna windings; similarly, when the inner leads and inner lead connecting lines are located on different planes, vias are set in the target sub-substrate layer and filled with conductive filler to achieve electrical connection between the inner leads and inner lead connecting lines.

[0087] The strip module of this invention includes contact pads, a support layer, and multiple conductive pads. The contact pads and conductive pads are located on both sides of the support layer and are electrically connected. The contact pads include effective contacts conforming to the ISO 7816 protocol. See also... Figure 1A This is one of the schematic diagrams of the strip module projection area structure of the dual-interface smart card substrate layer in a specific embodiment of the present invention, corresponding to the winding method. Figure 1B This is a schematic diagram of the strip module structure of a dual-interface smart card according to a specific embodiment of the present invention. As an example, Figure 1B Only the 8-pin module solution is shown here; the same applies to the 6-pin module solution, which will not be detailed further. Figure 1A As shown, the projection area of ​​the strip module includes five tightly wound first connection structure terminals (i.e., first connection structure terminals used to connect the conductive pads of the strip module). The projection area corresponding to each tightly wound first connection structure terminal matches the projection area corresponding to the effective contact after the strip module is installed. Figure 1BAs shown, the strip module has conductive pads on its surface corresponding to the effective contact points, and these conductive pads are electrically connected to the corresponding effective contacts. The tightly wound first connection structure terminal can be electrically connected to the corresponding conductive pad of the strip module via conductive adhesive, thereby achieving electrical connection with the effective contacts of the strip module. Preferably, the conductive pads are angled, which increases the contact area with the tightly wound first connection structure terminal and improves the reliability of the electrical connection. It is worth noting that the conductive pads are actually three-dimensional structures, and their height can be adjusted according to design requirements. The conductive pads can be made of metal materials such as copper or aluminum.

[0088] See Figure 1C This is the second schematic diagram of the strip module projection area structure of the dual-interface smart card substrate layer in a specific embodiment of the present invention, corresponding to the etching method. For example... Figure 1C As shown, the projection area of ​​the strip module includes five etched pad-shaped first connection structure terminals (i.e., first connection structure terminals for connecting the conductive pads of the strip module). The projection area corresponding to each etched pad-shaped first connection structure terminal matches the projection area corresponding to the effective contact after the strip module is installed. The strip module still adopts... Figure 1B As shown in the structure, the first connection structure terminals in the form of each etched pad can be electrically connected to the corresponding conductive pads of the strip module by soldering with conductive glue or solder balls, thereby realizing the electrical connection with the effective contact of the strip module.

[0089] Based on the above, the chip module 120 is mounted on the substrate layer, and its packaging form includes, but is not limited to, COB (chip-on-board) packaging and WLCSP (Wafer Level Chip Scale Packaging). For example... Figure 1D This is one of the structural diagrams of chip module 120 when using COB packaging; for example... Figure 1E This is one of the structural diagrams of chip module 120 when it is packaged in WLCSP.

[0090] See Figure 1DThe COB-packaged chip module 120 includes a substrate and a chip. A target surface of the substrate is used to mount the chip, and this target surface is one of the largest surfaces of the substrate. Preferably, the chip is mounted at the center of the target surface of the substrate, i.e., the line connecting the center point of the chip and the center point of the substrate is perpendicular to the target surface of the substrate. The target surface of the substrate also has multiple chip module contact pads to achieve electrical connection between the chip and the antenna and the first connection structure. Based on this, electrical connection between the chip and the strip module and the antenna can be achieved, thereby realizing contact communication and contactless communication of the dual-interface smart card. It is worth noting that, to ensure the basic contact and contactless functions of the smart card, the number of chip module contact pads includes at least 7 sets: at least 2 sets are used to achieve electrical connection between the two free ends of the chip and the antenna, and at least 5 sets are used to achieve electrical connection between the chip and the effective contacts of the strip module. Figure 1D The number of contact pads in the chip module can be adjusted according to actual application needs. Figure 1D The number of chip module contact pad groups shown is for illustrative purposes only. It is worth noting that each chip module contact pad group includes one chip contact pad and one conductive channel contact pad. The chip contact pad and the conductive channel contact pad can be integrally formed or can be two separate contact pads electrically connected by a wire or other conductive structure. The chip contact pad and the conductive channel contact pad are made of the same conductive material and can be manufactured using the same process. See also... Figure 1F ,for Figure 1D One of the schematic diagrams of the cross-sectional structure along the AA direction. For example... Figure 1F As shown, the chip contact pad is connected to the chip pins via chip interconnects. After the connection is complete, the chip, chip interconnects, and chip contact pads are encapsulated with encapsulating adhesive, which can be applied using processes such as epoxy resin or black glue. The conductive channel contact pad is used to electrically connect the first connection structure terminal (the terminal located in the chip module mounting area) or the antenna terminal. It is understood that the first connection structure terminal and the antenna terminal are not limited to the conductive channel endpoints of the first connection structure and the antenna; the terminal can be understood as a section of conductive channel of the first connection structure or the antenna near the projection area of ​​the strip module or near the conductive channel contact pad of the chip module.

[0091] Preferably, the plurality of chip module contact pads are evenly distributed around the chip. This shortens the length of the chip connection lines and optimizes the first connection structure and antenna arrangement. Of course, depending on the actual application requirements, the plurality of chip module contact pads can also adopt other layouts, such as being arranged side by side on one side of the chip, or having the chip module contact pads connected to the antenna and the chip module contact pads connected to the strip module arranged separately. This embodiment of the invention does not specifically limit these arrangements.

[0092] Optionally, the chip can also be flip-chip mounted on the target surface of the substrate. In flip-chip mounting, the chip's pins can be directly electrically connected to the chip contact pads on the substrate via solder balls. Based on this, compared to... Figure 1F As shown, in this embodiment of the invention, the electrical connection between the chip pins and the chip contact pad can be achieved without setting up chip connection lines.

[0093] It is worth noting that when the chip module 120 is installed, in the chip module installation area, the terminals of the antenna and the first connection structure overlap with the matching conductive channel contact pads on the chip module in the orthogonal projection direction of the target surface of the carrier layer. Based on this, this embodiment of the invention electrically connects one side terminal of the antenna and the first connection structure to the matching conductive channel contact pads of the chip module. The electrical connection can be achieved by welding, conductive adhesive bonding, or conductive filler connection. Specifically, the welding method can be spot welding, etc., and this embodiment of the invention does not specifically limit this. The chip module substrate can be a flexible PCB board or epoxy glass cloth, or a composite carrier material, such as a metal base plate supporting PVC or PE materials. Based on this, it can provide higher stress strength than PVC material alone, ensuring the reliability of the chip installation and use process, while reducing costs.

[0094] See Figure 1E The WLCSP-packaged chip module 120 consists only of the chip package and solder balls; the chip pins can be electrically connected to external modules via the solder balls. It is understandable that... Figure 1E The number and position of the solder balls can be adjusted as needed in practical applications, and this embodiment of the invention does not impose specific limitations on this. See also Figure 1G ,for Figure 1E A cross-sectional view of the structure along the AA direction is shown. The WLCSP package size is only 0%-20% larger than the bare chip size, and its thickness is thinner. This method can minimize the chip module's footprint while meeting the manufacturing process requirements of dual-interface smart cards. The solder ball array of the WLCSP packaged chip is electrically connected to the antenna and the terminals (conductive metal foil etched wiring) of the first connection structure designed in the substrate layer through soldering or conductive adhesive bonding. Precise soldering processes, such as reflow soldering or ultrasonic soldering, ensure the reliability and conductivity of the connection; anisotropic conductive adhesive is used to electrically connect the WLCSP packaged chip to the antenna and the terminals of the first connection structure, which is simpler and improves production efficiency. WLCSP packaging allows the chip module 120 to be embedded in the substrate layer with minimal footprint while maintaining excellent electrical performance and mechanical stability. Through precise positioning and reliable electrical connections, WLCSP packaging ensures the overall performance of the dual-interface smart card while extending the chip's lifespan, meeting the dual requirements of high performance and high reliability for modern dual-interface smart cards.

[0095] Preferably, for the wire-wound method, the chip module 120 is packaged using COB packaging; for the etching method, the chip module 120 can be packaged using either COB packaging or WLCSP packaging.

[0096] Constraint diagram: Location distribution of chip modules

[0097] Based on the aforementioned substrate layer structure, this embodiment of the invention maximizes chip lifespan while ensuring the mechanical and electrical performance of the dual-interface smart card by optimizing the chip module's location. Specifically, this embodiment of the invention generates multiple corresponding constraints to determine the optimal location of the chip module based on a comprehensive consideration of mechanical performance, electrical performance, and chip lifespan.

[0098] To facilitate the description of the planar positional relationships in the process of determining the preferred location of the chip module, see [link to relevant documentation]. Figure 1 This invention is described based on the orthographic projection areas formed on the target surface of the substrate layer 100 by the strip module, chip module 120, antenna 130, etc., namely the strip module projection area, chip module projection area, and antenna projection area. It is understood that the orthographic projection area is the area obtained by projecting along the normal direction of the target surface of the substrate layer 100. It is worth noting that the antenna projection area refers to the orthographic projection area corresponding to the antenna winding, excluding the orthographic projection area corresponding to the antenna leads. Based on this, the preferred position of the substrate layer chip module projection area is further determined.

[0099] The determination of the preferred location of the chip module projection area includes constraint areas generated by multiple constraint conditions. Optionally, the constraint areas may include, but are not limited to, the strip module projection area, antenna projection area, first bending area, second bending area, third bending area, fourth bending area, resistance projection area, and embossed projection area. The strip module projection area is the orthographic projection area of ​​the strip module on the target surface of the carrier layer after installation; the antenna projection area is the orthographic projection area corresponding to the antenna winding. The first bending area is the orthographic projection area corresponding to the area between the left edge of the dual-interface smart card (left edge of the carrier layer) and the first bending cutoff line during the card insertion bending test. The distance between the first bending cutoff line and the left edge of the dual-interface smart card is determined based on the second preset insertion length and the second preset radius of curvature of the card insertion bending test. The second bending area is the orthographic projection area corresponding to the area between the right edge of the dual-interface smart card (right edge of the carrier layer) and the second bending cutoff line during the card insertion bending test. The distance between the second bending cutoff line and the right edge of the dual-interface smart card is determined based on the first preset insertion length and the second preset radius of curvature of the card insertion bending test. The preset insertion length and the first preset radius of curvature for the card insertion bending test are determined; the third bending region is the orthographic projection region corresponding to the area between the upper edge of the dual-interface smart card (upper edge of the carrier layer) and the third bending cutoff line when the dual-interface smart card is inserted and bent, and the distance between the third bending cutoff line and the upper edge of the dual-interface smart card is determined according to the third preset insertion length and the third preset radius of curvature for the card insertion bending test; the fourth bending region is the orthographic projection region corresponding to the area between the lower edge of the dual-interface smart card (lower edge of the carrier layer) and the fourth bending cutoff line when the dual-interface smart card is inserted and bent, and the distance between the fourth bending cutoff line and the lower edge of the dual-interface smart card is determined according to the fourth preset insertion length and the fourth preset radius of curvature for the card insertion bending test; the resistance projection region is the target half-region where the strip module projection region is located in the two half-regions obtained by dividing the target surface of the carrier layer by the vertical central axis; the embossed projection region is the orthographic projection region of the carrier layer corresponding to the embossed region when the smart card is embossed. The constraint region is the area that the chip module projection area cannot be set or is restricted from being set. By selecting one or more constraint regions, the area that the chip module projection area can be set is finally determined.

[0100] The present invention provides a solution for separating the strip module and the chip. In other words, all embodiments of the present invention are implemented on the basis that the projection areas of the chip module and the strip module do not overlap on the orthographic projection areas of the target surface of the carrier layer.

[0101] In addition, this embodiment of the invention takes into account the impact of chip placement on antenna performance. If the projection area of ​​the chip module coincides with the antenna, the installation of the chip module 120 will affect the antenna performance or even cause antenna damage. Based on this, this embodiment of the invention generates a first constraint: the projection area of ​​the chip module avoids the projection area of ​​the antenna. Thus, the installation of the chip module 120 can be avoided from affecting the antenna performance or damaging the antenna.

[0102] This invention takes into account the torsion test and potential bending damage that will occur after the dual-interface smart card is manufactured. During the torsion test and in the event of bending damage, the torque is greatest along the central axis of the dual-interface smart card. Figure 2-Figure 2B As shown, including the vertical and horizontal central axes, if the chip module is located on the central axis of the dual-interface smart card, it will face a greater risk of damage. Based on this, the embodiment of the present invention generates a second constraint: the projection area of ​​the chip module avoids the central axis of the smart card. Based on this, damage to the chip can be avoided during the torsion test and bending process.

[0103] This invention considers the pressure and bending effects on the card caused by scenarios such as holding, gripping, and inserting / removing the card when using a dual-interface smart card. It is understood that the card's edges are areas with a high probability of pressure and bending during these scenarios. When the chip module is located in this area, the risk of damage increases. Therefore, a card insertion test fixture is designed and manufactured. This fixture is used to perform card insertion bending tests on the dual-interface smart card to simulate the potential impact areas of the aforementioned usage scenarios. When performing the card insertion bending test, refer to... Figure 1H As shown, the dual-interface smart card needs to be inserted into the card insertion test tool with a preset insertion length l, and then bent along the arc surface of the card insertion test tool with a radius of curvature r until the surface of the dual-interface smart card and the surface of the card insertion test tool are completely in contact. The area covered by the bend simulates the area where the card is most likely to be bent in actual use.

[0104] To avoid the impact of bending tests on the chip module, the projection area of ​​the chip module typically avoids the first bending area, which is the area where the left edge of the dual-interface smart card contacts the curved surface of the card insertion test tool after insertion. The first bending area is the orthographic projection area corresponding to the region between the left edge of the dual-interface smart card and the first bending cutoff line during the card insertion bending test. The distance between the first bending cutoff line and the left edge of the dual-interface smart card is determined based on the second preset insertion length and the second preset radius of curvature of the card insertion bending test. Based on this, the embodiment of the present invention generates a third constraint condition, which is: the projection area of ​​the chip module avoids the first bending area, the first bending area is the region between the left edge of the carrier layer and the first bending cutoff line, and the distance between the first bending cutoff line and the left edge of the carrier layer is determined based on the second preset insertion length and the second preset radius of curvature of the card insertion bending test; along the direction of the horizontal central axis, the left edge of the carrier layer is the edge of the carrier layer that is closest to the projection area of ​​the strip module; based on this, damage to the chip can be avoided during the card insertion bending test.

[0105] As one possible implementation, the distance L2 between the first bend cutoff line and the left edge of the dual-interface smart card can be calculated using the following formula: L2=l2+r2×π×1 / 2, where l2 is the second preset insertion length and r2 is the second preset radius of curvature.

[0106] As an example, the second preset insertion length is 1-3mm. Specifically, the second preset insertion length can be 1mm, 1.5mm, 2mm, 2.5mm, or 3mm. The range of the second preset radius of curvature is 5mm-20mm. Specifically, the second preset radius of curvature can be 5mm, 8mm, 10mm, 12mm, 15mm, 18mm, or 20mm.

[0107] Similarly, to avoid the impact of bending simulation testing on the chip module, the projection area of ​​the chip module typically avoids the second bending area, which is the area where the right edge of the dual-interface smart card contacts the curved surface of the card insertion test fixture after insertion. The second bending area is the orthographic projection area corresponding to the region between the right edge of the dual-interface smart card and the second bending cutoff line during the card insertion bending test. The distance between the second bending cutoff line and the right edge of the dual-interface smart card is determined based on the first preset insertion length and the first preset radius of curvature of the card insertion bending test. Based on this, the embodiment of the present invention generates a fourth constraint condition, which is: the projection area of ​​the chip module avoids the second bending area, the second bending area is the region between the right edge of the carrier layer and the second bending cutoff line, and the distance between the second bending cutoff line and the right edge of the carrier layer is determined based on the first preset insertion length and the first preset radius of curvature of the card insertion bending test; along the direction of the horizontal central axis, the right edge of the carrier layer is the edge of the carrier layer that is farthest from the projection area of ​​the strip module; based on this, damage to the chip can be avoided during the card insertion bending test.

[0108] As one possible implementation, the distance L1 between the second bend cutoff line and the left edge of the dual-interface smart card can be calculated using the following formula: L1=l1+r1×π×1 / 2, where l1 is the first preset insertion length and r1 is the first preset radius of curvature.

[0109] As an example, the first preset insertion length is 1-3mm, specifically, the first preset insertion length can be 1mm, 1.5mm, 2mm, 2.5mm, or 3mm, and the first preset radius of curvature ranges from 5mm to 20mm, specifically, the first preset radius of curvature can be 5mm, 8mm, 10mm, 12mm, 15mm, 18mm, or 20mm.

[0110] Similarly, to avoid the impact of bending tests on the chip module, the projection area of ​​the chip module typically avoids the third bending area, which is the area where the upper edge of the dual-interface smart card contacts the curved surface of the card insertion test fixture after the card insertion test fixture is inserted. The third bending area is the orthographic projection area corresponding to the area between the upper edge of the dual-interface smart card and the third bending cutoff line during the card insertion bending test. The distance between the third bending cutoff line and the upper edge of the dual-interface smart card is determined based on the third preset insertion length and the third preset radius of curvature of the card insertion bending test. Based on this, the embodiment of the present invention generates a fifth constraint condition: the chip module projection area avoids the third bending area, the third bending area is the area between the upper edge of the carrier layer and the third bending cutoff line, and the distance between the third bending cutoff line and the upper edge of the carrier layer is determined based on the preset insertion length and the radius of curvature of the card insertion test fixture; along the direction perpendicular to the central axis, the upper edge of the carrier layer is the edge of the carrier layer closest to the projection area of ​​the strip module; based on this, damage to the chip can be avoided during the card insertion bending test.

[0111] As one possible implementation, the distance L3 between the third bend cutoff line and the left edge of the dual-interface smart card can be calculated using the following formula: L3=l3+r3×π×1 / 2, where l3 is the second preset insertion length and r3 is the second preset radius of curvature.

[0112] As an example, the third preset insertion length is 1-3mm, specifically, the third preset insertion length can be 1mm, 1.5mm, 2mm, 2.5mm, or 3mm, and the third preset radius of curvature ranges from 5mm to 15mm, specifically, the third preset radius of curvature can be 5mm, 8mm, 10mm, 12mm, or 15mm.

[0113] Similarly, to avoid the impact of bending tests on the chip module, the projection area of ​​the chip module usually avoids the fourth bending area, which is the area where the upper edge of the dual-interface smart card contacts the curved surface of the card insertion test tool after the card insertion test tool is inserted. The fourth bending area is the orthographic projection area corresponding to the area between the lower edge of the dual-interface smart card and the fourth bending cutoff line when the dual-interface smart card is subjected to card insertion bending test. The distance between the fourth bending cutoff line and the lower edge of the dual-interface smart card is determined according to the fourth preset insertion length and the fourth preset radius of curvature of the card insertion bending test. Based on this, the embodiments of the present invention generate a sixth constraint condition: the sixth constraint condition is that the chip module projection area avoids the fourth bending area, the fourth bending area is the area between the lower edge of the carrier layer and the fourth bending cutoff line, and the distance between the fourth bending cutoff line and the lower edge of the carrier layer is determined according to the preset insertion length of the card bending test and the radius of curvature of the card bending test tool; along the direction of the vertical central axis, the lower edge of the carrier layer is the edge of the carrier layer that is farthest from the projection area of ​​the strip module; based on this, damage to the chip can be avoided during the card bending test.

[0114] As one possible implementation, the distance L4 between the fourth bend cutoff line and the left edge of the dual-interface smart card can be calculated using the following formula: L4=l4+r4×π×1 / 2, where l4 is the fourth preset insertion length and r4 is the fourth preset radius of curvature.

[0115] As an example, the fourth preset insertion length is 1-3mm. Specifically, the fourth preset insertion length can be 1mm, 1.5mm, 2mm, 2.5mm, or 3mm. The fourth preset radius of curvature is in the range of 5mm-15mm. Specifically, the fourth preset radius of curvature can be 5mm, 8mm, 10mm, 12mm, or 15mm.

[0116] This invention, through research, has found that during the use of dual-interface smart cards, the chip is subjected to continuous pressure after entering the card slot, increasing the resistance to card insertion and removal. Prolonged pressure also affects the chip's lifespan. Positioning the chip module on the right side of the vertical central axis is preferable to placing the chip on the left side of the vertical central axis (i.e.,...). Figure 2-Figure 2B The resistance projection area shown will significantly shorten the chip's compression stroke, reducing insertion resistance and extending chip lifespan. Based on this, the embodiments of the present invention further add a seventh constraint: the chip module projection area avoids the left side of the vertical central axis, i.e., the resistance projection area. Therefore, while ensuring the electrical performance of the dual-interface smart card, it is possible to reduce insertion resistance and maximize chip lifespan.

[0117] Building upon the above, the smart card may require embossing during manufacturing to highlight information such as the card number, cardholder's name, and expiration date. This embodiment of the invention considers the risk of chip damage during embossing in the dual-interface smart card manufacturing process and generates an eighth constraint: the chip module projection area avoids the embossed projection area, where the embossed projection area is the orthogonal projection area of ​​the carrier layer corresponding to the smart card's embossed area. Based on this, chip damage during the embossing process can be avoided.

[0118] Table 1 summarizes the various constraints and their corresponding locations and avoidance ranges.

[0119] Table 1. Constraints and their corresponding locations and avoidance ranges.

[0120]

[0121]

[0122] To facilitate characterizing the configurable area of ​​the chip module, based on the aforementioned eight constraints (first, second, third, fourth, fifth, sixth, seventh, or eighth constraint), and according to the corresponding boundaries and intersections of each constraint (see Table 2), the orthographic projection area of ​​the dual-interface smart card / bearing layer can be defined as eight regions (see Table 3), namely Region 1, Region 2, Region 3, Region 4, Region 5, Region 6, Region 7, and Region 8. These regions are related to the aforementioned constraints. By combining these regions according to different combinations of constraints to be considered, the optimal position of the chip module projection area can be determined. It is worth noting that when the antenna projection area is close to the edge of the dual-interface smart card, the space between the card edge and the outer edge of the antenna projection area is too small to allow for chip module installation; similarly, when the semi-circular antenna avoids the strip module (see Table 3), the optimal position of the chip module projection area can be determined. Figure 3A , 4C The left side of the strip module projection area is adjacent to the card edge, and the space between them is too small to allow for the installation of the chip module. To ensure the performance of both the antenna and the chip, the chip module settings in this invention all satisfy the first constraint condition, namely, avoiding the antenna projection area. Therefore, the area where the chip module projection area can be set effectively excludes the portion overlapping with the strip module projection area and the antenna projection area, as well as the excessively small area between the card edge and the outer edge of the antenna projection area, and the small area from the left side of the strip module projection area adjacent to the card edge to the card edge.

[0123] When all constraints are met, and the smart card is embossed, the preferred location region of the chip module projection area can be determined in this embodiment of the invention. This region is the area formed between the upper edge of the embossed projection area, the vertical central axis, the second bend cutoff line, and the third bend cutoff line, and does not overlap with the antenna projection. Furthermore, the chip module projection area does not intersect with the central axis of the target surface of the bearing layer. Within this region, the area above the horizontal central axis is designated as Region 1, and the area below the horizontal central axis is designated as Region 2-1 (the same applies to subsequent embodiments). For the antenna full-wrap scheme (see...),... Figure 2 , 2B The preferred location area for the chip module is region 1 formed by points A8, A9, A12, and A11, and region 2-1 (with embossing) formed by A11, A12, B2, and B1. When the smart card does not have embossing, the preferred location area for the chip module projection area can be determined in this embodiment of the invention, namely, the area formed between the vertical central axis, the second bend cutoff line, the third bend cutoff line, and the fourth bend cutoff line, which does not overlap with the antenna projection area, and the chip module projection area does not overlap with the central axis of the target surface of the bearing layer; in this area, the area above the horizontal central axis is determined as region 1, and the area below the horizontal central axis is determined as region 2-2 (the same applies to subsequent embodiments). For the antenna full-wrap scheme (see...), Figure 2 , 2B The preferred location area of ​​the chip module is region 1, which is composed of A11, A12, A9, and A8, and region 2-2, which is composed of A11, A12, B6, and B5 (without embossing). Region 2-1 and region 2-2 together constitute region 2.

[0124] Optionally, the shape of the chip module 120 is preferably rectangular or rectangular, and the range of the chip module's projection area is defined by the four corner points M1, M2, M3, M4 and the boundary. For the chip module's projection area to satisfy the constraints, it must be ensured that all boundaries and all four corner points of the chip module satisfy the constraints of that area. For example, when all constraints are satisfied simultaneously, the chip module's projection area is completely located within region 1 or region 2.

[0125] It is worth noting that the above-mentioned solution that simultaneously satisfies all constraints is the optimal implementation of this invention. In practical applications, provided that the chip module does not overlap with the projection area of ​​the strip module, only the first constraint can be considered, namely, the chip module avoids the projection areas of the antenna and the strip module, which is the maximum range that the chip module can be set to. Alternatively, in addition to considering the first constraint, other constraints can be combined, that is, the first constraint can be arbitrarily set and combined with the second, third, fourth, fifth, sixth, seventh, or / and eighth constraint (e.g., if the smart card has embossed markings, then the eighth constraint exists). That is, provided that the projection area of ​​the chip module does not overlap with the projection areas of the strip module and the antenna, it can be located in at least one of the following areas: the drag projection area, the horizontal or vertical central axis, the first bending area, the second bending area, the third bending area, or the fourth bending area. However, when the chip module projection area is located in the resistance projection area, on the horizontal or vertical central axis, or in the first, second, third, or fourth bending area, the material or structure of the chip module 120 needs to be reinforced to prevent damage. For example, using a more elastic encapsulating adhesive after solidification, such as black glue or UV glue, can help resist bending and compression. Alternatively, a more flexible substrate material can be used, or the overall thickness of the chip module can be reduced to minimize breakage caused by inconsistent deformation during compression and bending. When the dual-interface smart card has embossed printing, the chip module projection area is not located in the embossed projection area.

[0126] Region 3 is defined as the area bounded horizontally by the left edge of the supporting layer to the first bend cutoff line and vertically by the upper and lower edges of the supporting layer, corresponding to the first bending region. This region does not overlap with the strip module projection area and the antenna projection area. For the antenna full-wrap scheme (see...), Figure 2 , 2B Region 3 is defined by A1, A2, B9, and B8 (the region does not include the portion overlapping with the projection area of ​​the strip module; in the following embodiments, the regions covering all or part of the projection area of ​​the strip module are treated similarly and will not be specifically described again); the region corresponding to the second bending region, defined horizontally from the right edge of the bearing layer to the second bending cutoff line and vertically by the upper and lower edges of the bearing layer, that does not overlap with the antenna projection area is defined as region 4; for the antenna full-wrap scheme (see... Figure 2 , 2B Region 4 is defined by A4, A5, B12, and B11; Region 5 is defined as the area in the vertical direction bounded by the upper edge of the bearing layer to the cutoff line of the third bend, and in the horizontal direction bounded by the left and right edges of the bearing layer, which does not overlap with the antenna projection area; for the antenna full-wrap scheme (see...), Figure 2 ,2B Region 5 is defined by A1, A5, A10, and A6; the region corresponding to the fourth bending region, defined vertically by the lower edge of the supporting layer to the fourth bending cutoff line and horizontally by the left and right edges of the supporting layer, that does not overlap with the antenna projection region is defined as region 6; for the antenna full-wrap scheme (see...), Figure 2 , 2B Region 6 is defined by B3, B7, B12, and B8; the region formed between the left edge of the bearing layer corresponding to the drag projection region and the vertical central axis, as well as the upper and lower edges of the bearing layer, that does not overlap with the strip module projection region and the antenna projection region is defined as Region 7; for the antenna full-wrap scheme (see...), Figure 2 , 2B Region 7 is determined by A1, A3, B10, and B8; when the dual-interface smart card has an embossed projection area, the region that does not overlap with the antenna projection area is defined as region 8, which is the area formed between the upper edge of the embossed projection area and the lower edge of the carrier layer and the left and right edges of the carrier layer; for the antenna full-wrap scheme (see... Figure 2 , 2B Region 8 is defined by A13, A15, B12, and B8. The horizontal central axis defines line segment 9, and the vertical central axis defines line segment 10. Figure 2-Figure 2B Line segment 9, which is formed by endpoints A3 and B10, and line segment 10, which is formed by endpoints A16 and A17.

[0127] For antenna 3 / 4, 2 / 3 wrap, half-wrap to avoid the strip module projection area, and half-wrap without avoiding the strip module projection area, the smart card can still be divided into the above 8 areas. The definition of each area remains the same, but the representation of the area will change due to the positional relationship between the antenna and the area boundary, as shown in Table 3. When the antenna is half-wrapped, the lower outer edge of the antenna projection area is set close to the horizontal central axis.

[0128] Table 2 List of Regional Boundaries and Intersections

[0129]

[0130]

[0131]

[0132] Table 3. Projection area of ​​dual-interface smart card / carrier layer

[0133]

[0134]

[0135] In Table 3 above, the regions listed with * corresponding to the constraint conditions must exclude areas overlapping with the stripe module projection area and the antenna projection area. Additionally, areas too small between the card edge and the outer edge of the antenna projection area when the antenna projection area is near the smart card edge, and small areas from the left side of the stripe module projection area to the card edge must also be excluded. For the characterization of the full-around antenna case, the regions listed must exclude areas overlapping with the stripe module projection area. See [link to relevant documentation] for details. Figure 2 , 2B ***The regions listed for the representation of cases 2 / 3 or 3 / 4 must exclude areas that overlap with the projection region of the strip module. See details in [link to relevant documentation]. Figure 2A The regions listed for characterizing the semi-circular antenna's avoidance of the strip module's projection area must exclude areas overlapping with the strip module's projection area. See [link to documentation] for details. Figure 3A , 4C The regions listed for the description of the situation where a semi-circular antenna does not avoid the projection area of ​​a strip module must exclude areas that overlap with the projection area of ​​the strip module. See [link to relevant documentation] for details. Figure 4A .

[0136] As described above, the first constraint can be combined with the second, third, fourth, fifth, sixth, seventh, and / or eighth constraints in various ways. For example, the first constraint can be combined with the third constraint, or with the second, fourth, and fifth constraints, etc. Based on the combination of constraints, the area that can be set in the chip module is clearly defined. Due to the large number of combinations, they will not be listed exhaustively here. The preferred combinations of constraints in the embodiments of this application will be described in detail below.

[0137] Considering only the first and fourth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, and the second bending area; that is, the area formed from the left edge of the carrier layer to the second bending cutoff line and the upper and lower edges of the carrier layer, and does not overlap with the antenna projection area and the strip module projection area; specifically, the portion of the area formed by the aforementioned regions 1, 2-2, 3, 5, 6, and 7 that does not overlap with region 4. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A1, A4, B11, and B8 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0138] Considering the first, fourth, and second constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, and the horizontal and vertical central axis; that is, the area formed from the left edge of the support layer to the second bend cutoff line and the upper and lower edges of the support layer, and does not overlap with the antenna projection area and the strip module projection area, and the chip module projection area does not overlap with the central axis. Specifically, it refers to the portion of the area composed of the aforementioned regions 1, 2-2, 3, 5, 6, and 7 that does not overlap with region 4, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A1, A4, B11, and B8 that does not overlap with the projection area of ​​the strip module, line segment 9, and line segment 10. No embossing is set at this time.

[0139] Considering the first, fourth, and third constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, and the first bend area; that is, the area formed between the first bend cutoff line and the second bend cutoff line and the upper and lower edges of the carrier layer, which does not overlap with the antenna projection area and the strip module projection area. Specifically, it is the portion of the area formed by the aforementioned regions 1, 2-2, 5, 6, and 7 that does not overlap with regions 3 and 4. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A2, A4, B11, and B9 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0140] Considering the first, fourth, and fifth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, and the third bend area; that is, the area formed horizontally from the left edge of the support layer to the second bend cutoff line, and vertically from the third bend cutoff line to the lower edge of the support layer, which does not overlap with the antenna projection area and the strip module projection area. Specifically, it is the portion of the area composed of the aforementioned regions 1, 2-2, 3, 6, and 7 that does not overlap with regions 4 and 5. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A6, A9, B11, and B8 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0141] Considering the first, fourth, and sixth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, and the fourth bend area; that is, the area formed horizontally from the left edge of the support layer to the second bend cutoff line, and vertically from the upper edge of the support layer to the fourth bend cutoff line, which does not overlap with the antenna projection area and the strip module projection area. Specifically, it is the portion of the area composed of the aforementioned regions 1, 2-2, 3, 5, and 7 that does not overlap with regions 4 and 6. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A1, A4, B6, and B3 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0142] Considering the first, fourth, and seventh constraints, the preferred location of the chip module projection area is: the area where the chip module projection area avoids the strip module projection area, the antenna projection area, the second bending area, and the drag projection area; that is, the area between the vertical central axis and the second bending cutoff line and the upper and lower edges of the bearing layer, and the area that does not overlap with the antenna projection area. Specifically, this refers to the portions of regions 1, 2-2, 5, and 6 that do not overlap with regions 4 and 7. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the rectangular area defined by A3, A4, B11, and B10. No embossing is applied at this point. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as in the cases considering the first, fourth, third, and seventh constraints. No embossing is applied at this point.

[0143] Considering the first, fourth, second, and third constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, and the horizontal and vertical central axis. Specifically, it is the area formed between the first bend cutoff line and the second bend cutoff line and the upper and lower edges of the support layer, and does not overlap with the antenna projection area or the strip module projection area. Furthermore, the chip module projection area does not overlap with the central axis. Specifically, this refers to the portion of the area formed by regions 1, 2-2, 5, 6, and 7 that does not overlap with regions 3, 4, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A2, A4, B11, and B9 that does not overlap with the projection area of ​​the strip module, line segment 9, and line segment 10. No embossing is set at this time.

[0144] Considering the first, fourth, second, and fifth constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the third bend area, and the horizontal and vertical central axis. Specifically, it is the area formed by the horizontal direction from the left edge of the support layer to the second bend cutoff line, and the vertical direction from the third bend cutoff line to the lower edge of the support layer, and does not overlap with the antenna projection area or the strip module projection area. Furthermore, the chip module projection area does not overlap with the central axis. Specifically, it refers to the portion of the area formed by regions 1, 2-2, 3, 6, and 7 that does not overlap with regions 4, 5, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A6, A9, B11, and B8 that does not overlap with the projection area of ​​the strip module, line segment 9, and line segment 10. No embossing is set at this time.

[0145] Considering the first, fourth, second, and sixth constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the fourth bend area, and the horizontal and vertical central axes. Specifically, it is the area from the left edge of the horizontal support layer to the second bend cutoff line, and from the upper edge of the vertical support layer to the fourth bend cutoff line, and does not overlap with the antenna projection area or the strip module projection area. Furthermore, the chip module projection area does not overlap with the central axis. Specifically, it refers to the portion of the area formed by regions 1, 2-2, 3, and 5, and region 7, that does not overlap with regions 4, 6, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A1, A4, B6, and B3 that does not overlap with the projection area of ​​the strip module, line segment 9, or line segment 10. No embossing is set at this time.

[0146] Considering the first, fourth, second, and seventh constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the drag projection area, and the central axis; that is, the area from the vertical central axis to the second bend cutoff line and the upper and lower edges of the bearing layer, which does not overlap with the antenna projection area, and the chip module projection area does not overlap with the central axis. Specifically, this refers to the portion of the area formed by the aforementioned regions 1, 2-2, 5, and 6 that does not overlap with regions 4, 7, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...), Figure 2 , 2BThis refers to the area within the rectangle defined by A3, A4, B11, and B10 that does not overlap with line segments 9 and 10. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as in the cases considering the first, fourth, second, third, and seventh constraints. No embossing is applied at this time.

[0147] Considering the first, fourth, second, third, and fifth constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, the third bend area, and the central axis. Specifically, it is the area formed horizontally from the first bend cutoff line to the second bend cutoff line, and vertically from the third bend cutoff line to the lower edge of the support layer, and does not overlap with the antenna projection area or the strip module projection area. Furthermore, the chip module projection area does not overlap with the central axis. Specifically, this refers to the portion of the area formed by regions 1, 2-2, 6, and 7 that does not overlap with regions 3, 4, 5, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A7, A9, B11, and B9 that does not overlap with the projection area of ​​the strip module, line segment 9, or line segment 10. No embossing is set at this time.

[0148] Considering the first, fourth, second, third, and sixth constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, the fourth bend area, and the central axis. Specifically, it is the area formed horizontally from the first bend cutoff line to the second bend cutoff line, and vertically from the upper edge of the support layer to the fourth bend cutoff line, without overlapping with the antenna projection area and the strip module projection area, and the chip module projection area does not overlap with the central axis. Specifically, this refers to the portion of the area formed by regions 1, 2-2, 5, and 7 that does not overlap with regions 3, 4, 6, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A2, A4, B6, and B4 that does not overlap with the projection area of ​​the strip module, line segment 9, or line segment 10. No embossing is set at this time.

[0149] Considering the first, fourth, second, third, fifth, and sixth constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, the third bend area, the fourth bend area, and the central axis. Specifically, it is the area formed horizontally from the first bend cutoff line to the second bend cutoff line, and vertically from the third bend cutoff line to the fourth bend cutoff line, where it does not overlap with the antenna projection area or the strip module projection area, and the chip module projection area does not overlap with the central axis. Specifically, this refers to the portions of regions 1, 2-2, and 7 that do not overlap with regions 3, 4, 5, 6, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A7, A9, B6, and B4 that does not overlap with the projection area of ​​the strip module, line segment 9, or line segment 10. No embossing is set at this time.

[0150] Considering the first, fourth, second, third, fifth, and seventh constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the third bend area, and the drag projection area. Specifically, it is the area formed horizontally from the vertical central axis to the second bend cutoff line, and vertically from the third bend cutoff line to the lower edge of the support layer, without overlapping with the antenna projection area, and the chip module projection area does not intersect with the central axis. Specifically, it refers to the portion of the area formed by the aforementioned regions 1, 2-2, and 6 that does not overlap with regions 3, 4, 5, 7, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A8, A9, B11, and B10 that does not overlap with the projection area of ​​the strip module, line segment 9, and line segment 10. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as in the case considering the first, fourth, second, fifth, and seventh constraints. No embossing is applied at this time.

[0151] Considering the first, fourth, second, fifth, and sixth constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the third bend area, and the fourth bend area. Specifically, it is the area formed horizontally from the left edge of the support layer to the second bend cutoff line, and vertically from the third bend cutoff line to the fourth bend cutoff line, where it does not overlap with the antenna projection area or the strip module projection area, and the chip module projection area does not overlap with the central axis. Specifically, this refers to the portions of regions 1, 2-2, and 7 that do not overlap with regions 4, 5, 6, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A6, A9, B6, and B3 that does not overlap with the projection area of ​​the strip module, line segment 9, or line segment 10. No embossing is set at this time.

[0152] Considering the first, fourth, second, sixth, and seventh constraints, the preferred location of the chip module projection area is as follows: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the fourth bend area, and the drag projection area. Specifically, it is the area formed horizontally from the vertical central axis to the second bend cutoff line, and vertically from the upper edge of the bearing area to the fourth bend cutoff line, that does not overlap with the antenna projection area, and the chip module projection area does not overlap with the central axis. Specifically, it refers to the portion of the area formed by the aforementioned regions 1, 2-2, and 5 that does not overlap with regions 3, 4, 6, 7, line segment 9, and line segment 10. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A3, A4, B11, and B10 that does not overlap with the projection area of ​​the strip module, line segment 9, and line segment 10. No embossing is applied in this case. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as in the case considering the first, fourth, second, third, sixth, and seventh constraints. No embossing is applied in this case either.

[0153] Considering the first, fourth, third, and fifth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, and the third bend area; that is, the area formed horizontally from the first bend cutoff line to the second bend cutoff line, and vertically from the third bend cutoff line to the lower edge of the carrier layer, and does not overlap with the antenna projection area and the strip module projection area. Specifically, it is the portion of the area formed by the aforementioned areas 1, 2-2, 6, and 7 that does not overlap with areas 3, 4, and 5. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A7, A9, B11, and B9 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0154] Considering the first, fourth, third, and sixth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, and the fourth bend area; that is, the area formed horizontally from the first bend cutoff line to the second bend cutoff line, and vertically from the upper edge of the carrier layer to the fourth bend cutoff line, and does not overlap with the antenna projection area and the strip module projection area. Specifically, it is the portion of the area formed by the aforementioned areas 1, 2-2, 5, and 7 that does not overlap with areas 3, 4, and 6. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A2, A4, B6, and B4 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0155] Considering the first, fourth, third, fifth, and sixth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, the third bend area, and the fourth bend area; that is, the area formed horizontally from the first bend cutoff line to the second bend cutoff line, and vertically from the third bend cutoff line to the fourth bend cutoff line, and does not overlap with the antenna projection area and the strip module projection area. Specifically, it refers to the portion of the area formed by the aforementioned areas 1, 2-2, and 7 that does not overlap with areas 3, 4, 5, and 6. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A7, A9, B6, and B4 that does not overlap with the projected area of ​​the strip module. No embossing is set at this time.

[0156] Considering the first, fourth, third, fifth, and seventh constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the first bend area, the third bend area, and the drag projection area; that is, the area formed horizontally from the vertical central axis to the second bend cutoff line, and vertically from the third bend cutoff line to the lower edge of the support layer, which does not overlap with the antenna projection area. Specifically, it is the portion of the area formed by the aforementioned areas 1, 2-2, and 6 that does not overlap with areas 3, 4, 5, and 7. For the antenna full-wrap scheme (see...),... Figure 2 , 2B This refers to the area within the rectangle defined by A8, A9, B11, and B10 that does not overlap with the projected area of ​​the strip module. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as in the cases considering the first, fourth, fifth, and seventh constraints. No embossing is applied in this case.

[0157] Considering the first, fourth, third, sixth, and seventh constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the fourth bend area, and the drag projection area; that is, the area formed horizontally from the vertical central axis to the second bend cutoff line, and vertically from the upper edge of the support layer to the fourth bend cutoff line, which does not overlap with the antenna projection area. Specifically, it is the portion of the area formed by the aforementioned areas 1, 2-2, and 5 that does not overlap with areas 3, 4, 6, and 7. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the area within the rectangle defined by A3, A4, B6, and B5 that does not overlap with the projected area of ​​the strip module. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as under the first, fourth, sixth, and seventh constraint conditions. No embossing is applied in this case.

[0158] Considering the first, fourth, third, fifth, sixth, and seventh constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the third bend area, the fourth bend area, and the drag projection area; that is, the area formed horizontally from the vertical central axis to the second bend cutoff line, and vertically from the third bend cutoff line to the fourth bend cutoff line, and does not overlap with the antenna projection area. Specifically, it is the area jointly formed by the aforementioned region 1 and region 2-2. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the rectangular area defined by A8, A9, B6, and B5. Since the resistance projection area completely covers the first bending area, the aforementioned area is the same as under the first, fourth, fifth, sixth, and seventh constraint conditions. No embossing is applied in this case.

[0159] Considering the first, fourth, fifth, and sixth constraints, the preferred location of the chip module projection area is: the chip module projection area avoids the strip module projection area, the antenna projection area, the second bend area, the third bend area, and the fourth bend area; that is, the area formed horizontally from the left edge of the bearing area to the second bend cutoff line, and vertically from the third bend cutoff line to the fourth bend cutoff line, and does not overlap with the antenna projection area and the strip module projection area. Specifically, it is the portion of the area formed by the aforementioned areas 1, 2-2, 3, and 7 that does not overlap with areas 4, 5, and 6. For the antenna full-wrap scheme (see...), Figure 2 , 2B ), that is, the area in the rectangle determined by A6, A9, B6, and B3 that does not overlap with the projection area of ​​the strip module.

[0160] When embossing exists, in addition to the constraints considered in each of the above embodiments, an eighth constraint also needs to be considered. That is, the chip module also needs to avoid the embossed projection area. Therefore, the preferred position of the chip module will change from the original embodiment. Specifically, the lower edge cutoff condition of the preferred position of the chip module is replaced with the "upper edge of the embossed projection area," a condition of not overlapping with region 8 is added, and region 2-2 is replaced with region 2-1. For example, when embossing exists, in addition to considering the first and fourth constraints, the eighth constraint also needs to be considered. That is, the chip module also needs to avoid the embossed projection area. The preferred position area of ​​the chip module projection area is: horizontally from the left edge of the carrier layer to the second bend cutoff line, and vertically from the upper edge of the carrier layer to the upper edge of the embossed projection area, the area that does not overlap with the antenna projection area and the strip module projection area. Specifically, it refers to the parts of regions 1, 2-1, 3, 5, 6, and 7 that do not overlap with regions 4 and 8. For the antenna full-wrap scheme (see...), Figure 2 , 2B This refers to the region within the rectangle defined by A1, A4, B2, and A13 that does not overlap with the projected area of ​​the strip module. Based on the first and fourth constraint conditions, combined with other constraint conditions and in embodiments with raised printing, the possible location areas for the chip module are shown in Table 5.

[0161] According to the aforementioned optimal implementation, when embossing exists, and all constraints from the first to the eighth are satisfied, the preferred location of the chip module projection area is the region where region 1 and region 2-1 do not overlap with line segments 9 and 10. Since the resistance projection area completely covers the first bending region, the aforementioned region is the same as the case considering the first, fourth, second, fifth, sixth, seventh, and eighth constraints. When embossing does not exist, and all constraints from the first to the seventh are satisfied, the preferred location of the chip module projection area is the region where region 1 and region 2-2 do not overlap with the region where line segments 9 and 10 overlap. Since the resistance projection area completely covers the first bending region, the aforementioned region is the same as the case considering the first, fourth, second, fifth, sixth, and seventh constraints.

[0162] In this embodiment of the invention, when the smart card includes a magnetic stripe, the multiple orthographic projection areas also include a magnetic stripe projection area, which is the orthographic projection area corresponding to the magnetic stripe mounting area of ​​the carrier layer. Preferably, the chip module projection area does not overlap with the magnetic stripe area; however, given the current magnetic stripe manufacturing process and the fact that magnetic stripe card swiping does not cause damage to the chip module, the chip module projection area and the magnetic stripe area may overlap. (Refer to...) Figure 2 As shown. When the manufacturing process or card-swiping method of the magnetic stripe may adversely affect the chip module, the magnetic stripe area will also become a constraint, and the chip module projection area should avoid the magnetic stripe area; when the chip module projection area overlaps with the magnetic stripe projection area, it is necessary to enhance the chip module's resistance to pressure and bending.

[0163] See Figure 2 This is a schematic diagram illustrating the preferred positions of the substrate layer chip modules corresponding to different / same-layer antenna full-wrap configurations in a dual-interface smart card according to a specific embodiment of the present invention. (See also...) Figure 2A This is a schematic diagram illustrating the preferred positions of antennas 2 / 3 or 3 / 4 around the corresponding substrate layer chip module in a dual-interface smart card according to a specific embodiment of the present invention.

[0164] See Figure 2B and Figure 4 This is a schematic diagram showing the preferred positions of the substrate layer chip modules corresponding to different layers of the dual-interface smart card and the antenna full-wrap, as described in a specific embodiment of the present invention. Combined with... Figure 2B It can be seen that when the antenna and the first connection structure are set on different layers, the embodiments of the present invention can allow the antenna projection area to overlap with the strip module projection area without affecting the normal use of the antenna and the strip module, while ensuring the preferred position of the chip module projection area. Figure 5Q and 6LThe diagram shows a cross-section where the projection area of ​​the strip module overlaps with the antenna winding. Similarly, when the antenna and the first connection structure are set in different layers, and the antenna is wound in 3 / 4 and 2 / 3 configurations, the projection area of ​​the antenna and the projection area of ​​the strip module can overlap, but this is not illustrated further.

[0165] See Figure 3 This is one of the schematic diagrams of the substrate layer structure corresponding to the dual-interface smart card winding-same-layer-antenna half-winding in a specific embodiment of the present invention. Due to the large diameter of the winding wire, when the antenna is set in the same layer as the first connection structure, the antenna cannot pass under the projection area of ​​the strip module; otherwise, the thickness of the dual-interface smart card would be insufficient or its reliability would be reduced. Therefore, the antenna avoids the projection area of ​​the strip module. Based on this, see [reference needed]. Figure 3A This is a schematic diagram of the preferred position of the substrate layer chip module corresponding to the dual-interface smart card winding-same-layer-antenna half-winding in a specific embodiment of the present invention.

[0166] See Figure 4 This is one of the schematic diagrams of the substrate layer structure corresponding to the antenna half-wrap of different layers in a dual-interface smart card according to a specific embodiment of the present invention. In this case, since the antenna and the first connection structure are on different layers, the antenna does not need to avoid the projection area of ​​the strip module; that is, the antenna projection area and the strip module projection area can overlap. Based on this, 4A shows the preferred position of the substrate layer chip module corresponding to the antenna half-wrap of different layers in a dual-interface smart card according to a specific embodiment of the present invention. Considering future product requirements, in the case of different layers, the antenna can also avoid the strip module projection area, see [reference]. Figure 4B That is, the antenna projection area and the strip module projection area do not overlap. Based on this, see [link to relevant documentation]. Figure 4C The preferred positions of the substrate layer chip modules corresponding to the antenna half-wrap of different layers in the dual-interface smart card of the present invention are shown.

[0167] It is worth noting that in the above-mentioned different schemes involving full antenna winding, 3 / 4 winding, 2 / 3 winding, or half winding, combined with the first link structure and the antenna winding line set on the same or different layers, the method for determining the preferred position of the corresponding chip module projection area is the same. That is, the corresponding position and avoidance range defined by the constraint conditions (Table 1), the relationship between each orthographic projection area and the constraint conditions (columns 1-2 of Table 3), and the range conditions and areas that the chip module can be set in (columns 1-3 of Table 4; the same applies to constraint conditions not fully listed in Table 4) are the same. The only difference between the schemes is in determining the characterization of each area (columns 3-6 of Table 3, columns 4-7 of Table 4). Specifically, for the case of full antenna winding, the constraint condition position is referenced... Figure 2 and 2B The characterization of each orthographic projection region is shown in column 3 of Table 3, and the characterization of the configurable positions of the chip module projection region is shown in column 4 of Table 4. For the 2 / 3 or 3 / 4 antenna-around case, the constraint positions are referenced... Figure 2AThe characterization of each orthographic projection area is shown in column 4 of Table 3, and the configurable positions and characterizations of the chip module projection area are shown in column 5 of Table 4. For the case where the antenna partially avoids the strip module projection area, the constraint positions are as follows... Figure 3A and 4C The characterization of each orthographic projection area is shown in column 5 of Table 3, and the configurable positions and characterizations of the chip module projection area are shown in column 6 of Table 4. For the case where the antenna partially surrounds the strip module projection area without avoiding it, the constraint positions are as follows... Figure 4A For the characterization of each orthographic projection area, please refer to column 6 of Table 3. For the settable positions and characterization of the chip module projection area, please refer to column 7 of Table 4.

[0168] Table 4 Constraints satisfied by the chip module location (without embossing)

[0169]

[0170]

[0171]

[0172]

[0173]

[0174]

[0175] Table 5. Constraints satisfied by the chip module location (with embossed markings)

[0176]

[0177]

[0178]

[0179]

[0180]

[0181]

[0182] Tables 4 and 5 above are an incomplete list of constraint conditions, in which...

[0183] *The areas listed in the settable range conditions for the chip module must exclude areas that overlap with the projection areas of the strip module and the antenna. At the same time, the excessively small area between the card edge and the outer edge of the antenna projection area when the antenna projection area is near the edge of the smart card, as well as the small area from the left side of the strip module projection area to the card edge when it is near the card edge, must also be excluded.

[0184] The configurable areas listed for the chip module must exclude areas that overlap with the strip module projection area and the antenna projection area. Also exclude excessively small areas between the card edge and the outer edge of the antenna projection area when the antenna projection area is near the edge of the smart card, as well as small areas from the left side of the strip module projection area to the card edge when it is near the card edge.

[0185] ***The regions listed for characterizing the all-around antenna configuration exclude areas overlapping with the strip module's projection area. See [link to documentation] for details. Figure 2 , 2B ;

[0186] For cases 2 / 3 or 3 / 4, the regions listed should exclude those overlapping with the projection region of the strip module. See [link to relevant documentation] for details. Figure 2A ;

[0187] *****The regions listed for characterizing the semi-wrap antenna's avoidance of the strip module's projection area must exclude areas overlapping with the strip module's projection area. See [link to documentation] for details. Figure 3A , 4C ;

[0188] The examples illustrating the situation where a semi-wrap antenna does not avoid the projection area of ​​a strip module all exclude areas that overlap with the projection area of ​​the strip module. For details, please refer to [link to relevant documentation]. Figure 4A .

[0189] It should be understood that, based on the above-described corresponding positions, avoidance ranges, and orthographic projection area divisions of the constraint conditions, and on the basis of satisfying the avoidance strip module projection area and the antenna module projection area corresponding to the first constraint condition, the positions that can be set for the chip module projection area obtained by any combination of other constraint conditions are all within the scope of disclosure and protection of this invention.

[0190] It should be noted that, when considering the combination of constraints under the sixth constraint, if the vertical position of the fourth bend cutoff line corresponding to the sixth constraint is lower than the upper edge of the embossed projection area, that is, the embossed projection area completely covers the fourth bend area, the settable range conditions, area, and characteristics of the chip module projection area in the preferred embodiment of this application are shown in Table 5; at this time, whether or not the sixth constraint is considered will not affect the final set area of ​​the chip module projection area, but in order to correspond the constraints in Table 5 with those in Table 4, Table 5 also lists the cases considering the sixth constraint, so the final set area of ​​the chip module projection area will be the same in some cases in Table 5; when the vertical position of the fourth bend cutoff line corresponding to the sixth constraint is higher than the upper edge of the embossed projection area, that is, the fourth bend area completely covers the embossed projection area, the settable range conditions, area, and characteristics of the chip module projection area in the preferred embodiment of this application are shown in Table 4 in the case of the sixth constraint;

[0191] It should be noted that when the formula parameters for determining the position of the bend cutoff line change, the relationship between each bend cutoff line and the antenna projection area may change, thereby causing changes in the characterization of each projection area and the position and characterization of the chip module projection area. Furthermore, the above embodiments only show the specific areas where the chip module can be set under conventional winding methods; the shape of the antenna winding can be varied as needed. It should be understood that regardless of the relationship between the antenna projection area and the boundary lines of each area, or the shape of the antenna winding, the corresponding positions and avoidance ranges defined by the above-mentioned constraints, the relationship between each projection area and the constraints, and the range and area where the chip module can be set will not change. Based on the corresponding positions and avoidance ranges defined by the constraints, and combined with the setting of the constraints, the preferred position for setting the chip module can be obtained when the chip module does not overlap with the projection area of ​​the strip module and the constraint area, which is within the scope of the description, disclosure, and protection of this application.

[0192] The location of the chip module affects the positional relationship between the first connection structure and the antenna winding on the orthographic projection area of ​​the carrier layer. For the case where the antenna partially avoids the projection area of ​​the strip module, see [reference needed]. Figure 3B and Figure 4D When the chip module is located in the area inside the antenna winding (corresponding to respectively) Figure 3A The region comprised of A1, A5, B12, and B8. Figure 3A When connecting the first connection structure to the chip module (in the area consisting of A1, A5, B12, and B8), the first connection structure needs to cross the antenna winding. Preferably, the crossing point is located at an antenna bend or in an area with low antenna density to reduce mechanical stress damage caused by the overlap between the antenna and the first connection structure, thereby improving the reliability of the smart card; see also Figure 3C and Figure 4E When the chip module is located outside the antenna winding (respectively) Figure 3A The region formed by C6, C7, C13, and C12. Figure 4C When the area comprised of C6, C7, C13, and C12 is used, the first connection structure can connect to the chip module without crossing the antenna winding. However, some antenna leads will cross the antenna winding to connect the antenna terminals to the chip module. If the first connection structure is located outside the antenna winding area without crossing it, it should also not be placed in the embossed area to avoid damage from subsequent card embossing. Of course, in special designs, such as conductive metal foil etched antenna schemes, embossing damage can be overcome by widening the first connection structure. In this case, the first connection structure can be placed in the embossed area. This is a mature technology and will not be detailed here.

[0193] Correspondingly, for antennas with 2 / 3 or 3 / 4 windings, and for antennas with half-windings that do not avoid the projection area of ​​the strip module, when the antenna module is located inside the antenna winding, the first connection structure can connect to the chip module without crossing the antenna winding. However, some antenna leads will cross the antenna winding to connect the antenna terminals to the chip module. When the antenna module is located outside the antenna winding, the first connection structure needs to cross the antenna winding to connect to the chip module. Preferably, the crossing point is located at an antenna bend or in an area with low density to reduce mechanical stress damage caused by the overlap between the antenna and the first connection structure, thereby improving the reliability of the smart card. When the first connection structure crosses the antenna winding and is located outside the antenna winding area, it should also not be placed in the embossed area to avoid damage from subsequent card manufacturing embossing. Of course, in special designs, such as conductive metal foil etched antenna schemes, embossing damage can be overcome by widening the first connection structure, and the first connection structure can be placed in the embossed area. This scheme is a mature technology and will not be described in detail in this invention. These situations are not shown in the figures.

[0194] The dual-interface smart card of the present invention, based on all the above embodiments, further includes a supplementary support layer and a strip module on top of the substrate layer. The supplementary support layer is located on the outer surface of the dual-interface smart card and includes a first supplementary support layer and a second supplementary support layer, which are respectively pressed against the first and second surfaces of the substrate layer. The supplementary support layer can be made of materials such as PVC to form the upper and lower surfaces of the smart card, or other materials can be used; the embodiments of the present invention do not specifically limit this.

[0195] After the supplementary support layer is pressed and supported onto the smart card substrate layer, the strip module is installed in the strip module projection area. The strip module includes contact pads, a support layer, and multiple conductive pads arranged from top to bottom. By slotting the corresponding strip module projection area in the supplementary support layer and substrate layer to expose the terminals of the first connection structure, the strip module is installed in the strip module projection area. The conductive pads of the strip module are electrically connected to the matching first connection structure terminals in the substrate layer via anisotropic conductive adhesive or solder balls. The contact surface of the contact pads of the strip module is flush with the first surface of the supplementary support layer, i.e., located on the same plane. The contact surface of the contact pad refers to the surface of the contact pad that physically contacts an external terminal (e.g., a card reader) for communication. It is understood that the thickness of the support layer and conductive pads in the strip module can be adjusted according to process requirements.

[0196] It should be understood that the substrate layer of the dual-interface smart card in this application and the dual-interface smart card in the embodiments of this application have the same orthographic projection area on the target surface of the carrier layer, and the chip module can be set in a position that satisfies the constraints and combinations of constraints of all embodiments of the dual-interface smart card substrate layer described above.

[0197] Positional relationship between the first connecting structure, the antenna, and the supporting layer structure

[0198] In the dual-interface smart card of this embodiment, for the enameled conductive wire winding method, the first connection structure and the antenna are located in different sub-substrate layers; for the conductive metal foil etching wiring method, at least one of the inner lead and inner lead connecting line of the first connection structure, the antenna winding and antenna lead in the antenna is located in a different plane from the other three.

[0199] The antenna and the first connection structure can be generated by methods including but not limited to wire winding or etching. For the wire winding method, both the first connection structure and the antenna are enameled conductive wires; for the etching method, both the first connection structure and the antenna are conductive metal foils.

[0200] Simultaneously, corresponding to the winding method, the projection area of ​​the strip module includes at least five closely wound first connection structure terminals. The projection area corresponding to each closely wound first connection structure terminal matches the projection area corresponding to the effective contact after the strip module is installed. Electrical connection between the strip module and the first connection structure terminals can be achieved through anisotropic conductive adhesive. Corresponding to the etching method, the projection area of ​​the strip module includes at least five etched pad-shaped first connection structure terminals. The projection area corresponding to each etched pad-shaped first connection structure terminal matches the projection area corresponding to the effective contact after the strip module is installed. Electrical connection between the strip module and the first connection structure terminals can be achieved through anisotropic conductive adhesive or soldering. The chip module 120 is mounted on the substrate layer. The chip module mounting area includes at least five first connection structure terminals and at least two antenna terminals. The first connection structure terminals and antenna terminals match the electrical connection structure of the chip module and are electrically connected through soldering, anisotropic conductive adhesive, or conductive filler. The packaging methods for the chip module include, but are not limited to, COB (chip on board) packaging and WLCSP (Wafer Level Chip Scale Packaging). Preferably, for wire-wound packaging, the chip module 120 is packaged using COB packaging. For etching packaging, the chip module 120 can be packaged using either COB or WLCSP packaging.

[0201] Based on this, the structure of the substrate layer 100 of the dual-interface smart card in this embodiment of the invention will be different depending on the generation method of different antennas and the first connection structure.

[0202] In one embodiment of this application, the first connection structure is on a different layer from the antenna, and the conductive channel is fabricated by a winding method. Figure 5-5D for Figure 1A schematic diagram of the COB chip module structure in the case of wire winding in the cross-sectional view along the AA direction, corresponding to the case where the strip module mounting direction and the chip module mounting direction are on the same side of the substrate layer, that is, the case where the chip module is mounted upright. Figure 5I for Figure 1 One of the distorted top views (the chip module is represented by a dashed line) is a cross-sectional view along the AA direction, illustrating a schematic diagram of a flip-chip COB module in the winding configuration. This corresponds to the case where the strip module mounting direction and the chip module mounting direction are located on opposite sides of the substrate layer, i.e., the flip-chip module configuration. Figure 5 This shows a cross-section of the chip module installation process. Figures 5A-5D Image 5I shows a cross-section of the chip module after installation. It should be understood that... Figure 1 The example of a full-wrap antenna is just one illustration; 3 / 4 wrap, 2 / 3 wrap, and half-wrap methods are also applicable. Figures 5A-5D as well as Figure 5I As can be seen, in this embodiment of the invention, the substrate layer 100 can have two or more layers as its carrier layer, including at least a first target sub-substrate layer and a second target sub-substrate layer containing a first connection structure and an antenna, and can also have one or more additional sub-substrate layers as needed. To facilitate characterizing positional differences, this embodiment of the invention first describes the substrate layer structure and the corresponding surfaces of the chip module in the projection area of ​​the strip module. Specifically, the first surface of the substrate layer structure (target sub-substrate layer, additional sub-substrate layer) refers to the surface with the largest area in the sub-substrate layer and the closest vertical distance to the contact pad of the ultimately installed strip module; the second surface of the substrate layer refers to the surface with the largest area in the sub-substrate layer and the farthest vertical distance to the contact pad of the ultimately installed strip module. The first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure; in the case of a chip-on-board (COB) package for the chip module, it refers to the surface with the largest area in the substrate that does not have a chip installed.

[0203] Whether the chip module is mounted upright or flip-mounted, it is installed through mounting holes provided in the target sub-substrate layer. In each target sub-substrate layer, the mounting holes open uniformly along the normal direction of the target surface of the carrier layer. After the chip module is installed, the terminals of the first connecting structure and the antenna overlap with the conductive channel contact pads of the chip module on the target surface of the carrier layer. After an electrical connection process, the first connecting structure and the antenna terminals form an electrical connection with the conductive channel contact pads of the chip module. This electrical connection can be achieved by physical contact between the first connecting structure and the antenna terminals and the conductive channel contact pads of the chip module, such as through soldering. Alternatively, it can be formed without physical contact between the first connecting structure and the antenna terminals and the conductive channel contact pads of the chip module, but by placing an electrical connection material between them, such as conductive filler or conductive adhesive. It should be noted that after the mounting holes are formed, other processes will continue, such as the thermal deformation generated during the welding of the first connection structure and antenna terminals to the conductive channel contact pads of the chip module, or the thermal deformation generated during the lamination process. These processes may affect the shape of the mounting holes, resulting in possible changes in the size of the mounting holes. For example, the mounting holes may deform in a direction parallel or perpendicular to the target surface, or the upper edge of the mounting holes may deform. It is understandable that even if the size of the mounting holes in the final product changes slightly, it will not substantially change the shape rules of the mounting holes.

[0204] In one embodiment of this application, the substrate layer 100 includes a first sub-target sub-substrate layer and a second target sub-substrate layer, wherein the vertical distance between the first target sub-substrate layer and the contact pad of the ultimately installed strip module is less than the vertical distance between the second target sub-substrate layer and the contact pad of the ultimately installed strip module. In this case, one of the first connecting structure and the antenna is embedded in the first target sub-substrate layer, and the other is embedded in the second target sub-substrate layer. Based on the different positions of the first connecting structure and the antenna within the target sub-substrate layers, the following situations can be identified: First seed case: The first connecting structure is embedded in the first target sub-substrate layer, and the antenna is embedded in the second target sub-substrate layer; the first seed case can be further subdivided into four sub-situations: the first connecting structure is adjacent to the first or second surface of the first target sub-substrate layer, and the antenna is adjacent to the first or second surface of the second target sub-substrate layer. The second seed case is: the first connection structure is embedded in the second target sub-substrate layer, and the antenna is embedded in the first target sub-substrate layer; the second seed case can be further subdivided into four sub-cases: the first connection structure is adjacent to the first or second surface of the second target sub-substrate layer, and the antenna is adjacent to the first or second surface of the first target sub-substrate layer. Figure 5A Only one of the above scenarios is shown as an example.

[0205] The relationship between the chip module and the substrate layer can be divided into: upright mounting and flip-chip mounting. When the chip module is upright mounted, such as... Figures 5A-5DThe vertical distance between the first surface of the chip module and the first target sub-substrate layer is less than the vertical distance between the first surface of the chip module and the second target sub-substrate layer. When the chip module is flip-chip mounted, if... Figure 5I The vertical distance between the first surface of the chip module and the first target sub-substrate layer is greater than the vertical distance between the first surface of the chip module and the second target sub-substrate layer.

[0206] In one embodiment, when the chip module is installed, the encapsulating adhesive of the chip module is embedded in the mounting holes, while the substrate of the chip module is not embedded in the mounting holes. (Refer to...) Figures 5A-5D 5I, that is, along the direction parallel to the target surface of the carrier layer, the size of the mounting hole is smaller than the size of the chip module substrate and larger than the size of the chip module encapsulation adhesive. Based on this, the target sub-substrate layer will provide better support for the chip module.

[0207] When the thickness of one target sub-substrate layer is sufficient to accommodate the chip module encapsulation adhesive, the mounting holes can be located only in one target sub-substrate layer, with no mounting holes in the other target sub-substrate layer. Specifically, when the chip module is mounted upright, mounting holes are provided in the first target sub-substrate layer, such as... Figure 5D As shown; similarly, when the chip module is flip-chip mounted, mounting holes are provided in the second target sub-substrate layer. In this case, the mounting holes can be vias penetrating the corresponding target sub-substrate layer, or recesses to accommodate the chip module encapsulating adhesive.

[0208] When the thickness of a single target sub-substrate layer is insufficient to accommodate the chip module encapsulating adhesive, mounting holes are provided in both target sub-substrate layers. These mounting holes include a first mounting hole and a second mounting hole, respectively located in the two sub-substrate layers. The first mounting hole accommodates the portion of the chip module encapsulating adhesive adjacent to the base chip module board; this first mounting hole is a via. The second mounting hole accommodates the portion of the chip module encapsulating adhesive away from the chip module substrate; this second mounting hole can also be a via. Figure 5A Alternatively, it can be a notch for accommodating the chip module encapsulation adhesive without penetrating the target sub-substrate layer. Figure 5B ). Combination Figures 5A-5C When the chip module is being mounted, it is installed through a first mounting hole (i.e., mounting hole 1) in the first target sub-substrate layer and a second mounting hole (i.e., mounting hole 2) in the second target sub-substrate layer. Combined with... Figure 5I When the chip module is flip-chip mounted, the chip module is mounted through the second mounting hole (i.e., mounting hole 2) provided in the first target sub-substrate layer and the first mounting hole (i.e., mounting hole 1) provided in the second target sub-substrate layer.

[0209] Preferably, along the direction parallel to the target surface of the carrier layer, the size of the first mounting hole is greater than or equal to that of the second mounting hole. When the size of the first mounting hole is greater than that of the second mounting hole, the sub-substrate layer with the second mounting hole has a smaller opening, which makes it easier to avoid the corresponding position from being recessed during subsequent card manufacturing. Furthermore, the first and second sub-substrate layers form a step, which helps to release stress and reduce damage to the card and chip module caused by uneven stress. When the size of the first mounting hole is equal to that of the second mounting hole, the first and second mounting holes can be manufactured in one process, or in different processes, reducing alignment difficulties, simplifying the process, and saving costs. For simplicity, not all of the above situations are shown in the accompanying drawings.

[0210] Depending on the different ways of electrically connecting the conductive track contact pad of the chip module to the terminals of the first connection structure and the antenna, the detailed structure of the mounting hole can be divided into the following cases.

[0211] In one embodiment of the present invention, the mounting hole is only disposed in one target sub-substrate layer, and the conductive channel contact pad of the chip module is covered by another target sub-substrate layer. Therefore, embodiments of the present invention can provide electrical connection holes (e.g., in the first and second target sub-substrate layers, corresponding to the projection areas of the conductive channel contact pads of the chip module) at the locations of the first and second target sub-substrate layers. Figure 5D This design exposes the first connection structure terminal, antenna terminal, and conductive channel contact pad of the chip module simultaneously through electrical connection holes. These electrical connection holes are through-holes that penetrate the target sub-substrate layer. The orthographic projection areas of these electrical connection holes on the target surface of the carrier layer overlap with the orthographic projection areas of the first connection structure terminal, antenna terminal, and conductive channel contact pad of the chip module on the target surface of the carrier layer. Based on this, electrical connection processes such as spot welding and filling with conductive material are implemented through these electrical connection holes to connect the first connection structure terminal and antenna terminal to the matching conductive channel contact pads. The number of electrical connection holes matches the number of conductive channel contact pads in the chip module.

[0212] In another embodiment of the present invention, mounting holes are provided in both target sub-substrate layers.

[0213] In one embodiment of the present invention, the orthographic projection area of ​​the conductive channel contact pad of the chip module on the target surface of the carrier layer overlaps with the orthographic projection area of ​​the second mounting hole on the target surface of the carrier layer. Figure 5A , Figure 5IAs shown, since the orthographic projection area of ​​the conductive channel contact pad of the chip module on the target surface of the carrier layer overlaps with the orthographic projection areas of the first connection structure terminal and the antenna terminal on the target surface of the carrier layer, and since the size of the first mounting hole is larger than that of the second mounting hole, the orthographic projection areas of the conductive channel contact pad of the chip module on the target surface of the carrier layer, the orthographic projection areas of the first connection structure terminal and the antenna terminal on the target surface of the carrier layer, and the orthographic projection area of ​​the second mounting hole on the target surface of the carrier layer overlap. Part or all of the conductive channel contact pads provided on the chip module substrate, as well as the first connection structure terminal and the antenna terminal, are exposed in the mounting hole. Simultaneously, the orthographic projection areas of the second mounting hole and the first and second surfaces of the target sub-substrate layer on the normal plane of the target surface of the carrier layer overlap. The normal plane of the target surface of the carrier layer refers to the plane where the normal to the target surface of the carrier layer is located. That is, the mounting hole is a through-hole that penetrates the target sub-substrate layer. At this time, the conductive channel contact pad of the chip module can be reached through the mounting hole (both upright and flip-chip mounting are possible). Therefore, the electrical connection process of the conductive track contact pad that matches the first connection structure terminal and the antenna terminal domain can be achieved through the mounting hole, such as spot welding.

[0214] In other embodiments of the present invention, the orthographic projection area of ​​the conductive channel contact pad of the chip module on the target surface of the carrier layer does not overlap with the orthographic projection area of ​​the first mounting hole on the target surface of the carrier layer, that is, the conductive channel contact pad is not exposed in the mounting hole (e.g. Figure 5C (as shown); or, the second mounting hole and the second surface of the second target sub-substrate layer (in the case of upright chip module mounting) or the first surface of the first target sub-substrate layer (in the case of flip-chip module mounting) do not overlap in the orthographic projection area on the normal plane of the target surface of the carrier layer. In this case, the second mounting hole does not penetrate the surface of the target sub-substrate layer where it is located, but is only a notch (as shown). Figure 5B (As shown); In both of the above two cases, the conductive channel contact pads of the chip module cannot be reached through the mounting holes. Therefore, embodiments of the present invention can provide electrical connection holes (such as those shown) at the locations corresponding to the projection areas of the conductive channel contact pads of the chip module in the target sub-substrate layer. Figures 5B-5DThis design exposes the first connection structure terminal, antenna terminal, and conductive channel contact pad of the chip module simultaneously through electrical connection holes. These electrical connection holes are through-holes that penetrate both target sub-substrate layers. The orthographic projection areas of these electrical connection holes on the target surface of the carrier layer overlap with the orthographic projection areas of the first connection structure terminal, antenna terminal, and conductive channel contact pad of the chip module on the target surface of the carrier layer. Based on this, electrical connection processes such as spot welding and filling with conductive material are implemented through these electrical connection holes to connect the first connection structure terminal and antenna terminal to the matching conductive channel contact pads. The number of electrical connection holes matches the number of conductive channel contact pads in the chip module.

[0215] In embodiments of the present invention, the supporting layer may further include one or more additional sub-substrate layers. These additional sub-substrate layers are bonded to the upper and / or lower surfaces of the target sub-substrate layer by lamination, providing support and reinforcement to the target sub-substrate layer while increasing its flatness. On the one hand, to simplify the process, the additional sub-substrate layer may be directly laminated with the target sub-substrate layer without any pre-set structure (e.g., ...). Figure 5E-5F , Figure 5J At this point, the carrier layer on the chip module substrate, after the additional sub-substrate layer is laminated, is not a flat surface and has tolerable protrusions. On the other hand, in order to better adjust the flatness of the carrier layer, when the chip module substrate is not embedded with mounting holes, and / or when the encapsulant of the chip module protrudes from the mounting holes that accommodate it, the additional sub-substrate layer can be provided with clearance holes at the positions corresponding to the protrusions of the chip module substrate and / or the chip encapsulant (e.g., Figure 5G-5H This is to accommodate the portion of the chip module substrate not embedded in the mounting holes, and / or to accommodate the portion of the chip module encapsulant protruding from the mounting holes. This clearance hole can be a through-hole penetrating the additional sub-substrate layer, or it can be a notch forming without penetrating the additional sub-substrate layer. Furthermore, depending on the need for improvements in shape, stress, etc., the opening size of the clearance hole can be the same as or different from the mounting hole. Similarly, when one additional sub-substrate layer cannot achieve a leveling effect, multiple additional sub-substrate layers can be set. After the additional sub-substrate layers are set, the surface of the substrate layer no longer has protrusions. Based on this, after setting the additional sub-substrate layers, the target surface of the carrier layer will be flatter, while protecting the chip module and improving the mechanical properties of the carrier layer against bending, torsion, compression, and tension. It should be noted that... Figure 5E-5H 5J is intended to show some ways of setting up the additional sub-substrate layer, but the relationship between the mounting holes and the conductive contact pads of the chip module, as well as whether or not electrical connection holes are set, are not shown in detail and are not limited here.

[0216] It should be understood that when the lamination of the additional sub-substrate layer and the target sub-substrate layer does not affect the electrical connection process between the chip module and the conductive channel, no additional structure providing electrical connection is required in the additional sub-substrate layer. The lamination process between the additional sub-substrate layer and the target sub-substrate layer can be performed before or after the electrical connection process between the chip module and the conductive channel (e.g., ...). Figure 5H (Upper additional sub-substrate layer); When the lamination of the additional sub-substrate layer and the target sub-substrate layer affects the electrical connection process between the chip module and the conductive channel, there are at least two ways to overcome this effect: Method 1, after completing the electrical connection process between the chip module and the conductive channel, then laminate the target sub-substrate layer and the additional sub-substrate layer; Method 2, set a corresponding structure in the target sub-substrate layer to complete the electrical connection process. This specific structure can be an electrical connection via (e.g., an electrical connection via corresponding to the position of the target sub-substrate layer) set in the additional sub-substrate layer. Figure 5M-5O Electrical connection is achieved through interconnected vias. In specific structures, when the mounting holes in the target sub-substrate layer are vias and expose the conductive channel contact pads of the chip module, via-type clearance holes are also provided in the additional sub-substrate layer to expose the conductive channel contact pads of the chip module. Electrical connection is achieved through the interconnected mounting holes and clearance holes (e.g.,...). Figure 5P-5Q ).

[0217] In one embodiment of this application, see [link to embodiment]. Figure 5Q , it is Figure 2B or Figure 4 In one embodiment of the COB chip module in the case of winding in the cross-sectional view along the AA direction, since the first connection structure and the antenna are located on different target sub-substrate layers, the first connection structure and the antenna will not interfere with each other in the direction normal to the target surface of the bearing layer. Therefore, the antenna winding can be set below the projection area of ​​the strip module, that is, the projection area of ​​the strip module and the projection area of ​​the antenna winding overlap. At this time, the antenna winding can have more turns, which improves resonance.

[0218] In one embodiment of this application, the first connection structure is on a different layer from the antenna, and the conductive channel is fabricated by etching. Figure 6-6A as well as Figure 6C for Figure 1 Different structural schematic diagrams along the AA direction correspond to the case where the strip module mounting direction and the chip module mounting direction are located on the same side of the substrate layer, i.e., the chip module is mounted upright. Figure 6B and Figure 6D for Figure 1 One of the distorted top views (the chip module is represented by a dashed line) shows a different cross-sectional view along the AA direction, corresponding to the case where the strip module mounting direction and the chip module mounting direction are located on opposite sides of the substrate layer, i.e., the chip module is flip-chip mounted. Figure 6-6D The image shown is a cross-section of the chip module after installation. This is understandable. Figure 1The example of a fully wound antenna is just that—an example. In practice, the 3 / 4 or 2 / 3 wound methods also apply.

[0219] To facilitate characterizing positional differences, this embodiment of the invention first describes the corresponding surfaces of the carrier layer structure and the chip module. Specifically, the first surface of the carrier layer structure (target sub-substrate layer, additional sub-substrate layer) refers to the surface with the largest area in the sub-carrier layer that is closest to the contact pad of the ultimately installed strip module perpendicularly, and the second surface refers to the surface with the largest area in the sub-carrier layer that is furthest from the contact pad of the ultimately installed strip module perpendicularly. The first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure. When the chip module uses on-board chip-on-board (COB) packaging, it refers to the surface with the largest area in the substrate that does not have a chip mounted on it. When the chip module uses WLCSP packaging, it refers to the surface with the largest area of ​​the package body that does not have an electrical connection structure.

[0220] Due to the requirements of the etching conductive channels and the electrical connection process of the chip module, the target surface of the chip module is preferably located close to the conductive channels, and no target sub-substrate layer is sandwiched between the surface of the chip module where the electrical connection structure is set and the conductive channels. After the chip module is installed, the orthographic projection area of ​​the conductive channel contact pad of the COB module or the solder ball array of the WLCSP module on the target surface of the carrier layer overlaps with the orthographic projection area of ​​the corresponding first connection structure terminal and antenna terminal on the target surface of the carrier layer, and forms an electrical connection. The electrical connection can be achieved by soldering or anisotropic conductive adhesive.

[0221] For the etching method, the inner leads and their connecting lines in the first connection can be discrete structures, and the antenna windings and antenna leads in the antenna structure can also be discrete structures. Based on this, it is possible to ensure that at least one of the inner leads and their connecting lines in the first connection structure, and the antenna windings and leads in the antenna, is located on a different plane from the other three. However, to improve the reliability of the electrical connection between the chip module and the conductive channel, for the etching wiring method, preferably, the inner leads and antenna leads are located on the same plane, i.e., on the same surface of the target sub-substrate layer. The upper surface of the inner leads and antenna leads is closer to the contact pads of the ultimately installed strip module, and the lower surface is farther from the contact pads of the ultimately installed strip module.

[0222] In one embodiment of this application, the carrier layer of the substrate layer 100 contains only one target sub-substrate layer, which is the first target sub-substrate layer. Combined with... Figure 6Based on the position of the first connection structure and the antenna, it can be further subdivided into the following two sub-cases: The first sub-case is that the inner lead and the antenna lead are disposed on the first surface of the first target sub-substrate layer, and at least one of the inner lead connecting line and the antenna winding is adjacent to the second surface of the first target sub-substrate layer. The second sub-case is that the inner lead and the antenna lead are disposed on the second surface of the first target sub-substrate layer, and at least one of the inner lead connecting line and the antenna winding is adjacent to the first surface of the first target sub-substrate layer.

[0223] In one embodiment, the chip module is preferably a WLCSP module. When the chip module is mounted correctly, such as... Figure 6-6A The chip module is located on the upper surface of the inner leads and antenna leads. In the first seed scenario described above, the target sub-substrate layer does not need to have mounting holes (e.g., Figure 6 The chip module is supported on the target sub-substrate layer. In the second seed scenario described above, the target sub-substrate layer needs to be provided with mounting holes to accommodate the chip module. In this case, the mounting holes can be through holes penetrating the target sub-substrate layer or recesses to accommodate the chip module (e.g., ...). Figure 6A When flip-chip modules are used, such as... Figure 6B The chip module is located on the lower surface of the inner leads and antenna leads. In the first scenario described above, the target sub-substrate layer needs to have mounting holes to accommodate the chip module. These mounting holes can be through-holes penetrating the target sub-substrate layer or recesses (not shown) to accommodate the chip module. In the second scenario described above, the target sub-substrate layer does not need mounting holes, and the chip module is supported beneath it. When the mounting hole is a through-hole, after the chip module is installed, preferably, the first surface of the chip module is flush with the surface of the target sub-substrate layer it resides on.

[0224] In one embodiment, the chip module is a COB chip module. For COB chip modules, the encapsulation bumps are more fragile than the chip module substrate; preferably, mounting holes (e.g., ...) are provided in the target sub-substrate layer. Figure 6C This accommodates the protrusions of the chip module's encapsulation adhesive. Based on this, when the chip module is mounted correctly (e.g., ...), Figure 6C The first connection structure and antenna are located on the first surface of the target sub-substrate layer. The chip module substrate is supported on the first connection structure and antenna on the first surface of the target sub-substrate layer. The encapsulating adhesive of the chip module is accommodated in the mounting holes of the target sub-substrate layer. When the chip module is flip-chip mounted (e.g., ...), the first connection structure and antenna are located on the first surface of the target sub-substrate layer. The chip module substrate is supported on the first surface of the target sub-substrate layer. Figure 6D The first connection structure and antenna are located on the second surface of the target sub-substrate layer. The chip module substrate is supported on the first connection structure and antenna on the second surface of the target sub-substrate layer. The encapsulating adhesive of the chip module is accommodated in the mounting holes of the target sub-substrate layer. The mounting holes can be through holes penetrating the target sub-substrate layer or recesses accommodating the chip module.

[0225] In one embodiment, the carrier layer may also be provided with one or more additional sub-substrate layers (such as... Figure 6E This additional sub-substrate layer is used to press against the surface of the target sub-substrate layer that does not have conductive channels, thereby better supporting the target sub-substrate layer and its contained structures and improving the mechanical properties of the supporting layer against bending, torsion, compression, and tension. The additional sub-substrate layer does not physically contact the conductive channels. To improve the flatness of the substrate layer, the additional sub-substrate layer can have clearance holes to accommodate chip modules protruding from the target sub-substrate layer. These clearance holes can be through-holes or notches.

[0226] In another embodiment of this application, the substrate layer 100 includes two target sub-substrate layers. The layer closer to the contact pad of the ultimately installed strip module is the first target sub-substrate layer, and the layer farther from the contact pad is the second target sub-substrate layer. Based on the position of the first connection structure and the antenna, this can be further subdivided into three sub-cases: The first sub-case is where the inner lead and antenna lead are located on the first surface of the first target sub-substrate layer; the second sub-case is where the inner lead and antenna lead are located between the first and second target sub-substrate layers, i.e., on the second surface of the first target sub-substrate layer or the first surface of the second target sub-substrate layer; the third sub-case is where the inner lead and antenna lead are located on the second surface of the second target sub-substrate layer. Based on the location of the internal lead wire and the antenna winding, it can be further subdivided into the following three sub-cases. The first sub-case is divided into: at least one of the internal lead wire and the antenna winding is located on the first or second surface of the second target sub-substrate layer; the second sub-case is divided into: at least one of the internal lead wire and the antenna winding is located on the second surface of the second target sub-substrate layer or the first surface of the first target sub-substrate layer; the third sub-case is divided into: at least one of the internal lead wire and the antenna winding is located on the second surface of the first target sub-substrate layer or the first surface of the first target sub-substrate layer.

[0227] Preferably, the inner lead and the antenna lead are located between the first target sub-substrate layer and the second target sub-substrate layer. Figure 6F Based on the position of the first connection structure and the antenna, it can be further subdivided into the following two sub-cases: The first sub-case is that at least one of the inner lead connecting line and the antenna winding line is located on the first surface of the first target sub-substrate layer. The second sub-case is that at least one of the inner lead connecting line and the antenna winding line is located on the second surface of the second target sub-substrate layer.

[0228] Based on the above preferred configuration, in one embodiment, the chip module is preferably a WLCSP module. When the chip module is mounted correctly, as follows: Figure 6FThe target surface of the chip module is located on the upper surface of the inner leads and antenna leads. Preferably, mounting holes are provided in the first target sub-substrate layer to accommodate the chip module. When the inner lead connection wires and antenna windings are not supported by the first surface of the first target sub-substrate layer, the first target sub-substrate layer can directly cover the first surface of the chip module and the upper surface of the inner leads and antenna leads. When the chip module is flip-chip mounted, such as... Figure 6G The target surface of the chip module is located on the lower surface of the inner leads and antenna leads. Preferably, a mounting hole is provided in the second target sub-substrate layer to accommodate the chip module. When the inner lead connecting wires and antenna windings are not supported by the second surface of the second target sub-substrate layer, the second target sub-substrate layer can directly cover the first surface of the chip module and the upper surface of the inner leads and antenna leads. When the mounting hole is provided, the mounting hole can be a through hole penetrating the target sub-substrate layer or a notch for accommodating the chip module. When the mounting hole is a through hole, after the chip module is installed, preferably, the first surface of the chip module is flush with the surface of the target sub-substrate layer it is located on.

[0229] In one embodiment, the chip module is preferably a COB module. When the chip module is mounted correctly, such as... Figure 6H and Figure 6J The target surface of the chip module is located on the upper surface of the inner leads and antenna leads. Preferably, a first mounting hole is provided in the first target sub-substrate layer to accommodate the substrate of the COB chip module, and a second mounting hole is provided in the second target sub-substrate layer to accommodate the encapsulation protrusion of the COB chip module. When the inner lead connection wires and antenna windings are not supported by the first surface of the first target sub-substrate layer, the first target sub-substrate layer can directly cover the first surface of the chip module and the upper surface of the inner leads and antenna leads. When the chip module is flip-chip mounted... Figure 6I and 6K The target surface of the chip module is located on the lower surface of the inner leads and antenna leads. Preferably, a second mounting hole is provided in the first target sub-substrate layer to accommodate the encapsulation protrusion of the COB chip module, and a first mounting hole is provided in the second target sub-substrate layer to accommodate the substrate of the COB chip module. When the inner lead connecting wires and antenna windings are not supported by the second surface of the second target sub-substrate layer, the second target sub-substrate layer can directly cover the first surface of the chip module and the upper surface of the inner leads and antenna leads. When the mounting hole is provided, the mounting hole can be a through hole penetrating the target sub-substrate layer or a notch accommodating the chip module. When the mounting hole is a through hole, after the chip module is installed, preferably, the first surface of the chip module is flush with the surface of the target sub-substrate layer on which it is located.

[0230] In one embodiment, the carrier layer may further comprise one or more additional sub-substrate layers. Figure 6M-6NThe additional sub-substrate layer is bonded to the upper and / or lower surfaces of the target sub-substrate layer by lamination. Preferably, the additional sub-substrate layer is bonded to the surface of the target sub-substrate layer without conductive channels by lamination, thereby supporting and reinforcing the target sub-substrate layer and increasing the flatness of the supporting substrate layer. On the one hand, to simplify the process, the additional sub-substrate layer can be directly laminated to the target sub-substrate layer without any pre-set structure. When part of the chip module protrudes from the mounting hole, the supporting layer after lamination of the additional sub-substrate layer is not a flat surface and has tolerable protrusions. On the other hand, to better adjust the flatness of the supporting layer, when the chip module substrate is not embedded in the mounting hole, and / or when the encapsulant of the chip module protrudes from the mounting hole to accommodate it, the additional sub-substrate layer can provide clearance holes at the corresponding positions of the protruding chip module substrate and / or chip encapsulant. To accommodate portions of the chip module substrate not embedded in mounting holes, and / or to accommodate portions of the chip module encapsulant protruding from mounting holes, the clearance hole can be a through-hole penetrating the additional sub-substrate layer, or it can simply form a notch without penetrating the additional sub-substrate layer. Furthermore, depending on the need for improvements in shape, stress, etc., the opening size of the clearance hole can be the same as or different from the mounting hole. Similarly, when one additional sub-substrate layer cannot achieve a leveling effect, multiple additional sub-substrate layers can be set. After the additional sub-substrate layers are set, the surface of the substrate layer no longer has protrusions. Based on this, after setting the additional sub-substrate layers, the target surface of the carrier layer will be flatter, while protecting the chip module and improving the mechanical properties of the carrier layer against bending, torsion, compression, and tension.

[0231] In another embodiment of this application, the substrate layer 100 includes three target sub-substrate layers. The first target sub-substrate layer is the one closest in vertical distance to the contact pad of the ultimately installed strip module, the third target sub-substrate layer is the one furthest in vertical distance from the contact pad of the ultimately installed strip module, and the second target sub-substrate layer is located between the first and third target sub-substrate layers. Combined with... Figure 6OBased on the positions of the first connection structure and the antenna structure on the target sub-substrate layer, the following sub-cases can be identified: First seed case: the inner lead and the antenna lead are located on the first surface of the first target sub-substrate layer; Second seed case: the inner lead and the antenna lead are located between the first and second target sub-substrate layers; Third seed case: the inner lead and the antenna lead are located between the second and third target sub-substrate layers; Fourth seed case: the inner lead and the antenna lead are located on the second surface of the third target sub-substrate layer. Based on the positions of the inner lead connection wire and the antenna winding, the above sub-cases can be further divided into the following sub-cases: First seed case: at least one of the inner lead connection wire and the antenna winding is located on the first target sub-substrate layer. The second surface of the first target sub-substrate layer, the second surface of the second target sub-substrate layer, or the second surface of the third target sub-substrate layer; the second seed case, in which at least one of the inner lead connecting wire and the antenna winding wire is located on the first surface of the first target sub-substrate layer, the second surface of the second target sub-substrate layer, or the second surface of the third target sub-substrate layer; the third seed case, in which at least one of the inner lead connecting wire and the antenna winding wire is located on the first surface of the first target sub-substrate layer, the second surface of the first target sub-substrate layer, or the second surface of the third target sub-substrate layer; the fourth seed case, in which at least one of the inner lead connecting wire and the antenna winding wire is located on the first surface of the first target sub-substrate layer, the second surface of the first target sub-substrate layer, or the second surface of the second target sub-substrate layer;

[0232] Preferred configuration 1: The inner lead and antenna lead are located between the first target sub-substrate layer and the second target sub-substrate layer, and the inner lead connecting wire and antenna winding wire are located between the second target sub-substrate layer and the third target sub-substrate layer. Figure 6O , 6Q -6S; Preferred scenario two: The inner lead and antenna lead are located between the second target sub-substrate layer and the third target sub-substrate layer; the inner lead connecting wire and the antenna winding wire are located between the first target sub-substrate layer and the second target sub-substrate layer, such as Figure 6P At this point, all antenna structures and the first connection structure are sandwiched and protected by the target sub-substrate layer, improving reliability.

[0233] In one embodiment, the chip module is preferably a WLCSP module. For the preferred embodiment described above, such as... Figure 6Q and Figure 6S When the chip module is mounted upright, the target surface of the chip module is located on the upper surface of the inner leads and antenna leads. The first target sub-substrate layer can directly cover the first surface of the chip module and the upper surface of the inner leads and antenna leads, or mounting holes can be provided in the first target sub-substrate layer to accommodate the chip module. For the above preferred scenario two, as... Figure 6PWhen flip-chip module is used, mounting holes are provided in the third target sub-substrate layer to accommodate the chip module. The third target sub-substrate layer can directly cover the first surface of the chip module and the upper surface of the internal leads and antenna leads, or mounting holes can be provided in the third target sub-substrate layer to accommodate the chip module. The mounting holes can be through holes penetrating the target sub-substrate layer or recesses to accommodate the chip module. When the mounting holes are through holes, after the chip module is installed, preferably, the first surface of the chip module is flush with the surface of the target sub-substrate layer on which it is located.

[0234] In one embodiment, the chip module is preferably a COB module. In the preferred embodiment described above, when the chip module is mounted upright, the target surface of the chip module is located on the upper surface of the inner leads and the antenna leads, such as... Figure 6O and Figure 6R The first target sub-substrate layer can directly cover the first surface of the chip module and the upper surface of the internal leads and antenna leads. Alternatively, mounting holes can be formed in the first target sub-substrate layer to accommodate the substrate of the COB chip module. These mounting holes for accommodating the COB chip module substrate are called first mounting holes. Mounting holes can also be formed in the second target sub-substrate layer to accommodate the encapsulation protrusions of the COB chip module. These mounting holes for accommodating the encapsulation protrusions of the COB chip module are called second mounting holes. Regarding the preferred embodiment described above... Figure 6N When flip-chip modules are used, the second sub-target substrate layer has a second mounting hole to accommodate the encapsulating adhesive protrusions of the chip module. The third sub-target substrate layer can directly cover the first surface of the chip module and the upper surface of the internal leads and antenna leads, or it can have a first mounting hole in the third sub-target substrate layer to accommodate the substrate of the COB chip module. The mounting hole can be a through-hole penetrating the target sub-substrate layer or a notch to accommodate the chip module. When the mounting hole is a via, after the chip module is installed, preferably, the first surface of the chip module is flush with the surface of the target sub-substrate layer on which it is located.

[0235] In one embodiment, the carrier layer may further comprise one or more additional sub-substrate layers, such as Figure 6T and 6UThe additional sub-substrate layer is bonded to the surface of the target sub-substrate layer without conductive channels by lamination, supporting and reinforcing the target sub-substrate layer while increasing its flatness. On one hand, to simplify the process, the additional sub-substrate layer can be directly laminated to the target sub-substrate layer without any pre-defined structures. When a portion of the chip module protrudes from the mounting hole, the resulting support layer after lamination is not a perfectly flat surface and may have tolerable protrusions. On the other hand, to better adjust the flatness of the support layer, when the chip module substrate is not embedded in the mounting hole, and / or when the encapsulant of the chip module protrudes from the mounting hole, the additional sub-substrate layer can provide clearance holes at the locations where the chip module substrate and / or the chip encapsulant protrude. To accommodate portions of the chip module substrate not embedded in mounting holes, and / or to accommodate portions of the chip module encapsulant protruding from mounting holes, the clearance hole can be a through-hole penetrating the additional sub-substrate layer, or it can simply form a notch without penetrating the additional sub-substrate layer. Furthermore, depending on the need for improvements in shape, stress, etc., the opening size of the clearance hole can be the same as or different from the mounting hole. Similarly, when one additional sub-substrate layer cannot achieve a leveling effect, multiple additional sub-substrate layers can be set. After the additional sub-substrate layers are set, the surface of the substrate layer no longer has protrusions. Based on this, after setting the additional sub-substrate layers, the target surface of the carrier layer will be flatter, while protecting the chip module and improving the mechanical properties of the carrier layer against bending, torsion, compression, and tension.

[0236] It should be understood that, for conductive channels etched by means of etching, the setting of the target sub-substrate layer and the additional sub-substrate layer should not affect the electrical connection process between the chip module and the conductive channel. If it affects the electrical connection process, the corresponding target sub-substrate layer and / or additional sub-substrate layer should be set after the electrical connection process between the chip module and the conductive channel is completed. For example, when anisotropic conductive adhesive is selected for the electrical connection process, the chip module can be placed and bonded through the via mounting holes in the target sub-substrate layer. In this case, whether the target sub-substrate layer with via mounting holes is set before or after the electrical connection process between the chip module and the conductive channel does not affect the electrical connection process. Therefore, there is no requirement for the timing of setting the target sub-substrate layer. When soldering is selected for the electrical connection process, unless the via mounting hole opening is large enough to accommodate the chip module while allowing the soldering instrument to complete the soldering process, the corresponding target sub-substrate layer needs to be set after the electrical connection process. Based on the same principle, for cases where the target sub-substrate layer / additional sub-substrate layer has notched mounting holes or notched clearance holes, or where the target sub-substrate layer / additional substrate layer directly covers and presses together, the target sub-substrate layer is set after the electrical connection between the chip module and the conductive channel is completed.

[0237] In one embodiment of this application, such as Figure 6L , it is Figure 2B or Figure 4The schematic diagram of the WLCSP chip module in the etched case along the AA direction is shown in the cross-sectional view. Since the first connection structure and the antenna winding are located on different target sub-substrate layers, the first connection structure and the antenna winding will not interfere with each other in the direction normal to the target surface of the carrier layer. Therefore, the antenna winding can be set below the projection area of ​​the strip module, that is, the projection area of ​​the strip module and the projection area of ​​the antenna winding overlap. At this time, the antenna winding can have a larger width and more turns, which improves resonance.

[0238] See Figure 4F This is a top view of the dual-interface smart card according to a specific embodiment of the present invention. Figure 5F-5G for Figure 4F A cross-sectional view along the AA direction, corresponding to the winding situation; Figure 6V-6Y All Figure 4F A cross-sectional view along the AA direction, corresponding to the etching situation. Based on all the above embodiments, in addition to the substrate layer, the dual-interface smart card of this embodiment further includes a supplementary support layer and a strip module. The supplementary support layer is located on the outer surface of the dual-interface smart card and is pressed against the first and second surfaces of the carrier layer, respectively. The supplementary support layer can be a smooth layer structure that is directly pressed against the substrate layer. Alternatively, to increase the flatness of the card, supplementary clearance holes can be provided at the required locations in the supplementary support layer to accommodate the protrusions of the substrate layer. If supplementary clearance holes are provided, they can only be notches. The supplementary support layer can be made of materials such as PVC to form the upper and lower surfaces of the smart card, or other materials can be used. This embodiment of the invention does not specifically limit this. It is worth noting that only some embodiments of this application are shown in the figure. Based on the foregoing embodiments, it is known that the same applies to reasonable combinations of carrier layers composed of other target sub-substrate layers and additional sub-substrate layers, or situations where the first connection structure and antenna are located in other positions, the XOR chip module is mounted upright or inverted, or whether electrical connection holes are provided or not. This invention does not show them all for the sake of simplifying the illustration.

[0239] After the supplementary support layer is pressed and supported onto the smart card substrate layer, the strip module will be installed. The strip module includes contact pads, a support layer, and multiple conductive pads arranged from top to bottom. By slotting the corresponding projection area of ​​the strip module in the supplementary support layer and substrate layer, the terminals of the first connection structure are exposed, and the strip module is installed. The conductive pads of the strip module are electrically connected to the matching first connection structure terminals in the substrate layer via anisotropic conductive adhesive or solder balls. The contact surface of the contact pads of the strip module is on the same plane as the first surface of the supplementary support layer. The contact surface of the contact pad refers to the surface of the contact pad that physically contacts an external terminal (e.g., a card reader) for communication. It is understood that the thickness of the support layer and conductive pads in the strip module can be adjusted according to process requirements.

Claims

1. A dual-interface smart card substrate layer, characterized in that, include: The carrier layer, the first connection structure, the antenna, and the chip module; The first connection structure, the antenna, and the chip module are all carried by the carrier layer. The first connection structure and the antenna are conductive channels and are electrically connected to the chip module respectively. The first connection structure and the antenna are enameled metal wires. The orthographic projection area of ​​the chip module on the target surface of the carrier layer does not overlap with the projection area of ​​the strip module of the carrier layer, wherein the target surface of the carrier layer is one of the surfaces with the largest area of ​​the carrier layer; The carrier includes a first target sub-substrate layer and a second target sub-substrate layer, wherein one of the first connection structure or antenna is embedded in the first target sub-substrate layer and the other is embedded in the second target sub-substrate layer; The chip module includes a substrate and a chip, the chip being mounted on a target surface of the substrate, wherein the target surface of the substrate is one of the surfaces with the largest area of ​​the substrate; the chip surface is encapsulated with encapsulating adhesive; The first target sub-substrate layer and / or the second target sub-substrate layer include mounting holes. Along a direction parallel to the target surface of the carrier layer, the size of the mounting holes is smaller than the size of the chip module substrate, and the size of the mounting holes is larger than the size of the chip module encapsulant. The mounting holes accommodate the encapsulant of the chip module.

2. The dual-interface smart card substrate layer as described in claim 1, characterized in that, The chip module substrate has multiple chip module contact pads on the surface of the chip, which are used to realize the electrical connection between the chip and the antenna and the first connection structure. Each chip module contact pad group includes a chip contact pad and a conductive channel contact pad, and the chip contact pad is electrically connected to the conductive channel contact pad. The chip contact pad is electrically connected to the chip pins, and the conductive channel contact pad is electrically connected to the first connection structure terminal or antenna terminal. The encapsulating adhesive also encapsulates the chip contact pad.

3. The dual-interface smart card substrate layer as described in claim 2, characterized in that, The mounting hole is a through hole or notch located in the first target sub-substrate layer or the second target sub-substrate layer.

4. The dual-interface smart card substrate layer as described in claim 2, characterized in that, The mounting holes include a first mounting hole and a second mounting hole. The first mounting hole accommodates the portion of the chip module encapsulant adjacent to the chip module substrate, and the second mounting hole accommodates the portion of the chip module encapsulant away from the chip module substrate. The first mounting hole and the second mounting hole are located in different target sub-substrate layers and are interconnected. Along the target surface direction parallel to the bearing layer, the size of the first mounting hole is greater than or equal to the size of the second mounting hole.

5. The dual-interface smart card substrate layer as described in claim 3, characterized in that, The vertical distance between the first surface of the chip module and the first surface of the first target sub-substrate layer is less than the vertical distance between the first surface of the chip module and the second surface of the second target sub-substrate layer; The first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure. The mounting hole is located in the second target sub-substrate layer.

6. The dual interface as described in claim 3, characterized in that, The vertical distance between the first surface of the chip module and the first surface of the first target sub-substrate layer is greater than the vertical distance between the first surface of the chip module and the second surface of the second target sub-substrate layer. The first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure. The mounting hole is located in the first target sub-substrate layer.

7. The dual-interface smart card substrate layer as described in claim 4, characterized in that, The vertical distance between the first surface of the chip module and the first surface of the first target sub-substrate layer is less than the vertical distance between the first surface of the chip module and the second surface of the second target sub-substrate layer; The first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure. The first mounting hole is located in the first target sub-substrate layer, and the second mounting hole is located in the second target sub-substrate layer.

8. The dual interface as described in claim 4, characterized in that, The vertical distance between the first surface of the chip module and the first surface of the first target sub-substrate layer is greater than the vertical distance between the first surface of the chip module and the second surface of the second target sub-substrate layer. The first surface of the chip module refers to the surface with the largest area in the chip module that does not have an electrical connection structure. The first mounting hole is located in the second target sub-substrate layer, and the second mounting hole is located in the first target sub-substrate layer.

9. The dual-interface smart card substrate layer as described in claim 7 or 8, characterized in that, The first mounting hole and the second mounting hole are vias in the target sub-substrate layer; The conductive channel contact pad of the chip module, the first connection structure terminal and the antenna terminal, and the second mounting hole overlap on the target surface of the carrier layer.

10. The dual-interface smart card substrate layer as described in claim 7 or 8, characterized in that, The first mounting hole is a via in the target sub-substrate layer; The orthographic projection area of ​​the conductive channel contact pad of the chip module on the target surface of the carrier layer does not overlap with the orthographic projection area of ​​the first mounting hole on the target surface of the carrier layer. The conductive channel contact pad of the chip module overlaps with the orthographic projection area of ​​the first connection structure terminal and the antenna terminal on the target surface of the carrier layer.

11. The dual-interface smart card substrate layer as described in claim 7 or 8, characterized in that, The first mounting hole is a via in the target sub-substrate layer, and the second mounting hole does not penetrate the target sub-substrate layer. The conductive channel contact pad of the chip module overlaps with the orthographic projection area of ​​the first connection structure terminal and the antenna terminal on the target surface of the carrier layer.

12. The dual-interface smart card substrate layer as described in claims 5-6 and 10-11, characterized in that... The first target sub-substrate layer and the second target sub-substrate layer also include electrical connection vias; The orthographic projection area of ​​the electrical connection via on the target surface of the carrier layer overlaps with the orthographic projection area of ​​the first connection structure terminal, the antenna terminal, and the conductive channel contact pad of the chip module on the target surface of the carrier layer. The electrical connection via exposes the first connection structure terminal, the antenna terminal, and the conductive channel contact pad of the chip module.

13. The dual-interface smart card substrate layer as described in claim 12, characterized in that... The electrical connection via contains conductive filler.

14. The dual-interface smart card substrate layer as described in claims 1-13, characterized in that... The carrier layer further comprises one or more additional sub-substrate layers, which are located above and / or below the two target sub-substrate layers.

15. The dual-interface smart card substrate layer as described in claim 14, characterized in that, The one or more additional sub-substrate layers also include clearance holes, which are vias or notches, to accommodate the portion of the chip module not accommodated by the target sub-substrate layer.

16. The dual-interface smart card substrate layer as described in claims 1-15, characterized in that, The first connection structure is located on the first surface adjacent to the first target sub-substrate layer, and the antenna is located on the first surface of the second target sub-substrate layer; Alternatively, the first connection structure is adjacent to the second surface of the first target sub-substrate layer, and the antenna is adjacent to the second surface of the second target sub-substrate layer; Alternatively, the first connection structure is adjacent to the first surface of the second target sub-substrate layer, and the antenna is adjacent to the first surface of the first target sub-substrate layer; Alternatively, the first connection structure is adjacent to the second surface of the second target sub-substrate layer, and the antenna is adjacent to the second surface of the first target sub-substrate layer.

17. A dual-interface smart card, characterized in that, It includes: a strip module, a supplementary support layer, and a dual-interface smart card substrate layer as described in claims 1-16; The strip module includes a contact pad, a support layer, and multiple conductive pads. The contact pad and conductive pads are located on both sides of the support layer and are electrically connected to each other. The supplementary support layer includes a first supplementary support layer and a second supplementary support layer, and the dual-interface smart card substrate layer is located between the first supplementary support layer and the second supplementary support layer; The multiple conductive pads of the strip module are electrically connected to the corresponding first connection structures. The contact surface of the strip module contact pad is flush with the surface of the first supplementary support layer that is not connected to the dual-interface smart card substrate layer.

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