Microprocessor architecture and graphics processor

Abstract

The invention provides a microprocessor architecture and a graphics processor, the microprocessor architecture comprises the graphics processor and a memory, and the memory comprises a consistent access memory space and a non-consistent access memory space; wherein the graphics processor accesses the consistency access memory space through a consistency internet, or the graphics processor accesses the non-consistency access memory space through a direct path. The microprocessor architecture can reduce the delay and power consumption when the graphics processor accesses the memory.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more particularly to a microprocessor architecture and a graphics processor. Background Technology

[0002] As chip designs become increasingly large-scale, the integrated central processing unit (CPU), graphics processing unit (GPU), and memory also become larger, such as integrating more and more CPU cores and larger amounts of memory. Typically, see [link to relevant documentation]. Figure 1 As shown, the communication connection between the central processing unit, graphics processing unit and memory is realized through a consistent interconnect network within the microprocessor architecture.

[0003] Accessing memory through the Consistent Interconnect Network (CIN) requires numerous lookup operations, such as retrieving data from the CIN cache. However, in some cases, the graphics processing unit (GPU) only needs to request data in memory, which is not cached in the CIN. Therefore, cache lookup operations are unnecessary. In such cases, processing the GPU's memory access requests through the CIN would cause unnecessary latency and power consumption. Summary of the Invention

[0004] Based on the above-mentioned technical problems, this application proposes a microprocessor architecture and a graphics processor that can reduce the latency and power consumption of the graphics processor when accessing memory.

[0005] A first aspect of this application provides a microprocessor architecture including a graphics processor and memory, wherein the memory includes a consistent access memory space and a non-consistent access memory space; wherein the graphics processor accesses the consistent access memory space through a consistent interconnect network, or the graphics processor accesses the non-consistent access memory space through a direct path.

[0006] A second aspect of this application provides a graphics processor (GPU) applied to a microprocessor architecture, the microprocessor architecture further including memory, the memory comprising a consistent access memory space and a non-consistent access memory space; the GPU accesses the consistent access memory space via a consistent interconnect network, or the GPU accesses the non-consistent access memory space via a direct path.

[0007] Based on the above scheme, two paths are established between the graphics processing unit (GPU) and memory in the microprocessor architecture: a consistent interconnect network and a direct path between the GPU and memory. Furthermore, consistent and inconsistent access memory spaces are configured in memory corresponding to the GPU. Based on this architecture, when the GPU accesses the consistent access memory space, it does so through the consistent interconnect network; when it accesses the inconsistent access memory space, it does so directly through the direct path. In this way, memory access requests from the GPU that require access to the inconsistent access memory space can be sent directly to memory through the direct path between the GPU and memory, without needing to perform cache lookups through the consistent interconnect network, thereby reducing latency and power consumption.

[0008] In some implementations, the consistent access memory space is used to store a first type of data, and the inconsistent access memory space is used to store a second type of data; wherein the first type of data can be cached in the storage space of the consistent interconnect network, and the second type of data is stored only in the memory.

[0009] Based on this implementation, the memory is divided into a consistent access memory space and a non-consistent access memory space to store different types of data. This allows the processor to access different types of data through different memory spaces. At the same time, the data types of different memory spaces are matched with the memory space access paths, enabling efficient data access to different memory spaces.

[0010] In some implementations, the microprocessor architecture also includes a routing module; the routing module is used to receive memory access requests sent by the graphics processor and send the memory access requests to the consistent access memory space through the consistent interconnect network, or send the access requests to the non-consistent access memory space through the direct path.

[0011] Based on this implementation, the routing module is responsible for forwarding and routing memory access requests issued by the graphics processor, which can reduce the resource consumption of the graphics processor and facilitate the routing control of memory access requests.

[0012] In some implementations, the routing module stores address information of the consistent access memory space and address information of the inconsistent access memory space. The routing module sends the memory access request to the consistent access memory space via the consistent interconnect network, or sends the memory access request to the inconsistent access memory space via the direct path. This includes: the routing module comparing the destination address of the memory access request with the addresses of the consistent access memory space and the inconsistent access memory space to determine the memory space corresponding to the memory access request; if the memory space corresponding to the memory access request is determined to be the consistent access memory space, the routing module sends the memory access request to the consistent access memory space via the consistent interconnect network; or, if the memory space corresponding to the memory access request is determined to be the inconsistent access memory space, the routing module sends the memory access request to the inconsistent access memory space via the direct path.

[0013] Based on this implementation, the routing module automatically determines the memory space corresponding to the memory access request by the address of the memory access request, and then automatically selects a communication link to send the memory access request, thus achieving efficient routing and forwarding of memory access requests.

[0014] In some implementations, the routing module stores routing method information, which includes hash granularity information; the memory includes multiple memory blocks; when it is determined that the memory space corresponding to the memory access request is the inconsistent access memory space, the routing module sends the memory access request to the inconsistent access memory space through the direct path, including: the routing module performs a hash operation on the destination address of the memory access request according to the hash granularity, and determines the destination memory block corresponding to the destination address based on the hash operation result; the routing module sends the memory access request to the memory controller corresponding to the target memory block through the direct path.

[0015] Based on this implementation, the routing module can correctly send memory access requests to the corresponding memory blocks, thereby achieving accurate transmission of memory access requests.

[0016] In some implementations, the routing module performs a hash operation on the destination address of the memory access request according to the hash granularity, and determines the destination memory block corresponding to the destination address based on the hash operation result. This includes: the routing module determining the memory range requested by the memory access request based on the destination address of the memory access request; if the memory range is not larger than the hash granularity, the routing module performs a hash operation on the starting address of the destination address of the memory access request according to the hash granularity, and determines the target memory block corresponding to the destination address based on the hash operation result; or, if the memory range is larger than the hash granularity, the routing module splits the memory access request into multiple sub-requests according to the hash granularity, wherein the memory range requested by each sub-request is not larger than the hash granularity; the routing module performs a hash operation on the starting address of each sub-request according to the hash granularity, and determines the target memory block corresponding to each sub-request based on the hash operation result.

[0017] Based on this implementation, the routing module can split memory access requests, thereby accurately sending larger-granularity memory access requests to the corresponding memory blocks.

[0018] In some implementations, the graphics processor includes multiple graphics processors, each connected to the routing module. The routing module is configured with permission information for each graphics processor, including request priority information and / or resource usage permission information. When the memory access request includes memory access requests sent by each of the multiple graphics processors, the routing module determines the memory access request to be prioritized from the multiple memory access requests based on the permission information of each graphics processor. The prioritized memory access request is then sent to the consistent access memory space via the consistent interconnect network, or to the non-consistent access memory space via the direct path.

[0019] Based on this implementation, when multiple graphics processors access memory simultaneously, the routing module can forward memory access requests in an orderly manner, thereby ensuring the quality of system services.

[0020] In some implementations, the microprocessor architecture further includes a central processing unit (CPU) connected to the memory via the coherent interconnect network; the CPU is used to configure the coherent access memory space and the non-coherent access memory space for the graphics processor.

[0021] Based on this implementation method, memory space is allocated to the graphics processor through the central processing unit, realizing unified memory allocation for the entire system architecture and ensuring orderly planning of system memory.

[0022] In some implementations, where the microprocessor architecture includes the routing module, the central processing unit is further configured to configure request routing information in the routing module; the request routing information includes memory access space configuration information and routing method information; where the graphics processor includes multiple graphics processors, the request routing information also includes permission information for each graphics processor; wherein, the memory access space configuration information includes address information for consistent memory access and address information for inconsistent memory access; the routing method information includes hash granularity information, and the routing method information is consistent with the routing method of the consistent interconnect network for memory access requests; the permission information includes request priority information and / or resource usage permission information.

[0023] Based on this implementation, the central processing unit (CPU) configures request routing information for the routing module, enabling the routing module to perform memory access request routing operations based on the request routing information. Furthermore, this processing method allows the CPU to control the memory access process of the graphics processing unit (GPU), thus achieving centralized control over the GPU's memory access. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0025] Figures 1-4 The following are schematic diagrams of several microprocessor architectures provided for embodiments of this application.

[0026] Figure 5 This is a schematic diagram of memory space partitioning provided for an embodiment of this application.

[0027] Figure 6 This is a schematic diagram of another microprocessor architecture provided in an embodiment of this application. Detailed Implementation

[0028] As chip designs become increasingly large-scale, the integrated central processing unit (CPU), graphics processing unit (GPU), and memory also become larger, such as integrating more and more CPU cores and larger amounts of memory. Typically, see [link to relevant documentation]. Figure 1As shown, within the microprocessor architecture, a consistent interconnect network enables communication between the central processing unit, graphics processing unit, and memory.

[0029] The Central Processing Unit (CPU) can be one or more, or a CPU can include one or more processor cores. The Graphics Processing Unit (GPU) can be one or more, and a GPU can include one or more core processing units.

[0030] In addition, such as Figure 1 As shown, the microprocessor architecture may also include a video processing unit (VPU) and a display controller (DC). In some embodiments, the video processor and display controller described above may also be integrated into the graphics processor, thereby enabling graphics processing, video processing, and display control to be performed by a single processor. That is, one processor is responsible for the image processing tasks of the entire microprocessor architecture, while the central processing unit is used for other computational processing.

[0031] In embodiments of this specification, a graphics processor is used to refer to a unit in a microprocessor architecture that performs graphics processing tasks. That is, a graphics processor can refer to a standalone graphics processing unit (GPU), or it can be used to refer to a video processor or a display controller, or it can be used to refer to a combination of a graphics processor, a video processor, and a display controller.

[0032] Memory in a microprocessor architecture can include one or more memory blocks, which can be the same size or different sizes. For example Figure 1 As shown, the memory in a microprocessor can include four memory blocks: DDR0, DDR1, DDR2, and DDR3.

[0033] exist Figure 1 In the microprocessor architecture shown, both the central processing unit (CPU) and the graphics processing unit (GPU) are connected to memory via a coherent interconnect network. This coherent interconnect network is an on-chip network that satisfies cache coherency protocols. Since each processor in the microprocessor architecture accesses memory through this coherent interconnect network, cache coherency is guaranteed for the entire microprocessor architecture.

[0034] The coherent interconnect network employs a complex last-level cache, which is shared by all processors or processor cores. Each processor or processor core can also have its own dedicated cache. For example, a dedicated L1 and L2 cache can be configured within the processor or processor core, while a L3 cache can be configured within the coherent interconnect network.

[0035] When a processor or processor core needs to read or write data, it first queries the L1 cache for the target data. If the target data is not found in the L1 cache, it sends a request to the L2 cache to request the target data. If the target data exists in the L2 cache, the L2 cache returns the target data to the L1 cache and stores the target data in the L1 cache. If the target data is also not found in the L2 cache, it sends a request to the L3 cache to request the target data. If the target data exists in the L3 cache, the L3 cache returns the target data to the L2 cache, and the L2 cache stores the target data in its own cache and returns the target data to the L1 cache. If the target data is still not found in the L3 cache, it sends a request to memory to request the target data. After memory returns the target data to the L3 cache, the target data is then returned to the L2 cache and the L1 cache in turn.

[0036] The last-level cache in a coherent interconnect network helps the processor or processor core retrieve data from the cache instead of reading data from memory every time. Since the processor or processor core can access the cache faster than it can access memory, accessing memory through the coherent interconnect network helps improve data read and write efficiency.

[0037] The data processed by a graphics processor is usually large image or video data. In some cases, this data is not stored in the cache. In such cases, the graphics processor needs to request the corresponding data from memory and does not need to perform a cache lookup operation.

[0038] In response to the above situation, if the graphics processor's memory access requests are processed through a consistent interconnect network, a series of cache lookup operations must be performed until the target data is confirmed to be absent from the last-level cache, at which point it is retrieved from memory. Since the data requested by the graphics processor is only stored in memory, the cache lookup operations performed through the consistent interconnect network are redundant, causing unnecessary latency. Furthermore, performing a large number of meaningless cache lookup operations also results in unnecessary power consumption.

[0039] In response to the above situation, this application proposes a new microprocessor architecture and provides a new memory access scheme based on the microprocessor architecture, which can reduce the latency and power consumption of the graphics processor in the microprocessor architecture when accessing memory.

[0040] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0041] First, this application provides a microprocessor architecture.

[0042] See Figure 2 As shown, the microprocessor architecture provided in this embodiment includes a graphics processor and memory.

[0043] The graphics processing unit (GPU) can be one or more, and a graphics processing unit can include one or more core processing units.

[0044] In addition, such as Figure 2 As shown, the microprocessor architecture may also include a video processing unit (VPU) and a display controller (DC). In some embodiments, the video processor and display controller described above may also be integrated into the graphics processor, thereby enabling graphics processing, video processing, and display control to be performed by a single processor. That is, one processor is responsible for the image processing tasks of the entire microprocessor architecture, while the central processing unit is used for other computational processing.

[0045] In embodiments of this specification, a graphics processor is used to refer to a unit in a microprocessor architecture that performs graphics processing tasks. That is, a graphics processor can refer to a standalone graphics processing unit (GPU), or it can be used to refer to a video processor or a display controller, or it can be used to refer to a combination of a graphics processor, a video processor, and a display controller.

[0046] The number of graphics processors can be one or more. When there are multiple graphics processors, they can be the same or different; for example, it can include multiple graphics processors, multiple video processors, or a combination of multiple graphics processors and video processors.

[0047] The memory in a microprocessor architecture can include one or more memory blocks, which can be the same size or different sizes.

[0048] like Figure 2 As described in this application embodiment, a consistent access memory space and a non-consistent access memory space are set up in memory for the graphics processor. When there are multiple graphics processors, a corresponding consistent access memory space and a non-consistent access memory space can be set up for each graphics processor. That is, in Figure 2 In the microprocessor architecture shown, each graphics processor has its own corresponding consistent access memory space and non-consistent access memory space.

[0049] Consistent access memory space refers to memory space accessed through a consistent interconnect network; non-consistent access memory space refers to memory space that can be accessed without going through a consistent interconnect network.

[0050] The aforementioned consistent access memory space is used to store data that will be cached in the consistent interconnect network's storage space, that is, to store data that will be copied to the consistent interconnect network's cache. Therefore, accessing data in this consistent access memory space through the consistent interconnect network can improve data access speed.

[0051] The aforementioned inconsistent access memory space is used to store data that is only stored in memory and will not be stored in the consistent interconnect network; that is, it is used to store data in the cache that will not be copied to the consistent interconnect network. Accessing data in this inconsistent access memory space through the consistent interconnect network does not improve data access speed; on the contrary, it increases access latency and power consumption. Therefore, data in this inconsistent access memory space can be accessed without going through the consistent interconnect network.

[0052] In some embodiments, when the central processing unit writes data to memory, it divides the data into a first type of data and a second type of data, and stores the different types of data into different memory spaces.

[0053] Specifically, if the data to be written to memory is data that is only stored in memory and will not be stored in the consistent interconnect network storage space, such as data that the graphics processor needs to read and process directly from memory, then the data can be identified as second type data. When writing the second type data to memory, it needs to be written to the non-consistent access memory space.

[0054] If the data to be written to memory is not data that the graphics processor needs to read and process directly from memory, but rather data that will be cached in the storage space of the coherent interconnect network, such as data processed by the central processing unit, then the data can be identified as first-type data. When writing first-type data to memory, it needs to be written to the coherent access memory space.

[0055] In some embodiments, memory can be a single memory block, in which case consistent access memory space and inconsistent access memory space can be different storage spaces within that memory block.

[0056] In some embodiments, memory can be multiple memory blocks. In this case, consistent access memory space and inconsistent access memory space can be different storage spaces in the same memory block or storage spaces in different memory blocks.

[0057] Furthermore, when there are multiple graphics processors, a consistent access memory space and a non-consistent access memory space can be set up in memory for each graphics processor according to the above scheme.

[0058] In other embodiments, a memory controller is also provided in the microprocessor architecture to receive memory access requests and perform data read / write operations on the memory according to the memory access requests. The aforementioned consistent access memory space and inconsistent access memory space can correspond to the same memory controller, or separate memory controllers can be set up. When the memory includes multiple memory blocks, a separate memory controller can be set up for each memory block. This application does not limit the number or setting method of memory controllers.

[0059] like Figure 2 As shown, corresponding to the consistent access memory space and the non-consistent access memory space mentioned above, this application embodiment sets up two paths between the graphics processor and memory in the microprocessor architecture, namely the original consistent interconnect network and the newly added direct path between the graphics processor and the non-consistent access memory space.

[0060] The aforementioned direct path can be any data communication line, such as the PCIe bus (Peripheral Component Interconnect Express, high-speed serial computer expansion bus), AXI (Advanced Dextensible Interface) bus, etc.

[0061] The aforementioned consistent interconnect network is used to access the consistent memory space in memory, while the aforementioned direct path is used to access the inconsistent memory space in memory.

[0062] Based on the microprocessor architecture described above, when the graphics processor (GPU) needs to access the consistent access memory space, it can do so through the consistent interconnect network between the GPU and the memory. For example, the GPU sends a memory access request to the consistent interconnect network, which then forwards the request to the consistent access memory space. If the required data is found in the consistent interconnect network's cache when it sends the memory access request, the consistent interconnect network can directly return the access result to the GPU.

[0063] When a graphics processor (GPU) needs to access non-uniform memory, it can do so through a direct path between the GPU and main memory. For example, the GPU sends a memory access request to the direct path, which then forwards the request directly to the non-uniform memory.

[0064] As described above, the microprocessor architecture proposed in this application establishes two paths between the graphics processor (GPU) and memory: a consistent interconnect network and a direct path between the GPU and memory. Furthermore, consistent and inconsistent access memory spaces are configured in memory corresponding to the GPU. Based on this architecture, when the GPU accesses the consistent access memory space, it does so through the consistent interconnect network; when it accesses the inconsistent access memory space, it does so directly through the direct path. Thus, memory access requests from the GPU that require access to the inconsistent access memory space can be directly sent to memory through the direct path between the GPU and memory, without needing to perform cache lookup operations through the consistent interconnect network, thereby reducing latency and power consumption.

[0065] In another embodiment, see Figure 3 As shown, the microprocessor architecture provided in this embodiment includes a routing module, which is connected to the graphics processor. The routing module is then connected to the memory via a consistent interconnect network and a direct path, thereby making the routing module an intermediate medium for communication and interaction between the graphics processor and the memory.

[0066] The routing module is used to receive memory access requests sent by the graphics processor, and if it is confirmed that the memory access request is for accessing the consistent access memory space, it sends the memory access request to the consistent access memory space through the aforementioned consistent interconnect network; or, if it is confirmed that the memory access request is for accessing the non-consistent access memory space, it sends the access request to the non-consistent access memory space through the aforementioned direct path.

[0067] In other embodiments, see Figure 4 As shown, the microprocessor architecture provided in this embodiment also includes a central processing unit (CPU), which is connected to memory through a coherent interconnect network. The CPU can access any memory space of the memory through the coherent interconnect network.

[0068] The aforementioned central processing unit can be one or more, or a central processing unit can include one or more processor cores.

[0069] In this embodiment, the central processing unit can pre-configure a consistent access memory space and a non-consistent access memory space for the graphics processor.

[0070] For example, the central processing unit can directly divide the memory storage space into a consistent access memory space and a non-consistent access memory space, and then allocate the consistent access memory space and the non-consistent access memory space to the graphics processor for use.

[0071] Alternatively, the central processing unit (CPU) can allocate memory space for the graphics processing unit (GPU) in memory, and then divide that allocated memory space into a consistent access memory space and a non-consistent access memory space. The number of consistent access memory spaces and non-consistent access memory spaces can each be one or more. Furthermore, consistent access memory spaces and non-consistent access memory spaces should not overlap; however, overlap is possible between different consistent access memory spaces and between different non-consistent access memory spaces.

[0072] When there are multiple graphics processors in a microprocessor architecture, the central processing unit can configure a consistent access memory space and a non-consistent access memory space for each graphics processor in the manner described above.

[0073] Figure 5 The diagram illustrates the division of coherent and non-coherent access memory spaces within the memory space allocated to the graphics processor, including two coherent access memory spaces and two non-coherent access memory spaces.

[0074] In other embodiments, the central processing unit can also configure routing methods for the graphics processors, and when there are multiple graphics processors, permission information can be configured for each of the multiple graphics processors.

[0075] In this embodiment, the routing method mentioned above refers to routing memory access requests through hashing. That is, the memory block corresponding to the memory access request is determined by performing a hash operation on the request address of the memory access request, and then the memory access request is routed to the corresponding memory block.

[0076] Furthermore, this application supports hashing methods with different granularities, such as a 64-byte granularity hashing method or a 256-byte granularity hashing method. The 64-byte granularity hashing method involves truncating the lower 6 bits of the memory access request's starting address, then performing a hash operation on the remaining bits of that memory address. The resulting hash value determines the memory block corresponding to the memory access request. Similarly, the 256-byte granularity hashing method involves truncating the lower 8 bits of the memory access request's starting address, then performing a hash operation on the remaining bits of that memory address. The resulting hash value determines the memory block corresponding to the memory access request.

[0077] When configuring the routing method for the graphics processor, the CPU determines the hash granularity for hashing memory access requests. Furthermore, the CPU's routing method for the graphics processor is consistent with the routing method of the consistent interconnect network for memory access requests. In other words, the hash granularity configured by the CPU for the graphics processor is consistent with the hash granularity when the consistent interconnect network routes memory access requests.

[0078] The above-mentioned permission information for the graphics processor includes priority information and / or resource usage permission information for each graphics processor.

[0079] Priority information refers to the memory access priority of each graphics processor when multiple graphics processors access memory simultaneously. In this embodiment, the central processing unit supports two methods for configuring the priority of graphics processors: statically overriding the original QoS (Quality of Service) and dynamically adjusting QoS based on bandwidth and latency, thereby ensuring the memory access quality of different graphics processors.

[0080] Resource usage permission information refers to the permission information for different graphics processors to access memory resources. This permission information can allocate memory access resources to different graphics processors in an orderly manner when multiple graphics processors access memory simultaneously. Furthermore, in other embodiments, the resource usage permissions of different graphics processors can be flexibly adjusted.

[0081] After the central processing unit (CPU) allocates consistent access memory space and non-consistent access memory space for the graphics processing unit (GPU), and configures routing and permission information for the GPU, it stores the memory access configuration information and routing information as the request routing information corresponding to the GPU in a specific location. Figure 4The routing module shown includes a module that writes permission information for each graphics processor (GPU). This allows the routing module to store the request routing information and permission information corresponding to each GPU, and to route and forward memory access requests sent by each GPU based on this information.

[0082] See Figure 3 or Figure 4 The microprocessor architecture shown in some embodiments discloses that the routing module stores memory access space configuration information corresponding to the graphics processor, that is, it stores address information of the consistent access memory space and address information of the non-consistent access memory space corresponding to the graphics processor.

[0083] Based on this, when the routing module receives a memory access request sent by the graphics processor, it compares the destination address of the memory access request with the address of the consistent access memory space corresponding to the graphics processor and the address of the non-consistent access memory space corresponding to the graphics processor to determine the memory space corresponding to the memory access request.

[0084] Specifically, when the graphics processor needs to access memory for data read / write operations, it sends a memory access request to the routing module. This memory access request contains destination address information, including the starting address of the destination address and the memory range to be accessed. For example, the memory access request carries the starting address of the destination address and the request granularity. For instance, assuming the starting address of the destination address of the memory access request is 0x0000_0080 and the request granularity is 256 bytes, it means that the memory access request is for accessing 256 bytes of memory space starting from 0x0000_0080.

[0085] After receiving a memory access request from the graphics processor, the routing module compares the starting address of the destination address of the memory access request with the addresses of the consistent and inconsistent access memory spaces allocated to the graphics processor. It determines whether the starting address of the destination address falls within the address range of the consistent or inconsistent access memory space, thus identifying whether the memory space corresponding to the memory access request is a consistent or inconsistent access memory space. If the starting address of the destination address falls within the address range of the consistent access memory space, the memory space corresponding to the memory access request is determined to be a consistent access memory space; conversely, if the starting address falls within the address range of the inconsistent access memory space, the memory space corresponding to the memory access request is determined to be an inconsistent access memory space.

[0086] If the memory space corresponding to the memory access request is determined to be a consistent access memory space, the routing module sends the memory access request to the consistent access memory space through the consistent interconnect network. That is, the routing module sends the memory access request to the consistent interconnect network, and the consistent interconnect network then sends the memory access request to the consistent access memory space.

[0087] or,

[0088] If it is determined that the memory space corresponding to the memory access request is a non-consistent access memory space, the routing module sends the memory access request to the non-consistent access memory space through the direct path.

[0089] In some embodiments, if the memory includes a memory block and the memory block is configured with a consistent access memory space and a non-consistent access memory space corresponding to the graphics processor, the routing module can send the memory access request to the memory controller through a direct path, and then the memory controller can perform data read and write operations on the non-consistent access memory space based on the memory access request.

[0090] In other embodiments, if the memory comprises multiple memory blocks, the memory access request needs to be routed according to the routing method pre-configured by the central processing unit.

[0091] Specifically, the routing module forwards memory access requests to memory by executing steps A1 and A2 as follows:

[0092] A1. The routing module performs a hash operation on the destination address of the memory access request according to the hash granularity in the routing method, and determines the destination memory block corresponding to the destination address based on the hash operation result.

[0093] Specifically, the routing module truncates and hashes the starting address of the destination address of the memory access request according to the hash granularity recorded in the routing method. Specifically, it truncates the low-order bits of the starting address of the destination address of the memory access request according to the hash granularity recorded in the routing method, and then performs a hash operation on the remaining address bits of the starting address.

[0094] For example, assuming the starting address of the destination address of a memory access request is 0x0000_0080 and the hash granularity is 64 bytes, the lower 6 bits of this starting address 0x0000000000000000_0000000010000000 are truncated, and the remaining address bits 0x00000000000000000_0000000010 are hashed. The resulting hash is the number of the destination memory block corresponding to the destination address. For example, when memory includes multiple memory blocks, each memory block is pre-assigned a unique number. Assuming the memory includes memory block 0, memory block 1, memory block 2, and memory block 3, if the hash result of hashing the starting address of the destination address of a memory access request in the above manner is 1, then the target memory block corresponding to the memory access request can be determined to be memory block 1.

[0095] In other embodiments, when the memory comprises multiple memory blocks, the consistent access memory space and the inconsistent access memory space corresponding to the same graphics processor may be distributed across different memory blocks.

[0096] The memory access request issued by the graphics processor may be a long contiguous space within a coherent or non-coherent memory space. This contiguous space may actually be distributed across different memory blocks in memory, and each memory block corresponds to a different memory controller. In this case, the memory access request needs to be split and the split request sent to the memory controller of the corresponding memory block.

[0097] To achieve the above objectives, the central processing unit (CPU) configures a hash granularity for the graphics processing unit (GPU) and a packet splitting rule based on that hash granularity. The hash granularity configuration must ensure that hashing the destination address of a memory access request according to the configured granularity results in a memory block containing the complete memory range requested by the memory access request. The packet splitting rule refers to splitting the memory access request according to the hash granularity when the requested memory range is larger than the hash granularity. This ensures that the memory range requested by each sub-request is no larger than the hash granularity, guaranteeing that the memory block determined by hashing each sub-request contains the complete memory range requested by that sub-request.

[0098] Based on the above scheme, when the routing module receives a memory access request sent by the graphics processor, it determines the memory range requested by the memory access request according to the destination address of the memory access request.

[0099] For example, if a memory access request includes the starting address of the requested memory and the request granularity, the size of the memory range to be accessed can be determined based on the request granularity. For instance, if the request granularity of a memory access request is 256 bytes, then the memory range requested by the memory access request is a 256-byte memory range.

[0100] Alternatively, the memory access request can include the start and end addresses of the requested memory. The memory range determined by the start and end addresses is the memory range requested by the memory access request.

[0101] After determining the memory range requested by the memory access request, the routing module further determines whether the size of the memory range requested by the memory access request is greater than the hash granularity.

[0102] If the memory range requested by the memory access request is not greater than the hash granularity, the routing module can directly perform a hash operation on the starting address of the destination address of the memory access request according to the hash granularity, and determine the target memory block corresponding to the destination address based on the hash operation result.

[0103] If the memory access request requests a memory range larger than the hash granularity, the routing module splits the memory access request into multiple sub-requests based on the hash granularity, ensuring that the size of the memory range requested by each sub-request is no larger than the hash granularity.

[0104] For example, suppose the starting address of a memory access request is 0x0000_0080, the request granularity is 256 bytes, and the hash granularity is 64 bytes. It can be seen that the memory range requested by this memory access request is larger than the hash granularity. In this case, the routing module splits the 256-byte memory access request into 4 sub-requests. The starting addresses of each sub-request are 0x0000_0080, 0x0000_00c0, 0x0000_0100, and 0x0000_0140, and the granularity of each sub-request is 64 bytes.

[0105] After splitting the memory access request, the routing module performs a hash operation on the starting address of each sub-request according to the hash granularity, and determines the target memory block corresponding to each sub-request based on the hash operation result.

[0106] For example, for the sub-requests with starting addresses of 0x0000_0080, 0x0000_00c0, 0x0000_0100, and 0x0000_0140, the routing module performs a hash operation on the starting address of each sub-request and determines the target memory block corresponding to each sub-request based on the hash operation result. The specific hash operation method and the method of determining the target memory block based on the hash operation result can be found in the corresponding descriptions in the above embodiments.

[0107] A2. The routing module sends the memory access request to the memory controller corresponding to the target memory block through the direct path.

[0108] Specifically, after determining the target memory block corresponding to the memory access request, the routing module sends the memory access request to the memory controller corresponding to the target memory block through a direct path. The memory controller then performs data read and write operations on the target memory block according to the memory access request.

[0109] When the routing module splits a memory access request into multiple sub-requests and determines the target memory block corresponding to each sub-request, the routing module sends each sub-request to the memory controller corresponding to the target memory block of each sub-request through a direct path. The memory controller then performs data read and write operations on the target memory block according to the sub-request.

[0110] In other embodiments, when multiple graphics processors simultaneously send memory access requests to the routing module, the routing module, upon receiving the memory access requests from multiple graphics processors, determines the memory access request to be processed first from the received memory access requests based on the permission information of each graphics processor pre-configured in the routing module by the central processing unit.

[0111] For example, the permission information for each graphics processor includes its priority and / or resource usage permission information. For a given graphics processor, the higher its priority and / or the greater its resource usage permission, the higher the priority at which memory access requests sent by that graphics processor will be processed. Based on this implementation method, the memory access request that is prioritized for processing can be determined from multiple memory access requests.

[0112] After identifying the memory access request that is prioritized, the routing module further determines the memory space requested by the memory access request, as described in the above embodiments. If the memory space requested by the memory access request is a consistent access memory space, the routing module sends the memory access request to the consistent access memory space through the consistent interconnect network; if the memory space requested by the memory access request is a non-consistent access memory space, the routing module sends the memory access request to the non-consistent access memory space through a direct path. The specific request sending process can be found in the above embodiments.

[0113] In another embodiment, see Figure 6 As shown, the microprocessor architecture provided in this embodiment includes multiple graphics processors and multiple memory blocks.

[0114] like Figure 6 As shown, the multiple graphics processors are GPU, VPU and DC, and the multiple memory blocks are DDR0, DDR1, DDR2 and DDR3.

[0115] At the same time, multiple routing modules are set in this microprocessor architecture, such as Figure 6 The ROUTE0, ROUTE1, ROUTE2, ROUTE3, and ROUTE4 shown in the diagram are connected to the Consistency Interconnect Network and to each memory block via a direct path. This allows each routing module to send memory access requests to the Consistency Interconnect Network or to each memory block via a direct path.

[0116] The aforementioned routing modules are assigned to different graphics processors, for example... Figure 6 As shown, a routing module can connect to multiple different graphics processors, thereby receiving memory access requests sent by multiple different graphics processors; or, a graphics processor can also connect to multiple different graphics processors, so that the memory access requests sent by that graphics processor can be forwarded by different routing modules.

[0117] In implementing the scheme of this embodiment, the graphics processor (GPU) can be connected to one or more routing modules based on its memory access frequency. For example, when the GPU's memory access frequency is high, it indicates that the GPU needs to send memory access requests to memory frequently or intensively. In this case, to process the memory access requests sent by the GPU in a timely manner, the GPU can be connected to multiple routing modules. Based on this, when the GPU issues a memory access request, the request can be sent to the routing module with the least workload connected to the GPU, according to the workload status of the routing modules connected to the GPU, so that the memory access request is forwarded in a timely manner.

[0118] Alternatively, the routing module can be connected to one or more graphics processors based on its performance. For example, if the routing module has high performance, it can be connected to multiple graphics processors, allowing it to fully utilize its performance advantages and help more graphics processors send memory access requests. If the routing module has low performance, it can be connected to a single graphics processor, thus avoiding memory access blocking caused by receiving too many memory access requests.

[0119] In other embodiments, the connection relationship between multiple routing modules and multiple graphics processors can also be dynamically adjusted according to the real-time changes in the memory access frequency of each graphics processor and / or the bandwidth of each routing module.

[0120] Another embodiment of this application also provides a graphics processor that can be applied to the microprocessor architecture described in any of the above embodiments. Referring to the description of the above embodiments, the microprocessor architecture also includes memory, which includes a consistent access memory space and a non-consistent access memory space.

[0121] The graphics processor can access the aforementioned consistent access memory space through a consistent interconnect network, or access the aforementioned non-consistent access memory space through a direct path.

[0122] For details on the specific processing and implementation of the graphics processor accessing the consistent memory space or the non-consistent memory space described above, please refer to the description in the above embodiments.

[0123] The aforementioned graphics processors can be one or more, and a graphics processor can include one or more processor cores.

[0124] Furthermore, the aforementioned graphics processor can be a standalone graphics processing unit (GPU), a standalone video processing unit (VPU), or a display controller (DC). In some embodiments, the video processor and display controller can also be integrated within the graphics processor, thereby enabling graphics processing, video processing, and display control to be performed by a single graphics processor; that is, a single graphics processor is responsible for all image processing tasks within the microprocessor architecture.

[0125] In embodiments of this specification, a graphics processor is used to refer to a unit in a microprocessor architecture that performs graphics processing tasks. That is, a graphics processor can refer to a standalone graphics processing unit (GPU), or it can be used to refer to a video processor or a display controller, or it can be used to refer to a combination of a graphics processor, a video processor, and a display controller.

[0126] The graphics processor provided in this embodiment belongs to the same concept as the microprocessor architecture provided in the above embodiments of this application, and both can achieve the same beneficial effects. Technical details not described in detail in this embodiment can be found in the specific processing content of the microprocessor architecture provided in the above embodiments of this application, and will not be repeated here.

[0127] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0128] The steps in the methods of the various embodiments of this application can be adjusted, merged, or deleted in order according to actual needs, and the technical features described in each embodiment can be replaced or combined.

[0129] The modules and sub-modules in the various embodiments of the present application's devices and terminals can be merged, divided, and deleted according to actual needs.

[0130] It should be understood that the disclosed terminals, devices, and methods can be implemented in other ways, given the several embodiments provided in this application. For example, the terminal embodiments described above are merely illustrative. For instance, the division of modules or sub-modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0131] The modules or submodules described as separate components may or may not be physically separate. The components that constitute a module or submodule may or may not be physical modules or submodules; that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules can be selected to achieve the purpose of this embodiment's solution, depending on actual needs.

[0132] Furthermore, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated modules or sub-modules described above can be implemented in hardware or in the form of software functional modules or sub-modules.

[0133] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0134] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0135] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0136] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A microprocessor architecture, characterized in that, Includes a graphics processor and memory, wherein the memory includes a consistent access memory space and a non-consistent access memory space; The graphics processor accesses the consistent access memory space through a consistent interconnect network, or the graphics processor accesses the non-consistent access memory space through a direct path.

2. The microprocessor architecture according to claim 1, characterized in that, The consistent access memory space is used to store the first type of data, and the inconsistent access memory space is used to store the second type of data. The first type of data can be cached in the storage space of the consistent interconnection network, while the second type of data is only stored in the memory.

3. The microprocessor architecture according to claim 1, characterized in that, It also includes a routing module; The routing module is configured to receive memory access requests sent by the graphics processor and send the memory access requests to the consistent access memory space through the consistent interconnect network, or send the access requests to the non-consistent access memory space through the direct path.

4. The microprocessor architecture according to claim 3, characterized in that, The routing module stores the address information of the consistent access memory space and the address information of the non-consistent access memory space; The routing module sends the memory access request to the consistent access memory space through the consistent interconnect network, or sends the memory access request to the inconsistent access memory space through the direct path, including: The routing module compares the destination address of the memory access request with the address of the consistent memory space and the address of the inconsistent memory space to determine the memory space corresponding to the memory access request. If the memory space corresponding to the memory access request is determined to be the consistent access memory space, the routing module sends the memory access request to the consistent access memory space through the consistent interconnection network. or, If the memory space corresponding to the memory access request is determined to be the inconsistent access memory space, the routing module sends the memory access request to the inconsistent access memory space through the direct path.

5. The microprocessor architecture according to claim 4, characterized in that, The routing module stores routing method information, which includes hash granularity information; the memory includes multiple memory blocks. If it is determined that the memory space corresponding to the memory access request is the inconsistent access memory space, the routing module sends the memory access request to the inconsistent access memory space through the direct path, including: The routing module performs a hash operation on the destination address of the memory access request according to the hash granularity, and determines the destination memory block corresponding to the destination address based on the hash operation result; The routing module sends the memory access request to the memory controller corresponding to the target memory block through the direct path.

6. The microprocessor architecture according to claim 5, characterized in that, The routing module performs a hash operation on the destination address of the memory access request according to the hash granularity, and determines the destination memory block corresponding to the destination address based on the hash operation result, including: The routing module determines the memory range requested by the memory access request based on the destination address of the memory access request; When the memory range is not larger than the hash granularity, the routing module performs a hash operation on the starting address of the destination address of the memory access request according to the hash granularity, and determines the target memory block corresponding to the destination address based on the hash operation result; or, If the memory range is greater than the hash granularity, the routing module splits the memory access request into multiple sub-requests according to the hash granularity, wherein the memory range requested by each sub-request is not greater than the hash granularity; The routing module performs a hash operation on the starting address of each sub-request according to the hash granularity, and determines the target memory block corresponding to each sub-request based on the hash operation result.

7. The microprocessor architecture according to claim 3, characterized in that, The graphics processor includes multiple graphics processors, each of which is connected to the routing module. The routing module is configured with permission information for each graphics processor, including request priority information and / or resource usage permission information. When the memory access request includes memory access requests sent by multiple graphics processors, the routing module determines the memory access request to be prioritized from the multiple memory access requests based on the permission information of each graphics processor, and sends the prioritized memory access request to the consistent access memory space through the consistent interconnect network, or sends the prioritized memory access request to the non-consistent access memory space through the direct path.

8. The microprocessor architecture according to any one of claims 1 to 7, characterized in that, The microprocessor architecture also includes a central processing unit, which is connected to the memory via the coherent interconnect network; The central processing unit is used to configure the consistent access memory space and the non-consistent access memory space for the graphics processor.

9. The microprocessor architecture according to claim 8, characterized in that, In the case where the microprocessor architecture includes the routing module, the central processing unit is further configured to configure request routing information in the routing module; the request routing information includes memory access space configuration information and routing method information; in the case where the graphics processor includes multiple graphics processors, the request routing information also includes permission information for each graphics processor; The memory access space configuration information includes the address information of the consistent memory access space and the address information of the inconsistent memory access space; the routing method information includes hash granularity information, and the routing method information is consistent with the routing method of the consistent interconnect network for memory access requests; the permission information includes request priority information and / or resource usage permission information.

10. A graphics processor, characterized in that, Applied to a microprocessor architecture, the microprocessor architecture also includes memory, the memory including a consistent access memory space and a non-consistent access memory space; The graphics processor accesses the consistent access memory space through a consistent interconnect network, or the graphics processor accesses the non-consistent access memory space through a direct path.

Images