Occlusion count statistics system, method, graphics processor, electronic device

Abstract

The present disclosure relates to the technical field of graphic processors, and proposes a system and method for counting occlusion, a graphic processor and an electronic device. The system comprises a first cache shared by a plurality of cores, the first cache being arranged outside the cores and comprising a first buffer area, and any one of the cores is configured to perform depth detection on an inputted primitive to obtain an occlusion count of the primitive, generate a first write request and transmit the first write request to the first cache; the first cache is configured to perform operation on the occlusion count stored at an address included in the first write request and the occlusion count included in the first write request, and write the operation result into the address included in the first write request. After obtaining the occlusion count, any one of the cores can update the occlusion count stored in the first cache through the first write request, and the counting of the occlusion count does not have to wait until the rendering of all the cores is completed, thereby reducing the time delay between obtaining the final occlusion count and the end of the rendering, and improving the performance of the GPU.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of graphics processors, and particularly relates to a system and method for counting occlusion, a graphics processor and an electronic device. BACKGROUND

[0002] In the technical field of graphics processors, when a three-dimensional scene is rendered into a two-dimensional picture, some primitives may be occluded by other primitives. Whether a primitive is occluded is related to the depth of a pixel or a sample point in the primitive. When a pixel or a sample point is covered by two primitives, if the depth value of the pixel or the sample point in the first primitive is lower and the depth value of the pixel or the sample point in the second primitive is higher, the second primitive is occluded by the first primitive for the pixel. The occluded part is actually not needed to be rendered. Therefore, in a GPU rendering pipeline, when a depth test is performed, an occlusion count is usually counted, which can be used to determine whether a primitive is completely occluded so as to discard or retain the primitive in a subsequent rendering process.

[0003] In the prior art, the way of counting occlusion by a multi-core GPU is to obtain the occlusion counts stored by all cores and sum them up to obtain the final occlusion count using firmware after rendering of all cores is completed. Since the calculation and data transfer operations are time-consuming, there is a large delay between the time of obtaining the final occlusion count and the time of completing rendering, which reduces the performance of the GPU. How to reduce the delay between the time of obtaining the final occlusion count and the time of completing rendering and improve the performance of the GPU has become a technical problem to be solved in the field. SUMMARY

[0004] Therefore, the present disclosure provides a system and method for counting occlusion, a graphics processor and an electronic device. The system sets a first cache shared by multiple cores outside the cores. After obtaining the occlusion count, any core can update the occlusion count stored on the first cache through a first write request, without waiting for rendering of all cores to be completed before counting the occlusion count, thereby reducing the delay between the time of obtaining the final occlusion count and the time of completing rendering and improving the performance of the GPU.

[0005] According to an aspect of the present disclosure, there is provided a system for counting occlusion statistics, the system being arranged in a graphics processor, the system comprising a plurality of cores and a first cache shared by the plurality of cores, the first cache being arranged outside the cores and comprising a first buffer for counting occlusion statistics, any one of the cores being configured to, perform a depth test on an input primitive to obtain an occlusion statistic of the primitive, generate a first write request comprising the occlusion statistic and an address of the first buffer, and transmit the first write request to the first cache; and the first cache being configured to, in response to the first write request from any one of the cores, perform an operation on an occlusion statistic stored at the address included in the first write request and the occlusion statistic included in the first write request, and write the occlusion statistic obtained by the operation to the address included in the first write request to overwrite the occlusion statistic originally stored at the address.

[0006] In a possible implementation, the core comprises at least one processing unit and a second cache, any one of the processing units being configured to, perform a depth test on an input primitive to obtain an occlusion statistic of the primitive, generate a first write request comprising the occlusion statistic and an address of the first buffer, and transmit the first write request to the second cache in the core; and the second cache being configured to, forward the first write request from any one of the processing units to the first cache.

[0007] In a possible implementation, the first buffer comprises N first locations, the address of the first buffer comprises addresses of the N first locations, an i-th first location corresponds to an i-th occlusion statistic counting round, N is a positive integer, 0 < i ≤ N and i is an integer, and any one of the processing units is specifically configured to, in the i-th occlusion statistic counting round, perform a depth test on an input primitive to obtain an occlusion statistic of the primitive, and generate a first write request comprising the occlusion statistic and an address of the i-th first location.

[0008] In a possible implementation, the core includes at least one processing unit and a second cache, the second cache includes a second buffer for counting the occlusion count, and any one of the processing units is configured to perform depth detection on an input primitive to obtain an occlusion count of the primitive, generate a second write request including the occlusion count and an address of the second buffer in the core, and transmit the second write request to the second cache in the core; the second cache is configured to, in response to the second write request from any one of the processing units, perform an operation on the occlusion count stored at the address included in the second write request and the occlusion count included in the second write request, write the operation result to the address included in the second write request and overwrite the occlusion count originally stored at the address, and in response to the end of rendering of the core, generate a first write request including the occlusion count stored at the address of the second buffer and the address of the first buffer, and transmit the first write request to the first cache.

[0009] In a possible implementation, the first buffer includes N first positions, the address of the first buffer includes addresses of the N first positions, the second buffer includes N second positions, the address of the second buffer includes addresses of the N second positions, the i th second position of each core corresponds to the i th first position and the i th occlusion count counting round, N is a positive integer, 0 < i ≤ N and is an integer, and any one of the processing units is specifically configured to, in the i th occlusion count counting round, perform depth detection on an input primitive to obtain an occlusion count of the primitive, and generate a second write request including the occlusion count and an address of the i th second position in the core; and the second cache is specifically configured to, in response to the end of rendering of the core, generate a first write request including the occlusion count stored at the address of the i th second position and the address of the i th first position.

[0010] In a possible implementation, any one of the processing units is specifically configured to perform rasterization on an input primitive to determine a pixel or a sampling point covered by the primitive, calculate a depth value of the pixel or the sampling point, and increase the occlusion count of the primitive by one each time the depth value of a pixel or a sampling point is greater than a preset threshold.

[0011] In a possible implementation, the first cache is specifically configured to, in response to the first write request from any one of the cores, perform an operation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request in an atomic operation manner, and write the operation result to the address included in the first write request and overwrite the occlusion count originally stored at the address by using an atomic write operation.

[0012] In a possible implementation, the first write request further includes an operation type, and the operation type includes any one of addition, subtraction, multiplication, division, maximum value calculation, and minimum value calculation.

[0013] In a possible implementation, the system further includes a memory, the first buffer corresponds to a preset storage region on the memory, and the first cache is further configured to write the occlusion count stored in the first buffer to the preset storage region after confirming that the occlusion count is counted.

[0014] According to another aspect of the present disclosure, an occlusion count counting method is provided, which is applied to an occlusion count counting system, the system is arranged in a graphics processor, and includes a plurality of cores and a first cache shared by the plurality of cores, the first cache is arranged outside the cores and includes a first buffer for counting occlusion count, and the method includes: any one core performs depth detection on an input self primitive to obtain occlusion count of the primitive, generates a first write request including the occlusion count and an address of the first buffer, and transmits the first write request to the first cache; and the first cache performs operation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request in response to the first write request from any one core, writes the operation obtained occlusion count to the address included in the first write request and covers the occlusion count originally stored at the address.

[0015] In a possible implementation, the core includes at least one processing unit and a second cache, and the any one core performing depth detection on an input self primitive to obtain occlusion count of the primitive, generating a first write request including the occlusion count and an address of the first buffer, and transmitting the first write request to the first cache includes: any one processing unit performing depth detection on an input self primitive to obtain occlusion count of the primitive, generating a first write request including the occlusion count and an address of the first buffer, and transmitting the first write request to a second cache in the core; and the second cache forwards the first write request from any one processing unit to the first cache.

[0016] In a possible implementation, the first buffer includes N first positions, the address of the first buffer includes addresses of the N first positions, an i-th first position corresponds to an i-th occlusion count statistic round, N is a positive integer, 0 < i ≤ N and is an integer, the depth detection of the inputted primitive by any one of the processing units obtains an occlusion count of the primitive, and the first write request including the occlusion count and the address of the first buffer is generated, including: in the i-th occlusion count statistic round, the depth detection of the inputted primitive by any one of the processing units obtains an occlusion count of the primitive, and the first write request including the occlusion count and the address of the i-th first position is generated.

[0017] In a possible implementation, the core includes at least one processing unit and a second cache, the second cache includes a second buffer for counting occlusion counts, the depth detection of the inputted primitive by any one of the cores obtains an occlusion count of the primitive, the first write request including the occlusion count and the address of the first buffer is generated, and the first write request is transmitted to the first cache, including: the depth detection of the inputted primitive by any one of the processing units obtains an occlusion count of the primitive, the second write request including the occlusion count and the address of the second buffer in the core is generated, and the second write request is transmitted to the second cache in the core; the second cache, in response to the second write request from any one of the processing units, performs an operation on the occlusion count stored at the address included in the second write request and the occlusion count included in the second write request, writes the operation result into the address included in the second write request and covers the occlusion count originally stored at the address; in response to the end of rendering of the core, the first write request including the occlusion count stored at the address of the second buffer and the address of the first buffer is generated, and the first write request is transmitted to the first cache.

[0018] In a possible implementation, the first buffer includes N first positions, the address of the first buffer includes addresses of the N first positions, the second buffer includes N second positions, the address of the second buffer includes addresses of the N second positions, the i th second position of each core corresponds to the i th first position and the i th occlusion count statistical round, N is a positive integer, 0 < i ≤ N and is an integer, the occlusion count of the primitive input to the arbitrary processing unit is obtained through depth detection, and a second write request including the occlusion count and the address of the second buffer in the core is generated, which includes that the arbitrary processing unit obtains the occlusion count of the primitive input to the arbitrary processing unit through depth detection in the i th occlusion count statistical round, and generates a second write request including the occlusion count and the address of the i th second position in the core; the first write request including the occlusion count stored at the address of the second buffer and the address of the first buffer is generated in response to the end of rendering of the core, which includes that the first write request including the occlusion count stored at the address of the i th second position and the address of the i th first position is generated in response to the end of rendering of the core.

[0019] In a possible implementation, the occlusion count of the primitive input to the arbitrary processing unit is obtained through depth detection, which includes that the arbitrary processing unit rasterizes the primitive input to the arbitrary processing unit, and determines pixels or sampling points covered by the primitive; depth values of the pixels or the sampling points are calculated, and the occlusion count of the primitive is incremented by one each time a depth value of a pixel or a sampling point is greater than a preset threshold.

[0020] In a possible implementation, the first cache performs operation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request in response to the first write request from the arbitrary core, which includes that the first cache performs operation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request in an atomic operation manner in response to the first write request from the arbitrary core; and the operation result is written into the address included in the first write request and covers the occlusion count originally stored at the address through an atomic write operation.

[0021] In a possible implementation, the first write request further includes an operation type, and the operation type includes any one of addition, subtraction, multiplication, division, maximum value calculation, and minimum value calculation.

[0022] In a possible implementation, the system further comprises a memory, the first buffer corresponds to a preset storage area on the memory, and the method further comprises: after confirming that the occlusion count is complete, the first cache writes the occlusion count stored in the first buffer to the preset storage area.

[0023] According to another aspect of the present disclosure, a graphics processor is provided, comprising the above-mentioned occlusion count statistics system.

[0024] According to another aspect of the present disclosure, an electronic device is provided, comprising the above-mentioned graphics processor.

[0025] According to the occlusion count statistics system of the present disclosure, by arranging a first cache shared by a plurality of cores outside the plurality of cores, and the first cache comprising a first buffer for counting occlusion count, the occlusion count obtained by each core can be directly operated with the occlusion count stored in the first buffer; any one core is used to detect the depth of the input primitive to obtain the occlusion count of the primitive, generate a first write request comprising the occlusion count and the address of the first buffer, and transmit the first write request to the first cache, so that the first cache can determine the two source operands to be operated and the storage address of the destination operand according to the first write request; the first cache is used to respond to the first write request from any one core, to operate the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, write the occlusion count obtained by the operation to the address included in the first write request and overwrite the occlusion count originally stored at the address, so that the counting of the occlusion count of each core can be realized without firmware. According to the system, the occlusion count stored on the first cache can be updated through the first write request after the occlusion count is obtained by any one core, without waiting for the rendering of all cores to end before starting the occlusion count statistics, thereby reducing the delay between the time of obtaining the final occlusion count and the time of ending the rendering, and improving the performance of the GPU.

[0026] Other features and aspects of the present disclosure will become apparent from the following detailed description of example embodiments, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate example embodiments, features, and aspects of the present disclosure and serve to explain the principles of the present disclosure.

[0028] Figure 1 A schematic diagram showing the determination of the number of occluded pixels using an occlusion counter.

[0029] Figure 2 A schematic diagram showing an occlusion count statistics method of the prior art.

[0030] Figure 3a An exemplary application scenario of the occlusion count statistics system according to an embodiment of the present disclosure is shown.

[0031] Figure 3b An exemplary application scenario of the occlusion count statistics system according to an embodiment of the present disclosure is shown.

[0032] Figure 4 A schematic diagram showing the structure of the occlusion count statistics system according to an embodiment of the present disclosure is shown.

[0033] Figure 5 A schematic diagram showing the structure of the occlusion count statistics system according to an embodiment of the present disclosure is shown.

[0034] Figure 6 A schematic diagram showing the structure of the occlusion count statistics system according to an embodiment of the present disclosure is shown.

[0035] Figure 7 A schematic diagram showing the structure of the occlusion count statistics system according to an embodiment of the present disclosure is shown.

[0036] Figure 8 A schematic diagram showing the flow of the occlusion count statistics method according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0037] Various exemplary embodiments, features and aspects of the present disclosure will be explained in detail below with reference to the accompanying drawings. Like reference numerals in the drawings denote like or similar elements. Although various aspects of the embodiments are illustrated in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0038] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0039] In addition, for the purpose of convenience and brevity, detailed descriptions of well-known functions and structures incorporated herein can not be described in detail herein. It should be appreciated that the present disclosure can be practiced with the exact details as

[0040] Statistics of occlusion count needs to use an occlusion counter. The principle of the occlusion counter is introduced below. Figure 1 A schematic diagram showing the determination of the number of occluded pixels using the occlusion counter is shown.

[0041] As Figure 1As shown, the depth buffer can be used to store the depth values of the pixels (or sample points), and the depth values of the pixels (or sample points) stored in the depth buffer before the depth test starts can be the default initial values. The occlusion counter buffer can be used to store the occlusion count, i.e., the number of pixels (or sample points) that are occluded. The occlusion count stored in the occlusion counter buffer before the occlusion count statistics starts can be 0x0000.

[0042] The depth test can detect which pixels (or sample points) are covered by the primitive and the depth values of the pixels (or sample points) covered by the primitive. If the depth value of any pixel (or sample point) covered by the primitive is greater than the depth value of the pixel (or sample point) stored in the depth buffer, the pixel (or sample point) is considered to pass the depth test, and the depth value of the corresponding pixel (or sample point) in the depth buffer can be updated to the depth value of the pixel (or sample point) covered by the primitive. Meanwhile, the number of pixels (or sample points) that pass the depth test can be added to the occlusion count stored in the occlusion counter buffer. If the primitive does not cover any pixel (or sample point), or the depth value of each pixel (or sample point) covered by the primitive is less than the depth value of the pixel (or sample point) stored in the depth buffer, the primitive is considered to have no pixel (or sample point) passing the depth test, and the depth buffer and the occlusion counter buffer will not be updated.

[0043] Referring to Figure 1 , assume that the initial depth values of the pixels in the depth buffer before the depth test are equal to 0.1, and the depth values of the pixels covered by primitive A are all equal to 1.0, which are greater than the initial value 0.1. Therefore, primitive A has no pixel passing the depth test, and the depth buffer and the occlusion counter buffer are not updated after the depth test. The depth values of the pixels covered by primitive B are all equal to 0.0, which are less than the initial value 0.1. Therefore, the 24 pixels covered by primitive B all pass the depth test, and the depth values of the 24 pixels covered by primitive B in the depth buffer are updated to 0.0 after the depth test. The occlusion count stored in the occlusion counter buffer is updated to 0x0024.

[0044] Figure 2 A schematic diagram of the occlusion count statistics method of the related art is shown.

[0045] As Figure 2As shown, the prior art multi-core GPU implementation needs to apply a buffer on the cache in each core to store the occlusion count of the primitives rendered by the core. During the rendering process, multiple process units in each core update the occlusion count stored on the cache in the core. After the rendering of all cores is completed, firmware obtains the occlusion count stored by each core and sums them up to obtain the final occlusion count, which is then reported to the application interface (API).

[0046] The occlusion count statistics method of the related art has the following disadvantages. First, the calculation is completed by firmware, and the data transfer from the core to the firmware is more complex, so the time consumption of the calculation is relatively large. Moreover, the calculation of the firmware starts only after the rendering of all cores is completed, resulting in a large delay between the time of obtaining the final occlusion count and the time of completing the rendering, which reduces the performance of the GPU. Second, a buffer is applied on the cache in each core. When there are N statistics rounds of occlusion count, each buffer needs to include N occlusion count storage locations, which increases the hardware logic for managing the buffer and occupies more virtual address space. Third, the system also includes memory, and the cache in the core is set to speed up the access of the core to the memory. When the cache in the core applies the buffer, a mapping relationship between the buffer and the memory needs to be established, and each buffer needs to be mapped to an independent storage area on the memory. When there are N statistics rounds of occlusion count, each independent storage area needs to include N occlusion count storage locations, resulting in a high resource occupancy rate of the memory.

[0047] Therefore, the present disclosure proposes an occlusion count statistics system, method, graphics processor, and electronic device. The system sets a first cache shared by multiple cores outside the cores. After obtaining the occlusion count, any core can update the occlusion count stored on the first cache through a first write request, without waiting for the rendering of all cores to be completed before starting the occlusion count statistics, thereby reducing the delay between the time of obtaining the final occlusion count and the time of completing the rendering and improving the performance of the GPU.

[0048] Further, the occlusion count obtained by any process unit in the core of the system can be directly operated with the occlusion count stored on the first cache, without being stored on the cache in the core. Therefore, a buffer for storing the occlusion count does not need to be applied in the core, which simplifies the hardware logic for managing the buffer and reduces the use of virtual address space. The total space for storing the occlusion count on the first cache is much smaller than the total space of the buffers applied on the cache in each core in the related art. Therefore, less space needs to be reserved in the memory, and the occupancy of the memory resources is less.

[0049] Figure 3a and Figure 3b An example application scenario of the occlusion count statistics system according to an embodiment of the present disclosure is shown.

[0050] As shown in Figure 3a , the electronic device can include a CPU and a GPU, the GPU is provided with the occlusion count statistics system, and the CPU runs software with image rendering requirements.

[0051] As shown in Figure 3b , before starting the rendering of the primitives, the software first creates an occlusion count statistics task on the CPU, and drives the GPU to allocate a buffer (for example, the first buffer described below) for storing the occlusion count. Then, the software submits a rendering command (Render Cmd), which is transmitted to and executed by the GPU. During the rendering process, the depth detection is completed, and at the same time, the occlusion count statistics system is also responsible for executing the occlusion count statistics task, counting the occlusion count and storing it to the allocated buffer. Finally, after the completion of the occlusion count statistics task, the occlusion count statistics system reports the final occlusion count to the software through the API, and the software judges whether the rendered primitive is completely occluded or not in order to eliminate or retain the primitive in the subsequent rendering process.

[0052] Figure 4 A schematic diagram showing the structure of the occlusion count statistics system according to an embodiment of the present disclosure is shown.

[0053] As shown in Figure 4 , in a possible implementation, the present disclosure provides an occlusion count statistics system, which is arranged in a graphics processing unit (GPU), and the system includes a plurality of cores and a first cache shared by the plurality of cores, the first cache is arranged outside the cores and includes a first buffer for counting the occlusion count,

[0054] Any one of the cores is configured to perform depth detection on an input primitive to obtain the occlusion count of the primitive, generate a first write request including the occlusion count and an address of the first buffer, and transmit the first write request to the first cache;

[0055] The first cache is configured to, in response to the first write request from any one of the cores, perform an operation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, and write the operation result to the address included in the first write request to overwrite the original occlusion count stored at the address.

[0056] For example, the system can include a plurality of cores, each of which can render a primitive, so when the graphics processor renders a primitive, each core can perform depth testing on the primitive inputted thereto, and obtain an occlusion count of the primitive using an occlusion counter during the depth testing. The occlusion count can represent a number of occluded pixels or sample points, and the method of obtaining the occlusion count by performing depth testing on a primitive is described in detail below. Figure 1 As described above, the details are not repeated here.

[0057] Since the occlusion count is finally stored in the first buffer of the first cache, after obtaining the occlusion count, any one of the cores can further generate a first write request including the occlusion count and the address of the first buffer, and transmit the first write request to the first cache. The details of generating and transmitting the first write request are described below.

[0058] After the first cache receives the first write request from any one of the cores, the first cache can determine that the occlusion count included in the first write request is a source operand to be involved in an operation, the occlusion count stored at the address included in the first write request is another source operand to be involved in the operation, and the storage address of the destination operand is the address included in the first write request. The first cache can perform an operation on the two source operands, and write the occlusion count obtained by the operation, i.e., the destination operand, to the address included in the first write request and overwrite the occlusion count originally stored at the address. The details of the operation of the first cache and the writing of the occlusion count to the first buffer are described below.

[0059] In this case, as the cores continuously send the first write request to the first cache, the occlusion count stored in the first buffer is continuously updated, and until the first cache completes the response to the first write request from all the cores, the occlusion count stored in the first buffer is the final occlusion count.

[0060] According to the occlusion count statistics system, the first cache shared by the plurality of cores is arranged outside the plurality of cores, and the first cache includes a first buffer area used for counting the occlusion count, so that the occlusion count obtained by each core can be directly operated with the occlusion count stored in the first buffer area; any one core is used for performing depth detection on an input primitive to obtain the occlusion count of the primitive, generating a first write request including the occlusion count and the address of the first buffer area, and transmitting the first write request to the first cache, so that the first cache can determine two source operands to be operated and the storage address of the destination operand according to the first write request; the first cache is used for responding to the first write request from any one core, operating the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, writing the operation result to the address included in the first write request and covering the occlusion count originally stored at the address, so that the counting of the occlusion count of each core can be realized without firmware. According to the system, the occlusion count stored in the first cache can be updated through the first write request after the occlusion count is obtained by any one core, without waiting for the rendering of all cores to end before starting the counting of the occlusion count, so that the time delay between the time of obtaining the final occlusion count and the time of ending the rendering is reduced, and the performance of the GPU is improved.

[0061] In a possible implementation, the first cache is specifically used for,

[0062] In response to the first write request from any one core, the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request are operated in an atomic operation manner;

[0063] The operation result is written to the address included in the first write request and covers the occlusion count originally stored at the address through an atomic write operation.

[0064] For example, the first cache successively receives the first write requests from different cores. If the execution of the previous first write request is not completed before the execution of the next first write request is started, the data consistency is damaged, and the operation result is inaccurate. The global atomic operation has the characteristic of not being interrupted, and therefore the first cache can be set to respond to the first write request in the atomic operation manner by default. That is, the first cache can respond to the received first write request in the atomic operation manner, and complete the writing and covering of the operation result through the atomic write operation.

[0065] In this case, after the first cache starts responding to any one first write request, the first cache does not respond to other first write requests before the response of the first write request is completed (that is, the operation result is written to the address included in the first write request), so as to ensure the accuracy of the operation result.

[0066] For example, the first write request may also carry an atomic operation identifier. In this case, the first cache can determine that the response to the first write request should be performed atomically based on the identifier carried by the first write request. This disclosure does not limit whether the first write request must carry an atomic operation identifier.

[0067] In one possible implementation, the first write request further includes an operation type, which may include any one of addition, subtraction, multiplication, division, finding the maximum value, or finding the minimum value. When responding to the first write request, the operation is performed according to the operation type included in the first write request. Those skilled in the art will understand that the operation type may also include more types, such as logical AND, logical OR, etc. This disclosure does not limit the operation types that the cache can support.

[0068] The following is an example of how the core of this disclosure generates and transmits the first write request.

[0069] Figure 5 A schematic diagram showing the structure of an occlusion counting system according to an embodiment of the present disclosure is provided.

[0070] like Figure 5 As shown, in one possible implementation, the core includes at least one processing unit and a second cache.

[0071] Any processing unit is used to perform depth detection on the input primitives to obtain the occlusion count of the primitives, generate a first write request including the occlusion count and the address of the first buffer, and transmit the first write request to the second buffer in the core.

[0072] The second cache is used to forward the first write request from any processing unit to the first cache.

[0073] For example, a single core may include multiple processing units, each of which independently renders primitives; that is, it performs depth detection on the primitives it takes as input to obtain the occlusion count of those primitives. In this case, each processing unit may generate a first write request that includes its own obtained occlusion count and the address of a first buffer.

[0074] The core may also include a second cache for interaction between in-core and out-of-core objects. For example, a processing unit can transfer a first write request to a second cache within its core. The second cache then forwards the received first write request to the first cache.

[0075] In this case, the second cache only needs to implement forwarding of the first write request, does not need to store the occlusion count, does not need to apply a buffer for storing the occlusion count on the second cache, can simplify the hardware logic for managing the buffer, and also reduces the use of the virtual address space. The occlusion count obtained by each processing unit is calculated in real time with the occlusion count stored in the first cache, so that the final occlusion count is counted at the end of rendering, and the time delay between obtaining the final occlusion count and the end of rendering is greatly reduced, greatly improving the performance of the GPU.

[0076] The occlusion count counting system of the present disclosure also supports multiple rounds of occlusion count counting according to user needs. Figure 6 A schematic diagram showing the structure of an occlusion count counting system according to an embodiment of the present disclosure is shown.

[0077] As Figure 6 shown, in a possible implementation, the first buffer includes N first positions, the address of the first buffer includes the addresses of the N first positions, the i-th first position corresponds to the i-th occlusion count counting round, N is a positive integer, 0 < i ≤ N and is an integer,

[0078] Any one of the processing units is specifically configured to, in the i-th occlusion count counting round, perform depth detection on an inputted primitive to obtain an occlusion count of the primitive, and generate a first write request including the occlusion count and the address of the i-th first position.

[0079] For example, the user can pre-set the total number of occlusion count counting rounds, for example, N. Correspondingly, the first buffer can be divided into N first positions (slots), and the address of the first buffer can include the addresses of the N first positions. The i-th first position corresponds to the i-th occlusion count counting round, can be used in the i-th occlusion count counting round, and is used for storing the occlusion count obtained in the i-th occlusion count counting round.

[0080] For example, any one of the processing units is specifically configured to, in the i-th occlusion count counting round, perform depth detection on an inputted primitive to obtain an occlusion count of the primitive, and generate a first write request including the occlusion count and the address of the i-th first position. In the i-th occlusion count counting round, after the first cache receives the first write request, the occlusion count stored at the i-th first position and the occlusion count included in the first write request are calculated, and the calculation result is also written into the i-th first position.

[0081] That is, in the first occlusion count statistics round, all the first write requests include the address of the first first position s1, and other first positions are not used in the first occlusion count statistics round; in the second occlusion count statistics round, all the first write requests include the address of the second first position s2, and other first positions are not used in the second occlusion count statistics round; in the Nth occlusion count statistics round, all the first write requests include the address of the Nth first position sN, and other first positions are not used in the Nth occlusion count statistics round. After the N occlusion count statistics rounds end, the N first positions respectively store the occlusion counts obtained in the N occlusion count statistics rounds.

[0082] In this way, the occlusion count statistics system of the present disclosure can support multiple rounds of occlusion count statistics in one rendering process, improving the capability of the occlusion count statistics system.

[0083] In a possible implementation, any one of the processing units is specifically configured to,

[0084] perform rasterization on the input primitive itself to determine the pixels or sampling points covered by the primitive;

[0085] calculate the depth value of each pixel or sampling point, and when the depth value of a pixel or a sampling point is greater than a preset threshold, increase the occlusion count of the primitive by one.

[0086] The details of how the processing units calculate the occlusion count can be referred to the related description of Figure 1 and will not be repeated here. It should be understood that the way each processing unit calculates the occlusion count should be consistent, for example, both use the depth value of a pixel to compare with a preset threshold, or both use the depth value of a sampling point to compare with a preset threshold.

[0087] Figure 7 FIG. 1 shows a schematic diagram of the structure of an occlusion count statistics system according to an embodiment of the present disclosure.

[0088] As shown in Figure 7 In a possible implementation, the system further includes a memory, the first buffer corresponds to a preset storage area on the memory, and the first cache is further configured to, after confirming that the occlusion count statistics are complete, write the occlusion count stored in the first buffer to the preset storage area.

[0089] For example, the system may also include memory, with a first cache set up to speed up memory access. The first buffer corresponds to a preset storage area in memory; the first buffer can be mapped to the preset storage area. The first buffer and the preset storage area can have the same size, meaning the preset storage area also includes N occlusion count storage locations. When the user presets the total number of occlusion counts to N, the occlusion count is considered complete after the Nth round of occlusion count statistics. After confirming the completion of the occlusion count statistics, the first cache can write the occlusion counts stored in the first buffer to the preset storage area.

[0090] Those skilled in the art will understand that, in practical applications, the first cache can write the occlusion count to the preset storage area at more times, for example, once after each round of occlusion count statistics. This disclosure does not limit the frequency or timing of the first cache writing data to memory.

[0091] In this case, only N occlusion counting positions need to be reserved in memory to complete the occlusion counting, reducing the use of memory resources.

[0092] This disclosure also provides a method for counting and statistically analyzing occlusion. Figure 8 A schematic diagram illustrating the flow of an occlusion counting method according to an embodiment of the present disclosure is shown.

[0093] like Figure 8 As shown, in one possible implementation, the method is applied to an occlusion counting system, the system being configured in a graphics processor, the system including multiple cores and a first cache shared by the multiple cores, the first cache being located outside the cores and including a first buffer for counting occlusions, the method comprising:

[0094] Step S71: Any core performs depth detection on the primitives input to itself to obtain the occlusion count of the primitives, generates a first write request including the occlusion count and the address of the first buffer, and transmits the first write request to the first buffer.

[0095] In step S72, the first cache responds to a first write request from any core by performing a calculation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, and writes the calculated occlusion count to the address included in the first write request and overwrites the occlusion count originally stored at that address.

[0096] In a possible implementation, the core includes at least one processing unit and a second cache, the core performs depth detection on a primitive input to the core to obtain an occlusion count of the primitive, generates a first write request including the occlusion count and an address of the first buffer, and transmits the first write request to the first cache, and the method includes: any one of the processing units performs depth detection on a primitive input to the core to obtain an occlusion count of the primitive, generates a first write request including the occlusion count and an address of the first buffer, and transmits the first write request to the second cache in the core; and the second cache forwards the first write request from any one of the processing units to the first cache.

[0097] In a possible implementation, the first buffer includes N first locations, the address of the first buffer includes addresses of the N first locations, an i-th first location corresponds to an i-th occlusion count statistic round, N is a positive integer, 0 < i ≤ N and i is an integer, and the method of any one of the processing units performing depth detection on a primitive input to the core to obtain an occlusion count of the primitive, generating a first write request including the occlusion count and an address of the first buffer, includes: any one of the processing units performing depth detection on a primitive input to the core to obtain an occlusion count of the primitive in an i-th occlusion count statistic round, generating a first write request including the occlusion count and an address of an i-th first location.

[0098] In a possible implementation, the core includes at least one processing unit and a second cache, the second cache includes a second buffer for counting occlusion counts, the core performs depth detection on a primitive input to the core to obtain an occlusion count of the primitive, generates a first write request including the occlusion count and an address of the first buffer, and transmits the first write request to the first cache, and the method includes: any one of the processing units performs depth detection on a primitive input to the core to obtain an occlusion count of the primitive, generates a second write request including the occlusion count and an address of the second buffer in the core, and transmits the second write request to the second cache in the core; the second cache, in response to the second write request from any one of the processing units, performs an operation on an occlusion count stored at the address included in the second write request and the occlusion count included in the second write request, writes the operation result to the address included in the second write request and overwrites the occlusion count originally stored at the address; and in response to the end of rendering of the core, generates a first write request including the occlusion count stored at the address of the second buffer and the address of the first buffer, and transmits the first write request to the first cache.

[0099] In a possible implementation, the first buffer includes N first positions, the address of the first buffer includes addresses of the N first positions, the second buffer includes N second positions, the address of the second buffer includes addresses of the N second positions, the i-th second position of each core corresponds to the i-th first position and the i-th occlusion count statistic round, N is a positive integer, 0 < i ≤ N and is an integer, the occlusion count of the primitive input to the arbitrary processing unit is obtained through depth detection by the arbitrary processing unit, and the second write request including the occlusion count and the address of the second buffer in the core is generated, which comprises: in the i-th occlusion count statistic round, the occlusion count of the primitive input to the arbitrary processing unit is obtained through depth detection by the arbitrary processing unit, and the second write request including the occlusion count and the address of the i-th second position in the core is generated; the first write request including the occlusion count stored at the address of the second buffer and the address of the first buffer is generated in response to the end of rendering of the core, which comprises: in response to the end of rendering of the core, the first write request including the occlusion count stored at the address of the i-th second position and the address of the i-th first position is generated.

[0100] In a possible implementation, the occlusion count of the primitive input to the arbitrary processing unit is obtained through depth detection by the arbitrary processing unit, which comprises: the primitive input to the arbitrary processing unit is rasterized by the arbitrary processing unit, and the pixels or sampling points covered by the primitive are determined; the depth values of the pixels or the sampling points are calculated, and the occlusion count of the primitive is incremented by one each time the depth value of a pixel or a sampling point is greater than a preset threshold.

[0101] In a possible implementation, the first cache performs operation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request in response to the first write request from the arbitrary core, which comprises: the first cache performs operation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request in an atomic operation manner in response to the first write request from the arbitrary core; and the operation result is written into the address included in the first write request and covers the occlusion count originally stored at the address through an atomic write operation.

[0102] In a possible implementation, the first write request further includes an operation type, and the operation type includes any one of addition operation, subtraction operation, multiplication operation, division operation, maximum value operation and minimum value operation.

[0103] In a possible implementation, the system further comprises a memory, the first buffer corresponds to a preset storage area on the memory, and the method further comprises: after confirming that the occlusion count is complete, the first buffer writes the occlusion count stored in the first buffer into the preset storage area.

[0104] The embodiments of the present disclosure further provide a graphics processor comprising the occlusion count statistics system described above.

[0105] The embodiments of the present disclosure further provide an electronic device comprising the graphics processor described above.

[0106] The exemplary structures of the graphics processor and the electronic device can be found in Figure 3a .

[0107] The flowcharts and block diagrams in the accompanying drawings show the possible implementation architecture, function and operation of the systems, methods and computer program products according to the embodiments of the present disclosure. In this regard, each block in the flowcharts or block diagrams can represent a module, a program segment or a part of an instruction, which contains one or more executable instructions for implementing the specified logic function. In some alternative implementations, the functions noted in the blocks can also occur in different order from that noted in the accompanying drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and the combination of blocks in the block diagrams and / or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0108] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles, practical application or technical improvement in the art of the embodiments, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. A system for occlusion count statistics, the system comprising: The system is arranged in a graphics processor, and comprises a plurality of cores and a first cache shared by the plurality of cores, the first cache being arranged outside the cores and comprising a first buffer for counting occlusion counts, Any one core is configured to perform depth detection on an input primitive thereof to obtain an occlusion count of the primitive, generate a first write request comprising the occlusion count and an address of the first buffer, and transmit the first write request to the first cache. The first cache is configured to, in response to the first write request from any one core, perform an operation on an occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, and write the operation result to the address included in the first write request to overwrite the occlusion count originally stored at the address.

2. The system of claim 1, wherein, The core comprises at least one processing unit and a second cache, Any one processing unit is configured to perform depth detection on an input primitive thereof to obtain an occlusion count of the primitive, generate a first write request comprising the occlusion count and an address of the first buffer, and transmit the first write request to the second cache in the core. The second cache is configured to forward the first write request from any one processing unit to the first cache.

3. The system of claim 2, wherein, The first buffer comprises N first locations, the address of the first buffer comprises addresses of the N first locations, an i-th first location corresponds to an i-th occlusion count counting round, N is a positive integer, 0 < i ≤ N and is an integer, Any one processing unit is specifically configured to, in an i-th occlusion count counting round, perform depth detection on an input primitive thereof to obtain an occlusion count of the primitive, and generate a first write request comprising the occlusion count and an address of an i-th first location.

4. The system of claim 2 or 3, wherein, Any one processing unit is specifically configured to, perform rasterization on an input primitive thereof to determine pixels or sampling points covered by the primitive; calculate depth values of the pixels or the sampling points, and increase the occlusion count of the primitive by one each time a depth value of a pixel or a sampling point is greater than a preset threshold.

5. The system of claim 1, wherein, The first cache is specifically configured to, in response to the first write request from any one core, perform an operation on an occlusion count stored at the address included in the first write request and the occlusion count included in the first write request in an atomic operation manner; write the operation result to the address included in the first write request to overwrite the occlusion count originally stored at the address by an atomic write operation.

6. The system of claim 1, wherein, The first write request further comprises an operation type, and the operation type comprises any one of addition, subtraction, multiplication, division, maximum value calculation, and minimum value calculation.

7. The system of claim 3, wherein, The system further comprises a memory, and the first buffer corresponds to a preset storage region on the memory, The first cache is further configured to, after confirming that the counting of the occlusion counts is completed, write the occlusion counts stored in the first buffer to the preset storage region.

8. A method of occlusion count statistics, characterized by, The method is applied to an occlusion count statistics system, the system is arranged in a graphics processor, the system comprises a plurality of cores and a first cache shared by the plurality of cores, the first cache is arranged outside the cores and comprises a first buffer area for counting occlusion counts, and the method comprises: Any one core performs depth detection on an input primitive of itself to obtain an occlusion count of the primitive, generates a first write request comprising the occlusion count and an address of the first buffer area, and transmits the first write request to the first cache; The first cache, in response to the first write request from any one core, performs operation on the occlusion count stored at the address included in the first write request and the occlusion count included in the first write request, writes the operation-derived occlusion count to the address included in the first write request and covers the occlusion count originally stored at the address.

9. A graphics processor, comprising: An occlusion count statistics system comprising any one of claims 1-7.

10. An electronic device, comprising: A graphics processor comprising claim 9.

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