Integrated circuit device with swing detector and system including the same

Abstract

The invention relates to an integrated circuit device with a swing detector and a system including the integrated circuit device. A system includes: a first integrated circuit device; and a second integrated circuit device coupled to the first integrated circuit device through a first transmission line and a second transmission line, in which the first integrated circuit device includes: a swing detector configured to detect a voltage level difference between the first transmission line and the second transmission line; a comparator configured to compare a detection value of the swing detector with a reference swing value; and a comparison result transmission circuit configured to transmit a comparison result of the comparator to the second integrated circuit device.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0059708, filed on May 7, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to integrated circuit devices, and more specifically, to the transmission and reception of high-speed signals between integrated circuit devices. Background Technology

[0004] In response to the need for low power consumption and high-speed operation of the memory, commands and addresses are received synchronously with a low-speed master clock, while data is received synchronously with a high-speed data clock. Using a low-speed master clock reduces the current required to receive commands and addresses, while using a high-speed data clock enables high-speed data reception.

[0005] Typically, the data clock is activated and switched only during periods when it is needed, and deactivated during other periods to reduce current consumption. During the transition from deactivated to activated states, the data clock can be difficult to receive correctly due to factors such as inter-symbol interference (ISI). This interference often occurs in high-speed communication systems where symbols are transmitted so closely together in time that the end of one symbol overlaps with the beginning of the next. Summary of the Invention

[0006] According to one embodiment of this disclosure, a system may include: a first integrated circuit device; and a second integrated circuit device coupled to the first integrated circuit device via a first transmission line and a second transmission line, wherein the first integrated circuit device includes: a swing detector configured to detect a voltage level difference between the first transmission line and the second transmission line; a comparator configured to compare the detected value of the swing detector with a reference swing value; and a comparison result transmission circuit configured to transmit the comparison result of the comparator to the second integrated circuit device.

[0007] According to one embodiment of this disclosure, an integrated circuit device may include: a swing detector configured to detect a voltage level difference between a first transmission line and a second transmission line; a comparator configured to compare the detected value of the swing detector with a reference swing value; and a comparison result transmission circuit configured to transmit the comparison result of the comparator.

[0008] According to one embodiment of this disclosure, an integrated circuit device may include: a differential transmission circuit configured to transmit differential signals through a first transmission line and a second transmission line; a receiving circuit configured to receive pre-level drive strength information from a device receiving differential signals; and a pre-level drive circuit configured to perform a pre-level drive to reduce the voltage difference between the first transmission line and the second transmission line, and to adjust the strength of the pre-level drive according to the pre-level drive strength information. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0010] Figure 2 It is used to describe Figure 1 The timing diagram shown illustrates the operation of the memory system.

[0011] Figure 3 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0012] Figure 4 It is shown Figure 3 A block diagram of an embodiment of the time control circuit shown.

[0013] Figure 5 It is used to describe Figure 3 The timing diagram shown illustrates the operation of the memory controller.

[0014] Figure 6 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0015] Figure 7 It is shown Figure 6 A diagram of an embodiment of the reference voltage generator shown.

[0016] Figure 8 It is shown Figure 6 A block diagram of an embodiment of the swing detector shown.

[0017] Figure 9 It is shown Figure 6 A block diagram of another embodiment of the swing detector shown.

[0018] Figure 10 It is shown Figure 6 A block diagram of an embodiment of the pre-level drive circuit shown.

[0019] Figure 11 It is shown Figure 6 A block diagram of another embodiment of the pre-level drive circuit shown. Detailed Implementation

[0020] Various embodiments of this disclosure relate to a technique capable of stably receiving high-speed differential signals.

[0021] According to embodiments of this disclosure, high-speed differential signals can be received stably.

[0022] Hereinafter, various embodiments based on the technical spirit of this disclosure will be described with reference to the accompanying drawings.

[0023] Figure 1 This is a block diagram illustrating the configuration of a memory system 100 according to an embodiment of the present disclosure. Figure 1 Only the configuration directly related to the transmission of data clocks WCK and WCKB in memory system 100 is shown.

[0024] refer to Figure 1 The memory system 100 may include a memory controller 110 and a memory 150. The memory controller 110 may control the read and write operations of the memory 150 upon request from the host, and the memory 150 may perform read and write operations under the control of the memory controller 110.

[0025] The data clocks WCK and WCKB are clocks provided to the memory 150 from the memory controller 110. Therefore, the memory controller 110 may include a differential transmission circuit 111 for transmitting the data clocks WCK and WCKB, and the memory 150 may include a differential receiving circuit 151 for receiving the data clocks WCK and WCKB.

[0026] The differential transmission circuit 111 of the memory controller 110 can transmit data clocks WCK and WCKB via the first transmission line 101 and the second transmission line 102. Since the data clocks WCK and WCKB are differential signals, they include the primary data clock signal WCK and the secondary data clock signal WCKB. The differential transmission circuit 111 can transmit the primary data clock signal WCK via the first transmission line 101 and the secondary data clock signal WCKB via the second transmission line 102.

[0027] Data clocks WCK and WCKB are used to transmit data, but data is not transmitted continuously in the memory system 100. Therefore, during periods when data is not transmitted, i.e., during periods when data clocks WCK and WCKB are not needed, the differential transmission circuit 111 can be deactivated (i.e., disabled). The transmission activation signal WCK_EN can be a signal that activates or deactivates the differential transmission circuit 111. When the transmission activation signal WCK_EN is activated, the differential transmission circuit 111 can be activated (i.e., enabled) and transmit data clocks WCK and WCKN through the first transmission line 101 and the second transmission line 102. When the transmission activation signal WCK_EN is deactivated, the differential transmission circuit 111 can be deactivated. Therefore, the differential transmission circuit 111 can fix the voltage level of the first transmission line 101 at a low level and the voltage level of the second transmission line 102 at a high level, thereby preventing current consumption.

[0028] The differential receiving circuit 151 of the memory 150 can receive the data clocks WCK and WCKB transmitted from the memory controller 110 via the first transmission line 101 and the second transmission line 102. The data clocks WCK and WCKB received by the differential receiving circuit 151 can be used by the memory 150 to receive data.

[0029] Figure 2 It is used to describe Figure 1 The timing diagram of the operation of the memory system 100 shown is shown.

[0030] See Figure 2 When the transmission activation signal WCK_EN is deactivated at a low level, the voltage level of the first transmission line 101 can be fixed at a low level, while the voltage level of the second transmission line 102 can be fixed at a high level.

[0031] When the transmission activation signal WCK_EN is activated at a high level at time point 201, the main data clock signal WCK can be transmitted through the first transmission line 101, while the secondary data clock signal WCKB, which has a phase opposite to that of the main data clock signal WCK, can be transmitted through the second transmission line 102.

[0032] Before time point 201, the voltage level of the first transmission line 101 is fixed at a low level, while the voltage level of the second transmission line 102 is fixed at a high level. When the first transmission line 101 and the second transmission line 102 begin high-speed switching from time point 201, the memory 150, acting as the receiving end, may have difficulty receiving the data clocks WCK and WCKB transmitted through the transmission lines 101 and 102 due to inter-symbol interference (ISI) caused by reflections and distortions of the signals transmitted through the transmission lines 101 and 102.

[0033] Figure 3This is a block diagram illustrating the configuration of a memory system 300 according to an embodiment of the present disclosure. Figure 3 Only the configurations directly related to the transmission of data clocks WCK and WCKB are shown.

[0034] refer to Figure 3 The memory system 300 may include a memory controller 310 and a memory 350.

[0035] The memory controller 310 may include a differential transmission circuit 111, a pre-level drive circuit 313, and a timing control circuit 315. The memory 350 may include a differential receiving circuit 151.

[0036] The pre-level drive circuit 313 can perform a pre-level drive on the first transmission line 301 and the second transmission line 302. The pre-level drive can reduce the voltage difference between the first transmission line 301 and the second transmission line 302 before the differential transmission circuit 111 is activated. The pre-level drive circuit 313 can be activated based on the pre-level drive activation signal PRE-LEVEL_EN, and during activation, perform a pre-level drive to increase the voltage level of the first transmission line 301 and decrease the voltage level of the second transmission line 302.

[0037] The timing control circuit 315 can adjust the pre-level drive time of the pre-level drive circuit 313. The pre-level drive circuit 313 is activated for a predetermined time before the differential transmission circuit 111 is activated. In this case, the timing control circuit 315 can use the pre-level drive activation signal PRE-LEVEL_EN and adjust the length of the predetermined time. The timing control circuit 315 can generate a transmission activation signal WCK_EN. The activation signal EN input to the timing control circuit 315 can be a source signal for generating the transmission activation signal WCK_EN, while the selection signal SEL<0:k> can be a signal for adjusting the length of the activation period of the pre-level drive activation signal PRE-LEVEL_EN. Furthermore, the clock CLK input to the timing control circuit 315 can be a clock used for transmitting and receiving commands and addresses between the memory controller 310 and the memory 350.

[0038] Figure 4 It is shown Figure 3 A block diagram of an embodiment of the time control circuit 315 shown.

[0039] refer to Figure 4 The timing control circuit 315 may include multiple shift circuits 411 to 414, a selection circuit 420, a delay circuit 430, and a signal generation circuit 440.

[0040] Multiple shift circuits 411 to 414 can shift the activation signal EN synchronously with the clock CLK and generate a transfer activation signal WCK_EN. Each of the multiple shift circuits 411 to 414 can be a D flip-flop.

[0041] Selection circuit 420 can respond to selection signal SEL<0:k-1> to select output signal of shift circuits 411 to 413. <0> to <k-1>one of the.

[0042] Delay circuit 430 can add an asynchronous delay value to the signal selected by selection circuit 420. <s>The delay circuit 430 may include a delay line 431 and a selector 433. The delay line 431 can select the signal... <s>The signal is delayed and output, and the selector 433 can select the signal SEL. <k>The level selection delay line 431 output signal and the selected signal <s>One of the signals is selected and output. The selector 433 selects either the output signal of the delay line 431 or the bypass signal. <s>The asynchronous delay value can be added to or not added to the selected signal. <s>Since the delay circuit 430 is used to fine-tune the asynchronous delay value, the delay value of the delay line 431 can be shorter than one cycle of the clock CLK.

[0043] The signal generation circuit 440 can activate the pre-level drive activation signal PRE-LEVEL_EN in response to the activation of the output signal SET of the delay circuit 430, and deactivate the pre-level drive activation signal PRE-LEVEL_EN in response to the activation of the transmission activation signal WCK_EN. Therefore, the pre-level drive activation signal PRE-LEVEL_EN can be activated earlier than the transmission activation signal WCK_EN, and deactivated during the activation period of the transmission activation signal WCK_EN. The length of the activation period of the pre-level drive activation signal PRE-LEVEL_EN can be obtained by subtracting the selected signal from the activation time of the transmission activation signal WCK_EN. <s>The value is obtained by adding the activation time to the delay value of the delay circuit 430.

[0044] When the activation period of the pre-level drive activation signal PRE-LEVEL_EN is not required, the delay circuit 430 for fine-tuning the activation period of the pre-level drive activation signal PRE-LEVEL_EN can be omitted from the timing control circuit 315. The signal selected by the selection circuit 420... <s>It can be directly input into the signal generation circuit 440.

[0045] Figure 5 It is used to describe Figure 3 The timing diagram of the operation of the memory controller 310 shown is shown.

[0046] For ease of description, in the following text, Figure 4 The number of shift circuits 411 to 414 is 5, and the selection circuit 420 selects the output signal of shift circuit 413. <3> Furthermore, the selector 433 of the delay circuit 430 selects the bypass signal. <s>.

[0047] refer to Figure 5 It can be seen that the output signal SET of the delay circuit 430 is activated at time point 503, four clock cycles (4*tCLK) after the activation time point 501 of the activation signal EN, and the pre-level drive activation signal PRE-LEVEL_EN is activated in response to the output signal SET. Furthermore, it can be seen that the transmission activation signal WCK_EN is activated at time point 505, five clock cycles (5*tCLK) after the activation time point 501 of the activation signal EN, and the pre-level drive activation signal PRE-LEVEL_EN is deactivated in response to the transmission activation signal WCK_EN. The pre-level drive activation signal PRE-LEVEL_EN can be activated during a clock period before the transmission activation signal WCK_EN is activated.

[0048] When the transmission activation signal WCK_EN is deactivated, the voltage level of the first transmission line 301 can be fixed at the level of the ground voltage VSS through the differential transmission circuit 111, while the voltage level of the second transmission line 302 can be fixed at the level of the power supply voltage VDD through the differential transmission circuit 111.

[0049] During the time period between time points 503 and 505 when the pre-level drive activation signal PRE-LEVEL_EN is activated, the first transmission line 301 and the second transmission line 302 can be pre-level driven by the pre-level drive circuit 313. The pre-level drive circuit 313 can increase the voltage level of the first transmission line 301 and decrease the voltage level of the second transmission line 302, thereby reducing the voltage difference between the first transmission line 301 and the second transmission line 302.

[0050] The transmission activation signal WCK_EN can be activated starting at time 505 after a pre-level drive, and the data clocks WCK and WCKB can be transmitted at high speed through the first transmission line 301 and the second transmission line 302. Since the data clocks WCK and WCKB are transmitted only after the voltage difference between the first transmission line 301 and the second transmission line 302 is reduced by the pre-level drive, inter-symbol interference (ISI) caused by signal reflection and distortion can be reduced, and the memory 350, as the receiving end, can receive the data clocks WCK and WCKB transmitted through transmission lines 301 and 302 more stably.

[0051] As described above, the length of the pre-level drive period can be adjusted by the timing control circuit 315. It is advantageous for the length of the pre-level drive period to increase with the frequency of the data clocks WCK and WCKB, and for the length of the pre-level drive period to decrease with the frequency of the data clocks WCK and WCKB.

[0052] Figure 6 This is a block diagram illustrating the configuration of a memory system 600 according to an embodiment of the present disclosure. Figure 3 The memory system 300 is different. Figure 6 The memory system 600 may also include a configuration for adjusting the training operation of the pre-level drive strength.

[0053] refer to Figure 6 The memory controller 610 may include a differential transmission circuit 111, a pre-level drive circuit 613, a timing control circuit 315, and a receiving circuit 617.

[0054] The training signal TRAIN is activated during the training operation, which involves adjusting the strength of the pre-level drive. When the training signal TRAIN is activated, the transmission activation signal WCK_EN', input to the differential transmission circuit 111 via inverter 619 and AND gate 621, can be deactivated, while the pre-level drive activation signal PRE-LEVEL_EN', input to the pre-level drive circuit 613 via OR gate 623, can be activated. During the training operation, the differential transmission circuit 111 can be deactivated, while the pre-level drive circuit 613 can be activated.

[0055] The receiving circuit 617 can receive a rising signal UP and a falling signal DN as pre-level drive strength information transferred from the memory 650. The pre-level drive circuit 613 can adjust the pre-level drive strength in response to the rising signal UP and the falling signal DN. The pre-level drive circuit 613 can adjust the pre-level drive strength to be higher when the rising signal UP is activated, and adjust the pre-level drive strength to be lower when the falling signal DN is activated.

[0056] The memory 650 may include a differential receiving circuit 151, a swing detector 653, a reference voltage generator 655, a reference swing detector 657, a comparator 659, and a comparison result transmission circuit 661.

[0057] The swing detector 653 can detect the voltage difference between the first transmission line 601 and the second transmission line 602 during training operations when the training signal TRAIN is activated. The swing detector 653 can also detect the voltage difference between the first transmission line 601 and the second transmission line 602 during pre-level drive. The detection result ACODE of the swing detector 653 can be generated in the form of a digital code.

[0058] The reference voltage generator 655 can generate a low reference voltage VL (which is the target voltage value of the first transmission line 601) and a high reference voltage VH (which is the target voltage value of the second transmission line 602) during the pre-level drive.

[0059] The reference swing detector 657 can detect the voltage difference between the low reference voltage VL and the high reference voltage VH during the training operation when the training signal TRAIN is activated, and generate a reference detection result BCODE in the form of a digital code.

[0060] Comparator 659 compares the detection result ACODE of the swing detector 653 with the reference detection result BCODE of the reference swing detector 657 during the training operation when the training signal TRAIN is activated, and generates a rising signal UP and a falling signal DN. When the detection result ACODE is greater than the reference detection result BCODE, i.e., when the voltage difference between the first transmission line 601 and the second transmission line 602 is greater than the voltage difference between the high reference voltage VH and the low reference voltage VL, the rising signal UP can be activated to reduce the voltage difference because the strength of the pre-level drive needs to be increased. Conversely, when the reference detection result BCODE is greater than the detection result ACODE, i.e., when the voltage difference between the first transmission line 601 and the second transmission line 602 is less than the voltage difference between the high reference voltage VH and the low reference voltage VL, the falling signal DN can be activated.

[0061] The comparison result transmission circuit 661 can transmit the rising signal UP and the falling signal DN generated by the comparator 659 to the memory 650.

[0062] During training operations, the differential transmission circuit 111 of the memory controller 610 is deactivated, and the pre-level drive circuit 613 is activated. Therefore, the first and second transmission lines 601 and 602 can be pre-level driven. The oscillation detector 653 of the memory 650 detects the voltage difference between the first transmission line 601 and the second transmission line 602, and the comparator 659 compares the value generated by the oscillation detector 653 (i.e., ACODE) with a reference value (i.e., BCODE). The memory 650 can transmit the rising signal UP and falling signal DN generated based on the comparison result to the memory controller 610, and the pre-level drive circuit 613 of the memory controller 610 can adjust the strength of the pre-level drive to be higher or lower in response to the rising signal UP and falling signal DN. Therefore, during the pre-level drive, the voltage difference between the first transmission line 601 and the second transmission line 602 can be adjusted to have the same value as the ideal voltage difference. When the voltage difference between the first transmission line 601 and the second transmission line 602 is adjusted to an ideal voltage difference during the pre-level drive, the differential receiver circuit 151 of the memory 650 can receive the data clocks WCK and WCKB more stably.

[0063] Figure 7 To show Figure 6 A diagram of an embodiment of the reference voltage generator 655 shown.

[0064] See Figure 7 The reference voltage generator 655 may include resistors 701, 702, 703, and 704, which are coupled to each other between the power supply voltage terminal VDD and the ground voltage terminal VSS. The reference voltage generator 655 can generate a high reference voltage VH and a low reference voltage VL according to the voltage distribution of resistors 701, 702, 703, and 704.

[0065] Figure 8 It is shown Figure 6 A block diagram of an embodiment of the swing detector 653 is shown. The reference swing detector 657 may have the same characteristics as... Figure 8 The swing detector 653 shown has the same configuration.

[0066] See Figure 8 The swing detector 653 may include a first analog-to-digital converter (ADC) 810, a second analog-to-digital converter 820, and a subtractor 830.

[0067] The first analog-to-digital converter 810 can convert the voltage level of the first transmission line 601 into a first digital code CODE1. Furthermore, the second analog-to-digital converter 820 can convert the voltage level of the second transmission line 602 into a second digital code CODE2.

[0068] Subtractor 830 can subtract the value of the first digital code CODE1 from the value of the second digital code CODE2 to generate a detection result ACODE. Therefore, the detection result ACODE can be a digital code corresponding to the difference between the voltage level of the first transmission line 601 and the voltage level of the second transmission line 602.

[0069] The first analog-to-digital converter 810, the second analog-to-digital converter 820, and the subtractor 830 can be activated and operated when the training signal TRAIN is activated, and deactivated when the training signal TRAIN is deactivated.

[0070] Figure 9 It is shown Figure 6 A block diagram of another embodiment of the swing detector 653 shown. The reference swing detector 657 may have the same... Figure 9 The swing detector 653 shown has the same configuration.

[0071] See Figure 9 The swing detector 653 may include a first oscillator 910, a second oscillator 920, a first counter 930, a second counter 940, and a subtractor 950.

[0072] The first oscillator 910 can generate a first periodic wave OSC1 corresponding to the voltage level of the first transmission line 601. The first oscillator 910 can be a voltage-controlled oscillator (VCO), and the frequency of the first periodic wave OSC1 increases as the voltage level of the first transmission line 601 increases.

[0073] The second oscillator 920 can generate a second periodic wave OSC2 corresponding to the voltage level of the second transmission line 602. The second oscillator 920 can be a voltage-controlled oscillator, and the frequency of the second periodic wave OSC2 increases as the voltage level of the second transmission line 602 increases.

[0074] The first counter 930 can count the number of activations of the first periodic wave OSC1 and generate a first count value CNT1. As the voltage level of the first transmission line 601 increases, the frequency of the first periodic wave OSC1 increases; therefore, the first count value CNT1 can increase as the voltage level of the first transmission line 601 increases.

[0075] The second counter 940 can count the number of activations of the second periodic wave OSC2 and generate a second count value CNT2. As the voltage level of the second transmission line 602 increases, the frequency of the second periodic wave OSC2 increases; therefore, the second count value CNT2 can increase as the voltage level of the second transmission line 602 increases.

[0076] Subtractor 950 can subtract the first count value CNT1 from the second count value CNT2 and generate a detection result ACODE. Therefore, the detection result ACODE can be a digital code corresponding to the difference between the voltage level of the first transmission line 601 and the voltage level of the second transmission line 602.

[0077] The first oscillator 910, the second oscillator 920, the first counter 930, the second counter 940, and the subtractor 950 can be activated and operated when the training signal TRAIN is activated, and deactivated when the training signal TRAIN is deactivated.

[0078] Figure 10 It is shown Figure 6 A block diagram of an embodiment of the pre-level drive circuit 613 shown.

[0079] See Figure 10 The pre-level drive circuit 613 may include a drive capability control code generator 1010, pull-up drivers 1020, 1030 and 1040, and pull-down drivers 1050, 1060 and 1070.

[0080] The drive capability control code generator 1010 can generate drive capability control codes INT<0:N> in response to a rising signal UP and a falling signal DN. The drive capability control code generator 1010 can increase the number of signals with high values ​​in the drive capability control code INT<0:N> each time the rising signal UP is activated, and decrease the number of signals with high values ​​in the drive capability control code INT<0:N> each time the falling signal DN is activated. For example, when two signals in the drive capability control code INT<0:N> have high values, once the rising signal UP is activated, all three signals in the drive capability control code INT<0:N> can have high values.

[0081] Pull-up drivers 1020, 1030, and 1040 can perform pull-up driving to increase the voltage level of the first transmission line 601 during the period when the pre-level drive activation signal PRE-LEVEL_EN' is activated. The number of activated drivers in pull-up drivers 1020, 1030, and 1040 can be determined based on the drive capability control code INT<0:N>. When the pre-level drive activation signal PRE-LEVEL_EN' is activated, the pull-up driver in pull-up drivers 1020, 1030, and 1040 whose code signal is high can be activated and perform pull-up driving on the first transmission line 601. For example, when the pre-level drive activation signal PRE-LEVEL_EN' is activated, the pull-up driver whose code signal is high in pull-up drivers 1020, 1030, and 1040 can perform pull-up driving on the first transmission line 601. <0> It is a high level, and the code signal INT <1> When the signal is low, pull-up driver 1020 can be activated and pull-up driven on the first transmission line 601, but pull-up driver 1030 can be deactivated.

[0082] Pull-up drivers 1020, 1030, and 1040 may include corresponding NAND gates 1021, 1031, and 1041 for the receive code signal INT<0:N> and the pre-level drive activation signal PRE-LEVEL_EN', as well as two corresponding PMOS transistors 1022, 1023, 1032, 1033, 1042, and 1043 connected in series to perform pull-up drive on the first transmission line 601. Since the ground voltage VSS is input to the gates of PMOS transistors 1023, 1033, and 1043, PMOS transistors 1023, 1033, and 1043 can always remain on, while PMOS transistors 1022, 1032, and 1042 can be turned on or off in response to the output signals of NAND gates 1021, 1031, and 1041. Since the pull-up drivers 1020, 1030 and 1040 are drivers that slightly increase the voltage level of the first transmission line 601 during pre-level drive, their drive capability can be designed to be relatively weak.

[0083] Pull-down drivers 1050, 1060, and 1070 can perform pull-down driving to reduce the voltage level of the second transmission line 602 during the period when the pre-level drive activation signal PRE-LEVEL_EN' is activated. The number of activated drivers in pull-down drivers 1050, 1060, and 1070 can be determined based on the drive capability control code INT<0:N>. When the pre-level drive activation signal PRE-LEVEL_EN' is activated, the pull-down driver in pull-down drivers 1050, 1060, and 1070 whose code signal is high can be activated and perform pull-down driving on the second transmission line 602. For example, when the pre-level drive activation signal PRE-LEVEL_EN' is activated, the pull-down driver whose code signal is high in pull-down drivers 1050, 1060, and 1070 can perform pull-down driving on the second transmission line 602. <0> It is a high level, and the code signal INT <1> When the signal is low, pull-down driver 1050 can be activated and pull-down driven to the second transmission line 60, but pull-down driver 1060 can be deactivated.

[0084] The pull-down drivers 1050, 1060, and 1070 may include: corresponding inverters 1051, 1061, and 1071 that invert the code signal INT<0:N>; corresponding inverters 1052, 1062, and 1072 that invert the pre-level drive activation signal PRE_LEVEL_EN'; corresponding NOR gates 1053, 1063, and 1073 that receive the output signals of the corresponding inverters 1051, 1061, 1071, 1052, 1062, and 1072; and corresponding NMOS transistors 1054, 1055, 1064, 1065, 1074, and 1075 connected in series to perform pull-down driving on the second transmission line 602. Since the power supply voltage VDD is input to the gates of NMOS transistors 1054, 1064, and 1074, NMOS transistors 1054, 1064, and 1074 can remain on at all times, while NMOS transistors 1055, 1065, and 1075 can be turned on or off in response to the output signals of NOR gates 1053, 1063, and 1073. Because pull-down drivers 1050, 1060, and 1070 are drivers that slightly reduce the voltage level of the second transmission line 602 during pre-level driving, their drive capability can be designed to be relatively weak.

[0085] The example uses the drive capability control code INT<0:N> in the form of a thermometer code, but the drive capability control code INT<0:N> can also be in binary code form. In this case, the drive capabilities of drivers 1020, 1030, 1040, 1050, 1060, and 1070 can be designed with binary weights.

[0086] exist Figure 10 In this circuit, transistors 1023, 1033, 1043, 1054, 1064, and 1074 remain on; therefore, transistors 1023, 1033, 1043, 1054, 1064, and 1074 can be omitted.

[0087] Figure 11 To show Figure 6 A block diagram of another embodiment of the pre-level drive circuit 613 shown.

[0088] See Figure 11 As can be seen, the configurations of pull-up drivers 1020, 1030, and 1040, and pull-down drivers 1050, 1060, and 1070 are similar to... Figure 10 The configurations shown are different.

[0089] It can be seen that in pull-up drivers 1020, 1030 and 1040, the pre-level drive activation signal PRE-LEVEL_EN', inverted by inverters 1101, 1103 and 1105, is input to transistors 1022, 1032 and 1042, and the drive capability control code INT<0:N>, inverted by inverters 1102, 1104 and 1106, is input to the corresponding transistors 1023, 1033 and 1043.

[0090] It can be seen that in pull-down drivers 1050, 1060 and 1070, the pre-level drive activation signal PRE-LEVEL_EN' is directly input to transistors 1054, 1064 and 1074, while the drive capability control code INT<0:N> is directly input to the corresponding transistors 1055, 1065 and 1075.

[0091] The detailed configurations of pull-up drivers 1020, 1030, and 1040, and pull-down drivers 1050, 1060, and 1070 have changed, while the pull-up drivers 1020, 1030, and 1040, and the pull-down drivers 1050, 1060, and 1070 can be configured according to... Figure 10 Operate in the same way as shown.

[0092] In the above embodiments, configurations for stably transmitting and receiving data clocks (which are high-speed differential signals) between the memory controller and the memory have been described. Clearly, these configurations can be used to stably transmit and receive any high-speed differential signals not only between the memory controller and the memory, but also between two different integrated circuit devices.

[0093] Although embodiments based on the technical spirit of this disclosure have been described above with reference to the accompanying drawings, this is merely for describing embodiments according to the concepts of this disclosure, and this disclosure is not limited to the above embodiments. Those skilled in the art to which this disclosure pertains can make various substitutions, modifications, and changes to the embodiments without departing from the technical spirit of this disclosure as defined in the following claims, and it should be understood that such substitutions, modifications, and changes are within the scope of this disclosure. Furthermore, embodiments can be combined to form additional embodiments.< / s> < / s> < / s> < / s> < / s> < / s> < / k> < / s> < / s>

Claims

1. A system comprising: First integrated circuit device; as well as A second integrated circuit device is coupled to the first integrated circuit device via a first transmission line and a second transmission line. The first integrated circuit device includes: A swing detector that detects the voltage level difference between the first transmission line and the second transmission line; A comparator that compares the detected value of the oscillation detector with a reference oscillation value; and A comparison result transmission circuit transmits the comparison result of the comparator to the second integrated circuit device.

2. The system according to claim 1, wherein, The second integrated circuit device includes: A differential transmission circuit transmits differential signals through the first transmission line and the second transmission line; and A pre-level drive circuit that: performs a pre-level drive to reduce the voltage difference between the first transmission line and the second transmission line, and adjusts the strength of the pre-level drive based on the comparison result transmitted from the first integrated circuit device.

3. The system according to claim 2, wherein, The wobbling detector, the comparator, and the comparison result transmission circuit of the first integrated circuit device operate during the training operation.

4. The system according to claim 2, wherein, The first integrated circuit device further includes: A reference voltage generator that produces a high reference voltage and a low reference voltage; and A reference swing detector detects the voltage difference between the high reference voltage and the low reference voltage and provides the detection result as the reference swing value.

5. The system according to claim 2, wherein, The second integrated circuit device further includes a timing control circuit that adjusts the pre-level drive time of the pre-level drive circuit.

6. The system according to claim 5, wherein, The pre-level drive circuit is activated for a predetermined time before the differential transmission circuit is activated, and the time control circuit adjusts the predetermined time.

7. The system according to claim 2, wherein, When the first integrated circuit device is a memory and the second integrated circuit device is a memory controller, the differential signal is a data clock.

8. The system according to claim 2 further includes a differential receiving circuit, the differential receiving circuit receiving the differential signal transmitted through the first transmission line and the second transmission line.

9. An integrated circuit device, comprising: A swing detector that detects the voltage level difference between the first transmission line and the second transmission line; A comparator that compares the detected value of the oscillation detector with a reference oscillation value; as well as A comparison result transmission circuit transmits the comparison result of the comparator.

10. The integrated circuit device according to claim 9, further comprising: A reference voltage generator that produces high and low reference voltages; and A reference swing detector detects the voltage difference between the high reference voltage and the low reference voltage and provides the detection result as the reference swing value.

11. The integrated circuit device according to claim 9, wherein, The swing detector includes: A first analog-to-digital converter converts the voltage level of the first transmission line into a first digital code; A second analog-to-digital converter converts the voltage level of the second transmission line into a second digital code; and The subtractor generates the detection value by using the difference between the first digital code and the second digital code.

12. The integrated circuit device according to claim 9, wherein, The swing detector includes: A first oscillator generates a first periodic wave, which corresponds to the voltage level of the first transmission line. The second oscillator generates a second periodic wave, which corresponds to the voltage level of the second transmission line. A first counter counts the number of times the first periodic wave is activated to generate a first count value; A second counter counts the number of activations of the second periodic wave to generate a second count value; and The subtractor generates the detection value by using the difference between the first count value and the second count value.

13. The integrated circuit device according to claim 9 further includes a differential receiving circuit, the differential receiving circuit receiving differential signals transmitted through the first transmission line and the second transmission line.

14. The integrated circuit device according to claim 9, wherein, When the integrated circuit device is a memory, the data clock is transmitted to the memory through the first transmission line and the second transmission line.

15. The integrated circuit device according to claim 14, wherein, The swing detector, the comparator, and the comparison result transmission circuit operate during the training operation.

16. An integrated circuit device, comprising: A differential transmission circuit that transmits differential signals via a first transmission line and a second transmission line; A receiving circuit that receives pre-level drive strength information from a device that receives the differential signal; as well as A pre-level drive circuit that: performs a pre-level drive to reduce the voltage difference between the first transmission line and the second transmission line, and adjusts the intensity of the pre-level drive according to the pre-level drive intensity information.

17. The integrated circuit device of claim 16, further comprising a timing control circuit, the timing control circuit adjusting the pre-level drive time of the pre-level drive circuit.

18. The integrated circuit device according to claim 17, wherein, The pre-level drive circuit is activated for a predetermined time before the differential transmission circuit is activated, and the time control circuit adjusts the predetermined time.

19. The integrated circuit device according to claim 18, wherein, The time control circuit includes: Multiple shift circuits, which shift the activation signal in sync with the clock to generate the transmission activation signal of the differential transmission circuit; A selection circuit, which, in response to selection information, selects one of the preceding signals of the transmission activation signal from the plurality of shift circuits; and A signal generation circuit that: activates a pre-level drive activation signal for activating the pre-level drive circuit in response to a signal selected by the selection circuit, and deactivates the pre-level drive activation signal in response to the transmission activation signal.

20. The integrated circuit device according to claim 19, wherein, The time control circuit further includes a delay circuit, which delays the signal selected by the selection circuit and transmits the delayed signal to the signal generation circuit.

21. The integrated circuit device according to claim 16, wherein, The pre-level drive circuit includes: Multiple pull-up drivers that perform pull-up driving on the first transmission line; and Multiple pull-down drivers that perform pull-down driving on the second transmission line, The number of activated drivers in the pull-up and pull-down drivers is determined based on the pre-level drive strength information.

22. The integrated circuit device according to claim 16, wherein, When the integrated circuit device is a memory controller, the differential signal is a data clock.

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