Managing erase operations in memory system

Abstract

The disclosure relates to managing erase operations in a memory system. Methods, systems, and devices are described for performing erase operations in a memory system. An example system includes a memory device and a memory controller. A memory device includes a memory cell array and a peripheral circuit coupled to the memory cell array. Before an erase pulse is applied to a source line coupled to an array of memory cells, the peripheral circuit performs pre-program operations on word lines and select gate lines of the memory cell array, respectively, by performing a first pre-program operation on the word lines for a first time period and a second pre-program operation on the first select gate line for a second time period.

Description

Technical Field

[0001] This disclosure relates generally to memory systems, and more specifically to the management of erase operations on memory systems. Background Technology

[0002] Erasing operations in memory devices, particularly flash memory, present several challenges, including wear on memory cells that can limit their lifespan due to a finite number of erase cycles. Storage inefficiencies associated with erase operations can be addressed to maintain data integrity and device performance. Summary of the Invention

[0003] This disclosure describes the management of erase operations in a memory system.

[0004] In one aspect, this disclosure describes a method performed by peripheral circuitry in a memory device. The method includes: performing pre-programming operations on word lines and select gate lines of the memory cell array, respectively, before applying an erase pulse to a source line coupled to the memory device; and applying the erase pulse to the source line. The select gate line includes a first select gate line, and performing the pre-programming operations on the word line and select gate line includes: performing a first pre-programming operation on the word line during a first time period, and performing a second pre-programming operation on the first select gate line during a second time period different from the first time period.

[0005] In another aspect, this disclosure describes a memory device. The memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array. The peripheral circuitry is configured to: perform pre-programming operations on word lines and select gate lines of the memory cell array before applying an erase pulse to a source line of the memory cell array coupled to the memory device; and apply the erase pulse to the source line. The select gate line includes a first select gate line, and performing pre-programming operations on the word line and select gate line includes: performing a first pre-programming operation on the word line during a first time period, and performing a second pre-programming operation on the first select gate line during a second time period different from the first time period.

[0006] In another aspect, this disclosure describes a system including a memory device and a controller coupled to the memory device. The memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array. The peripheral circuitry is configured to: perform pre-programming operations on word lines and select gate lines of the memory cell array before applying an erase pulse to a source line of the memory cell array coupled to the memory device; and apply the erase pulse to the source line. The select gate line includes a first select gate line, and performing pre-programming operations on the word line and select gate line includes: performing a first pre-programming operation on the word line during a first time period, and performing a second pre-programming operation on the first select gate line during a second time period different from the first time period.

[0007] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. Attached Figure Description

[0008] Figure 1 A block diagram of an example system according to one or more embodiments of this disclosure is shown.

[0009] Figure 2A A diagram of an example memory card according to one or more embodiments of the present disclosure is shown.

[0010] Figure 2B An illustration of an example solid-state drive (SSD) according to one or more embodiments of the present disclosure is shown.

[0011] Figure 3 A schematic circuit diagram of an example memory device according to one or more embodiments of the present disclosure is shown.

[0012] Figure 4 A side view of a cross-section of an example memory cell array according to one or more embodiments of the present disclosure is shown.

[0013] Figure 5 A block diagram of an example memory device according to one or more embodiments of the present disclosure is shown.

[0014] Figure 6 The threshold voltage distribution of memory cells in an example programming operation according to one or more embodiments of this disclosure is shown.

[0015] Figure 7A and Figure 7B The waveform of the word line voltage applied to a selected word line during an example programming operation is shown according to one or more embodiments of the present disclosure.

[0016] Figure 8 A flowchart illustrating an example process of an erase operation managed by a memory device according to one or more embodiments of this disclosure is shown.

[0017] Figure 9 A diagram illustrating an example process for performing pre-programmed operations according to one or more embodiments of this disclosure is shown.

[0018] Figure 10 An example of applying an erase pulse to a block of memory cells in a memory cell array according to one or more embodiments of this disclosure is shown.

[0019] Figure 11 A diagram illustrates an example process of applying different voltage pulses to the source lines, select gates, and word lines coupled to a memory cell array, according to one or more embodiments of the present disclosure.

[0020] Similar reference numerals and names in the various figures indicate similar elements. Detailed Implementation

[0021] Erasing operations in memory devices are processes used to reset data in memory cells to a default state, typically making them ready for new data to be written. This operation is essential in flash memory technologies such as NAND and NOR, where it involves applying specific electrical signals to remove stored charge from the memory cells, thereby erasing the stored information. Several types of erase operations exist in memory devices, particularly in the context of flash memory, each with its own mechanism and characteristics. These types of erase operations include Fowler-Nordheim (FN) tunneling erase, channel hot electron (CHE) injection erase, source-side injection (SSI), thermal erase, gate-induced drain leakage (GIDL) erase, and others. Each of these methods has its own set of advantages, limitations, and applicability, depending on the specific requirements of the memory device, such as speed, endurance, power consumption, and the need for partial or block-level erasure. For example, GIDL erase is known for its lower power consumption and the potential for finer granularity, but it must be carefully managed to balance the performance, lifespan, and reliability of the memory device.

[0022] GIDL in semiconductor manufacturing is a phenomenon that occurs in transistors (such as metal-oxide-semiconductor field-effect transistors (MOSFETs)) of memory devices. This is particularly relevant in modern, miniaturized transistors. GIDL occurs when a high electric field is present at the drain junction under off-state conditions (when the transistor should be off). This high field is caused by the gate voltage. In some cases, especially as transistors are miniaturized, this electric field can become strong enough to cause a large current to flow from the drain to the substrate, even when the transistor is off. This current is undesirable because it leads to power dissipation and affects the overall performance of the semiconductor device.

[0023] The main factors contributing to GIDL include thin oxide layers, high drain voltage, and material properties. GIDL can lead to increased quiescent power consumption, a significant issue for battery-powered devices such as smartphones and laptops. It can also affect the reliability and lifespan of semiconductor devices.

[0024] GIDL erasure is a technique used in certain types of non-volatile memory (such as flash memory) to improve performance by erasing data more efficiently. This technique utilizes the GIDL effect, which is often considered a parasitic effect in transistor operation, to advantageously erase data from memory cells.

[0025] In GIDL erasure, a strong electric field is intentionally generated on the thin gate oxide of the memory transistor, similar to the conditions that induce GIDL in a conventional transistor. This electric field causes electrons to tunnel from the floating gate of the transistor through the gate oxide to the substrate, effectively removing the stored charge from the floating gate. Since the charge state of the floating gate determines the data stored in the memory cell, this process effectively erases the data.

[0026] Compared to conventional erasure methods, GIDL erasure can be more energy-efficient because it may require lower voltage and current. It can potentially offer faster erase times, which can improve the overall performance of memory devices. As semiconductor device sizes shrink, conventional erasure mechanisms face challenges due to the physical limitations of the materials and structures used. GIDL erasure provides an alternative mechanism that can be more easily scaled with advanced manufacturing techniques.

[0027] While the GIDL erasure method offers potential benefits in terms of power efficiency, erasure speed, and scalability, it also presents challenges in terms of memory cell control and long-term reliability.

[0028] For example, GIDL erasure can cause voltage shifts or variations on the select gate due to the inherent variability of the tunneling rate and physical differences between individual memory cells. This can lead to non-uniform erasure and affect the performance and reliability of the memory device. The GIDL effect relies on quantum tunneling, a process that can be affected by subtle variations in the transistor's physical structure, such as differences in oxide thickness, doping concentration, and surface roughness. Even under the same erasure conditions, these variations can result in different tunneling rates for different cells. The variability of the tunneling rate can lead to non-uniform erasure across the memory array. Some cells may lose their charge faster than others, resulting in variations in the cell's threshold voltage after erasure.

[0029] For example, excessive charge removal may occur, leading to an over-erased state of the memory cell. This over-erasing can shift the threshold voltage of the memory cell into a range that is undesirable for normal operation. Conversely, if the GIDL effect is not strong enough or inconsistent, some cells may not be completely erased, resulting in variations in the threshold voltage.

[0030] In some implementations, adding a pre-programming operation before the erase operation can help compensate for voltage offsets caused by GIDL erasure. This technique helps to standardize the starting conditions of memory cells before erasure, resulting in a more uniform erase process for memory cells.

[0031] In some cases, transistors in different segments of a memory array can experience different threshold voltage offset levels. For example, a memory array may include memory cells coupled by word lines and select-gate transistors (also called select gates) coupled by select-gate lines. Select-gate transistors may also comprise multiple layers or be arranged in different planes. Memory cells and select-gate transistors may experience voltage offsets in different directions and / or at different levels. This variation in voltage offset can be attributed to several factors, such as physical layout and structure, different operational roles, exposure to erase and write cycles, material and manufacturing variability, electrical interference and crosstalk, and thermal effects. Therefore, preprogramming processes with joint control of word lines and select-gate lines present challenges in achieving accurate voltage threshold control due to the different adjustment requirements of word lines and select gates during preprogramming. Furthermore, varying word line loads exert different effects on the select gate, further complicating voltage threshold control. To compensate for the varying levels of voltage offset experienced by different segments of the memory array during erase operations, non-uniform or custom preprogramming schemes can be used, which decouple different segments of the memory array or perform different or separate preprogramming operations. For example, as described in more detail below, different pre-programming operations can be performed on different segments of the memory array during different time periods. Therefore, instead of conventional uniform pre-programming methods, such as applying the same pre-programming operation to both word lines and select gate lines, a pre-programming method that decouples these programming operations can be used. In some implementations, instead of using a single controller or control module to jointly control the pre-programming operations of word lines and select gate lines, the described non-uniform or customized pre-programming scheme can be achieved by employing different controllers or control modules to separately control the pre-programming of word lines and select gate lines. Separate control allows for customized configuration of pre-programming parameters (e.g., voltage, duration, and rate), particularly independently for word lines and select gate lines. The described techniques enable more precise tuning of the pre-programming results, effectively minimizing differences in the pre-programming effect between select gates and word lines across various planar configurations. Therefore, the described techniques can provide an improved mechanism to mitigate different voltage offset patterns associated with word lines and select gate lines, thereby enhancing control over margin losses attributable to erase interruptions. In some implementations, the described techniques can lead to extended erase duration and improve the reliability and performance of memory devices by ensuring more consistent erase and programming characteristics.

[0032] Figure 1A block diagram of an example system 100 according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having a storage device therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102. Memory system 102 includes one or more memory devices 104 and a memory controller 106. Host 108 may be, for example, a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host 108 may be configured to send data to or receive data from memory device 104. In order to send data to or receive data from memory device 104, in addition to data, host 108 may also send instructions to memory system 102.

[0033] Memory device 104 can be any memory device disclosed herein. In some embodiments, memory device 104 (e.g., a NAND flash memory device) can allocate one or more memory cells (e.g., xLCs, i.e., configured to have N bits of data per xLC) based on data pages having N bits of data per xLC. N In one of the memory cells at each level, where N is an integer greater than 1, a programming operation is performed. In some examples, xLC can store two bits per cell (MLC), three bits per cell (TLC), or four bits per cell (QLC).

[0034] In some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in embedded multimedia cards (eMMC) or high duty cycle SSDs used as data storage devices in mobile devices such as smartphones, tablets, laptops, enterprise storage arrays, etc.

[0035] Memory controller 106 can be configured to control the operation of memory device 104 (e.g., read, erase, and program (or write) operations). For example, based on instructions received from host 108, memory controller 106 can transmit various commands (e.g., program (or write) commands, read commands, erase commands, etc.) to memory device 104 to control the operation of memory device 104. In some embodiments, memory controller 106 transmits a programming command to memory device 104 to initiate a programming operation to be performed by memory device 104. During the ongoing programming operation, an interrupt can occur, for example, from host 108 (e.g., a read operation on another page). Memory controller 106 can be configured to transmit an interrupt command to memory device 104 to suspend the programming operation. In some embodiments, memory controller 106 can also be configured to transmit a resume command to memory device 104 to resume and complete the suspended program operation upon completion of other operations triggered by the interrupt.

[0036] The memory controller 106 may also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with an external device via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), High Speed ​​PCI (PCI-e), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0037] The memory controller 106 and one or more memory devices 104 can be integrated into various types of memory devices and can be included in, for example, the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0038] In such Figure 2AIn one example shown, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA), CF card, Smart Media (SM) card, Memory Stick, Multimedia Card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include components configured to couple the memory card 202 to a host computer (e.g., Figure 1 The memory card connector 204 of the host (108) in the middle.

[0039] In such Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components configured to couple the SSD 206 to a host (e.g., Figure 1 The SSD connector 208 of the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the corresponding storage capacity and / or operating speed of the memory card 202.

[0040] Figure 3 A schematic circuit diagram of a memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is shown. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate memory cell including a floating-gate transistor or a charge-trapping memory cell including a charge-trapping transistor.

[0041] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states (levels) and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first threshold voltage range, and a second memory state "1" may correspond to a second threshold voltage range. In some implementations, each memory cell 306 is an xLC capable of storing more than a single bit of data with more than four memory states (levels). For example, an xLC may store two bits per cell (MLC), three bits per cell (TLC), or four bits per cell (QLC). Each xLC can be programmed to take a range of possible nominal storage values ​​(i.e., 2). N (N bits of data, such as Gray code). In one example, the MLC can be programmed to take one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0042] like Figure 3 As shown, each NAND memory string 308 may further include a source select gate (SSG) transistor 310 at its source end and a drain select gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and DSG transistor 312 may be configured to activate the selection of the NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). That is, according to some embodiments, all NAND memory strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the drain of each NAND memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection or deselect voltage to the gate of the corresponding DSG transistor 312 via one or more DSG lines 313 and / or by applying a selection or deselect voltage to the gate of the corresponding SSG transistor 310 via one or more SSG lines 315.

[0043] like Figure 3As shown, NAND memory strings 308 can be organized into multiple blocks 304, where each block 304 can have a common source line 314, for example, coupled to the ACS. In some embodiments, each block 304 is the basic data unit for erase operations, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in the selected block 304, the source line 314 coupled to the selected block 304 and the unselected block 304 in the same plane as the selected block 304 can be biased with an erase voltage (Vers), such as a high positive bias voltage (e.g., 20V or higher). Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0044] like Figure 3 As shown, the memory cell array 301 may include an array of memory cells 306 in multiple rows and multiple columns in each block 304. According to some embodiments, a row of memory cells 306 corresponds to one or more pages, and a column of memory cells corresponds to a NAND memory string 308. Multiple rows of memory cells 306 may be coupled to word lines 318, and multiple columns of memory cells 306 may be coupled to bit lines 316. Peripheral circuitry 302 may be coupled to the memory cell array 301 via bit lines 316 and word lines 318.

[0045] Figure 4 A cross-sectional side view of a memory cell array 301 including NAND memory strings 308, according to some aspects of this disclosure, is shown. Figure 4 As shown, the NAND memory string 308 may extend vertically through the memory stack 404 above the substrate 402. The substrate 402 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0046] The memory stack 404 may include staggered gate conductive layers 406 and gate-to-gate dielectric layers 408. The number of pairs of gate conductive layers 406 and gate-to-gate dielectric layers 408 in the memory stack 404 determines the number of memory cells 306 in the memory cell array 301. The gate conductive layers 406 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate surrounding the gate of a memory cell 306, a gate of a DSG transistor 312, or a gate of an SSG transistor 310, and may extend laterally as a DSG line 313 at the top of the memory stack 404, an SSG line 315 at the bottom of the memory stack 404, or a word line 318 between DSG lines 313 and SSG lines 315.

[0047] like Figure 4 As shown, the NAND memory string 308 includes a channel structure 412 extending vertically through the memory stack 404. In some embodiments, the channel structure 412 includes channel holes filled with one or more semiconductor materials (e.g., as semiconductor channel 420) and one or more dielectric materials (e.g., as memory film 418). In some embodiments, the semiconductor channel 420 includes silicon, such as polysilicon. In some embodiments, the memory film 418 is a composite dielectric layer including a tunneling layer 426, a storage layer 424 (also referred to as a "charge trapping / storage layer"), and a barrier layer 422. The channel structure 412 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 420, tunneling layer 426, storage layer 424, and barrier layer 422 are arranged radially from the center of the pillar toward the outer surface in this order. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 424 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 422 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film 418 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0048] like Figure 4As shown, according to some embodiments, a well 414 (e.g., a P-well and / or an N-well) is formed in a substrate 402, and the source terminal of the NAND memory string 308 is in contact with the well 414. For example, a source line 314 may be coupled to the well 414 to apply an erase voltage to the well 414 (i.e., the source of the NAND memory string 308) during an erase operation. In some embodiments, the NAND memory string 308 also includes a channel plug 416 at the drain terminal of the NAND memory string 308. It should be understood that, although Figure 4 Additional components that may form the memory cell array 301, but not shown in the diagram, include, but are not limited to, gate line gaps / source contacts, local contacts, interconnect layers, etc.

[0049] like Figure 4 As shown, the memory stack 404 includes two segments or groups of cells within the stack, namely an upper deck 440 and a lower deck 440. In the context of 3D memory devices, memory cells are vertically stacked in multiple layers to increase storage density. In this context, a "deck" is a subset of these layers. For example, if a memory string has 64 layers, it can be divided into an upper deck and a lower deck, each consisting of 32 layers. The partitioning of the decks is not only physical but also functional. Each deck can be accessed and manipulated independently, which can improve performance, reduce power consumption, and increase the efficiency of memory operations. In the example shown, the lower deck 440 refers to the layer closer to the substrate 402, and the upper deck 430 refers to the layer further away from the substrate 402. By organizing memory cells into decks, interference between cells can be reduced, which can improve data integrity and read / write speeds. Different decks can be used to implement wear leveling strategies, distributing write and erase cycles across the memory chip to extend its lifetime. This architecture also allows for scalability in memory designs. For example, manufacturers can increase storage capacity by adding more layers (i.e., stacking) without significantly increasing the chip's footprint.

[0050] In some cases, variations in the dimensions of the channel structure along the vertical direction (e.g., the stacking direction of the memory cells) in the stack of memory strings in a 3D memory device may occur due to several factors inherent in the manufacturing process. For example, variations in the dimensions of the channel structure may occur due to one or more of the following factors: deposition inconsistencies, etching variability, lithography challenges, stress and strain during manufacturing, chemical mechanical polishing (CMP) irregularities, thermal effects, diffusion and material interactions, or limitations of current technology.

[0051] In the example shown, the channel structure 412 within each of the upper stack 430 and the lower stack 440 exhibits a decreasing size from the top layer to the bottom layer. This gradation is manifested as a gradual decrease in the cross-sectional area of ​​the channel structure 412, whereby the top layer of each stack has the largest channel size, and this channel size decreases in each subsequent layer down to the bottom layer of the stack.

[0052] Note that, for illustrative purposes, Figure 4 The memory string 308 is shown as comprising two stacks. In some examples, the memory string 308 may have any suitable number of stacks, wherein each stack may have any suitable number of layers, such as four stacks consisting of eight layers each, eight stacks consisting of eight or twelve layers each, sixteen stacks consisting of eight layers each, or twenty-two stacks consisting of eight layers each.

[0053] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array 301 by applying voltage and / or current signals to each selected memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and by sensing voltage and / or current signals from each selected memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0054] Figure 5 The diagram illustrates some exemplary peripheral circuitry, including a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may also be included. Figure 5 Additional peripheral circuitry not shown.

[0055] Page buffer / sensor amplifier 504 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store data to be programmed into a page of memory cell array 301. In another example, page buffer / sensor amplifier 504 can verify the programmed selected memory cell 306 in each programming / verification cycle (cycle) of a programming operation to ensure that data has been properly programmed into the memory cell 306 coupled to select word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify small voltage swings to a recognizable logic level during read operations. As described in detail below and consistent with the scope of this disclosure, in programming operations, the page buffer / sensor amplifier 504 may include multiple page buffer circuits respectively coupled to bit line 316. Each page buffer circuit includes a set of memory cells (e.g., latches) for temporarily storing an N-bit data (e.g., in Gray code form) received from the data bus 518 and providing this N-bit data to the corresponding selected memory cell 306 via the corresponding bit line 316 using a multiple cache load scheme in programming operations.

[0056] The column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and to select one or more NAND memory strings 308 by applying bit line voltages generated from voltage generator 510. The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect block 304 of memory cell array 301 and select / deselect word line 318 of block 304. The row decoder / word line driver 508 can also be configured to drive word line 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive SSG line 315 and DSG line 313. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, channel pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 301.

[0057] Control logic 512 can be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to retrieve data from a memory controller (e.g., Figure 1 106 in the middle) and / or host (e.g., Figure 1 The interface 516 receives control commands from the control logic 512 and buffers and relays them to the control logic 512, and receives status information from the control logic 512 and buffers and relays it to the memory controller and / or the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and acts as a data input / output (I / O) interface and data buffer to buffer and relay data to and from the memory cell array 301.

[0058] Figure 6 An exemplary threshold voltage distribution of a memory cell in programming operations according to some aspects of this disclosure is shown. As described above, each memory cell 306 can be configured to have a threshold voltage distribution of 2... N One of the level values ​​stores one N-bit data, where N is an integer greater than 1 (e.g., N=2 for MLC, N=3 for TLC, N=4 for QLC, etc.). Each level can correspond to 2 bits of memory cell 306. N Threshold voltage (V) TH One of the ranges. Taking TLC as an example, where N=3, such as... Figure 6 As shown, memory cell 306 can be programmed to one of eight voltage levels, including one level for the erase state and seven levels for the programming state. Each level can correspond to a specific threshold voltage (V) for memory cell 306. TH ) range. For example, the range corresponding to the lowest threshold voltage ( Figure 6 The level of the leftmost threshold voltage distribution in the diagram can be considered as level 0, corresponding to the second-to-last lowest threshold voltage range ( Figure 6 The level of the second-leftmost threshold voltage distribution in the range can be considered as level 1, and so on until the range corresponding to the highest threshold voltage ( Figure 6 The level of the rightmost threshold voltage distribution in the data is 7.

[0059] Each level can correspond to 2 to be stored in the selected memory unit 306. N One of N-bit data entries. In some implementations, 2 NN-bit data can be represented by Gray code (in Gray code form). Gray code (also known as reflected binary code (RBC) or reflected binary (RB)) is an ordering of binary digits such that two consecutive values ​​differ in only one bit (binary digit). For example, Table 1 below shows the representation of... Figure 6 The example uses a one-to-one mapping of binary codes between eight levels (LV0 to LV7) and eight 3-bit data segments. As shown in Table 1, each 3-bit data segment can consist of three binary values ​​(b1, b2, and b3). In one example, level 1 can correspond to a 3-bit data segment with the value 000. In another example, level 7 can correspond to another 3-bit data segment with the value 101.

[0060] Table 1

[0061]

[0062]

[0063] Also refer to Figure 5 During programming operations, user data can be used to program memory cells 306 in selected rows coupled to select word line 318. In some embodiments, user data is transmitted via data bus 518 to page buffer / sensor amplifier 504, which is configured to convert the user data into data to be programmed into the corresponding row of memory cells 306 based on a preset Gray code. According to some embodiments, control logic 512 is configured to send control signals (e.g., enable signals) to page buffer / sensor amplifier 504 based on a preset Gray code (which defines a mapping between each programming level and a corresponding N-bit data bit) to allow page buffer / sensor amplifier 504 to generate data for sequential programming operations. During an ongoing programming operation, current data can be temporarily stored in page buffer / sensor amplifier 504, and page buffer / sensor amplifier 504 can be configured to provide corresponding data to each memory cell 306 coupled to select word line 318 via corresponding bit line 316.

[0064] In order to perform programming operations, in addition to the page buffer / sensor amplifier 504 providing corresponding data to each selected memory cell 306, the row decoder / word line driver 508 can be configured to apply programming and verification voltages to the select word line 318 coupled to the selected row of the memory cell 306 in one or more programming / verification cycles, so as to raise the threshold voltage of each selected memory cell 306 to a desired level (into the desired threshold voltage range) based on the corresponding data.

[0065] Figure 7A and Figure 7BThe waveforms of word line voltages applied to word lines during programming operations according to some embodiments of this disclosure are shown. For example... Figure 7A As shown, the programming operation includes one or more programming / verification loops (cycles) 702. For example... Figure 7B As shown, in each programming / verification cycle 702, the line decoder / word line driver 508 can be configured to apply a programming voltage (V) to the word line (e.g., word line 318). pgm and apply one or more (e.g., up to 2) N -1) Verification voltage (V) vf This is to verify whether the target memory cell has been properly programmed to the target programming level. N -1 verification voltage can correspond to 2 N 2 of the levels N -1 level (e.g., 2) N -1 programming level). That is, the peripheral circuit 302 can be configured to use 2 N 2 of the levels N -1 level-verified selection row memory cell 306. Each selection memory cell 306 can be programmed as 2 based on the corresponding data to be stored in the selection memory cell 306 (i.e., the current data stored in the corresponding page buffer circuit 702). N -1 level. Still using a TLC with N=3 as an example, the selection memory cell 306 can be sequentially programmed into one of the seven programming levels (e.g., Figure 6 (As shown in the diagram). Seven verification voltages, each corresponding to one of the seven programming levels, can be applied to verify whether the memory cell has been programmed to the target programming level.

[0066] Figure 8 An example process 800 for performing an erase operation in a memory device according to some embodiments of this disclosure is shown. Process 800 can be performed by any suitable means as described herein, such as memory device 104, memory device 106, or memory device 300. The operations shown in process 800 may not be exhaustive, and other operations may be performed before, after, or between any of the shown operations. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 8 The different execution orders shown.

[0067] In some embodiments, the erase operation may include a pre-programming operation performed before applying the erase pulse, for example, to compensate for voltage offsets caused by the erase pulse. In process 800, the memory device (e.g., memory device 300) performs pre-programming operations (802) on the word lines and select gate lines of the memory cell array in the memory device, respectively. In some embodiments, the memory device performs the pre-programming operation before applying the erase pulse to the source lines coupled to the memory cell array. In some examples, the memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array. The peripheral circuitry may be configured to control the pre-programming operation.

[0068] In some implementations, the erase operation may be a GIDL erase operation, and the erase pulse is the erase pulse of the GIDL erase operation.

[0069] In some examples, the pre-programming operation may include applying a specific voltage to the control gate of the memory cell, causing the memory cell to store charge in its floating gate. This process effectively programs all memory cells to the same or similar threshold voltage level. After pre-programming, the memory cells can all begin the erase process from the same or similar threshold voltage level. This uniformity helps mitigate the problem of some cells being over-erased or under-erased compared to other cells, which can occur due to the inherent variability in the GIDL erase process.

[0070] In some cases, transistors in different segments of a memory array can experience different threshold voltage offset levels. For example, the select gate coupled to the select gate line and the memory cell coupled to the word line can experience different voltage offset levels. To compensate for the varying voltage offset levels experienced by different segments of the memory array, a non-uniform pre-programming scheme can be used. For example, different pre-programming operations can be performed on different segments of the memory array at different time periods.

[0071] In some embodiments, the select gate line includes a first select gate line. In such an embodiment, the memory device performs a non-uniform preprogramming operation by performing a first preprogramming operation (804) on the word line during a first time period and a second preprogramming operation (806) on the first select gate line during a second time period different from the first time period.

[0072] In some implementations, the start time of the second time period is before the start time of the first time period. In some implementations, the start time of the first time period is before the start time of the second time period.

[0073] In some implementations, the first time period and the second time period do not overlap. For example, the start time of the second time period may be later than the end time of the first time period. For example, non-overlapping pre-programming operations may occur when the first pre-programming operation and the second pre-programming operation share the same voltage source.

[0074] In some implementations, the first and second time periods partially overlap. For example, the start time of the second time period may be later than the start time of the first time period but earlier than the end time of the first time period. In some examples, the pre-programming phases of these components may partially overlap when different pre-programming operations are applied to word lines and select gate lines. For example, the first and second time periods may partially overlap when a voltage source supplying programming voltage is used for pre-programming word lines and another voltage source supplies pass voltage to the select gate line. Using different voltage sources allows for simultaneous adjustment of the pre-programming parameters of each component, thereby enabling simultaneous but different pre-programming processes.

[0075] In some implementations, performing a first pre-programming operation on a word line during a first time period includes applying a first voltage to the word line during the first time period and applying a second voltage to a first select gate line during the first time period. In such implementations, the first voltage is higher than the second voltage. In some examples, the first voltage may be a programming voltage, which is a specific voltage level applied to the word line to change the state (i.e., program) of a memory cell coupled to the word line, while the second voltage may be a pass voltage, which is a specific voltage level applied to the select gate line to prevent unintentional interference from other memory cells or select gates coupled to the select gate line. In some examples, the voltage level of the first voltage is in the range of 11-25 volts, and the voltage level of the second voltage is in the range of 3-11 volts.

[0076] In some implementations, performing a second pre-programming operation on the first select gate line during the second time period includes applying a third voltage to the first select gate line during the second time period and applying a fourth voltage to the word line during the second time period, wherein the third voltage is higher than the fourth voltage. In some examples, the third voltage may be a programming voltage, and the fourth voltage may be a pass voltage. In some examples, the voltage level of the third voltage is in the range of 11-25 volts, and the voltage level of the fourth voltage is in the range of 3-11 volts.

[0077] In some implementations, the voltage level of the first voltage is the same as the voltage level of the third voltage, and the voltage level of the second voltage is the same as the voltage level of the fourth voltage.

[0078] In some implementations, the third voltage level is higher than the first voltage level. For example, word lines controlling data access in a memory cell may require a voltage lower than the voltage applied to the select gate. Pre-programming the word lines can raise the memory cell from a lower state to a higher state, thereby reducing the risk of over-erasure. Although this process can modify the stored data, subsequent erase operations ensure that these changes do not have a persistent effect. Assuming the word lines are scheduled for erasure, the pre-programming voltage can be relatively lower than the select gate voltage. The select gate, responsible for isolating memory segments during operations such as erase or programming, may require a higher voltage for effective isolation.

[0079] By employing different pre-programming strategies for different transistors in different sections of the memory array, conditions on the memory array can be standardized, resulting in more uniform and predictable performance across all memory cells. Custom pre-programming of word lines and select gates allows adjustment of the starting threshold voltage of the memory cells, ensuring that the memory cells operate within the desired range, for example, for subsequent erase operations.

[0080] In some implementations, in addition to the first select gate line, the select gate line includes one or more select gate lines. The select gate lines can be in different layers or planes. Pre-programming operations on the word lines and pre-programming operations on the select gate lines are performed separately. In some implementations, for example, pre-programming operations on the select gate lines are also performed separately based on the layer or plane in which the select gate lines reside.

[0081] In some embodiments, the select gate line further includes a second select gate line. In such embodiments, performing pre-programming operations on the word line and the select gate line respectively includes performing a first pre-programming operation on the word line during a first time period, performing a second pre-programming operation on the first select line during a second time period, and performing a third pre-programming operation on the second select line during a third time period, wherein the third time period differs from the first time period. In some embodiments, the third time period differs from both the first and second time periods.

[0082] In some implementations, there is no strict order for performing the first pre-programming operation on the word line, the second pre-programming operation on the first select line, and the third pre-programming operation on the second select line. For example, the three pre-programming operations can be performed in any order.

[0083] In some embodiments, the first select gate line and the second select gate line are bottom select gate (BSG) lines. In some embodiments, one of the first select gate line and the second select gate line is a BSG line, and the other is a top select gate (TSG) line.

[0084] In some implementations, the durations of two or more time periods may be the same or different. In some implementations, the voltages applied to the word line and the corresponding select gate line may be different. In some implementations, the duration of the time period and the voltage used in the time period may be designed, determined, or otherwise configured based on one or more loads on the word line, the position of the word line relative to the select gate line, and other factors that may cause voltage offset.

[0085] Figure 9 A diagram illustrating an example process for performing pre-programming operations on word lines and select gate lines in an example memory device according to one or more embodiments of the present disclosure. The example memory device includes at least two layers of BSG, BSG0-1 and BSG0-2. Figure 9 In the example shown, different pre-programming operations are applied to word line WL and select gates BSG0-1 and BSG0-2 at different time periods. In the example shown, during the first time period "T1", a pre-programming operation is performed on the second select gate line BSG0-2. During T1, a pass voltage is applied to word line WL and the first BSG line BSG0-1, and a programming voltage is applied to the second BSG line BSG0-2. In the second time period "T2", a pre-programming operation is performed on the first select gate line BSG0-1. During T2, a pass voltage is applied to word line WL and the second BSG line BSG0-2, and a programming voltage is applied to the first BSG line BSG0-1. In the third time period "T3", a pre-programming operation is performed on word line WL. During T3, a programming voltage is applied to word line WL, and a pass voltage is applied to the first BSG BSG0-1 and the second BSG BSG0-2. Figure 9 In the example shown, the three time periods T1, T2, and T3 do not overlap. In some other cases, the three time periods may partially overlap. In some implementations, the three time periods may have the same duration, while in other implementations, the three time periods may have different durations.

[0086] Non-uniform pre-programming schemes can be beneficial, especially when different select gates experience varying threshold voltage offsets. For example, different select gates may experience varying threshold voltage offset levels attributable to GIDL erase. This variability can be caused by differences in physical layout, manufacturing inconsistencies, or varying local electrical environments within the memory array. The manner in which a ramp step, or voltage is applied during programming or erasing operations, can also affect how GIDL affects the select gates. Slower or gentler ramp steps can lead to different GIDL effects compared to rapid voltage changes. This is because the rate of voltage change can affect the amount of charge accumulation and resulting stress on the gate oxide. Furthermore, each select gate may experience different local conditions, such as temperature variations, different levels of electrical interference, or stress from neighboring cells. These conditions can alter how each gate responds to the same erase or programming voltage. To combat these variations, applying different pre-programming operations to the select gates allows for a more customized approach to maintaining consistent performance and reliability in semiconductor memory devices.

[0087] After the pre-programming operation, a normal erase operation can be performed, for example, by applying an erase pulse to the source line. Because the cells start from a uniform state, the erase operation can be more controlled and predictable, resulting in a more consistent threshold voltage across the memory array after the erase.

[0088] Return to reference Figure 8 After performing pre-programming operations on the word line and select gate, the memory device applies an erase pulse to the source line (808).

[0089] In some examples, applying an erase pulse to the source line may include identifying one or more blocks of memory cells that need to be erased, isolating the target block from the rest of the memory array by applying an appropriate voltage to the select gate, keeping all word lines in the block at a low voltage (e.g., ground potential), and applying a high voltage to the source line.

[0090] Figure 10 An example of applying an erase pulse to a block of memory cells in a memory cell array according to one or more embodiments of this disclosure is shown. Figure 10 As shown, an erase pulse with a voltage level of approximately 20 volts is applied to the source line 1010 coupled to the memory block 1000.

[0091] In some implementations, the erase pulse duration is long enough to ensure all cells in the block are fully erased, but not so long that it causes over-erasure or stresses the memory cells, potentially reducing their lifespan. In some examples, the erase pulse duration may be determined based on manufacturer specifications, material properties, device characteristics, adaptive algorithms, and safety considerations.

[0092] In some implementations, when an erase pulse is applied to the source line, the memory device maintains the voltage of the selected gate line at an initial voltage, such as ground, during the initial phase of the erase pulse. In such implementations, the voltage of the erase pulse gradually increases over time during the initial phase. When the erase pulse reaches a threshold, the memory device allows the voltage of the selected gate line to increase, for example, by floating the selected gate line or setting the gate of the selected gate line to float. For example, refer to... Figure 11 The erase pulse applied to the source line starts from a low voltage "V". ss (For example, ground potential) starts, and then gradually rises to a high voltage "V" erase The erase pulse continues to maintain a high voltage "V". erase "The predetermined time period, then the voltage drops to a low level." ss In the example shown, when the erase pulse is applied to the source line, the voltage of the select gate line initially remains at a low voltage "V". ss ", such as ground potential. When the erase pulse reaches a predetermined threshold "V" rls When the selected gate line is set to floating, the voltage of the selected gate line begins to rise. When the voltage pulse applied to the selected gate line reaches a predetermined high voltage, it remains at the predetermined high voltage for a predetermined period of time, and then drops to a low voltage "V". ss In the example shown, the voltage of the word line is initially maintained at a high voltage "V". cc "and when the erase pulse applied to the source line begins from a low voltage "V" ss "As it rises, it begins to fall to a low voltage." (V) ss ".

[0093] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other and in ways not specifically shown in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0094] Generally, terms can be understood at least in part according to their usage in the context. For example, depending at least in part on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a," "an," or "the" can be understood to convey either a singular or a plural usage. Furthermore, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and can alternatively allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0095] The foregoing description of a particular implementation can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementations.

[0096] The scope and extent of this disclosure should not be limited to any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents. Therefore, other embodiments are also within the scope of the claims.

Claims

1. A method for performing an erase operation in a memory device, comprising: Before applying an erase pulse to the source line of the memory cell array coupled to the memory device, pre-programming operations are performed on the word line and select gate line of the memory cell array, respectively, wherein the select gate line includes a first select gate line, and wherein performing the pre-programming operations on the word line and the select gate line includes: A first pre-programming operation is performed on the word line during the first time period; and Perform a second pre-programming operation on the first selected gate line during a second time period different from the first time period; and The erase pulse is applied to the source line.

2. The method according to claim 1, wherein, The method includes: When the erase pulse is applied to the source line, the voltage of the selected gate line is maintained at an initial voltage during the initial phase of the erase pulse, wherein the voltage of the erase pulse increases over time during the initial phase; and In response to determining that the erase pulse has reached a threshold, the selected gate line is floated.

3. The method according to any one of claims 1-2, wherein, The start time of the second time period is before the start time of the first time period.

4. The method according to any one of claims 1-3, wherein, Performing the first pre-programming operation on the word line during the first time period includes: A first voltage is applied to the word line during the first time period; and During the first time period, a second voltage is applied to the first selected gate line. Wherein, the first voltage is higher than the second voltage.

5. The method according to claim 4, wherein, The first voltage is the programming voltage, and the second voltage is the pass voltage.

6. The method according to claim 4, wherein, The voltage level of the first voltage is in the range of 11-25 volts, and the voltage level of the second voltage is in the range of 3-11 volts.

7. The method according to claim 4, wherein, Performing the second pre-programming operation on the first selected gate line during the second time period includes: During the second time period, a third voltage is applied to the first selected gate line; and During the second time period, a fourth voltage is applied to the word line. The third voltage is higher than the fourth voltage.

8. The method according to claim 7, wherein, The third voltage is higher than the first voltage.

9. The method according to any one of claims 1-8, wherein: The selected gate line further includes a second selected gate line; as well as Performing the pre-programming operation on the word line and the select gate line respectively further includes: A third pre-programming operation is performed on the second selected gate line during a third time period, wherein the third time period is different from the first time period and the second time period.

10. The method according to claim 9, wherein, The first select gate line and the second select gate line are bottom select gate (BSG) lines.

11. A memory device, comprising: Memory cell array; as well as Peripheral circuitry coupled to the memory cell array, wherein the peripheral circuitry is configured as follows: Before applying an erase pulse to the source line of the memory cell array coupled to the memory device, pre-programming operations are performed on the word line and select gate line of the memory cell array, respectively, wherein the select gate line includes a first select gate line, and wherein performing the pre-programming operations on the word line and the select gate line includes: A first pre-programming operation is performed on the word line during the first time period; and Perform a second pre-programming operation on the first selected gate line during a second time period different from the first time period; and The erase pulse is applied to the source line.

12. The memory device according to claim 11, wherein, The peripheral circuit is configured as follows: When the erase pulse is applied to the source line, the voltage of the selected gate line is maintained at an initial voltage during the initial phase of the erase pulse, wherein the voltage of the erase pulse gradually increases over time during the initial phase; and In response to determining that the erase pulse has reached a predetermined threshold, the voltage of the selected gate line is increased.

13. The memory device according to any one of claims 11-12, wherein, The start time of the second time period is before the start time of the first time period.

14. The memory device according to any one of claims 11-13, wherein, Performing the first pre-programming operation on the word line during the first time period includes: A first voltage is applied to the word line during the first time period; and During the first time period, a second voltage is applied to the first selected gate line. Wherein, the first voltage is higher than the second voltage.

15. The memory device according to claim 14, wherein, The first voltage is the programming voltage, and the second voltage is the pass voltage.

16. The memory device according to claim 14, wherein, The voltage level of the first voltage is in the range of 11-25 volts, and the voltage level of the second voltage is in the range of 3-11 volts.

17. The memory device according to claim 14, wherein, Performing the second pre-programming operation on the first selected gate line during the second time period includes: During the second time period, a third voltage is applied to the first selected gate line; and During the second time period, a fourth voltage is applied to the word line. The third voltage is higher than the fourth voltage.

18. The memory device according to claim 17, wherein, The third voltage is higher than the first voltage.

19. The memory device according to any one of claims 11-18, wherein: The selected gate line further includes a second selected gate line; and Performing the pre-programming operation on the word line and the select gate line respectively further includes: A third pre-programming operation is performed on the second selected gate line during a third time period, wherein the third time period is different from the first time period and the second time period.

20. A system comprising a memory device and a controller coupled to said memory device, wherein, The memory device includes: Memory cell array; and Peripheral circuitry coupled to the memory cell array, wherein the peripheral circuitry is configured as follows: Before applying an erase pulse to the source line of the memory cell array coupled to the memory device, pre-programming operations are performed on the word line and select gate line of the memory cell array, respectively, wherein the select gate line includes a first select gate line, and wherein performing the pre-programming operations on the word line and the select gate line includes: A first pre-programming operation is performed on the word line during the first time period; and Perform a second pre-programming operation on the first selected gate line during a second time period different from the first time period; and The erase pulse is applied to the source line.

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