Memory subsystem with improved erase management

Abstract

The invention relates to a memory subsystem with improved erase management. A system includes: a plurality of memory components; and a processing device operably coupled with the plurality of memory components, the processing device to perform operations including: receiving, from a host system, a request to read data stored on the plurality of memory components; determining that the data contains a plurality of errors; identifying a plurality of locations of the plurality of errors, wherein each location of the plurality of locations corresponds to a respective error of the plurality of errors; in response to determining that the plurality of locations fall in a single memory component of the plurality of memory components, excluding the single memory component from future decoding and correcting the data to produce corrected data; sending the corrected data to the host system; and including the single memory component for future decoding.

Description

Technical Field

[0001] This disclosure generally relates to a memory subsystem, and more specifically, to a memory subsystem with improved erase management. Background Technology

[0002] The memory subsystem may include one or more memory components for storing data. These memory components may be, for example, non-volatile memory components and volatile memory components. Generally, a host system may utilize the memory subsystem to store data at the memory components and retrieve data from the memory components. Summary of the Invention

[0003] According to one aspect of this disclosure, a system is provided. The system includes: a plurality of memory components; and a processing means operatively coupled to the plurality of memory components, the processing means being configured to perform operations including: receiving from a host system a request to read data stored on the plurality of memory components; determining that the data contains a plurality of errors; identifying a plurality of locations of the plurality of errors, wherein each of the plurality of locations corresponds to a corresponding error among the plurality of errors; in response to determining that the plurality of locations fall in a single memory component among the plurality of memory components, excluding the single memory component from future decoding and correcting the data to generate corrected data; sending the corrected data to the host system; and including the single memory component for future decoding.

[0004] According to another aspect of this disclosure, a method is provided. The method includes: receiving, by a processing means, a request from a host system to read data stored on a plurality of memory components; determining that the data contains a plurality of errors; identifying a plurality of locations of the plurality of errors, wherein each of the plurality of locations corresponds to a specific error among the plurality of errors; in response to determining that the plurality of locations are associated with a single memory component among the plurality of memory components, correcting the data to produce corrected data; sending the corrected data to the host system; and marking addresses of the plurality of locations associated with the single memory component, wherein the markings are used to indicate that an error was detected at the plurality of locations in future decoding.

[0005] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided. The non-transitory computer-readable storage medium includes instructions, when executed by a processing means, to cause the processing means to perform the following operations: receiving from a host system a request to read data stored on a plurality of memory components; determining that the data contains a plurality of errors; identifying a plurality of locations of the plurality of errors, wherein each of the plurality of locations corresponds to a corresponding error among the plurality of errors; in response to determining that the plurality of locations fall in a single memory component among the plurality of memory components, excluding the single memory component from future decoding and correcting the data to generate corrected data; sending the corrected data to the host system; and including the single memory component for future decoding. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1 This describes an instance computing environment including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart of an example method for performing error correction code decoding operations with improved erasure management, according to some embodiments.

[0009] Figure 3 This describes instance data stored on a memory component according to some embodiments of the present disclosure, wherein... Figure 2 The method is used to perform error correction code decoding operations with improved erase management.

[0010] Figure 4 This describes instance data stored on a memory component with improved erase management, according to some embodiments of the present disclosure.

[0011] Figure 5 and 6 This is a flowchart of an example method for performing improved erase management on data stored on a memory component, according to some embodiments.

[0012] Figure 7 This is a block diagram of an example computer system in which the embodiments of this disclosure are operable. Detailed Implementation

[0013] This disclosure relates to a memory subsystem with improved erase management. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following description is in conjunction with… Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may include high-density non-volatile memory devices where it is desirable to retain data when no power is supplied to the memory device. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die contains one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane contains a set of physical blocks. Each block consists of a set of pages. Each page contains a set of memory cells. A memory cell is an electronic circuit that stores information. Depending on the type of memory cell, a memory cell may store one or more bits of binary information and has various logic states related to the number of bits stored. Logic states may be represented by binary values ​​(e.g., "0" and "1") or combinations of such values.

[0015] Traditionally, several techniques exist for attempting to improve performance and / or reduce errors contained in data stored in a memory subsystem. One technique for improving the reliability of data stored in a memory subsystem is the application of error correction codes. Applying error correction codes can refer to techniques used to express data sequences so that errors introduced into the data can be detected and corrected based on the remaining data. Typically, the encoder encodes the data to be written along with extra data bits to form a codeword, and stripes the codeword across memory components of the memory subsystem. When striped data is to be read, the decoder decodes the codeword by removing the extra data bits and providing the required original data. Error correction codes can limit the number of errors that can be detected and corrected. For example, if the number of errors exceeds a threshold associated with the error correction code, one or more errors cannot be corrected, and in some cases, the memory component of the memory subsystem storing data with such errors can be identified as faulty. However, in some cases, only a portion of the memory component contains errors, while the rest of the memory component remains functional. Identifying the entire memory component as faulty will exclude the entire memory component from use and waste memory resources that are still actually usable.

[0016] This disclosure addresses the aforementioned and other drawbacks by providing a memory subsystem that implements an error correction code (ECC) decoding operation with improved erase management. Implementing an ECC decoding operation involves applying error correction codes to data in an attempt to decode it. Error correction code decoding operations can lead to decoding failures, where one or more errors contained in the data cannot be corrected and the locations of these errors can be identified (“erased”). Identifying the locations of errors on memory components is known and can be referred to as erase detection. In some cases, when the location of an error falls within a single memory component, the error correction code decoding operation can further result in the identification and marking of that single memory component as faulty, thus excluding it from future decoding. Improved erase management enhances erase detection and fault marking by unmarking a single memory component, allowing it to be reused for future decoding. Reusing a single memory component for future decoding allows the remaining memory locations within the single memory component, besides the identified error locations, to be used. In most cases, since the remaining memory locations in the memory components are still functional, improved erase management can further enable the identification of addresses at erroneous locations, allowing the identified addresses to directly indicate the results of erase detections, thereby eliminating the need to perform new erase detections.

[0017] Specifically, the host system may send data to be stored on the memory components of the memory subsystem. The controller of the memory subsystem may encode the data into codewords and store the codewords in the memory components. A codeword may refer to data expressed in a specific sequence to enable the detection and correction of errors introduced during data transmission and storage. Upon receiving a request to read data, the controller of the memory subsystem may attempt to decode the codewords using an ECC decoding operation. The ECC decoding operation may include a first ECC decoding operation without using error location information and a second ECC decoding operation using error location information. In some embodiments, the first and second ECC decoding operations may use the same error correction code. In some embodiments, the type of error correction code may include block codes (e.g., Reed-Solomon codes, etc.).

[0018] For example, the controller of the memory subsystem may determine that one or more errors cannot be corrected using the first ECC decoding operation, and therefore determine that the decoding using the first ECC decoding operation is unsuccessful. The controller of the memory subsystem may identify the location of the error and determine whether the identified error location falls within a single memory component.

[0019] In some implementations, in response to determining that the identified location of the error falls within a single memory component, the memory subsystem controller may mark the single memory component as faulty and perform a second ECC decoding operation to generate corrected data. The memory subsystem controller may then send the corrected data to the host system requesting the read data. The memory subsystem controller may then demark the single memory component to include it for future decoding. That is, when the memory subsystem receives a new read request, the memory subsystem controller may still attempt to decode the data stored on the memory component containing the demarked memory component.

[0020] In some implementations, in response to determining that an identified location of an error falls within a single memory component, the controller of the memory subsystem may perform a second ECC decoding operation to generate corrected data and send the corrected data to the host system requesting the read data. In some implementations, the controller of the memory subsystem may skip the marking and demarking operations of a single memory component and instead mark the address of the identified location of the error falling within the single memory component. In some implementations, as described above, the controller of the memory subsystem receives a request that may specify an address that can be used to reference the error location in a single memory component. The controller of the memory subsystem may mark this address, which can be used to indicate the result of an erase detection. That is, when the memory subsystem receives a new read request, the controller of the memory subsystem may determine whether to mark the address specified in the new read request. In response to determining the marked address, the controller of the memory subsystem may directly determine that the location referenced by the address in a single memory component contains one or more errors without performing conventional error detection or erase detection.

[0021] The advantages of this disclosure include improved memory resource endurance for the memory subsystem by reusing memory components that have been marked as faulty. Furthermore, this improvement in memory endurance can be achieved without adding additional memory components to the memory subsystem, thereby reducing data center size and / or cost. Additionally, aspects of this disclosure avoid latency caused by performing additional erase detection. These aspects also improve data reliability of the memory subsystem by reducing the probability of false identification of memory component failures, which can improve overall memory subsystem performance as access operations are successful.

[0022] Figure 1 This description illustrates an example computing environment 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as memory components 112A to 112N.

[0023] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash memory drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0024] The computing system 100 may be a computing device such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capability, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked commercial device), or such computing device containing memory and processing device.

[0025] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0026] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller, a CXL controller). The host system 120 uses the memory subsystem 110 to, for example, write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0027] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Compute Fast Link (CXL) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), and Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus or a CXL bus), host system 120 can further utilize an NVM Fast (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transmitting control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0028] Memory components 112A to 112N may include different types of non-volatile memory devices and / or any combination of volatile memory devices. The volatile memory devices may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0029] Examples of non-volatile memory devices include NAND flash memory and in-situ write memory, such as three-dimensional cross-point (“3D cross-point”) memory devices, which are cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory cells can perform bit storage based on changes in volume resistance along with stackable cross-grid data access arrays. Furthermore, in contrast to many flash memory-based memories, cross-point non-volatile memory can perform in-situ write operations, whereby the non-volatile memory cells can be programmed without previously erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of memory components 112A to 112N may include one or more arrays of memory cells. One type of memory cell (e.g., single-level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC)) may store multiple bits per cell. In some embodiments, each of memory components 112A to 112N may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. Memory cells of memory device 130 may be grouped into pages, which may refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks. Some types of memory (e.g., 3D cross-point) may group pages across dies and channels to form management units.

[0031] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memories (e.g., 2D NAND, 3D NAND) have been described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with memory components 112A to 112N to perform operations, such as reading data, writing data, or erasing data at memory components 112A to 112N, and other such operations. Controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. Controller 115 may be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0033] Controller 115 may include processing means configured to execute instructions stored in local memory 119, including one or more processors (e.g., processor 117). In the illustrated example, the local memory 119 of controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logical flows, and routines that control the operation of memory subsystem 110, including handling communication between memory subsystem 110 and host system 120.

[0034] In some embodiments, local memory 119 may include memory registers storing memory pointers, fetched data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although already... Figure 1 The instance memory subsystem 110 is described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host, or by a processor or controller separate from the memory subsystem).

[0035] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory components 112A to 112N. The memory subsystem controller 115 may handle other operations such as wear leveling, discard item collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical MU addresses, physical block addresses) associated with memory components 112A to 112N. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access memory components 112A to 112N and translate responses associated with memory components 112A to 112N into information for the host system 120.

[0036] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) capable of receiving addresses from the memory subsystem controller 115 and decoding the addresses to access memory components 112A to 112N.

[0037] In some embodiments, each of the memory components 112A to 112N includes a local media controller 135, which operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of each of the memory components 112A to 112N. An external controller (e.g., the memory subsystem controller 115) may externally manage the memory components 112A to 112N (e.g., perform media management operations on the memory components 112A to 112N). In some embodiments, the memory subsystem 110 is a managed memory device, which is a raw memory device having on-die control logic (e.g., the local media controller 135) and a controller (e.g., the memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] The memory subsystem 110 may include an erase manager 113 (e.g., circuitry, dedicated logic, programmable logic, firmware, etc.) for performing ECC decoding operations with improved erase management. In some embodiments, the memory subsystem controller 115 includes at least a portion of the erase manager 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the erase manager 113 is part of the host system 110, an application, or an operating system. Reference is made below. Figures 2 to 6 Further details regarding the operation of the erase manager 113 are described below.

[0039] Those skilled in the art should understand that additional circuitry and signals can be provided, and that the process has been simplified. Figure 1 Components. It should be recognized that references... Figure 1 The functionality of the various block components described need not be separated into different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0040] Figure 2 This is a flowchart of an example method 200 for performing an ECC decoding operation with improved erase management according to some embodiments of the present disclosure. Method 200 may be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1The erase manager 113 executes the process. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0041] At operation 210, the processing logic receives a request to read data stored on memory components 112A to 112N. The data stored on memory components 112A to 112N contains host data encoded using ECC encoding operations. Host data refers to raw data received from the host system for storage. In some embodiments, the data stored on memory components 112A to 112N contains codewords, and the codewords are formed by combining the host data with redundant data (e.g., parity data) generated by the ECC encoding operations. In one example, host system 120 may send host data to memory subsystem 110 for storage; the controller 115 of memory subsystem 110 may include an encoder that performs ECC encoding operations on the host data to generate redundant data and appends the redundant data to the host data to form a codeword; and the controller 115 may store the codeword in memory components 112A to 112N. In some embodiments, different data blocks of the codeword may be written across corresponding data blocks of memory components 112A to 112N. In some implementations, each of the memory components 112A to 112N is a bare die.

[0042] In some implementations, ECC encoding operations operate on symbols, where each symbol represents a certain number of bits. For example, bits stored on each of the memory components 112A to 112N may be referred to as a corresponding symbol, and thus data (e.g., codewords) contains multiple symbols.

[0043] For example, the host system can send a request to write raw data, and the encoder in the memory subsystem can use the raw data as data symbols, where each data symbol represents a fixed number of bits of host data. The encoder can generate parity symbols and append them to the data symbols, where each parity symbol represents a fixed number of bits of parity data. The data symbols and parity symbols together form a codeword. The memory subsystem controller can store the codeword in one or more memory components, where the codeword includes the data symbols and parity symbols.

[0044] In some embodiments, ECC encoding operations may use maximum distance separable codes, such as Reed-Solomon codes. Reed-Solomon codes encode host data by adding extra redundant bits to the host data. Mathematical operations (e.g., polynomials) may be generated based on the host data, and these redundant bits may be obtained using these mathematical operations. For example, k symbols with s bits per symbol can be encoded into an n-symbol codeword, where (nk) redundant (e.g., parity) symbols are added to the k symbols. The n-symbol codeword may be stored in different memory components 112A to 112N.

[0045] Various factors (e.g., noisy communication, memory component failure, asynchronous power loss, etc.) can cause data inclusion errors in codewords (e.g., flipped bits, missing bits, etc.). If errors exist in codewords stored across memory components 112A to 112N, redundant (e.g., parity) symbols or other bits of the codewords can be used in the original mathematical operations to obtain the original host data and correct the errors in the codewords. For example, the memory subsystem can use parity symbols to reconstruct the data symbols when data symbols in other memory components contain errors.

[0046] At operation 220, the processing device uses a first error correction code (ECC) decoding operation to decode data stored on memory components 112A to 112N. The first ECC decoding operation may include applying ECC to a codeword to attempt decoding the codeword (e.g., removing parity bits) and / or correcting one or more errors. For example, applying ECC to data stored on memory components 112A to 112N may result in obtaining updated data containing at least one corrected bit, changing the bit containing the error to the corrected bit. In some embodiments, the first ECC decoding operation uses Reed-Solomon codes, and mathematical operations (e.g., polynomials) used to encode the codeword may be used with one or more original bits and / or parity bits of the codeword to obtain the corrected bit.

[0047] At operation 230, the processing device determines whether the data decoding was successful. A decoding failure can occur when the data contains one or more errors on memory components 112A to 112N, where the errors cannot be corrected by the ECC decoding operation described at operation 220. That is, the processing device determines whether the data contains one or more errors that cannot be corrected by the ECC decoding operation. For example, applying ECC to data stored on memory components 112A to 112N may cause a decoding failure because the number of errors exceeds the maximum number of errors that can be corrected by applying ECC. The maximum number of errors may be the number of corresponding data on memory components 112A to 112N that cannot be reconstructed by the ECC decoding operation.

[0048] In some embodiments, the first ECC decoding operation uses Reed-Solomon codes, and the maximum number of errors that can be corrected is m symbols (e.g., 3 symbols of Reed-Solomon codes (72, 64, 8)). When the data contains errors on m symbols or less, the processing device determines that the data decoding is successful. When the data contains errors on more than m symbols, the processing device determines that the data decoding is unsuccessful.

[0049] If data decoding is successful, the processing device provides the decoded data at operation 235. The decoded data can be provided to the requester requesting data access (e.g., host system 120). If data decoding is unsuccessful, at operation 240, the processing device identifies the location where the error occurred. For example, the processing device identifies multiple locations of multiple errors, each of which corresponds to a specific error among multiple errors. That is, at operation 240, the processing device identifies the location of corresponding data stored on memory components 112A to 112N that cannot be decoded by the decoding at operation 220.

[0050] In some embodiments, at operation 240, the processing device can identify the location by performing mathematical operations and evaluating polynomials at certain locations (typically corresponding to the roots of the primitive polynomials used in the encoding). Methods such as the Berlekamp-Massey algorithm are used to construct the erroneous location polynomials based on a set of equations.

[0051] At operation 250, the processing device determines whether the location identified at operation 240 falls within a single memory component. That is, the processing device determines whether the location where the error occurred falls within a single memory component. For example, the processing device may assume the location where the error occurred falls within a single memory component, attempt to recover from the error, and obtain a non-recoverable response to confirm that the location where the error occurred falls within a single memory component.

[0052] At operation 255, in response to the determination that the location has fallen into a single memory component, the processing device determines that the error cannot be corrected and sends an error notification regarding the request to read the data.

[0053] At operation 260, in response to the determined location falling into a single memory component, the processing device marks the single memory component as faulty (e.g., temporarily erased). Marking a single memory component may result in excluding the single memory component from future memory allocations, avoiding future decoding of data stored on the single memory component, and / or sending an error message in response to receiving a request to access the single memory component.

[0054] At operation 260, the processing device performs a second ECC decoding operation to correct the data to produce corrected data, and at operation 270, sends the corrected data to the requester requesting access to the data (e.g., host system 120). In some embodiments, because the processing device knows the location of the error and marks a single memory component as faulty, the processing device may perform a second ECC operation (e.g., a redundancy operation) to correct the data. The redundancy operation may include performing logical operations on the data using information about the error location to reconstruct the data. The redundancy operation may include identifying decodable data stored in the memory component and applying logical operations (e.g., XOR) based on the identified data to reconstruct the corresponding data on the memory component that cannot be decoded. For example, if a data symbol stored in one of the memory components 112A to 112N contains an error, the processing device may perform a redundancy operation on error-free data symbols in the other memory components to reconstruct the data symbol with the error. The redundancy operation ensures that the error in the data symbol is removed by reconstructing the data symbol for the memory component containing the data symbol with the error.

[0055] use Figure 3 As illustrative examples of memory components 112A to 112N, Figure 3 This describes instance data symbols 301A, 301B, 301C, and 301D stored on memory component 112A. Each data symbol 301A to 301D may contain data stripes 310, 320, 330, 340, etc. Striping refers to dividing data into blocks of data written across each memory component 112A to 112N. In some embodiments, each data stripe 310 to 340 may represent a codeword encoded before being written to memory components 112A to 112N. Therefore, each data stripe 310 to 340 may contain the original data to be stored and additional parity data determined using error correction codes and added to the original data. Each data stripe 310 to 340 may contain any suitable amount of data. In some embodiments, data stripes 310 to 340 may be determined by host system 120 or read in any order requested by a user of host system 120. In some implementations, each data stripe 310 to 340 may correspond to an address or address range that references a location (e.g., bit 1, bit 2, etc.) of memory components 112A to 112N.

[0056] like Figure 3The processing device can receive a request to read data stripe 310 (e.g., operation 210). In some embodiments, the request specifies an address or address range corresponding to data stripe 310. The processing device can decode each data block 340A to 340N of data stripe 310 stored on memory components 112A to 112N (e.g., operation 220). Decoding of data stripe 310 can be attempted, but as illustrated, data blocks 340A and 340B of data stripe 310 may contain data with one or more errors (represented by X). The processing device can perform an error correction code decoding operation (e.g., a first ECC decoding operation) (e.g., operation 230) to remove errors from data blocks 340A and 340B. Once the errors in data blocks 340A and 340B have been removed, data stripe 310 can be decoded, and the processing device can determine that the decoding was successful. The processing device can send the decoded data stripe 310 to a requester (e.g., host system 120) that requests to read the data stripe 310.

[0057] like Figure 3 The processing device can further explain that it can receive a request to read data stripe 330 (e.g., operation 210). In some embodiments, the request specifies an address or address range corresponding to data stripe 330. The processing device can decode each data block 350A to 350N of data stripe 330 stored on memory components 112A to 112N (e.g., operation 220). Decoding of data stripe 330 can be attempted, but as explained, data blocks 350A, 350B, 350C, and 350D of data stripe 330 may contain data with one or more errors (represented by X). The processing device can perform an error correction code decoding operation (e.g., a first ECC decoding operation) (e.g., operation 230) but cannot remove the errors in data blocks 350A to 350D. For example, the error correction code decoding operation can be limited to removing three errors in data blocks 350A to 350D, and the processing device can determine that one or more errors in data blocks 350A to 350D cannot be corrected, and therefore determine that decoding is unsuccessful. The processing device can identify the location of the error in data blocks 350A to 350D (e.g., operation 250). The processing device can determine that the location of the error in data blocks 350A to 350D falls within memory component 112A (e.g., operation 250). If the location of the error in a data block (not shown) does not fall within memory component 112A, the processing device can send a notification indicating the error in the request to the requester of the requested data (e.g., host system 120).

[0058] Once the processing device determines that the erroneous location of data blocks 350A to 350D falls within memory component 112A, the processing device can mark data blocks 350A to 350D as erased, which means that each of data blocks 350A to 350D contains erroneous (or erased data), and mark memory component 112A (e.g., operation 260) as faulty, which means that memory component 112A is excluded from future decoding.

[0059] In some embodiments, the processing device may perform another error correction code decoding operation (e.g., a second ECC decoding operation) (e.g., operation 270) to generate a corrected data stripe 330. The processing device may send the corrected data stripe 330 to a requester (e.g., host system 120) that requests to read the data stripe 330.

[0060] Return to reference Figure 2 After performing one or more error-correcting decoding operations as described above (e.g., operations 220 to 280), memory component 112A (e.g., operation 260) is marked as faulty, meaning that memory component 112A is excluded from future decoding. At operation 290, the processing device may unmark a single memory component (e.g., Figure 3 (Memory component 112A). Unmarking a single memory component can result in including the single memory component for future memory allocation and / or enabling data stored on the single memory component for future decoding.

[0061] like Figure 3 As shown, memory component 112A contains a large number of error-free data blocks, such as data blocks in data stripes 320 and 340. Demarking memory component 112A allows these data blocks to be reused for decoding. In some embodiments, demarking a memory component means that memory component 112A is included for future decoding.

[0062] In some implementations, at operation 295, the processing device may mark an address or address range at a location identified at operation 240. Marking the address can indicate that data stored at addresses corresponding to marked and unmarked memory components contains one or more errors, and therefore, the address can be used to avoid future error correction operations for said address, such as avoiding operations 220, 230, 240, 250, and / or 270. For example, as... Figure 4 As shown, data symbols 401A, 401B, 401C, and 401D are stored on memory component 112A, data symbols 403A, 403B, 403C, and 403D are stored on memory component 112B, and data symbols 405A, 405B, 405C, and 405D are stored on memory component 112C.

[0063] Each of data block 410A (data symbol 401A), data block 410B (data symbol 401B), data block 410C (data symbol 401C), and data block 410D (data symbol 401D) contains one or more errors (represented by X). Data blocks 410A to 410D correspond to the address at location 420. The processing device may mark the address at location 420 of the memory component 112A. In some embodiments, the processing device may receive an access request containing the address at location 420 and may determine whether the address at location 420 has been marked. In response to determining that the address at location 420 has been marked, the processing device may avoid performing error detection and / or erase detection.

[0064] Each of data block 430A (data symbol 403A), data block 430B (data symbol 403B), data block 430C (data symbol 403C), and data block 430D (data symbol 403D) contains one or more errors (indicated by X). Data blocks 430A to 430D correspond to the address at location 440. The processing device may mark the address at location 440 of the memory component 112B. In some embodiments, the processing device may receive an access request containing the address at location 440 and may determine whether the address at location 440 has been marked. In response to determining that the address at location 440 has been marked, the processing device may avoid performing error detection and / or erase detection.

[0065] Each of data block 450A (data symbol 405A), data block 450B (data symbol 405B), data block 450C (data symbol 405C), and data block 450D (data symbol 405D) contains one or more errors (represented by X). Data blocks 450A to 450D correspond to the address at location 460. The processing device may mark the address at location 460 of the memory component 112C. In some embodiments, the processing device may receive an access request containing the address at location 460 and may determine whether the address at location 460 has been marked. In response to determining that the address at location 460 has been marked, the processing device may avoid performing error detection and / or erase detection.

[0066] like Figure 4 As shown, the processing device can mark the addresses of multiple locations (e.g., location 420 of memory component 112A, location 440 of memory component 112B, and location 460 of memory component 112C).

[0067] Figure 5 and 6This is a flowchart of example methods 500 and 600 for performing error correction code decoding operations with improved erase management on data stored on memory components 112A to 112N according to some embodiments. Methods 500 and 600 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, methods 500 and 600 are performed by… Figure 1 The erase manager 113 executes the process. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0068] At operation 510, the processing device may receive a request from a host system (e.g., host system 120) to read data stored on memory components 112A to 112N. The data may contain data stripes representing codewords encoded using error correction codes. In some embodiments, the error correction codes include Reed-Solomon codes. In some embodiments, operation 510 may be the same as or similar to operation 210.

[0069] At operation 520, the processing device may determine that the data contains multiple errors. In some embodiments, the processing device may use an error correction code to decode the codeword (e.g., a first ECC decoding operation) and determine that the multiple errors cannot be corrected by the first ECC decoding operation. In some examples, the data may contain one or more errors that prevent the corresponding data from being successfully decoded. In some embodiments, applying the error correction code to data stored on memory components 112A to 112N yields updated data containing at least one corrected bit. In some embodiments, applying the error correction code may involve applying mathematical operations to a portion or all of the data to derive the corrected bit. The corrected bit can be used to change the bit with the error. In some embodiments, the processing device may determine that the number of errors exceeds the maximum number of errors that can be corrected by the first ECC decoding operation. In some embodiments, the processing device may determine that the number of data blocks with one or more errors exceeds the maximum number of data that can be corrected by the first ECC decoding operation. In some embodiments, the processing device may determine that the number of symbols with one or more errors exceeds the maximum number of symbols that can be corrected by the first ECC decoding operation. In some embodiments, operation 520 may be the same as or similar to operations 220 and 230.

[0070] At operation 530, the processing device can identify multiple locations of multiple errors, each of which corresponds to a specific error among the multiple errors. In some embodiments, operation 530 may be the same as or similar to operation 240.

[0071] At operation 540, in response to determining that a plurality of locations fall within a single memory component among a plurality of memory components, the processing device may exclude the single memory component from future decoding and correct the data to produce corrected data. In some embodiments, an error correction code (ECC) decoding operation (e.g., a second ECC decoding operation) is used to perform the correction data to produce corrected data. The processing device performs a redundancy operation on data blocks to correct specific data blocks containing errors, wherein the redundancy operation may involve using parity data and data stored on memory components 112A to 112N to obtain updated data containing at least one corrected bit. In some embodiments, to perform the redundancy operation, the processing device may identify a subgroup of data blocks in memory components 112A to 112N that do not contain errors, and apply a logical operation (e.g., XOR) based on the subgroup of data blocks to reconstruct the data of other data blocks containing errors. As depicted, after performing the ECC decoding operation, the data is corrected and errors are removed at operation 540. In some embodiments, operation 540 may be the same as or similar to operations 250, 260, and 270.

[0072] At operation 550, the processing device may send corrected data to the host system. That is, it may read error-free data and provide it to the requester (e.g., host system 120). In some embodiments, operation 550 may be the same as or similar to operation 280.

[0073] At operation 560, the processing apparatus may include a single memory component for future decoding. The single memory component excluded from future decoding at operation 540 is now reused for future decoding. In some embodiments, operation 560 may be the same as or similar to operation 290.

[0074] refer to Figure 6 At operation 610, the processing device may receive a request from a host system (e.g., host system 120) to read data stored on memory components 112A to 112N. The data may contain data stripes representing codewords encoded using error correction codes. In some embodiments, the error correction codes include Reed-Solomon codes. In some embodiments, operation 610 may be the same as or similar to operation 210.

[0075] At operation 620, the processing device may determine that the data contains multiple errors. In some embodiments, the processing device may use an error correction code to decode the codeword (e.g., a first ECC decoding operation) and determine that the multiple errors cannot be corrected by the first ECC decoding operation. In some examples, the data may contain one or more errors that prevent the corresponding data from being successfully decoded. In some embodiments, applying the error correction code to data stored on memory components 112A to 112N yields updated data containing at least one corrected bit. In some embodiments, applying the error correction code may involve applying mathematical operations to a portion or all of the data to derive the corrected bit. The corrected bit can be used to change the bit with the error. In some embodiments, the processing device may determine that the number of errors exceeds the maximum number of errors that can be corrected by the first ECC decoding operation. In some embodiments, the processing device may determine that the number of data blocks with one or more errors exceeds the maximum number of data blocks that can be corrected by the first ECC decoding operation. In some embodiments, the processing device may determine that the number of symbols with one or more errors exceeds the maximum number of symbols that can be corrected by the first ECC decoding operation. In some embodiments, operation 620 may be the same as or similar to operations 220 and 230.

[0076] At operation 630, the processing device can identify multiple locations of multiple errors, each of which corresponds to a specific error among the multiple errors. In some embodiments, operation 630 may be the same as or similar to operation 240.

[0077] At operation 640, in response to determining that multiple locations are associated with a single memory component among multiple memory components, the processing device may correct data to produce corrected data. In some embodiments, an error correction code (ECC) decoding operation (e.g., a second ECC decoding operation) is used to perform the data correction to produce corrected data. The processing device performs a redundancy operation on data blocks to correct specific data blocks containing errors, wherein the redundancy operation may involve using parity data and data stored on memory components 112A to 112N to obtain updated data containing at least one corrected bit. In some embodiments, to perform the redundancy operation, the processing device may identify a subgroup of data blocks in memory components 112A to 112N that do not contain errors, and apply a logical operation (e.g., XOR) based on the subgroup of data blocks to reconstruct data for other data blocks containing errors. As depicted, after performing the ECC decoding operation, data is corrected and errors are removed at operation 640. In some embodiments, operation 640 may be the same as or similar to operations 250 and 270. In some embodiments, the processing device may avoid excluding a single memory component from future decoding. In some implementations, the processing device can avoid marking individual memory components as faulty.

[0078] At operation 650, the processing device may send corrected data to the host system. That is, it may read error-free data and provide it to the requester (e.g., host system 120). In some embodiments, operation 650 may be the same as or similar to operation 280.

[0079] At operation 660, the processing device may mark one or more addresses (e.g., addresses or address ranges) of multiple locations associated with a single memory component, wherein the marking is used to indicate error detection and / or erase detection at the multiple locations during future decoding, rather than performing conventionally used error correction operations. That is, the marked addresses are used to indicate that the data stored at the addresses contains one or more errors, and therefore, the addresses can be used to avoid future error correction operations for said addresses. In some embodiments, operation 560 may be the same as or similar to operation 295.

[0080] Figure 7 An example machine illustrating computer system 700 is described, within which a set of instructions is executable to cause said machine to perform any or more of the methods discussed herein. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110, or may be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (The operation of the erase manager 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0081] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by said machine. Furthermore, while describing a single machine, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0082] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data memory system 718, which communicate with each other via a bus 730.

[0083] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication via network 720.

[0084] The data storage system 718 may include a machine-readable storage medium 724 (also referred to as computer-readable medium) thereon storing one or more sets of instructions 726 or software embodying any or more of the methodologies or functions described herein. The instructions 726 may also reside wholly or at least partially within the main memory 704 and / or the processing device 702 during execution by the computer system 700, which also constitute machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0085] In one embodiment, instruction 726 includes implementation corresponding to a management component (e.g., Figure 1 The erase manager 113) provides functional instructions. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0086] Certain portions of the foregoing detailed description have been presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. Here and generally, an algorithm is considered a self-consistent sequence of operations that leads to a desired result. These operations are those that require physical manipulation of physical quantities. Usually, but not necessarily, these quantities are in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, and sometimes, for customary use, these signals are referred to in principle as bits, values, elements, symbols, characters, items, numbers, or the like.

[0087] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0088] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0089] The algorithms and displays presented herein are not inherently associated with any particular computer or other device. Various general-purpose systems can be used in conjunction with programs taught herein, or, as may prove convenient, more specialized devices can be constructed to execute the methods. The structures for various such systems will appear as described below. Furthermore, this disclosure is not described with reference to any particular programming language. It will be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0090] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0091] In the foregoing description, embodiments thereof have been described with reference to specific examples of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. Therefore, the description and drawings should be regarded in an illustrative rather than restrictive sense.

Claims

1. A system comprising: Multiple memory components; and A processing device operatively coupled to the plurality of memory components, the processing device being configured to perform operations including: Receive a request from the host system to read data stored on the plurality of memory components; It was determined that the data contained multiple errors; Identify multiple locations of the plurality of errors, wherein each of the plurality of locations corresponds to a corresponding error among the plurality of errors; In response to determining that the plurality of locations fall in a single memory component among the plurality of memory components, the single memory component is excluded from future decoding and the data is corrected to produce corrected data; Send the corrected data to the host system; and The single memory component is included for future decoding.

2. The system according to claim 1, wherein the operation further comprises: The addresses of the plurality of locations of the single memory component are marked; In response to receiving a second request specifying the address, determine whether the address has been marked; and In response to determining that the address is marked, it is determined that a set of known locations corresponding to the address contains one or more errors.

3. The system of claim 2, wherein the request specifies the address.

4. The system of claim 1, wherein determining that the data contains the plurality of errors further comprises: The data is decoded using an error correction code (ECC) decoding operation. and It was determined that the aforementioned errors could not be corrected by the error correction code (ECC) decoding operation.

5. The system of claim 4, wherein determining that the plurality of errors cannot be corrected by the error correction code (ECC) decoding operation further comprises: Determine whether the number of the plurality of errors exceeds the maximum number of errors that can be corrected by the error correction code (ECC) decoding operation.

6. The system of claim 1, wherein an error correction code (ECC) decoding operation is used to perform the correction of the data to produce the corrected data.

7. The system of claim 1, wherein the data comprises a plurality of symbols, and each of the plurality of symbols contains a corresponding error among the plurality of errors.

8. The system of claim 1, wherein each of the plurality of memory components is a die.

9. A method comprising: The processing unit receives a request from the host system to read data stored on multiple memory components; It was determined that the data contained multiple errors; Identify multiple locations of the plurality of errors, wherein each of the plurality of locations corresponds to a corresponding error among the plurality of errors; In response to determining that the plurality of locations are associated with a single memory component among the plurality of memory components, the data is corrected to produce corrected data; The calibrated data is sent to the host system; and The addresses of the plurality of locations associated with the single memory component are marked, wherein the marks are used to indicate that an error was detected at the plurality of locations in future decoding.

10. The method of claim 9, further comprising: In response to receiving a second request specifying the address, determine whether the address has been marked; and In response to determining that the address is marked, it is determined that a set of known locations corresponding to the address contains one or more errors.

11. The method of claim 9, wherein the request specifies the address.

12. The method of claim 9, wherein determining that the data contains the plurality of errors further comprises: The data is decoded using an error correction code (ECC) decoding operation. and It was determined that the aforementioned errors could not be corrected by the error correction code (ECC) decoding operation.

13. The method of claim 12, wherein determining that the plurality of errors cannot be corrected by the error correction code (ECC) decoding operation further comprises: Determine whether the number of the plurality of errors exceeds the maximum number of errors that can be corrected by the error correction code (ECC) decoding operation.

14. The method of claim 9, wherein an error correction code (ECC) decoding operation is used to perform correction of the data to produce the corrected data.

15. The method of claim 9, wherein the data comprises a plurality of symbols, and each of the plurality of symbols contains a corresponding error among the plurality of errors.

16. The method of claim 9, wherein each of the plurality of memory components is a die.

17. A non-transitory computer-readable storage medium comprising, when executed by a processing means, instructions that cause the processing means to perform operations including: Receive a request from the host system to read data stored on multiple memory components; It was determined that the data contained multiple errors; Identify multiple locations of the plurality of errors, wherein each of the plurality of locations corresponds to a corresponding error among the plurality of errors; In response to determining that the plurality of locations fall in a single memory component among the plurality of memory components, the single memory component is excluded from future decoding and the data is corrected to produce corrected data; Send the corrected data to the host system; and The single memory component is included for future decoding.

18. The non-transitory computer-readable storage medium of claim 17, wherein the operation further comprises: The addresses of the plurality of locations of the single memory component are marked; In response to receiving a second request specifying the address, determine whether the address has been marked; and In response to determining that the address is marked, it is determined that a set of known locations corresponding to the address contains one or more errors.

19. The non-transitory computer-readable storage medium of claim 18, wherein the request specifies the address.

20. The non-transitory computer-readable storage medium of claim 17, wherein determining that the data contains the plurality of errors further comprises: The data is decoded using an error correction code (ECC) decoding operation. and It was determined that the aforementioned errors could not be corrected by the error correction code (ECC) decoding operation.

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