Formation method of semiconductor structure
By forming an anti-adhesion layer and selectively depositing a wetting barrier layer in a semiconductor structure, the resistance and RC delay problems of metal interconnect structures are solved, and higher electrical performance is achieved.
Patent Information
- Application Number
- CN202410573351.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-09
- Publication Date
- 2025-11-11
AI Technical Summary
The yield and performance of existing metal interconnect structures need to be improved, especially the RC delay problem caused by the reduced linewidth of the metal interconnect structure in the later process.
During the formation of the semiconductor structure, an anti-adhesion layer is formed at the bottom of the opening, a wetting barrier layer is selectively deposited, and a second interconnect structure is formed in the opening after the anti-adhesion layer is removed, so that the second interconnect structure is in direct contact with the first interconnect structure, thereby reducing the RC delay caused by resistance and capacitance.
By using a direct-contact interconnect structure design, the RC delay caused by the resistance and capacitance of the semiconductor structure is reduced, thereby improving the electrical performance of the semiconductor structure.
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Figure CN120933233A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] In recent years, with the development of integrated circuit technology, the integration level of integrated circuits and semiconductor technology have made great progress. In semiconductor manufacturing processes, as the size of integrated circuits continues to shrink, the linewidth of the metal interconnect structure in the back-end of line (BEOL) process is also continuously decreasing.
[0003] The formation of metal interconnect structures in the back-end process typically includes the formation of via structures and metal lines, but the yield and performance of metal interconnect structures currently need to be improved. Summary of the Invention
[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is beneficial to further improve the performance of the semiconductor structure.
[0005] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate structure in which a first interconnect structure is formed, the substrate structure exposing the top of the first interconnect structure; forming a first dielectric layer on the substrate structure, the first dielectric layer having an opening exposing the top of the first interconnect structure; forming an anti-adhesion layer at the bottom of the opening, the anti-adhesion layer exposing the sidewall of the opening; after forming the anti-adhesion layer, selectively depositing a wetting barrier layer on the sidewall of the opening; after forming the wetting barrier layer, removing the anti-adhesion layer to expose the first interconnect structure at the bottom of the opening; and after removing the anti-adhesion layer, forming a second interconnect structure in the opening, the second interconnect structure being in direct contact with the corresponding first interconnect structure.
[0006] Optionally, the step of forming the wetting barrier layer includes: selectively depositing a barrier layer on the sidewall of the opening, wherein the barrier layer exposes the bottom of the opening; and selectively depositing an wetting layer on the sidewall of the barrier layer, wherein the wetting layer exposes the bottom of the opening.
[0007] Optionally, the material of the barrier layer includes a low-k dielectric material.
[0008] Optionally, the low-k dielectric material includes one or both of SiCN and SiCO.
[0009] Optionally, the wetting layer includes one or more of the following: a cobalt layer, a ruthenium layer, a ruthenium-doped cobalt layer, and a cobalt-doped ruthenium layer.
[0010] Optionally, the process for selectively depositing a wetting barrier layer on the sidewall of the opening includes chemical vapor deposition or atomic layer deposition.
[0011] Optionally, forming an anti-adhesion layer at the bottom of the opening includes selectively adsorbing an anti-adhesion layer at the bottom of the opening, the anti-adhesion layer being made of a material having polar and non-polar groups, the polar groups being bonded to a first interconnect structure surface at the bottom of the opening, and the non-polar groups being used to provide an anti-adhesion surface for the anti-adhesion layer.
[0012] Optionally, the process for selectively depositing the anti-adhesion layer includes chemical vapor deposition.
[0013] Optionally, the process parameters for chemical vapor deposition include: a process temperature of 100°C to 400°C; a process pressure of 0.1 Torr to 100 Torr; a precursor used including one or more of benzotriazolyl thiols, propylene, butyne, and decane; and a carrier gas including one or more of argon, nitrogen, and helium.
[0014] Optionally, in the step of forming an anti-adhesion layer at the bottom of the opening, the material of the anti-adhesion layer includes one or more of benzotriazolyl thiol, propylene, butyne, and decane.
[0015] Optionally, in the step of forming an anti-adhesion layer at the bottom of the opening, the thickness of the anti-adhesion layer is 0.5 nm to 5 nm.
[0016] Optionally, before forming the first dielectric layer on the substrate structure, the method for forming the semiconductor structure further includes: forming a stop layer on top of the substrate structure and the first interconnect structure; in the step of forming the first dielectric layer on the substrate structure, an opening is formed in the first dielectric layer that penetrates the stop layer and exposes the top of the first interconnect structure; in the step of forming an anti-adhesion layer at the bottom of the opening, the top of the anti-adhesion layer is lower than or flush with the top of the stop layer.
[0017] Optionally, the step of forming the second interconnect structure includes: forming a seed layer on the sidewall of the wetting barrier layer and on top of the first interconnect structure; filling the seed layer with interconnect material, wherein the filling method includes: reflowing the seed layer to form interconnect material, or electroplating interconnect material on the seed layer.
[0018] Optionally, the step of forming the second interconnect structure includes repeatedly alternating the step of forming the seed layer and the step of filling the interconnect material, and employing a reflow treatment of the seed layer to form the interconnect material; or, the step of forming the second interconnect structure includes repeatedly alternating the step of forming the seed layer and the step of filling the interconnect material, and employing a reflow treatment of the seed layer to form the interconnect material before the last formation of the seed layer, and electroplating the interconnect material on the seed layer after the last formation of the seed layer.
[0019] Optionally, the process for forming the seed layer includes physical vapor deposition.
[0020] Optionally, the process for removing the anti-adhesion layer includes a plasma treatment process.
[0021] Optionally, the gas used in the plasma treatment process includes one or both of hydrogen and argon.
[0022] Optionally, the parameters of the plasma treatment process include: the treatment gas comprising a mixture of hydrogen and argon; the volume ratio of hydrogen to argon being 1% to 90%; and the process time being 2 to 200 seconds; or, the parameters of the plasma treatment process include: the treatment gas being hydrogen; the flow rate of the hydrogen being 50 standard milliliters per minute to 5000 standard milliliters per minute; and the process time being 2 to 200 seconds; or, the parameters of the plasma treatment process include: the treatment gas being argon; the flow rate of the argon being 50 standard milliliters per minute to 5000 standard milliliters per minute; and the process time being 2 to 200 seconds.
[0023] Optionally, the step of providing the substrate structure includes: providing a substrate and a second dielectric layer located on the substrate, wherein a first interconnect structure is formed in the second dielectric layer.
[0024] Optionally, in the step of forming the first dielectric layer on the substrate structure, the opening includes an interconnect trench and a through hole communicating with the bottom of the interconnect trench.
[0025] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0026] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate structure in which a first interconnect structure is formed, the substrate structure exposing the top of the first interconnect structure; forming a first dielectric layer on the substrate structure, the first dielectric layer having an opening exposing the top of the first interconnect structure; forming an anti-adhesion layer at the bottom of the opening, the anti-adhesion layer exposing the sidewall of the opening; after forming the anti-adhesion layer, selectively depositing a wetting barrier layer on the sidewall of the opening; after forming the wetting barrier layer, removing the anti-adhesion layer to expose the first interconnect structure at the bottom of the opening; and after removing the anti-adhesion layer, forming a second interconnect structure in the opening, the second interconnect structure being in direct contact with the corresponding first interconnect structure. In this embodiment of the invention, since an anti-adhesion layer is formed at the bottom of the opening, and the side of the anti-adhesion layer facing away from the bottom of the opening has anti-adhesion properties, the wetting barrier layer is formed only on the sidewall of the opening. Subsequently, the anti-adhesion layer is removed, exposing the first interconnect structure at the bottom of the opening. Then, a second interconnect structure is formed in the opening. Therefore, the second interconnect structure is in direct contact with the corresponding first interconnect structure, thereby reducing the resistance of the second interconnect structure and improving the RC delay caused by resistance and capacitance in the semiconductor structure, thereby improving the electrical performance of the semiconductor structure.
[0027] In an optional embodiment, forming an anti-adhesion layer at the bottom of the opening includes: selectively adsorbing an anti-adhesion layer at the bottom of the opening, wherein the material of the anti-adhesion layer has polar and non-polar groups, the polar groups are bonded to the surface of a first interconnect structure at the bottom of the opening, and the non-polar groups provide an anti-adhesion surface for the anti-adhesion layer; wherein the material of the anti-adhesion layer contains electron-deficient polar groups and stable non-polar groups, wherein the electron-deficient polar groups readily bond with metal atoms, while the stable non-polar groups do not readily bond with atoms of other materials, therefore, the electron-deficient... Polar groups readily bond with atoms at the top of the first interconnect layer, meaning they adsorb onto the top of the first interconnect structure but not onto the dielectric layer. Therefore, an anti-adhesion layer can be formed directly at the bottom of the opening using selective deposition, allowing the electron-deficient polar groups in the anti-adhesion layer to bond with atoms of the first interconnect structure. Simultaneously, stable non-polar groups in the anti-adhesion layer are located on the top surface of the anti-adhesion layer, meaning the surface of the anti-adhesion layer facing away from the first interconnect structure has anti-adhesion properties. Consequently, during the subsequent formation of the wetting barrier layer, the wetting barrier layer is deposited only on the sidewalls of the dielectric layer and not on the top of the first interconnect structure. Attached Figure Description
[0028] Figures 1 to 4 A schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure;
[0029] Figures 5 to 14 This is a schematic diagram of the structure corresponding to each step in the embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0030] Currently, the performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using an example of a semiconductor structure and its formation method. Figures 1 to 4 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0031] refer to Figure 1 A substrate structure 10 is provided, in which a first interconnect structure 11 is formed, the top of the first interconnect structure 11 is exposed, and a second dielectric layer 14 is formed on the substrate structure 10.
[0032] Specifically, the step of providing the substrate structure 10 includes: providing a substrate (not shown) and a first dielectric layer 13 located on the substrate, wherein a first interconnect structure 11 is formed in the first dielectric layer 13.
[0033] refer to Figure 2 The second dielectric layer 14 is graphically formed to create an opening 15 that exposes the top of the first interconnect structure 11.
[0034] refer to Figure 3 A barrier layer 16 is formed on the sidewalls and bottom of the opening 15.
[0035] Continue to refer to Figure 3 A conformal covering wetting layer 17 is formed on the barrier layer 16.
[0036] refer to Figure 4 After the wetting layer 17 is formed, a second interconnect structure 18 is formed in the opening 15.
[0037] Research has found that, for example Figure 4 As shown, the barrier layer 16 and the wetting layer 17 are located between the bottom of the second interconnect structure 18 and the top of the first interconnect structure 11. Therefore, the second interconnect structure 18 and the first interconnect structure 11 are not in direct contact, thereby increasing the contact resistance between the second interconnect structure 18 and the first interconnect structure 11, which in turn increases the RC delay caused by resistance and capacitance in the semiconductor structure, and thus reduces the electrical performance of the semiconductor structure.
[0038] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate structure in which a first interconnect structure is formed, the substrate structure exposing the top of the first interconnect structure; forming a first dielectric layer on the substrate structure, the first dielectric layer having an opening exposing the top of the first interconnect structure; forming an anti-adhesion layer at the bottom of the opening, the anti-adhesion layer exposing the sidewall of the opening; after forming the anti-adhesion layer, selectively depositing a wetting barrier layer on the sidewall of the opening; after forming the wetting barrier layer, removing the anti-adhesion layer to expose the first interconnect structure at the bottom of the opening; and after removing the anti-adhesion layer, forming a second interconnect structure in the opening, the second interconnect structure being in direct contact with the corresponding first interconnect structure.
[0039] In the solution disclosed in the embodiments of the present invention, since an anti-adhesion layer is formed at the bottom of the opening, and the side of the anti-adhesion layer facing away from the bottom of the opening has anti-adhesion properties, the wetting barrier layer is only formed on the sidewall of the opening. After the anti-adhesion layer is removed, the first interconnect structure at the bottom of the opening is exposed, and then a second interconnect structure is formed in the opening. Therefore, the second interconnect structure is in direct contact with the corresponding first interconnect structure, thereby reducing the resistance of the second interconnect structure and correspondingly improving the RC delay caused by resistance and capacitance in the semiconductor structure, thereby improving the electrical performance of the semiconductor structure.
[0040] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0041] Figures 5 to 14 This is a schematic diagram of the structure corresponding to each step in the embodiment of the semiconductor structure formation method of the present invention.
[0042] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.
[0043] refer to Figure 5 A substrate structure 100 is provided, wherein a first interconnect structure 101 is formed in the substrate structure 100, and the top of the first interconnect structure 101 is exposed.
[0044] The substrate structure 100 provides a process platform for forming semiconductor structures. Depending on the actual process, the substrate structure 100 includes a substrate and functional structures formed on the substrate, such as semiconductor devices like MOS field-effect transistors and resistor structures.
[0045] In this embodiment, the step of providing the substrate structure 100 includes: providing a substrate (not shown) and a second dielectric layer 102 located on the substrate, wherein a first interconnect structure 101 is formed in the second dielectric layer 102.
[0046] As an example, the substrate is a silicon substrate. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, or other types of substrates such as silicon-on-insulator or germanium-on-insulator.
[0047] The second dielectric layer 102 is used to achieve electrical isolation between adjacent first interconnect structures 101.
[0048] In this embodiment, the material of the second dielectric layer 102 is an insulating material, including one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN and SiON.
[0049] The first interconnect structure 101 is used to achieve electrical connection with the subsequently formed second interconnect structure.
[0050] In this embodiment, the first interconnect structure 101 is made of copper. Copper has low resistivity, which helps reduce the RC delay of the device, and copper also has excellent electromigration resistance. In other embodiments, depending on actual process requirements, the first interconnect structure can also be made of metals such as aluminum or tungsten.
[0051] refer to Figure 6 and in conjunction with references Figure 5 A first dielectric layer 104 is formed on the substrate structure 100, and an opening 110 is formed in the first dielectric layer 104 to expose the top of the first interconnect structure 101.
[0052] The first dielectric layer 104 is used to provide a process operation platform for the subsequent formation of the second interconnect structure, and also to ensure that adjacent second interconnect structures are mutually insulated.
[0053] In this embodiment, the material of the first dielectric layer 104 is an insulating material, including one or more of SiOC, SiOCH, SiC, SiCN, SiO2, SiN and SiON.
[0054] The opening 110 is used to provide space for the subsequent formation of a second interconnect structure.
[0055] It should be noted that, before forming the first dielectric layer 104 on the substrate structure 100, the method for forming the semiconductor structure further includes forming a stop layer 120 on top of the substrate structure 100 and the first interconnect structure 101.
[0056] The top surface of the stop layer 120 is used to define the etching stop position for etching the first dielectric layer 104.
[0057] In this embodiment, the material of the stop layer 120 includes one or more of Al2O3, AlN, HfO2, Ta2O5, SiO2, SiN, SiOC, SiON, SiC and SiCN.
[0058] It should also be noted that, in the step of forming the first dielectric layer 104 on the substrate structure 100, the first dielectric layer 104 has an opening 110 that penetrates the stop layer 120 and exposes the top of the first interconnect structure 101, so as to reduce the difficulty of electrically connecting the subsequently formed second interconnect structure to the first interconnect structure 101.
[0059] In this embodiment, the opening 110 is an opening of a dual damascene structure. Therefore, in the step of forming the first dielectric layer 104 on the substrate structure 100, the opening 110 includes an interconnect groove (not shown) and a through hole (not shown) communicating with the bottom of the interconnect groove.
[0060] Interconnect slots are used to provide space for the subsequent formation of interconnect layers.
[0061] Through holes are used to provide space for the subsequent formation of through-hole interconnect structures.
[0062] It should be noted that when the opening 110 is a double damask structure, the opening 110 can be formed in a variety of ways, such as all-in-one etching (AIO etch), via-first, or trench-first.
[0063] It should also be noted that, depending on the actual situation, in other embodiments, the opening may also be an opening of a single damascene structure.
[0064] Furthermore, the opening 110 can have a variety of different top line widths to meet different design requirements. Specifically, the interconnecting slot can have a variety of different line widths.
[0065] As an example, the opening 110 may include a first type of opening (not shown) and a second type of opening (not shown), wherein the top line width of the first type of opening is greater than the top line width of the second type of opening.
[0066] It should be noted that, prior to forming the opening 110, a hard mask layer (not shown) may be formed on the first dielectric layer 104. The patterned hard mask layer is used as a mask for forming interconnect trenches.
[0067] As an example, the material of the hard mask layer includes one or more of TiN, WC, Al2O3, SiN, SiON, and SiOC.
[0068] refer to Figure 7 An anti-adhesion layer 105 is formed at the bottom of the opening 110, and the anti-adhesion layer 105 exposes the sidewall of the opening 110.
[0069] The anti-adhesion layer 105 is used to prevent the subsequent formation of the wetting barrier layer from depositing on top of the first interconnect structure 101.
[0070] Specifically, an anti-adhesion layer 105 is formed at the bottom of the opening 110. The side of the anti-adhesion layer 105 facing away from the bottom of the opening 110 has anti-adhesion properties, so that the wetting barrier layer is only formed on the sidewall of the opening 110. After the anti-adhesion layer 105 is removed, the first interconnect structure 101 at the bottom of the opening 110 is exposed. Then, a second interconnect structure is formed in the opening 110. Therefore, the second interconnect structure is in direct contact with the corresponding first interconnect structure 101. The wetting barrier layer at the bottom of the second interconnect structure is removed, thereby reducing the resistance of the second interconnect structure. This improves the RC delay caused by resistance and capacitance in the semiconductor structure, thereby improving the electrical performance of the semiconductor structure.
[0071] In this embodiment, the method of forming an anti-adhesion layer 105 at the bottom of the opening 110 includes: selectively adsorbing the anti-adhesion layer 105 at the bottom of the opening 110, wherein the material of the anti-adhesion layer 105 has polar groups and non-polar groups, wherein the polar groups are bonded to the surface of the first interconnect structure 101 at the bottom of the opening 110, and the non-polar groups are used to provide an anti-adhesion surface for the anti-adhesion layer 105.
[0072] It should be noted that the material of the anti-adhesion layer 105 contains electron-deficient polar groups and stable non-polar groups. The electron-deficient polar groups are easy to bond with metal atoms, while the stable non-polar groups are not easy to bond with atoms of other materials. Therefore, the electron-deficient polar groups in the anti-adhesion layer 105 are easy to bond with the atoms on the top of the first interconnect structure 101, that is, adsorbed to the top of the first interconnect structure 101 and not adsorbed to the dielectric layer. Therefore, the anti-adhesion layer 105 can be formed directly at the bottom of the opening 110 by selective deposition, so that the electron-deficient polar groups in the anti-adhesion layer 105 bond with the atoms of the first interconnect structure 101. This not only simplifies the process flow, but also minimizes the loss to the sidewalls and bottom of the opening 110.
[0073] Meanwhile, the stable non-polar groups in the anti-adhesion layer 105 are located on the top surface of the anti-adhesion layer 105, that is, the surface of the anti-adhesion layer 105 facing away from the first interconnect structure 101 has anti-adhesion properties. As a result, during the subsequent formation of the wetting barrier layer, the wetting barrier layer is only deposited on the sidewall of the dielectric layer and not on the top of the first interconnect structure 101.
[0074] In this embodiment, in the step of forming an anti-adhesion layer 105 at the bottom of the opening 110, the material of the anti-adhesion layer 105 includes one or more of benzotriazolyl thiol, propylene, butyne and decane.
[0075] Specifically, benzotriazolylthiol, propylene, butyne, and decane all contain electron-deficient polar groups and stable nonpolar groups. The electron-deficient polar groups readily bond with the atoms at the top of the first interconnect structure 101, meaning the material layer can be adsorbed onto the top of the first interconnect structure 101. The stable nonpolar groups do not readily bond with atoms of other materials, so the material layer will not adsorb onto the dielectric layer. Furthermore, the stable nonpolar groups are located on the top surface of the material layer, meaning the surface of the material layer facing away from the first interconnect structure 101 has anti-adhesion properties. As a result, during the subsequent formation of the wetting barrier layer, the wetting barrier layer is deposited only on the sidewalls of the dielectric layer and not on the top of the first interconnect structure 101.
[0076] In this embodiment, the process for selectively depositing the anti-adhesion layer 105 includes a chemical vapor deposition process.
[0077] Chemical vapor deposition (CVD) has a better deposition effect, which can increase the probability that the anti-adhesion layer 105 is adsorbed onto the top of the first interconnect structure 101, that is, increase the area of the anti-adhesion layer 105 covering the top of the first interconnect structure 101. This improves the effect that in the subsequent formation of the wetting barrier layer, the wetting barrier layer is only deposited on the sidewall of the dielectric layer and not on the top of the first interconnect structure 101.
[0078] In this embodiment, the process parameters for chemical vapor deposition include: a process temperature of 100°C to 400°C; a process pressure of 0.1 Torr to 100 Torr; a precursor used including one or more of benzotriazolyl thiols, propylene, butyne, and decane; and a carrier gas including one or more of argon, nitrogen, and helium.
[0079] Specifically, the precursor for the chemical vapor deposition process is one or more of benzotriazolyl thiol, propylene, butyne, and decane. These precursors all contain both electron-deficient polar groups and stable nonpolar groups. The electron-deficient polar groups readily bond with atoms at the top of the first interconnect structure 101, meaning the precursor can adsorb onto the top of the first interconnect structure 101 to form an anti-adhesion layer 105. The stable nonpolar groups do not readily bond with atoms of other materials, thus preventing the precursor from adsorbing onto the dielectric layer. Furthermore, the stable nonpolar groups are located on the top surface of the formed anti-adhesion layer 105, meaning the surface of the anti-adhesion layer 105 facing away from the first interconnect structure 101 has anti-adhesion properties. Therefore, during the subsequent formation of the wetting barrier layer, the wetting barrier layer is deposited only on the sidewalls of the dielectric layer and not on the top of the first interconnect structure 101. The carrier gas used is one or more of argon, nitrogen, and helium, and the precursor enters the reaction chamber through the carrier gas.
[0080] The process temperature for chemical vapor deposition should not be too low or too high. If the process temperature is too low, it will be more difficult for the polar groups in the precursor to dissociate, thereby weakening the stability of the anti-adhesion layer 105 formed by the bonding between the polar groups in the precursor and the atoms at the top of the first interconnect structure 101. If the process temperature is too high, it will be more likely to increase the dissociation ability of the non-polar groups in the precursor, thereby reducing the stability of the non-polar groups in the precursor, and thus weakening the anti-adhesion of the formed anti-adhesion layer 105. Therefore, in this embodiment, the process temperature is 100 degrees Celsius to 400 degrees Celsius.
[0081] The process pressure for chemical vapor deposition should not be too high or too low. If the process pressure is too high, it can easily cause additional particle defects in the gas phase reaction within the cavity; if the process pressure is too low, it can easily result in poor performance in improving the uniformity of precursor adsorption on the substrate. Therefore, in this embodiment, the process pressure is between 0.1 Torr and 100 Torr.
[0082] By setting the process temperature and pressure of chemical vapor deposition within a reasonable range and coordinating them with each other, the deposition rate and process stability can be improved while reducing process costs and minimizing side effects.
[0083] In this embodiment, during the step of forming the anti-adhesion layer 105 at the bottom of the opening 110, the thickness of the anti-adhesion layer 105 should not be too large or too small. If the thickness of the anti-adhesion layer 105 is too large, it is easy to cause an increase in the internal stress of the anti-adhesion layer 105, thereby causing problems such as cracks or defects in the anti-adhesion layer 105; if the thickness of the anti-adhesion layer 105 is too small, it is easy to cause uneven coverage of the first interconnect structure 101 by the anti-adhesion layer 105, thereby resulting in poor anti-adhesion performance of the surface of the anti-adhesion layer 105 facing away from the first interconnect structure 101. Therefore, in this embodiment, during the step of forming the anti-adhesion layer 105 at the bottom of the opening 110, the thickness of the anti-adhesion layer 105 is 0.5 nm to 5 nm.
[0084] In this embodiment, in the step of forming an anti-adhesion layer 105 at the bottom of the opening 110, the top of the anti-adhesion layer 105 is lower than or flush with the top of the stop layer 120.
[0085] It should be noted that the top of the anti-adhesion layer 105 is lower than or flush with the top of the stop layer 120, thereby ensuring that the formed wetting barrier layer completely covers the sidewall of the first dielectric layer 104, and thus prevents metal ions in the subsequently formed second interconnect structure from diffusing into the first dielectric layer 104.
[0086] refer to Figures 8 to 9 After forming the anti-adhesion layer 105, a wetting barrier layer 106 is selectively deposited on the sidewall of the opening 110.
[0087] It should be noted that, since the wetting barrier layer 106 in this embodiment is located on the sidewall of the opening 110, and a second interconnect structure is subsequently formed in the opening 110, that is, the wetting barrier layer 106 is located between the sidewall of the second interconnect structure and the first dielectric layer 104, exposing the top of the first interconnect structure 101, and the bottom of the second interconnect structure is in contact with the corresponding top of the first interconnect structure 101, there is no wetting barrier layer 106 at the bottom of the second interconnect structure, thereby reducing the contact resistance between the second interconnect structure and the first interconnect structure 101, correspondingly improving the RC delay caused by resistance and capacitance in the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.
[0088] It should be noted that since the wetting barrier layer 106 can be selectively deposited on the surface of the first dielectric layer 104, the step of removing the wetting barrier layer 106 at the bottom of the opening 110 can be omitted, thereby avoiding damage to the first interconnect structure 101 or the wetting barrier layer 106 located on the sidewall of the opening 110 caused by the step of removing the wetting barrier layer 106 at the bottom of the opening 110.
[0089] Specifically, the steps for forming the wetting barrier layer 106 include: (Refer to...) Figure 8 A barrier layer 107 is selectively deposited on the sidewall of the opening 110, and the barrier layer 107 exposes the bottom of the opening 110; Reference Figure 9 A wetting layer 108 is selectively deposited on the sidewall of the barrier layer 107, and the wetting layer 108 exposes the bottom of the opening 110.
[0090] In this embodiment, the fact that the barrier layer 107 exposes the bottom of the opening 110 and the wetting layer 108 exposes the bottom of the opening 110 both mean that the barrier layer 107 and the wetting layer 108 expose the top of the anti-adhesion layer 105.
[0091] The barrier layer 107 serves to block the diffusion of metal ions in the subsequently formed second interconnect structure.
[0092] In this embodiment, the barrier layer 107 is made of a low-k dielectric material, which can effectively reduce the parasitic capacitance between interconnect structures and thus reduce the RC delay of the device. At the same time, the low-k dielectric material can also play a good role in blocking ion diffusion.
[0093] As an example, the low-k dielectric material includes one or both of SiCN and SiCO.
[0094] Specifically, SiC and SiCO can effectively block ion diffusion, and the process of forming the barrier layer 107 using these materials is simple and has low cost.
[0095] The wetting layer 108 is used to improve the adhesion between the barrier layer 107 and the subsequently formed second interconnect structure.
[0096] In this embodiment, the wetting layer 108 includes one or more of the following: a cobalt layer, a ruthenium layer, a ruthenium-doped cobalt layer, and a cobalt-doped ruthenium layer.
[0097] Specifically, the cobalt layer, ruthenium layer, ruthenium-doped cobalt layer, and cobalt-doped ruthenium layer all have low resistivity, which is beneficial to reducing the resistance of the subsequently formed interconnect structure and improving the performance of the semiconductor structure. At the same time, the cobalt layer, ruthenium layer, ruthenium-doped cobalt layer, and cobalt-doped ruthenium layer all have good wettability, which is beneficial to forming a uniform and pore-free interconnect structure and improving the quality of the interconnect structure.
[0098] In this embodiment, the process of selectively depositing the wetting barrier layer 106 on the sidewall of the opening 110 includes chemical vapor deposition or atomic layer deposition.
[0099] Specifically, both chemical vapor deposition and atomic layer deposition processes have good selective deposition effects, which allows the wetting barrier layer 106 to be deposited better on the sidewall of the opening 110.
[0100] refer to Figure 10 After the wetting barrier layer 106 is formed, the anti-adhesion layer 105 is removed, exposing the first interconnect structure 101 at the bottom of the opening 110.
[0101] This exposes the first interconnect structure 101 at the bottom of the opening 110 so that the subsequently formed second interconnect structure can directly contact the first interconnect structure 101.
[0102] In this embodiment, the process for removing the anti-adhesion layer 105 includes a plasma treatment process.
[0103] Specifically, the plasma treatment process has good selectivity. By adjusting the process parameters of the plasma treatment process, the anti-adhesion layer 105 can be selectively removed, thereby avoiding damage to the first interconnect structure 101 or the wetting barrier layer 106 located on the sidewall of the opening 110 caused by the step of removing the anti-adhesion layer 105.
[0104] In this embodiment, the gas used in the plasma treatment process includes one or both of hydrogen and argon.
[0105] The hydrogen gas in the plasma treatment process has high chemical activity and can effectively react with the polar groups in the anti-adhesion layer 105, thereby removing the anti-adhesion layer 105.
[0106] Argon gas in the plasma treatment process is an inert gas. The plasma generated by it mainly removes the anti-adhesion layer 105 by bombarding it with ions. It does not react chemically with other film layers (e.g., the first interconnect structure 101) and avoids the introduction of impurities.
[0107] Specifically, the gas used in the plasma treatment process can be selected based on the actual process requirements.
[0108] In this embodiment, the parameters of the plasma treatment process include: the treatment gas is a mixture of hydrogen and argon; the volume ratio of hydrogen to argon is 1% to 90%; and the process time is 2 seconds to 200 seconds.
[0109] It should be noted that the volume ratio of hydrogen to argon in the plasma processing process should not be too high or too low. If the volume ratio is too high, it can lead to difficulties in storing and processing the hydrogen and argon mixture, increasing process costs. If the volume ratio is too low, it can result in residue of the anti-adhesion layer 105, thereby increasing the contact resistance between the first interconnect structure 101 and the second interconnect structure. Therefore, in this embodiment, the volume ratio of hydrogen to argon in the plasma processing process is between 1% and 90%.
[0110] It should also be noted that the process time in the plasma treatment process should not be too long or too short. If the process time is too long, it can easily damage the surface of the first interconnect structure 101, and at the same time, it will reduce production efficiency and increase process costs. If the process time is too short, it can easily leave the anti-adhesion layer 105 residue, thereby increasing the contact resistance between the first interconnect structure 101 and the second interconnect structure. Therefore, in this embodiment, the process time in the plasma treatment process is 2 seconds to 200 seconds.
[0111] In other embodiments, the plasma treatment process uses hydrogen as the processing gas. Accordingly, the parameters for the hydrogen-based plasma treatment process include: a hydrogen flow rate of 50 standard milliliters per minute to 5000 standard milliliters per minute; and a process time of 2 seconds to 200 seconds.
[0112] It should be noted that the hydrogen flow rate in the plasma treatment process should not be too high or too low. If the hydrogen flow rate is too high, the hydrogen may not react sufficiently with the polar groups in the anti-adhesion layer 105 and may be discharged, reducing the utilization rate of hydrogen and thus increasing process costs. If the hydrogen flow rate is too low, the anti-adhesion layer 105 may remain, thereby increasing the contact resistance between the first interconnect structure 101 and the second interconnect structure. Therefore, in this embodiment, the hydrogen flow rate in the plasma treatment process is between 50 standard milliliters per minute and 5000 standard milliliters per minute.
[0113] It should also be noted that the process time in the plasma treatment process should not be too long or too short. If the process time is too long, hydrogen gas can easily damage the surface of the first interconnect structure 101, and at the same time, it will reduce production efficiency and increase process costs. If the process time is too short, the anti-adhesion layer 105 may remain, thereby increasing the contact resistance between the first interconnect structure 101 and the second interconnect structure. Therefore, in this embodiment, the process time in the plasma treatment process is 2 seconds to 200 seconds.
[0114] In other embodiments, the plasma treatment process uses argon as the processing gas. Accordingly, the parameters for the argon-based plasma treatment process include: an argon flow rate of 50 standard milliliters per minute to 5000 standard milliliters per minute; and a process time of 2 seconds to 200 seconds.
[0115] It should be noted that the argon flow rate in the plasma treatment process should not be too high or too low. If the argon flow rate is too high, the plasma generated by the argon will bombard the anti-adhesion layer 105 for too short a time before being expelled, reducing the utilization rate of the argon and thus increasing the process cost. If the argon flow rate is too low, the time required to remove the anti-adhesion layer 105 will be increased, thus reducing production efficiency. Therefore, in this embodiment, the argon flow rate in the plasma treatment process is between 50 standard milliliters per minute and 5000 standard milliliters per minute.
[0116] It should also be noted that the process time in the plasma treatment process should not be too long or too short. If the process time is too long, the argon gas can easily damage the surface of the first interconnect structure 101, and at the same time, it will reduce production efficiency and increase process costs. If the process time is too short, the anti-adhesion layer 105 may remain, thereby increasing the contact resistance between the first interconnect structure 101 and the second interconnect structure. Therefore, in this embodiment, the process time in the plasma treatment process is 2 seconds to 200 seconds.
[0117] refer to Figures 11 to 14 After removing the anti-adhesion layer 105, a second interconnect structure 103 is formed in the opening 110, and the second interconnect structure 103 is in direct contact with the corresponding first interconnect structure 101.
[0118] The second interconnect structure 103 is used to make an electrical connection with the first interconnect structure 101.
[0119] It should be noted that the material of the second interconnect structure 103 is the same as that of the first interconnect structure 101. In this embodiment, the material of the second interconnect structure 103 is copper. Copper has good electrical conductivity and low resistance, which is beneficial for obtaining a second interconnect structure 103 with good conductivity.
[0120] In some embodiments, the material of the second interconnect structure 103 may be different from the material of the first interconnect structure 101. In other embodiments, depending on actual process requirements, the material of the second interconnect structure may also be a metal such as aluminum or tungsten.
[0121] The structure type of the second interconnection structure 103 can be a single damask structure or a double damask structure.
[0122] In this embodiment, the opening 110 includes an interconnect groove (not shown) and a through hole (not shown) communicating with the bottom of the interconnect groove. Therefore, the second interconnect structure 103 includes an interconnect layer (not shown) formed in the interconnect groove and a through hole structure (not shown) formed in the through hole. The through hole structure is located between the interconnect layer and the first interconnect structure 101, and the line width of the through hole structure is smaller than the line width of the interconnect layer.
[0123] Interconnect layers are used to implement circuit layout.
[0124] The via structure is used to connect the interconnect layer and the first interconnect structure 101, thereby realizing the electrical connection between the interconnect layer and the internal circuitry of the semiconductor structure.
[0125] The steps for forming the second interconnect structure 103 are described in detail below with reference to the accompanying drawings.
[0126] refer to Figure 11 A seed layer 114 is formed on the sidewall of the wetting barrier layer 106 and on the top of the first interconnect structure 101.
[0127] Specifically, the seed layer 114 provides a uniform starting surface for the subsequent formation of interconnect structures, which helps to reduce the probability of defects such as voids and cracks in the subsequent interconnect structures, thereby improving the quality and reliability of the formed interconnect structures.
[0128] The material of the seed layer 114 is determined based on the material of the second interconnect structure 103. In this embodiment, the material of the seed layer 114 is copper. In other embodiments, the seed layer may also be made of other metallic materials suitable for growing the material of the second interconnect structure.
[0129] refer to Figures 12 to 13 The interconnect material 115 is filled in by means of: reflowing the seed layer 114 to form the interconnect material 115, or electroplating the interconnect material 115 on the seed layer 114.
[0130] It should be noted that in the method of reflowing the seed layer 114 to form the interconnect material 115, the reflowing process can alleviate the thermal and mechanical stress in the seed layer, reduce the formation of cracks and defects, and improve the quality of the interconnect material 115.
[0131] It should be noted that in the method of electroplating interconnect material 115 on the seed layer 114, the electroplating process can enhance the bonding force between the formed interconnect material 115 and the seed layer 114, improve the adhesion of the interconnect material 115, and at the same time, the interconnect material 115 formed by the electroplating process has high conductivity, thereby improving the semiconductor structure performance.
[0132] Reference Figures 11 to 13 The step of forming the second interconnect structure 103 includes repeatedly alternating the steps of forming the seed layer 114 and filling the interconnect material 115, and employing a reflow process on the seed layer 114 to form the interconnect material 115.
[0133] In other words, multiple filling processes are performed to form the interconnect material 115, and each filling process includes the following steps: (Refer to...) Figure 11 A seed layer 114 is formed on the sidewall of the wetting barrier layer 106 and on top of the first interconnect structure 101; Reference Figures 12 to 13 The seed layer 114 is then subjected to a reflow process. The seed layer 114 formed in the subsequent filling process is located on the interconnect material 115 formed in the previous filling process, and the thickness of the interconnect material 115 gradually increases with the number of filling processes.
[0134] It should be noted that the steps of forming the second interconnect structure 103 include repeatedly alternating the steps of forming the seed layer 114 and filling the interconnect material 115, and the seed layer 114 is reflowed to form the interconnect material 115. Since the reflow process has a good ability to fill gaps, this process can be applied to form a small-sized second interconnect structure 103.
[0135] For example, the opening 110 includes a first type opening and a second type opening, where the top line width of the first type opening is greater than that of the second type opening. By repeatedly alternating the steps of forming the seed layer 114 and filling the interconnect material 115, a second interconnect structure 103 that fills the second type opening can be formed.
[0136] In other embodiments, the step of forming the second interconnect structure includes alternating the steps of forming the seed layer and filling the interconnect material multiple times, and before the last seed layer is formed, the seed layer is reflowed to form the interconnect material, and after the last seed layer is formed, the interconnect material is electroplated on the seed layer.
[0137] It should be noted that combining the reflow process of the seed layer with the electroplating process can improve the efficiency of filling interconnect materials. At the same time, it is beneficial to form higher density interconnect materials, thereby improving the electrical performance of semiconductors.
[0138] For example, by repeatedly alternating between the step of forming the seed layer and the step of filling the interconnect material, an interconnect material that fills the second type of opening can be formed, and then by the step of forming the seed layer and the step of electroplating the interconnect material on the seed layer, the remaining space of the first type of opening can be filled with the interconnect material.
[0139] It is understandable that the method of forming the second interconnect structure 103 can be selected according to the actual situation.
[0140] In this embodiment, the process for forming the seed layer 114 includes physical vapor deposition.
[0141] Specifically, by adjusting the process parameters in the physical vapor deposition process, the thickness of the seed layer 114 can be precisely controlled. At the same time, the physical vapor deposition process can uniformly deposit the material of the seed layer 114 on the first medium layer 104, thereby improving the quality of the seed layer 114.
[0142] refer to Figure 14 After forming interconnect material 115 in opening 110, the interconnect material 115 is subjected to a planarization process to form a second interconnect structure 103.
[0143] It should be noted that the planarization process of the interconnect material 115 helps to reduce the surface undulations in the formation of the second interconnect structure 103 and improve the dimensional accuracy of the second interconnect structure 103.
[0144] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate structure is provided in which a first interconnect structure is formed, the substrate structure exposing the top of the first interconnect structure; A first dielectric layer is formed on the substrate structure, and an opening is formed in the first dielectric layer to expose the top of the first interconnect structure; An anti-adhesion layer is formed at the bottom of the opening, the anti-adhesion layer exposing the sidewall of the opening; After the anti-adhesion layer is formed, a wetting barrier layer is selectively deposited on the sidewall of the opening; After the wetting barrier layer is formed, the anti-adhesion layer is removed, exposing the first interconnect structure at the bottom of the opening; After removing the anti-adhesion layer, a second interconnect structure is formed in the opening, and the second interconnect structure is in direct contact with the corresponding first interconnect structure.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The step of forming an impregnation barrier layer includes: selectively depositing a barrier layer on the sidewall of the opening, wherein the barrier layer exposes the bottom of the opening; and selectively depositing an impregnation layer on the sidewall of the barrier layer, wherein the impregnation layer exposes the bottom of the opening.
3. The method for forming a semiconductor structure as described in claim 2, characterized in that, The barrier layer is made of a low-k dielectric material.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The low-k dielectric material includes one or both of SiCN and SiCO.
5. The method for forming a semiconductor structure as described in claim 2, characterized in that, The wetting layer includes one or more of the following: a cobalt layer, a ruthenium layer, a ruthenium-doped cobalt layer, and a cobalt-doped ruthenium layer.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of selectively depositing a wetting barrier layer on the sidewall of the opening includes chemical vapor deposition or atomic layer deposition.
7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of forming an anti-adhesion layer at the bottom of the opening includes: selectively adsorbing an anti-adhesion layer at the bottom of the opening, the anti-adhesion layer being made of a material having polar and non-polar groups, the polar groups being bonded to a first interconnect structure surface at the bottom of the opening, and the non-polar groups being used to provide an anti-adhesion surface for the anti-adhesion layer.
8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The process for selectively depositing the anti-adhesion layer includes chemical vapor deposition.
9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The process parameters for chemical vapor deposition include: a process temperature of 100°C to 400°C; a process pressure of 0.1 Torr to 100 Torr; a precursor used including one or more of benzotriazolyl thiols, propylene, butyne, and decane; and a carrier gas including one or more of argon, nitrogen, and helium.
10. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that, In the step of forming an anti-adhesion layer at the bottom of the opening, the material of the anti-adhesion layer includes one or more of benzotriazolyl thiol, propylene, butyne, and decane.
11. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that, In the step of forming an anti-adhesion layer at the bottom of the opening, the thickness of the anti-adhesion layer is 0.5 nm to 5 nm.
12. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that, Before forming the first dielectric layer on the substrate structure, the method for forming the semiconductor structure further includes: forming a stop layer on top of the substrate structure and the first interconnect structure; In the step of forming a first dielectric layer on the substrate structure, an opening is formed in the first dielectric layer that penetrates the stop layer and exposes the top of the first interconnect structure; In the step of forming an anti-adhesion layer at the bottom of the opening, the top of the anti-adhesion layer is lower than or flush with the top of the stop layer.
13. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that, The step of forming the second interconnect structure includes: forming a seed layer on the sidewall of the wetting barrier layer and on top of the first interconnect structure; The interconnect material is filled in by means of: reflowing the seed layer to form the interconnect material, or electroplating the interconnect material onto the seed layer.
14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The steps for forming the second interconnect structure include alternating the steps of forming the seed layer and filling the interconnect material multiple times, and the seed layer is reflowed to form the interconnect material. or, The steps of forming the second interconnect structure include alternating the steps of forming the seed layer and filling the interconnect material multiple times, and before the last seed layer is formed, the seed layer is reflowed to form the interconnect material, and after the last seed layer is formed, the interconnect material is electroplated on the seed layer.
15. The method for forming a semiconductor structure as described in claim 13, characterized in that, The process for forming the seed layer includes physical vapor deposition.
16. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that, The process for removing the anti-adhesion layer includes a plasma treatment process.
17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The plasma treatment process uses one or both of hydrogen and argon.
18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The parameters of the plasma treatment process include: the treatment gas is a mixture of hydrogen and argon; the volume ratio of hydrogen to argon is 1% to 90%; and the process time is 2 seconds to 200 seconds. Alternatively, the parameters of the plasma treatment process include: the treatment gas is hydrogen; the flow rate of the hydrogen is from 50 standard milliliters per minute to 5000 standard milliliters per minute; and the process time is from 2 seconds to 200 seconds. Alternatively, the parameters of the plasma treatment process include: the treatment gas is argon; the flow rate of the argon is from 50 standard milliliters per minute to 5000 standard milliliters per minute; and the process time is from 2 seconds to 200 seconds.
19. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that, The step of providing a substrate structure includes: providing a substrate and a second dielectric layer located on the substrate, wherein a first interconnect structure is formed in the second dielectric layer.
20. The method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that, In the step of forming a first dielectric layer on the substrate structure, the opening includes an interconnect trench and a through hole communicating with the bottom of the interconnect trench.