Semiconductor structure with heterogeneous contact and manufacturing method thereof

Abstract

A semiconductor structure including a hybrid contact includes a first hybrid contact in a dielectric layer, where the first hybrid contact is made of copper, a first top conductive layer in the dielectric layer and below the first hybrid contact, and a second top conductive layer in the dielectric layer and below the second hybrid contact. Wherein the first top conductive layer is made of aluminum, a first composite liner layer is located between the first heterogeneous contact and the first top conductive layer, and the first composite liner layer covers two side walls and a bottom surface of the first heterogeneous contact from a cross-sectional view, wherein the first composite liner layer is composed of a titanium layer, a titanium nitride layer, a tantalum nitride layer and a tantalum layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor structure containing heterogeneous contacts and a method for fabricating the same, which has the effect of reducing the interface resistance between copper and aluminum. Background Technology

[0002] In the existing technology, common chip packaging methods include chip on film (COF), chip on glass (COG), or chip on plastic (COP).

[0003] As technology advances, semiconductor devices are shrinking in size and becoming increasingly precise, rendering the aforementioned packaging methods insufficient to meet current technological demands. There is a need to develop packaging methods with higher precision and smaller dimensions to meet practical application requirements.

[0004] In current technologies, hybrid bonding is a commonly used method. For example, contact structures formed on two different substrates can be made in contact and electrically connected through hybrid bonding. Compared with connection methods such as wire bonding or forming solder balls, this bonding method can significantly reduce the area and increase the component density. Therefore, hybrid bonding technology is increasingly used in the field of semiconductor manufacturing processes. Summary of the Invention

[0005] The present invention provides a semiconductor structure including a hybrid bond contact, comprising a first heterobond contact located in a dielectric layer, wherein the first heterobond contact is made of copper, a first top conductive layer located in the dielectric layer and below the first heterobond contact, wherein the first top conductive layer is made of aluminum, and a first composite pad layer located between the first heterobond contact and the first top conductive layer. From a cross-sectional view, the first composite pad layer covers the two sidewalls and a bottom surface of the first heterobond contact, wherein the first composite pad layer is composed of a titanium layer, a titanium nitride layer, a tantalum nitride layer and a tantalum layer.

[0006] The present invention also provides a method for fabricating a semiconductor structure including a hybrid bond contact, comprising forming a first heterogeneous contact located in a dielectric layer, wherein the first heterogeneous contact is made of copper; forming a first top conductive layer located in the dielectric layer and below the first heterogeneous contact, wherein the first top conductive layer is made of aluminum; and forming a first composite pad layer located between the first heterogeneous contact and the first top conductive layer. From a cross-sectional view, the first composite pad layer covers both sidewalls and a bottom surface of the first heterogeneous contact, wherein the first composite pad layer is composed of a titanium layer, a titanium nitride layer, a tantalum nitride layer, and a tantalum layer.

[0007] This invention provides a semiconductor structure with a hybrid bond contact and its fabrication method. The key feature is that when the semiconductor structure includes an interface between copper and aluminum components, a spacer layer is added between the copper and aluminum components. This spacer layer consists of four layers: a titanium layer, a titanium nitride layer, a tantalum nitride layer, and a tantalum layer. Furthermore, during heating, an additional titanium aluminide layer is formed between the aluminum component and the titanium layer. According to the applicant's experiments, the addition of these spacer layers effectively reduces the interface resistance between the copper and aluminum components. In addition, the formed titanium aluminide layer effectively prevents aluminum atoms from drifting from the aluminum component to other components during the fabrication process, thus preventing them from affecting electrical properties. Therefore, the structure and method provided by this invention have the advantage of improving component quality and yield. Attached Figure Description

[0008] To facilitate understanding of the following text, reference should be made to the accompanying drawings and detailed descriptions while reading this invention. Specific embodiments of the invention are explained in detail through reference to the corresponding drawings, which illustrate the working principles of these embodiments. Furthermore, for clarity, features in the drawings may not be drawn to scale, and therefore the dimensions of some features in certain drawings may be intentionally enlarged or reduced.

[0009] Figure 1 This is a schematic diagram of the semiconductor structure of the present invention and a partially enlarged view of the structure;

[0010] Figure 2 This is an enlarged cross-sectional view of the area near the copper-aluminum interface of a semiconductor structure according to another embodiment of the present invention;

[0011] Figure 3 This is a cross-sectional structural diagram of different chips bonded together, as an embodiment of the present invention.

[0012] Symbol Explanation

[0013] 10: Aluminized titanium layer

[0014] 12: Titanium layer

[0015] 14: Titanium nitride layer

[0016] 16: Tantalum nitride layer

[0017] 18: Tantalum layer

[0018] 20: Tantalum nitride layer

[0019] 22: Tantalum layer

[0020] 30: Tantalum layer

[0021] 32: Tantalum nitride layer

[0022] 34: Titanium nitride layer

[0023] 36: Titanium layer

[0024] 38: Aluminized titanium layer

[0025] 41: Metal layer

[0026] 42: Dielectric layer

[0027] 43: Metal layer

[0028] 44: Dielectric layer

[0029] 45: Metal layer

[0030] 46: Dielectric layer

[0031] 51: Composite liner layer

[0032] 52: Aluminized titanium layer

[0033] 53: Composite liner layer

[0034] 54: Composite liner layer

[0035] 55: Aluminized titanium layer

[0036] C1: First chip

[0037] C2: Second chip

[0038] C3: Third chip

[0039] HB: Heterogeneous Contact

[0040] HBP1: Contact pad

[0041] HBP2: Contact pad

[0042] HBP3: Contact pad

[0043] HBV1: Contact column

[0044] HBV2: Contact Post

[0045] HBV3: Contact column

[0046] L1: Top conductive layer

[0047] L2: Top conductive layer

[0048] L3: Top conductive layer

[0049] M10: Metallic circuit layer

[0050] M11: Metallic circuit layer

[0051] V10: Contact Post Detailed Implementation

[0052] To enable those skilled in the art to further understand the present invention, preferred embodiments of the invention are described below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings.

[0053] For ease of explanation, the accompanying drawings are merely illustrative to facilitate understanding of the invention, and their detailed proportions can be adjusted according to design requirements. The vertical relationships between relative elements in the drawings described herein should be understood by those skilled in the art to refer to the relative positions of objects; therefore, all can be flipped to present the same components, and this should all fall within the scope of this specification, as stated herein.

[0054] Although the present invention uses terms such as first, second, third, etc., to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as a second element, component, region, layer, or section.

[0055] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, such as within 10%, 5%, 3%, 2%, 1%, or 0.5%. It should be noted that the quantities provided in the specification are approximate, meaning that the meaning of "about" or "substantially" may be implied even without specific mention of it.

[0056] The terms "coupled," "coupled," and "electrically connected" as used in this invention include any direct or indirect means of electrical connection. For example, if the text describes a first component coupled to a second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0057] Although the invention is described below by way of specific embodiments, the inventive principles of the invention can also be applied to other embodiments. Furthermore, in order to avoid obscuring the spirit of the invention, certain details have been omitted; these omitted details fall within the scope of knowledge of those skilled in the art.

[0058] Please refer to Figure 1 The diagram illustrates a schematic representation of the semiconductor structure of the present invention, as well as enlarged views of some parts of the structure. For example... Figure 1 As shown, multiple metal layers 41 are formed in the dielectric layer 42 of a semiconductor chip C1. The metal layers 41 further include metal circuit layers extending in the horizontal direction and contact pillars penetrating the dielectric layer in the vertical direction. Figure 1 The left half of the diagram shows a partially enlarged view of semiconductor wafer 1, where some metal layers are labeled as metal line layer M11, contact pillar V10, and metal line layer M10. It is worth noting that there may be other contact pillars or metal line layers below metal line layer M10 (such as metal layer 41 in the right half). Furthermore, different metal line layers and different contact pillars may be located in different dielectric layers. The dielectric layer material may include insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride. Figure 1 For the sake of brevity in the accompanying diagrams, other contact pillars or metal circuit layers below the dielectric layer and metal circuit layer M10 are omitted. Generally, the numbers M10, V10, and M10 in this diagram indicate the number of metal circuit layers or contact pillars stacked from bottom to top in the semiconductor structure. For example, M11 is the 11th metal circuit layer stacked in the semiconductor structure. However, it is understood that the number of stacked metal circuit layers or contact pillars may vary depending on the semiconductor structure. Figure 1 This is merely one example, and the actual number of stacked metal circuit layers or contact posts may vary depending on requirements. In other words, Figure 1 The topmost metal circuit layer shown may be M11, or in other embodiments it may be M8, M9, M12, M15 or Mx (where x represents other positive integers), all of which are within the scope of this invention.

[0059] The above Figure 1The metal circuit layer or contact post is preferably made of copper. Copper has the advantage of good conductivity and is therefore often used to fabricate circuit layers in semiconductor structures. However, copper is prone to oxidation when exposed to air, which significantly reduces its conductivity. Therefore, the above fabrication process is preferably carried out in an oxygen-free environment. However, this increases the difficulty of quality testing of the metal circuit layer.

[0060] like Figure 1 As shown, in this invention, a top conductive layer L1 is formed on the surface of the metal circuit layer M11. The top conductive layer L1 is made of aluminum. The top conductive layer L1 can be considered as the topmost metal circuit layer in a multilayer metal circuit structure. That is, the semiconductor structure contains multiple metal circuit layers and contact pillars for connecting various electronic components. Except for the top conductive layer L1, the remaining metal circuit layers and contact pillars below it are preferably made of copper. In other words, after the multilayer metal circuit structure is fabricated, only the top conductive layer L1 is exposed to the air, while the other metal circuit layers or contact pillars are covered or buried in the dielectric layer and do not directly contact the air.

[0061] This invention allows for an electrical testing step on the multilayer metal circuitry after the top conductive layer L1 is completed and before subsequent components are formed. As mentioned above, aluminum is less reactive with air, making it more suitable for electrical testing in air compared to copper. The electrical tests include checking for open circuits or resistance. If the test results meet predetermined specifications, subsequent steps can proceed. Conversely, if the test results do not meet specifications, it indicates that the multilayer metal circuitry has problems and is damaged. In this case, process adjustment steps may be performed to identify the problematic process or parameters, and the damaged semiconductor structure may be discarded or recycled.

[0062] If the above electrical test steps are passed, such as Figure 1As shown, a hybrid bonding contact HB is subsequently formed on the top conductive layer L1. The hybrid bonding contact HB includes contact pillars HBV1 and contact pads HBP1. Contact pillars HBV1 directly contact the top conductive layer L1. Both contact pillars HBV1 and contact pads HBP1 are preferably made of copper. The area of ​​contact pads HBP1 is preferably larger than the area of ​​contact pillars HBV1, but is not limited thereto. In this embodiment, contact pillars HBV1 are used to connect contact pads HBP1 and the top conductive layer L1, while contact pads HBP1 are used to connect another semiconductor structure, such as another semiconductor structure that also includes multiple circuit layers and contact pads. The contact pads of the two semiconductor structures are directly contacted and connected face-to-face. This packaging method is also called hybrid bonding. Compared to other types of packaging methods in semiconductor manufacturing processes (such as solder packaging, wire bonding, etc.), hybrid bonding can effectively increase component density and reduce component volume.

[0063] In the stacked structure of the aforementioned components, the purpose of forming the top conductive layer L1 is to prevent the topmost metal layer (i.e., the top conductive layer L1) from being oxidized during electrical testing, thus affecting the test results. Therefore, forming the top conductive layer L1 in the manufacturing process is necessary. However, the applicant has also discovered that the metal layer below the top conductive layer L1 (e.g., the metal circuit layer M11) and the metal layer above it (e.g., the contact post HBV1) are both made of copper. Copper and aluminum, two different metals, are prone to causing an increase in interface resistance when joined, which is detrimental to the quality of the components.

[0064] Therefore, the applicant has improved the copper-aluminum interface to increase its conductivity and improve component quality. For details, please refer to... Figure 2 , Figure 2 An enlarged cross-sectional view of the area near the copper-aluminum interface of a semiconductor structure according to another embodiment of the present invention is shown. Figure 2As shown, in this embodiment, multiple material layers are added between the copper element and the aluminum element. The aluminum element is, for example, the aforementioned top conductive layer L1, and the copper element is, for example, the contact pillar HBV1. In this embodiment, multiple material layers are added between the top conductive layer L1 and the contact pillar HBV1, including, from bottom to top, a titanium (Ti) layer 12, a titanium nitride (TiN) layer 14, a tantalum nitride (TaN) layer 16, and a tantalum (Ta) layer 18. Note that in general semiconductor technology, the padding layers formed around the conductive layer are usually only combinations of titanium plus titanium nitride, or tantalum plus tantalum nitride. In this invention, a total of four padding layers are provided between the aluminum element and the copper element: a titanium (Ti) layer 12, a titanium nitride (TiN) layer 14, a tantalum nitride (TaN) layer 16, and a tantalum (Ta) layer 18. Each padding layer exhibits a U-shaped structure in cross-section, sequentially covering the bottom surface and sidewalls of the contact pillar HBV1 from the inside out. According to the applicant's experimental results, the four-layer padding layer, compared to the existing technology which only forms a two-layer padding layer (such as one of the two combinations of titanium plus titanium nitride or tantalum plus tantalum nitride), can effectively reduce the interface resistance between copper and aluminum components and improve the quality of the components.

[0065] In addition, since the top conductive layer L1 directly contacts the titanium layer 12, the manufacturing process temperature for forming other material layers will be increased to over 100 degrees Celsius. At this temperature, a titanium aluminide (TiAl3) layer 10 will be formed between the top conductive layer L1 and the titanium layer 12. From the cross-sectional view, the titanium aluminide layer 10 exhibits an "I" shape, meaning it does not have a U-shape like the titanium layer 12, titanium nitride layer 14, tantalum nitride layer 16, and tantalum layer 18, but rather a flat structure. Therefore, the titanium aluminide layer 10 only contacts the bottom surface of the titanium layer 12, and not its sides.

[0066] A padding layer is also formed around the top conductive layer L1 and the contact post HBV1. However, if it is not the interface between copper and aluminum components, but between copper components, then the four padding layers described above are not required. Instead, only one of the following combinations is needed: titanium plus titanium nitride, or tantalum plus tantalum nitride. For example, if both the contact post HBV1 and the contact pad HBP1 are copper components, then the padding layer between them is simply tantalum nitride layer 20 and tantalum layer 22. Similarly, a four-layer padding layer can be formed at the interface between the top conductive layer L1 and the underlying metal circuit layer M11, including tantalum layer 30, tantalum nitride layer 32, titanium nitride layer 34, and titanium layer 36. Likewise, between the top conductive layer L1 and the titanium layer 36, since aluminum and titanium are in direct contact, an aluminized titanium layer 38 is formed. This aluminized titanium layer 38 covers the bottom and side walls of the top conductive layer L1, meaning that from the side, the aluminized titanium layer 38 has a U-shape.

[0067] In this embodiment, the titanium layer 12 has a thickness of approximately 500 angstroms, the titanium nitride layer 14 has a thickness of approximately 50 angstroms, the tantalum nitride layer 16 has a thickness of approximately 80 angstroms, and the tantalum layer 18 has a thickness of approximately 50 angstroms. However, the thicknesses of the above-mentioned components are only one embodiment of the present invention, and the present invention is not limited thereto.

[0068] It is worth noting that the titanium aluminide layer 10 formed above the top conductive layer L1 and the titanium aluminide layer 38 formed below it also have the function of preventing atomic drift. More specifically, when the contact post HBV1 is formed, aluminum atoms in the top conductive layer L1 will diffuse into other components during the heating process, and the titanium aluminide layer 10 and titanium aluminide layer 38 formed here have the function of preventing aluminum atoms from drifting into the copper components above or below.

[0069] In the concept of the present invention described above, if the top conductive layer in the semiconductor chip (i.e., the conductive layer closest to the top, excluding contact pads HBP1 and contact pillars HBV1) is an aluminum element, then four layers of padding are required to reduce the interface resistance between the copper and aluminum elements and to prevent the diffusion of aluminum atoms during heating. However, if the top conductive layer in the semiconductor chip is a copper element, meaning that the lower metal conductive layer, the top conductive layer, and the upper contact pads and contact pillars are all copper elements, then four layers of padding are not required; instead, only layers such as tantalum and tantalum nitride need to be formed between the copper elements.

[0070] Figure 3 A cross-sectional schematic diagram illustrating a bonding structure of different chips together according to an embodiment of the present invention is shown. Figure 3 As shown, a first chip C1, a second chip C2, and a third chip C3 are bonded to each other. The size of the first chip C1 is larger than that of the second chip C2 and the third chip C3, therefore the second chip C2 and the third chip C3 are simultaneously bonded to the first chip C1. The first chip C1 contains multiple conductive layers 41 located within multiple dielectric layers 42; the second chip C2 contains multiple conductive layers 43 located within multiple dielectric layers 44; and the third chip C3 contains multiple conductive layers 45 located within multiple dielectric layers 46. The structure of the conductive layers 41, 43, and 45 is similar to... Figure 1 The aforementioned structures include the metal circuit layer M11, contact post V10, and other metal circuit layers. The dielectric layers 42, 44, and 46 may be multi-layered insulating layer stacks, such as multi-layered stacks of insulating layers like silicon oxide, silicon nitride, and silicon oxynitride. For simplicity in the accompanying drawings, conductive layers 41, 43, and 45 represent multi-layered conductive layers, and dielectric layers 42, 44, and 46 represent multi-layered dielectric layers.

[0071] As mentioned in the previous paragraphs, in some manufacturing processes, using aluminum for the top conductive layer (i.e., the conductive layer closest to the top, excluding contact pads HBP1 and contact pillars HBV1) in a multilayer conductive layer can prevent component oxidation and improve yield during component testing. However, in other manufacturing processes, such as those with higher yields or lower precision requirements, electrical testing may not be necessary. In these cases, it is preferable to use copper instead of aluminum for the top conductive layer. For example, in this embodiment, Figure 3 The top conductive layers L1 and L3 of the first chip C1 and the third chip C3 are made of aluminum, while the top conductive layer L2 of the second chip C2 is made of copper. Furthermore, all other circuit layers contained in the first chip C1, the second chip C2, and the third chip are copper components. Specifically, the contact post HBV1, contact pad HBP1, and conductive layer 41 of the first chip C1 are copper components; the contact post HBV2, contact pad HBP2, and conductive layer 43 of the second chip C2 are copper components; and the contact post HBV3, contact pad HBP3, and conductive layer 43 of the third chip C3 are copper components.

[0072] As previously described, in this invention, when a copper component contacts an aluminum component, a four-layer spacer layer needs to be formed between the copper and aluminum components, comprising a titanium (Ti) layer, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, and a tantalum (Ta) layer. The order of these layers can be referenced... Figure 2 As shown. Furthermore, an aluminized titanium layer also forms at the interface between the titanium layer and the aluminum component. Therefore, as... Figure 3 As shown, the first chip C1 includes a composite pad layer 51 covering both sides and the bottom of the contact post HBV1. The composite pad layer 51 comprises four layers: a titanium layer, a titanium nitride layer, a tantalum nitride layer, and a tantalum layer. Below the composite pad layer 51, there is also an aluminum titanium nitride layer 52, located between the top conductive layer L1 and the composite pad layer 51. Similarly, since the top conductive layer L3 in the third chip C3 is also aluminum, the third chip C3 includes a composite pad layer 54 covering both sides and the bottom of the contact post HBV3. The composite pad layer 54 comprises four layers: a titanium layer, a titanium nitride layer, a tantalum nitride layer, and a tantalum layer. Between the composite pad layer 54 and the top conductive layer L3, there is also an aluminum titanium nitride layer 55. As for the second chip C2, since the top conductive layer L2 is not made of aluminum but of copper, the composite pad layer 53 between the contact post HBV2 and the top conductive layer L2 does not contain a four-layer structure, but is composed of a tantalum nitride layer and a tantalum layer, a total of two layers.

[0073] Based on the above description and accompanying drawings, this invention provides a semiconductor structure including a hybrid bond contact, which can be referred to... Figure 2or Figure 3 It includes a first heterogeneous contact HB located in a dielectric layer 42, wherein the first heterogeneous contact HB is made of copper; a first top conductive layer L1 located in the dielectric layer 42 and below the first heterogeneous contact HB, wherein the first top conductive layer L1 is made of aluminum; and a first composite pad layer (i.e. Figure 2 The titanium layer 12, titanium nitride layer 14, tantalum nitride layer 16, and tantalum layer 18 are located between the first heterogeneous contact HB and the first top conductive layer L1. From a cross-sectional view, the first composite liner layer covers the two side walls and the bottom surface of the first heterogeneous contact HB. The first composite liner layer is composed of a titanium layer 12, a titanium nitride layer 14, a tantalum nitride layer 16, and a tantalum layer 18.

[0074] In some embodiments of the present invention, in the first composite liner layer, titanium layer 12, titanium nitride layer 14, tantalum nitride layer 16 and tantalum layer 18 are arranged from bottom to top.

[0075] In some embodiments of the present invention, a titanium aluminide (TiAl3) layer is further included between the first composite liner layer and the first top conductive layer L1.

[0076] In some embodiments of the present invention, the titanium aluminide (TiAl3) layer directly contacts a bottom surface of the first top conductive layer L1 and the titanium layer 12 in the first composite liner layer.

[0077] In some embodiments of the invention, the titanium aluminide (TiAl3) layer does not contact the sidewalls of the titanium layer 12 in the first composite liner layer.

[0078] In some embodiments of the present invention, a circuit layer (e.g., a metal conductive layer M11) is further included below the first top conductive layer L1, wherein the circuit layer M11 is made of copper.

[0079] In some embodiments of the present invention, the first heterogeneous contact HB includes an upper portion HBP1 and a lower portion HBV1, wherein the width of the upper portion HBP1 is greater than the width of the lower portion HBV1, and the first composite liner layer covers a bottom surface and two side walls of the lower portion HBV1.

[0080] In some embodiments of the invention, an additional padding layer (i.e.) is also included. Figure 2 The tantalum nitride layer 20 and tantalum layer 22 in the first heterogeneous contact HB cover a bottom surface and two side walls of the upper half of HBP1, wherein another pad layer is composed of a tantalum layer 22 and a tantalum nitride layer 20, and does not contain a titanium layer or a titanium nitride layer.

[0081] In some embodiments of the present invention, the first heterogeneous contact HB, the first top conductive layer L1 and the first composite pad layer are located in a first chip C1, and further include a second chip C2 and a third chip C3, wherein the size of the first chip C1 is larger than that of the second chip C2 and the third chip C3, and the first chip C1 is simultaneously bonded to the second chip C2 and the third chip C3.

[0082] In some embodiments of the present invention, the second chip C2 includes a second heterogeneous contact ( Figure 3 The contact post HBV2 and contact pad HBP2, a second top conductive layer L2 and a second pad layer 53 are electrically connected to each other, and the third chip C3 contains a third heterogeneous contact ( Figure 3 The contact post HBV3 and contact pad HBP3, a third top conductive layer L3 and a third composite pad layer 54 are electrically connected to each other. The second top conductive layer L2 in the second chip C2 is made of copper, the second pad layer 53 is made of a tantalum layer and a tantalum nitride layer, the third top conductive layer L3 in the third chip C3 is made of aluminum, and the third composite pad layer 54 is made of a titanium layer, a titanium nitride layer, a tantalum layer and a tantalum nitride layer.

[0083] The present invention further provides a method for fabricating a semiconductor structure including a hybrid bond contact, comprising forming a first heterogeneous contact HB located in a dielectric layer 42, wherein the first heterogeneous contact HB is made of copper; forming a first top conductive layer L1 located in the dielectric layer 42 and below the first heterogeneous contact HB, wherein the first top conductive layer L1 is made of aluminum; and forming a first composite pad layer (i.e., Figure 2 The titanium layer 12, titanium nitride layer 14, tantalum nitride layer 16, and tantalum layer 18 are located between the first heterogeneous contact HB and the first top conductive layer L1. From a cross-sectional view, the first composite liner layer covers the two side walls and the bottom surface of the first heterogeneous contact HB. The first composite liner layer is composed of a titanium layer 12, a titanium nitride layer 14, a tantalum nitride layer 16, and a tantalum layer 18.

[0084] In summary, this invention provides a semiconductor structure with a hybrid bond contact and its fabrication method. The key feature is that when the semiconductor structure includes an interface between copper and aluminum components, a spacer layer is added between the copper and aluminum components. This spacer layer consists of four layers: a titanium layer, a titanium nitride layer, a tantalum nitride layer, and a tantalum layer. Furthermore, during heating, an additional titanium aluminide layer is formed between the aluminum component and the titanium layer. According to the applicant's experiments, the interfacial resistance between the copper and aluminum components is effectively reduced after adding these spacer layers. In addition, the formed titanium aluminide layer effectively prevents aluminum atoms from drifting from the aluminum component to other components during the fabrication process, thus affecting electrical properties. Therefore, the structure and method provided by this invention have the advantage of improving component quality and yield.

[0085] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor structure comprising a hybrid bond contact, comprising: The first heterogeneous contact is located in the dielectric layer, wherein the first heterogeneous contact is made of copper; A first top conductive layer is located within the dielectric layer and below the first heterogeneous contact, wherein the first top conductive layer is made of aluminum; The first composite liner layer is located between the first heterogeneous contact and the first top conductive layer. From the cross-sectional view, the first composite liner layer covers the two side walls and the bottom surface of the first heterogeneous contact. The first composite liner layer is composed of a titanium layer, a titanium nitride layer, a tantalum nitride layer, and a tantalum layer.

2. The semiconductor structure comprising heterogeneous contacts as claimed in claim 1, wherein in the first composite pad layer, the titanium layer, the titanium nitride layer, the tantalum nitride layer, and the tantalum layer are arranged from bottom to top.

3. The semiconductor structure with heterogeneous contacts as claimed in claim 1, further comprising a titanium aluminide (TiAl3) layer located between the first composite pad layer and the first top conductive layer.

4. The semiconductor structure comprising heterogeneous contacts as described in claim 3, wherein the titanium aluminide (TiAl3) layer directly contacts the bottom surface of the titanium layer in the first top conductive layer and the first composite pad layer.

5. The semiconductor structure comprising heterogeneous contacts as described in claim 3, wherein the titanium aluminide (TiAl3) layer does not contact the sidewalls of the titanium layer in the first composite pad layer.

6. The semiconductor structure with heterogeneous contacts as claimed in claim 1, further comprising a circuit layer located below the first top conductive layer, wherein the circuit layer is made of copper.

7. The semiconductor structure including a heterogeneous contact as claimed in claim 1, wherein the first heterogeneous contact includes an upper portion and a lower portion, wherein the width of the upper portion is greater than the width of the lower portion, and the first composite pad layer covers the bottom surface and sidewalls of the lower portion.

8. The semiconductor structure comprising a heterogeneous contact as claimed in claim 7, further comprising another pad layer covering the bottom surface and sidewalls of the upper portion of the first heterogeneous contact, wherein the other pad layer is composed of a tantalum layer and a tantalum nitride layer, and does not contain a titanium layer or a titanium nitride layer.

9. The semiconductor structure comprising a heterogeneous contact as claimed in claim 1, wherein the first heterogeneous contact, the first top conductive layer, and the first composite pad layer are located in a first chip, and further comprising a second chip and a third chip, wherein the size of the first chip is larger than that of the second chip and the third chip, and the first chip is simultaneously bonded to the second chip and the third chip.

10. The semiconductor structure including heterogeneous contacts as claimed in claim 9, wherein the second chip includes a second heterogeneous contact, a second top conductive layer, and a second pad layer electrically connected to each other, and the third chip includes a third heterogeneous contact, a third top conductive layer, and a third composite pad layer electrically connected to each other, wherein the second top conductive layer in the second chip is made of copper, the second pad layer is made of a tantalum layer and a tantalum nitride layer, the third top conductive layer in the third chip is made of aluminum, and the third composite pad layer is made of a titanium layer, a titanium nitride layer, a tantalum layer, and a tantalum nitride layer.

11. A method for fabricating a semiconductor structure including a hybrid bond contact, comprising: A first heterogeneous contact is formed in the dielectric layer, wherein the first heterogeneous contact is made of copper; A first top conductive layer is formed within the dielectric layer and below the first heterogeneous contact, wherein the first top conductive layer is made of aluminum; A first composite liner layer is formed between the first heterogeneous contact and the first top conductive layer. From the cross-sectional view, the first composite liner layer covers the two side walls and the bottom surface of the first heterogeneous contact. The first composite liner layer is composed of a titanium layer, a titanium nitride layer, a tantalum nitride layer, and a tantalum layer.

12. The method of fabricating a semiconductor structure including heterogeneous contacts as claimed in claim 11, wherein in the first composite pad layer, the titanium layer, the titanium nitride layer, the tantalum nitride layer, and the tantalum layer are arranged from bottom to top.

13. The method of fabricating a semiconductor structure including heterogeneous contacts as claimed in claim 11, further comprising forming a titanium aluminide (TiAl3) layer between the first composite pad layer and the first top conductive layer.

14. The method for fabricating a semiconductor structure including heterogeneous contacts as described in claim 13, wherein the titanium aluminide (TiAl3) layer directly contacts the bottom surface of the titanium layer in the first top conductive layer and the first composite pad layer.

15. The method for fabricating a semiconductor structure including heterogeneous contacts as described in claim 13, wherein the titanium aluminide (TiAl3) layer does not contact the sidewalls of the titanium layer in the first composite pad layer.

16. The method of fabricating a semiconductor structure including heterogeneous contacts as claimed in claim 11, further comprising forming a circuit layer below the first top conductive layer, wherein the circuit layer is made of copper.

17. The method for fabricating a semiconductor structure including a heterogeneous contact as claimed in claim 11, wherein the first heterogeneous contact includes an upper portion and a lower portion, wherein the width of the upper portion is greater than the width of the lower portion, and the first composite pad layer covers the bottom surface and sidewalls of the lower portion.

18. The method of fabricating a semiconductor structure including a heterogeneous contact as claimed in claim 17, further comprising forming another pad layer covering the bottom surface and sidewalls of the upper portion of the first heterogeneous contact, wherein the other pad layer is composed of a tantalum layer and a tantalum nitride layer, and does not contain a titanium layer or a titanium nitride layer.

19. The method for fabricating a semiconductor structure including a heterogeneous contact as claimed in claim 11, wherein the first heterogeneous contact, the first top conductive layer, and the first composite pad layer are located in a first chip, and further include a second chip and a third chip, wherein the size of the first chip is larger than that of the second chip and the third chip, and the first chip is simultaneously bonded to the second chip and the third chip.

20. The method for fabricating a semiconductor structure including heterogeneous contacts as described in claim 19, wherein the second chip includes a second heterogeneous contact, a second top conductive layer, and a second pad layer electrically connected to each other, and the third chip includes a third heterogeneous contact, a third top conductive layer, and a third composite pad layer electrically connected to each other, wherein the second top conductive layer in the second chip is made of copper, the second pad layer is made of tantalum layer and tantalum nitride layer, the third top conductive layer in the third chip is made of aluminum, and the third composite pad layer is made of titanium layer, titanium nitride layer, tantalum layer, and tantalum nitride layer.

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