Deep groove silicon capacitor based on cross-shaped structure unit obliquely laid and densely arranged array

Abstract

The invention discloses a deep groove silicon capacitor based on an inclined laying and close arrangement array of a cross-shaped structure unit, and belongs to the technical field of silicon capacitors. According to the structure, a plurality of cross-shaped groove structure units are etched on a silicon substrate, the groove structure units rotate by an angle alpha with the center of the groove structure units as the axis and then are laid in an inclined mode according to the interval d to form a close-packed array, the angle alpha meets the requirement that d is the minimum interval between the groove structure units, and d is the minimum interval between the groove structure units. And a single-layer capacitor dielectric structure or a multi-layer capacitor dielectric parallel structure is arranged in the groove structure unit. The invention has the advantages of higher capacitance density, better film deposition effect and coverage rate, and excellent performance.

Description

Technical Field

[0001] This invention belongs to the field of silicon capacitor technology, and particularly relates to a deep trench silicon capacitor based on a diagonally laid-up close array of cross-shaped structural units. Background Technology

[0002] Silicon capacitors, as highly integrated, high-performance passive (passive) devices manufactured using semiconductor processes, are becoming core components in emerging fields such as 5G / 6G communications, artificial intelligence, new energy vehicles, high-end medical devices, and aerospace due to their ultra-high precision, ultra-small size, excellent high-frequency characteristics, and outstanding temperature stability.

[0003] Current techniques for improving the capacitance density of silicon capacitors mainly focus on three dimensions: First, increasing the trench depth to expand the electrode surface area, but when the aspect ratio exceeds 40:1, it is easy to cause uneven etching, filling voids, and wafer warping caused by mechanical stress; Second, using high dielectric constant (high K) materials (such as Al2O3, HfO2) to replace the traditional SiO2 dielectric layer, however, a single high K material can easily lead to increased leakage current and reduced breakdown voltage, and the continuous improvement of the K value is limited; Third, reducing the thickness of the dielectric layer can enhance the capacitance per unit area, but there is a trade-off between thickness and withstand voltage.

[0004] The methods described above all face bottlenecks due to material physical limitations or soaring marginal costs in the manufacturing process. Therefore, many studies focus on optimizing the geometry of the trench structural units themselves, thereby further improving surface area utilization while maintaining good process yield. For example, a cross-shaped structural unit, such as... Figure 1 As shown, this not only significantly increases capacitance density but also provides better structural stability and process gas flow within the trench. However, in existing technologies, the structural units in each row or column of the cross-shaped structural unit are arranged horizontally or vertically according to a spacing d, and adjacent rows or columns are arranged sequentially in a staggered half-cycle pattern to form a semi-cycle staggered array, such as... Figure 2 As shown, there are many ineffective gap regions in this structure, which limits the improvement of capacitance density. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a deep trench silicon capacitor based on a cross-shaped structural unit with a closely spaced oblique array.

[0006] To achieve the above-mentioned objectives, this invention provides a deep trench silicon capacitor based on a closely spaced, obliquely tiled array of cross-shaped structural units. Several cross-shaped trench structural units are etched on a silicon substrate. These trench structural units are then rotated clockwise or counterclockwise by an angle α around their center axis, and then spaced according to... d A close-packed array is formed by diagonal tiling, wherein the angle α satisfies The d The minimum spacing between the trench structure units is defined as follows: the trench structure unit is provided with a single-layer capacitor dielectric structure or a multi-layer capacitor dielectric parallel structure.

[0007] Preferably, the diagonally laid cross-shaped groove structure unit has 4 short sides of equal length and 8 long sides of equal length, wherein the length of the short sides is... s The length of the longer side is s + d The planar capacitance of a single column in a trench structure unit is: Sidewall capacitance of a single column in a trench structure unit: Number of columns per unit area of ​​trench structural unit: Capacitance density: ; In the formula: It is the vacuum permittivity, with units of F / m; The relative permittivity of the medium is a dimensionless constant. The thickness of the dielectric layer is expressed in meters (m). s The shorter side of the column is the minimum line width allowed by the process, in meters (m). d The interval between individual columns of the trench structure unit is expressed in meters (m). L It is the etching depth, measured in meters (m).

[0008] Preferably, the single-layer capacitor dielectric structure is arranged in an "electrode-dielectric-electrode" configuration, and the multilayer capacitor dielectric parallel structure is arranged in an "electrode-x (dielectric-electrode)" configuration, where x is an integer greater than 1.

[0009] Preferably, the electrode and the dielectric are formed by atomic layer deposition or chemical vapor deposition of the corresponding raw materials.

[0010] Preferably, the raw material of the electrode is a metal, heavily doped polycrystalline silicon, or a low-resistivity monocrystalline silicon substrate.

[0011] Preferably, the raw material of the medium is any one or more of SiO2, SiN, Al2O3, HfO2, and ZrO2.

[0012] Preferably, each corner of the "cross-shaped" groove structure unit is chamfered, especially rounded.

[0013] Compared with the prior art, the beneficial effects of the present invention are: 1. The deep trench silicon capacitor of the present invention adopts a diagonally laid-up dense array of cross-shaped structural units, which can obtain a higher unit surface area and thus achieve a higher capacitance density.

[0014] 2. The deep trench silicon capacitor of the present invention adopts a diagonally laid-up close array of cross-shaped structural units. The gap size between adjacent cross-shaped structural units is more uniform, which is conducive to the uniform distribution and smooth flow of gas in the trench, thereby achieving a uniform thin film deposition effect and improving the step coverage of thin film deposition. Attached Figure Description

[0015] Figure 1 This refers to the trench structure unit in the existing technology.

[0016] Figure 2 This is a schematic diagram of a deep trench silicon capacitor constructed from trench structure units arranged in a half-cycle staggered array, as described in the prior art.

[0017] Figure 3 This is a schematic diagram of the deep trench silicon capacitor based on a cross-shaped structural unit with a closely packed oblique array according to the present invention.

[0018] Figure 4 For when s > d A schematic diagram of the structure of a half-cycle staggered array.

[0019] Figure 5 For when s > d A schematic diagram of the structure of a diagonally tiled dense array.

[0020] Figure 6 For when d ≥ s A schematic diagram of the structure of a half-cycle staggered array.

[0021] Figure 7 For when d ≥ s A schematic diagram of the structure of a diagonally tiled dense array.

[0022] Figure 8 For when s > d At that time, the gas velocity distribution diagram of the half-period staggered array.

[0023] Figure 9 For when s > d At that time, the gas velocity distribution diagram of the obliquely tiled close-packed array.

[0024] Figure 10 for Figure 8 Enlarged view of point A in the middle.

[0025] Figure 11 for Figure 9 Enlarged view of section B in the middle.

[0026] Figure 12 for d ≥s At that time, the gas velocity distribution in the half-period staggered array is shown.

[0027] Figure 13 for d ≥ s At that time, the gas velocity distribution diagram in the obliquely tiled close-packed array.

[0028] Figure 14 for s > d At that time, the gas pressure distribution diagram in the half-period staggered array.

[0029] Figure 15 for s > d At that time, the gas pressure distribution diagram in the obliquely tiled close-packed array.

[0030] Figure 16 for d ≥ s At that time, the gas pressure distribution diagram in the half-period staggered array.

[0031] Figure 17 for d ≥ s At that time, the gas pressure distribution diagram in the obliquely tiled close-packed array. Detailed Implementation

[0032] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0033] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0034] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "inner," and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the accompanying drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0035] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0036] As Figure 3-7 shown, the present invention provides a deep trench silicon capacitor based on a cross-shaped structural unit with a tiled and closely arranged array. Its structure is as follows: several cross-shaped trench structural units are etched on a silicon substrate. The several trench structural units are centered on their axes and rotated by an angle α (for the convenience of description, only clockwise rotation is shown in the attached Figure 3 、 5 、7 of this embodiment), and then tiled at a spacing d to form a closely arranged array. The angle α satisfies (i.e., α is approximately 26.57°). After rotation and tiling, the cross-shaped trench structural units in the closely arranged array have 4 short sides of equal length and 8 long sides of equal length. The length of the short side is s , and the length of the long side is s + d。 In the present invention, d is defined as the minimum spacing between trench structural units. The aspect ratio of the trench structural units of the present invention can be any value. Specifically, in this embodiment, the trench has a single-layer capacitor dielectric structure of "electrode - dielectric - electrode" or a multi-layer capacitor dielectric parallel structure of "electrode - x (dielectric - electrode)", where x is an integer greater than 1. The electrode can be a metal material deposited by atomic layer deposition (ALD), or heavily doped polysilicon (poly silicon) deposited by chemical vapor deposition (CVD), or a low-resistance single-crystal silicon substrate; the dielectric can be a conventional or high k -value dielectric material such as SiO2, SiN, Al2O3, HfO2, ZrO2, etc. deposited by atomic layer deposition or chemical vapor deposition, or a combination of several of them.

[0037] The cross-shaped trench structural unit referred to in this embodiment refers to a structure that has both axial symmetry and central symmetry and conforms to the pattern contour of the Chinese character "十". In particular, as Figure 3As shown, the corners of the trench structure unit, such as A and B, are rounded chamfered structures.

[0038] Figure 4 , 5 It shows in s > d Under certain conditions, the structural characteristics of conventional half-period staggered arrays and skewed close-packed arrays are described. The minimum linewidth of the structural unit is defined as... s The minimum spacing between the trench structure units is d At this point, the minimum linewidth in the half-cycle staggered array and the skewed close-packed array are not located at the same position. The capacitance density calculations for the two are as follows: See Figure 4 ,when s > d In this case, a conventional semi-periodic staggered array cross-shaped groove structure element has 4 long sides of equal length and 8 short sides of equal length. In this case, the short sides serve as the minimum linewidth, and their value is... s The length of the longer side is 2. s - d The capacitance density of a conventional half-cycle staggered array deep trench silicon capacitor is calculated as follows: Planar capacitance of a single column in a trench structure unit: Sidewall capacitance of a single column in a trench structure unit: Number of single columns per unit area of ​​trench structural unit: Capacitance density: .

[0039] See Figure 5 ,when s > d At this point, the diagonally tiled, closely spaced, cross-shaped groove structure unit has 4 short sides of equal length and 8 long sides of equal length. In this case, the short sides serve as the minimum linewidth, and their value is... s The length of the longer side is s+d The capacitance density of the deep trench silicon capacitor in the obliquely tiled close-packed array of this embodiment is calculated as follows: The planar capacitance of a single column in a trench structure unit is: Sidewall capacitance of a single column in a trench structure unit: Number of single columns per unit area of ​​trench structural unit: Capacitance density .

[0040] In the formula: It is the vacuum permittivity; It is the relative permittivity of the medium; The thickness of the dielectric layer; L It is the etching depth. When s > d It can be proven at that time. Therefore, capacitance density: skewed close-packed array > conventional half-cycle staggered array.

[0041] The proof is as follows: Known s and d It is a positive number, and s > d .

[0042]

[0043] To compare The magnitude of the comparison with 0 is used to determine the value of the comparison. The magnitude of 0 can be further converted into a judgment. The size of 1.

[0044]

[0045] By variable substitution, let ,in, t >1. Substitute into the above expression: .

[0046] Comparison is needed The comparison with 1 is used to determine the value of 1. .

[0047] Equivalent to: or

[0048] Because when t When the denominator is greater than 1, the direction of the inequality remains unchanged, so the function is defined as follows: .

[0049] Expand the calculation: , so: .

[0050] exist t When =1: .

[0051] Factorize: .

[0052] when t When >1, t -1>0, analyze the quadratic part Discriminant , root is Approximatelyt ≈-0.737 and t ≈-0.424. The quadratic function opens upwards (coefficient 16 > 0), therefore when t When >0.424, 16 t ²+5 t-5 and t- 1 > 0, therefore h ( t ) > 0. This means: f ( t )>1, t >1.

[0053] Therefore when s > d Time (i.e.) t >1), expression .

[0054] Figure 6 , 7 It shows in d ≥ s Under these conditions, the structural characteristics of conventional half-cycle staggered arrays and skewed close-packed arrays are analyzed. In this case, the minimum linewidth in both the half-cycle staggered array and the skewed close-packed array is located at the same position. The capacitance density calculations for both are as follows: See Figure 6 ,when d ≥ s In this case, a conventional half-cycle staggered array "cross-shaped groove structure unit" has 4 short sides of equal length and 8 long sides of equal length. At this point, the short sides serve as the minimum linewidth, and their value is... s The length of the longer side is ( s+d The capacitance density of a deep trench silicon capacitor in a conventional half-cycle staggered array is calculated as follows: Planar capacitance of a single column in a trench structure unit: ; Sidewall capacitance of a single column in a trench structure unit: ; Number of single columns per unit area of ​​trench structural unit: ; Capacitance density: .

[0055] See Figure 7 ,then d ≥ s At this point, the diagonally tiled, closely spaced cross-shaped groove structure unit has 4 short sides of equal length and 8 long sides of equal length. In this case, the short sides serve as the minimum linewidth, and their value is... s The length of the longer side is s+d The capacitance density of the deep trench silicon capacitor in the obliquely tiled close-packed array of this embodiment is calculated as follows: The planar capacitance of a single column in a trench structure unit is: ; Sidewall capacitance of a single column in a trench structure unit: ; Number of single columns per unit area of ​​trench structural unit: ; Capacitance density: .

[0056] In the formula: It is the vacuum permittivity; It is the relative permittivity of the medium; The thickness of the dielectric layer; L It refers to the etching depth.

[0057] at this time,

[0058] when d ≥ s It is easy to prove at that time. Capacitance density: skewed close-packed array ≥ conventional half-cycle staggered array.

[0059] Assumption s= 0.1 , d= 0.5 The etching aspect ratio is 40:1, that is... L=4 Based on the above expression, it can be calculated that the sidewall capacitance density of the skewed close-packed array is about 10% higher than that of the half-cycle staggered array.

[0060] Therefore, it can be seen that the deep trench silicon capacitor of the slanted dense array of the present invention has a higher capacitance density than the existing conventional half-cycle staggered array.

[0061] Figures 8-13 Gas velocity distribution diagrams are shown in conventional semi-periodic staggered arrays and skewed close-packed arrays. The experimental procedure involved taking... s= 0.5 , d= 0.1 as well as s= 0.1 , d= 0.5 (against s > d and d ≥ s (Two scenarios were considered), and gas flow velocity simulations were performed on both structures. The results are as follows: when s > d When, see Figure 8 , 10Significant and highly variable gas velocity non-uniformity is observed within each groove of a conventional half-cycle staggered array (represented by the red inverted triangle and yellow area in the figure). This leads to non-uniformity during film deposition, resulting in a film that is thicker in the center and gradually thins outwards. See [reference needed] Figure 9 , 11 In the structure of this invention, the central position has a large flow velocity (the red cross-shaped area in the figure), while other areas exhibit good flow velocity uniformity.

[0062] Similarly, d ≥ s When, see Figure 12 In conventional semi-period staggered arrays, significant gas velocity non-uniformity (large red areas in the figure) is observed in a large region within each strip trench, and the variation is substantial. This causes non-uniformity during film deposition, resulting in a phenomenon where the film is thicker in the center and gradually thins outwards. See also... Figure 9 , 11 In the structure of this invention, the central position has a large flow velocity (red square area in the figure), while other areas show good flow velocity uniformity.

[0063] Figure 14 , Figure 17 Simulation results of the pressure distribution along the vertical direction inside the trench are presented. It can be seen that, under all conditions, the pressure difference in the vertical direction inside the trench of the present invention is lower than that of the comparative structure. This indicates that the gas flow resistance in the trench of the comparative structure is significantly greater than that of the present invention, thus affecting the film deposition rate and the trench filling efficiency. High pressure at the top means a higher concentration of reactive gases, i.e., more concentrated reactants, resulting in a faster film deposition rate. For trenches with a high aspect ratio, overhangs will form at the top of the trench, ultimately leading to voids inside the trench and preventing dense filling.

[0064] The results from the above three dimensions indicate that, compared to the deep trench silicon capacitors in the prior art that use a half-cycle staggered array, the deep trench silicon capacitors in this embodiment of the invention, based on a cross-shaped structural unit with a slanted dense array, have better capacitance density, better thin film deposition effect, and better coverage.

[0065] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A deep trench silicon capacitor based on a diagonally tiled close-packed array of cross-shaped structural units, characterized in that, Several cross-shaped trench structure units are etched on a silicon substrate. These trench structure units are rotated by an angle α around their center axis and then spaced according to... d A close-packed array is formed by diagonal tiling, wherein the rotation is clockwise or counterclockwise, and the angle α satisfies... The d The minimum spacing between the trench structure units is defined as follows: the trench structure unit is provided with a single-layer capacitor dielectric structure or a multi-layer capacitor dielectric parallel structure.

2. A deep trench silicon capacitor based on a cross-shaped structural unit with a closely packed oblique array, as described in claim 1, is characterized in that... The diagonally laid cross-shaped groove structure unit has 4 short sides of equal length and 8 long sides of equal length, where the length of the short sides is... s The length of the longer side is s + d ; The planar capacitance of a single column in a trench structure unit is: The unit is F; Sidewall capacitance of a single column in a trench structure unit: The unit is F; the number of single columns in the trench structure unit per unit area: The unit is: 1 / m 2 Capacitance density: The unit is: F / m 2 ; In the formula: It is the vacuum permittivity, with units of F / m; It is the relative permittivity of the medium, which is a dimensionless constant; The thickness of the dielectric layer is expressed in meters (m). s The shorter side of the column is the minimum line width allowed by the process, in meters (m). d The interval between individual columns in the column groove structure unit is expressed in meters (m). L It is the etching depth, measured in meters (m).

3. A deep trench silicon capacitor based on a cross-shaped structural unit with a closely packed oblique array, as described in claim 1 or 2, characterized in that, The single-layer capacitor dielectric structure is arranged in an "electrode-dielectric-electrode" configuration, and the multilayer capacitor dielectric parallel structure is arranged in an "electrode-x (dielectric-electrode)" configuration, where x is an integer greater than 1.

4. A deep trench silicon capacitor based on a cross-shaped structural unit with a closely packed oblique array, as described in claim 3, is characterized in that... The electrode and the medium are formed by means of corresponding raw materials through atomic layer deposition or chemical vapor deposition.

5. A deep trench silicon capacitor based on a cross-shaped structural unit with a closely packed oblique array, as described in claim 3, is characterized in that... The raw material for the electrode is metal, heavily doped polycrystalline silicon, or low-resistivity monocrystalline silicon substrate.

6. A deep trench silicon capacitor based on a cross-shaped structural unit with a closely packed oblique array, as described in claim 3, is characterized in that... The raw material of the medium is any one or more of SiO2, Si3N4, Al2O3, HfO2, and ZrO2.

7. A deep trench silicon capacitor based on a cross-shaped structural unit with a closely packed oblique array, as described in claim 1 or 2, characterized in that, The corners of the cross-shaped groove structure unit are chamfered.

8. A deep trench silicon capacitor based on a cross-shaped structural unit with a closely packed oblique array, as described in claim 7, is characterized in that... The corners of the cross-shaped groove structure unit are rounded.

Images