Semiconductor element and forming method thereof

Abstract

The invention provides a semiconductor element. The semiconductor element comprises a substrate, a plurality of gate structures, a gap wall and a plurality of contact windows, the plurality of gate structures are disposed on the substrate. Each gate structure includes a tunneling dielectric layer and a word line stack disposed on the tunneling dielectric layer. The spacer is disposed on the tunneling dielectric layer and covers a sidewall of the word line stack. The plurality of contact windows are respectively disposed between the plurality of gate structures, wherein the tunneling dielectric layer includes protruding portions protruding outwardly from sidewalls of the spacer to the corresponding contact windows.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for forming the same. Background Technology

[0002] As semiconductor devices become smaller, more functional components can be integrated onto a single chip. Consequently, the linewidth in semiconductor devices is also shrinking to meet the demand for thinner and lighter electronic products. However, semiconductor manufacturing processes also face many challenges. For example, the shoulders of word line stacks can be damaged by subsequent etching processes, potentially leading to word line leakage. Summary of the Invention

[0003] This invention provides a semiconductor device including a substrate, a plurality of gate structures, spacers, and a plurality of contact windows. The plurality of gate structures are disposed on the substrate. Each gate structure includes a tunneling dielectric layer and word lines stacked on the tunneling dielectric layer. Spacers are disposed on the tunneling dielectric layer and cover the sidewalls of the word lines stack. A plurality of contact windows are respectively disposed between the plurality of gate structures, wherein the tunneling dielectric layer includes protrusions extending outward from the sidewalls of the spacers to the corresponding contact windows.

[0004] The present invention provides a method for forming a semiconductor device, comprising forming a dielectric layer on a substrate; forming a plurality of word line stacks and a gap wall covering the sidewalls of the plurality of word line stacks on the dielectric layer; forming a sacrificial material between the plurality of word line stacks; removing the sacrificial material to form a plurality of first openings, wherein the plurality of first openings expose the surface of the dielectric layer; forming a protective layer to cover the sidewalls of the gap wall and the bottom surface of the plurality of first openings; with the protective layer in place, performing a first etching process to remove the protective layer and the dielectric layer at the bottom of the plurality of first openings to form a plurality of second openings in the dielectric layer exposing the top surface of the substrate; and forming a plurality of contact windows in the plurality of first openings and the plurality of second openings respectively.

[0005] Based on the above, after removing the sacrificial material between multiple word line stacks, the embodiments of the present invention form a protective layer to cover the surface of the multiple word line stacks, so as to avoid subsequent etching processes damaging the shoulders and sidewalls of the multiple word line stacks, which can effectively solve the existing word line leakage problem and thus improve the yield and reliability of semiconductor devices. Attached Figure Description

[0006] Figures 1A to 1E and Figures 2A to 2B This is a cross-sectional schematic diagram of the manufacturing process of semiconductor devices according to different embodiments of the present invention. Detailed Implementation

[0007] Figures 1A to 1E This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor device according to the first embodiment of the present invention.

[0008] Please refer to Figure 1A This embodiment provides a semiconductor element 1 (such as...) Figure 1E The manufacturing method (shown) comprises the following steps. First, an initial structure 1a is provided, which includes a substrate 100, a dielectric layer 102, a plurality of word line stacks 111, and at least one second gate structure 210. The substrate 100 may include a first region R1 and a second region R2. The first region R1 may be a unit cell region, and the second region R2 may be a peripheral region. The substrate 100 may be a semiconductor substrate, a semiconductor compound substrate, or a semiconductor over insulator (SOI) substrate. The substrate 100 may be a silicon substrate.

[0009] The dielectric layer 102 can be disposed on the substrate 100 of the first region R1. The material of the dielectric layer 102 can be, for example, silicon oxide, and its formation method can be chemical vapor deposition (CVD), thermal oxidation, etc. The dielectric layer 102 can be subsequently patterned to form a tunneling dielectric layer 112 (e.g., Figure 1D (As shown).

[0010] Multiple word line stacks 111 may be configured on dielectric layer 102 to form multiple first gate structures 110. The first gate structures 110 may be flash memory structures. Specifically, each word line stack 111 may sequentially include, from bottom to top, a first conductor layer 114, an inter-gate dielectric layer 116, a second conductor layer 118, a third conductor layer 120, a first capping layer 122, and a second capping layer 124. The material of the first conductor layer 114 may be, for example, doped polysilicon, undoped polysilicon, or a combination thereof, and its formation method may be chemical vapor deposition. The inter-gate dielectric layer 116 may be, for example, a composite layer composed of oxide / nitride / oxide (ONO), but the invention is not limited thereto; this composite layer may have three, five, or more layers; the formation method of the inter-gate dielectric layer 116 may be, for example, chemical vapor deposition. The material of the second conductor layer 118 may be, for example, doped polycrystalline silicon, undoped polycrystalline silicon, or a combination thereof, and it may be formed by chemical vapor deposition. The material of the third conductor layer 120 may include a metallic material, such as W, Cu, or AlCu, and it may be formed by physical vapor deposition. The materials of the first capping layer 122 and the second capping layer 124 may include dielectric materials, such as silicon nitride, silicon oxynitride, or a combination thereof, and they may be formed by chemical vapor deposition. The first capping layer 122 and the second capping layer 124 may include different dielectric materials. For example, the first capping layer 122 is a silicon nitride layer, while the second capping layer 124 is a silicon oxide layer.

[0011] At least one second gate structure 210 may be disposed on the substrate 100 of the second region R2. Specifically, the second gate structure 210 may sequentially include, from bottom to top, a gate dielectric layer 212, a fourth conductor layer 214, a fifth conductor layer 216, a third capping layer 218, and a fourth capping layer 220. The material of the gate dielectric layer 212 may be, for example, silicon oxide, and its formation method may be chemical vapor deposition, thermal oxidation, etc. The material of the fourth conductor layer 214 may include a conductor material, such as doped polysilicon, undoped polysilicon, or a combination thereof, and its formation method may be chemical vapor deposition. The material of the fifth conductor layer 216 may include a metallic material, such as W, Cu, AlCu, etc., and its formation method may be physical vapor deposition. The materials of the third capping layer 218 and the fourth capping layer 220 may include dielectric materials, such as silicon nitride, silicon oxynitride, or a combination thereof, and their formation method may be chemical vapor deposition. The third capping layer 218 and the fourth capping layer 220 may include different dielectric materials. For example, the third capping layer 218 is a silicon nitride layer, while the fourth capping layer 220 is a silicon oxide layer.

[0012] The first gate structure 110 and the second gate structure 210 may have different dimensions, such as different heights and / or different widths. Furthermore, the thickness of the gate dielectric layer 212 of the second gate structure 210 may differ from the thickness of the dielectric layer 102 of the first gate structure 110. Moreover, although... Figure 1A Only a single second gate structure 210 is shown, but the invention is not limited thereto. The number of second gate structures 210 can be adjusted as needed.

[0013] like Figure 1A As shown, the initial structure 1a also includes spacers 126 and 226, a sacrificial material 130, a stop layer 228, an interlayer dielectric (ILD) layer 230, and a planarization layer 232. Specifically, spacer 126 may be formed on the dielectric layer 102 of the first region R1 and cover the sidewalls of the plurality of word line stacks 111. On the other hand, spacer 226 may be formed on the second region R2 and cover the sidewalls of the second gate structure 210. Spacers 126 and 226 may include a single-layer structure, a double-layer structure, or a multi-layer structure. For example, spacers 126 and 226 each include a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0014] Sacrificial material 130 can be formed between multiple word line stacks 111. Specifically, sacrificial material 130 can fill the spaces between the multiple word line stacks 111 to... Figure 1A The cross-section is T-shaped. The material of the sacrificial material 130 may include a conductive material, such as doped polycrystalline silicon, undoped polycrystalline silicon, or a combination thereof, and may be formed by chemical vapor deposition.

[0015] The stop layer 228 may conformally cover the second gate structure 210 and the sidewalls of the word line stack 111 adjacent to the second region R2. The material of the stop layer 228 may include a dielectric material, such as a nitrogen-containing dielectric material like silicon nitride or silicon oxynitride, and it may be formed by chemical vapor deposition.

[0016] The interlayer dielectric layer 230 may be formed on the stop layer 228 of the second region R2 and on the stop layer 228 of the sidewall of the word line stack 111 adjacent to the second region R2. The material of the interlayer dielectric layer 230 includes silicon oxide, low-k dielectric materials, and other dielectric materials. Here, low-k dielectric material means a dielectric constant less than or equal to 4.

[0017] The planarization layer 232 may be formed on the interlayer dielectric layer 230 and the sacrificial material 130, and extends to cover a portion of the top surface of the word line stack 111. The material of the planarization layer 232 may be, for example, silicon nitride, and it may be formed by chemical vapor deposition.

[0018] Please refer to Figure 1B The sacrificial material 130 is removed to form a plurality of first openings 141. Specifically, the planarization layer 232 is first removed to expose the sacrificial material 130, and then the sacrificial material 130 is removed to expose the surface of the dielectric layer 102. That is, the first openings 141 can expose the surface of the dielectric layer 102 and the surface of the gap wall 126 of the sidewall of the overlay word line stack 111. In this case, as Figure 1B As shown, the remaining planarization layer 132 on the first region R1 is formed on a portion of the top surface of the word line stack 111 to separate the first opening 141.

[0019] Please refer to Figure 1C A protective material 140 is formed to cover the sidewalls of the spacer wall 126 and the bottom surface of the first opening 141. Specifically, the protective material 140 may cover the surface of the first opening 141, the surface of the planarization layer 132, and the surface of the planarization layer 232. The protective material 140 may include a barrier metal (e.g., Ti, TiN, Ta, TaN, etc.), and its formation method may be a radio frequency magnetron sputtering (RF) deposition process. It is worth noting that the protective material 140 formed by the RF deposition process has poor step coverage. That is, the thickness T1 of the protective material 140 covering the sidewalls of the first opening 141 (or the spacer wall 126) is less than the thickness T2 of the protective material 140 covering the bottom surface of the first opening 141. The step coverage of the protective material 140 is between 20% and 50%, where the step coverage is defined as the ratio of thickness T1 to thickness T2 (T1 / T2).

[0020] Please refer to Figure 1C and Figure 1D With the protective material 140 in place, a first etching process is performed to remove the protective material 140 and dielectric layer 102 at the bottom of the first opening 141, thereby forming a plurality of second openings 142 in the dielectric layer 112 that expose the top surface of the substrate 100. The first etching process can be a dry etching process, such as reactive ion etching (RIE). Specifically, the first etching process includes a first etching step and a second etching step. The first etching step is used to remove a portion of the protective material 140, while the second etching step is used to remove a portion of the dielectric layer 102. Therefore, the first etching step and the second etching step can use different etching gases. For example, when the protective material 140 is TiN and the dielectric layer 102 is silicon oxide, the first etching step includes a chlorine-based etching gas, while the second etching step includes a fluorine-based etching gas. In addition to the protective material 140 at the bottom of the first opening 141, the first etching process also removes the protective material 140 from the top surface of the planarization layer 132 and the top surface of the spacer wall 126 (or the shoulder of the word line stack 111). It is worth noting that because the second etching step has high etching selectivity for the dielectric layer 112, the protective material 140 can protect the shoulder and sidewalls of the word line stack 111 from damage by the first etching process, thus maintaining the shape of the word line stack 111 and preventing word line leakage. Here, high etching selectivity means that in the second etching step, a large amount of the dielectric layer 102 can be removed without removing or with minimal removal of the protective material 140. Therefore, the spacer wall 126 and the second top cap layer 124 covered by the protective material 140 are not removed during the second etching step to maintain the shape of the word line stack 111.

[0021] Therefore, after the first etching process, the dielectric layer 102 is patterned into a tunneling dielectric layer 112, and the protective material 140 is patterned into a protective layer 144, as shown below. Figure 1D As shown. A protective layer 144 may be disposed on the tunneling dielectric layer 112 and cover the sidewalls of the spacer wall 126. Notably, the tunneling dielectric layer 112 has a protrusion 112p, which protrudes outward from the sidewall of the spacer wall 126 to the second opening 142. That is, the lateral width W1 of the tunneling dielectric layer 112 may be greater than the lateral width W2 of the pair of spacer walls 126. The first opening 141 is spatially connected to the corresponding second opening 142 to form a combined opening 145. Furthermore, after the first etching process, the bottom width of the first opening 141 is the same as the average width of the corresponding second opening 142.

[0022] Please refer to Figure 1D and Figure 1EA metal silicide layer 146 is formed at the bottom of the combined opening 145 to contact the substrate 100. The material of the metal silicide layer 146 includes cobalt silicide (CoSi), and it can be formed by a metal silicide process. Next, a plurality of contact windows 150 are formed in the combined opening 145 (including the first opening 141 and the second opening 142) to complete the semiconductor device 1. Specifically, after forming the metal silicide layer 146, a liner 152 is formed to cover the protective layer 144, the protrusion 112p of the tunneling dielectric layer 112, and the metal silicide layer 146. Then, a metal material 154 is formed on the liner 152 to fill the combined opening 145, thereby completing the contact windows 150.

[0023] The material of the substrate 152 includes a barrier metal (e.g., Ti, TiN, Ta, TaN, etc.), and it can be formed by chemical vapor deposition. Unlike the RF deposition process described above, the substrate 152 formed by this chemical vapor deposition method has a better step coverage. That is, the substrate 152 can be considered as a conformal layer with uniform thickness. The step coverage of the substrate 152 is between 95% and 99%. In one embodiment, the metal material 154 may include W, Cu, AlCu, etc., and it can be formed by physical vapor deposition. In addition, after depositing the metal material 154, a planarization process (e.g., CMP process) can be performed to remove excess metal material 154 above the planarization layer 132 to avoid short circuits between the contact windows 150 between adjacent word line stacks 111. In this case, the top surface of the contact window 150 can be substantially coplanar with the top surface of the planarization layer 132.

[0024] It is worth noting that the liner 152 and the protective layer 144 may have the same material, such as TiN. The liner 152 and the protective layer 144 can be considered as a combined liner 155 having a film of the same material. Furthermore, the protective layer 144 only covers the sidewalls of the spacer wall 126 and does not cover the bottom surface of the combined opening 145, and the liner 152 conformally covers both the protective layer 144 and the combined opening 145. Therefore, the thickness T3 of the combined liner 155 covering the sidewalls of the spacer wall 126 can be greater than the thickness T4 of the combined liner 155 covering the metal silicide layer 146. The ratio of thickness T3 to thickness T4 can be between 1.2 and 1.5.

[0025] This embodiment provides a semiconductor device 1 including: a substrate 100, a plurality of first gate structures 110, a spacer wall 126, and a plurality of contact windows 150. Each first gate structure 110 may include: a tunneling dielectric layer 112 and a word line stack 111 disposed on the tunneling dielectric layer 112. The spacer wall 126 may be disposed on the tunneling dielectric layer 112 and cover the sidewalls of the word line stack 126. The plurality of contact windows 150 may be respectively disposed between the plurality of first gate structures 110. The tunneling dielectric layer 112 includes a protrusion 112p protruding outward from the sidewall of the spacer wall 126 to the corresponding contact window 150. Each contact window 150 may include a combined liner 155 and a metal material 152. The combined liner 155 may cover the sidewall of the spacer wall 126, the protrusion 112p of the tunneling dielectric layer 112, and the top surface of the substrate 100. Metal material 152 is disposed on composite substrate 155 such that composite substrate 155 surrounds metal material 152. Semiconductor device 1 further includes a metal silicide layer 146 vertically disposed between the top surface of substrate 100 and composite substrate 155. Contact window 150 may be a source / drain contact window for electrical connection to source / drain regions (not shown) in substrate 100 via metal silicide layer 146.

[0026] Figures 2A to 2B This is a cross-sectional schematic diagram of the manufacturing process of a semiconductor device according to the second embodiment of the present invention.

[0027] by Figure 1D Structure Figures 2A to 2B The manufacturing steps. Please refer to... Figure 1D and Figure 2A A second etching process is then performed to completely remove the protective layer 144, thereby exposing the sidewalls of the spacer wall 126. This second etching process can be a wet etching process, which has high etching selectivity for the protective layer 144. Therefore, during the second etching process, the protective layer 144 can be completely removed without removing or only partially removing the spacer wall 126. Since the protrusion 112p of the tunneling dielectric layer 112 protrudes outward from the sidewall of the spacer wall 126 to the second opening 142, the width W3 of the first opening 141 can be greater than the width W4 of the second opening 142 after the protective layer 144 is completely removed.

[0028] Please refer to Figure 2A and Figure 2BA metal silicide layer 146 is formed at the bottom of the combined opening 145 to contact the substrate 100. It is noteworthy that because the first opening 141 has a large width W3 due to the absence of a protective layer 144, the metal silicide layer 146 can completely contact the top surface of the substrate 100. In this case, the metal silicide layer 146 can have a large contact area to reduce the contact resistance between the source / drain regions (not shown) in the substrate 100 and the subsequently formed contact windows 150. Next, a plurality of contact windows 150 are formed in the combined opening 145 to complete the semiconductor device 2. Specifically, after forming the metal silicide layer 146, a liner 152 is formed to cover the spacer wall 126, the protrusion 112p of the tunneling dielectric layer 112, and the metal silicide layer 146. Then, a metal material 154 is formed on the liner 152 to fill the combined opening 145, thereby completing the contact windows 150.

[0029] The material of the liner 152 includes a barrier metal (e.g., Ti, TiN, Ta, TaN, etc.), and it can be formed by chemical vapor deposition. Unlike the RF deposition process described above, the liner 152 formed by this chemical vapor deposition method has a better stepped coverage. That is, the liner 152 can be considered as a conformal layer with uniform thickness. Therefore, the thickness T5 of the liner 152 covering the sidewall of the spacer wall 126 can be substantially equal to the thickness T6 of the liner 152 covering the metal silicide layer 146. The metal material 154 can include W, Cu, AlCu, etc., and it can be formed by physical vapor deposition.

[0030] In summary, after removing the sacrificial material between multiple word line stacks, the embodiments of the present invention form a protective layer to cover the surfaces of the multiple word line stacks, thereby preventing subsequent etching processes from damaging the shoulders and sidewalls of the multiple word line stacks. In this way, the embodiments of the present invention can effectively solve the existing word line leakage problem, thereby improving the yield and reliability of semiconductor devices.

Claims

1. A semiconductor element, comprising: Multiple gate structures are disposed on a substrate, wherein each gate structure includes: Tunneling dielectric layer; and Word lines are stacked and configured on the tunneling dielectric layer; A spacer wall, disposed on the tunneling dielectric layer and covering the sidewalls of the word line stack; and Multiple contact windows are respectively disposed between the multiple gate structures, wherein the tunneling dielectric layer includes a protrusion that extends outward from the sidewall of the gap wall to the corresponding contact window.

2. The semiconductor element of claim 1, wherein each contact window comprises: A liner covering the sidewalls of the gap wall, the protrusions of the tunneling dielectric layer, and the top surface of the substrate; as well as Metallic material is disposed on the liner.

3. The semiconductor device of claim 2, wherein the first thickness of the liner covering the sidewall of the gap wall is greater than the second thickness of the liner covering the top surface of the substrate.

4. The semiconductor element of claim 2, wherein the first thickness of the liner covering the sidewall of the gap wall is substantially equal to the second thickness of the liner covering the top surface of the substrate.

5. The semiconductor device according to claim 2, further comprising: A metal silicide layer is vertically disposed between the top surface of the substrate and the liner.

6. A method for forming a semiconductor device, comprising: A dielectric layer is formed on the substrate; Multiple word line stacks and gap walls covering the sidewalls of the multiple word line stacks are formed on the dielectric layer; Sacrificial material is formed between the stacks of the multiple word lines; The sacrificial material is removed to form a plurality of first openings, wherein the plurality of first openings expose the surface of the dielectric layer; A protective layer is formed to cover the sidewalls of the gap wall and the bottom surface of the plurality of first openings; With the protective layer in place, a first etching process is performed to remove the protective layer and the dielectric layer at the bottom of the plurality of first openings, so as to form a plurality of second openings in the dielectric layer that expose the top surface of the substrate; as well as Multiple contact windows are formed in the plurality of first openings and the plurality of second openings, respectively.

7. The method for forming a semiconductor device according to claim 6, wherein after performing the first etching process, the method further comprises: A second etching process is performed to completely remove the protective layer, thereby exposing the sidewalls of the spacer wall.

8. The method for forming a semiconductor element according to claim 7, wherein after the second etching process, the width of the first opening is greater than the width of the second opening.

9. The method of forming a semiconductor element according to claim 6, wherein after the first etching process, a plurality of tunneling dielectric layers are formed between the plurality of word line stacks and the substrate, and each tunneling dielectric layer includes a protrusion extending outward from the sidewall of the spacer wall to a corresponding contact window.

10. The method of forming a semiconductor element according to claim 9, wherein each contact window comprises: A liner covering the sidewalls of the gap wall, the protrusions of the tunneling dielectric layer, and the top surface of the substrate; as well as Metallic material is disposed on the liner.

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