Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate, a first dielectric layer is formed on the substrate, and a front-layer interconnection structure is formed in the first dielectric layer; the second dielectric layer is located at the top of the first dielectric layer and the top of the front-layer interconnection structure, and the second dielectric layer exposes the top of the front-layer interconnection structure; the interconnection structures are located in the second dielectric layer, and the bottoms of the interconnection structures make contact with the tops of the corresponding interconnection structures on the front layer; and the adhesion barrier layer is located between the side wall of the interconnection structure and the second dielectric layer. According to the embodiment of the invention, the adhesion barrier layer is located between the side wall of the interconnection structure and the second dielectric layer, the top of the front layer interconnection structure is exposed, and the bottom of the interconnection structure is in contact with the top of the corresponding front layer interconnection structure, so that the bottom of the interconnection structure is not provided with the adhesion barrier layer, the resistance of the interconnection structure is reduced, and the reliability of the interconnection structure is improved. RC delay caused by resistors and capacitors in the semiconductor structure is correspondingly improved, and the electrical performance of the semiconductor structure is further improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In recent years, with the development of integrated circuit technology, the integration level of integrated circuits and semiconductor technology have made great progress. In semiconductor manufacturing processes, as the size of integrated circuits continues to shrink, the linewidth of the metal interconnect structure in the back-end of line (BEOL) process is also continuously decreasing.

[0003] The formation of metal interconnect structures in the back-end process typically includes the formation of via structures and metal lines, but the yield and performance of metal interconnect structures currently need to be improved. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate on which a first dielectric layer is formed, wherein a front interconnect structure is formed in the first dielectric layer; a second dielectric layer located on top of the first dielectric layer and the front interconnect structure, wherein the second dielectric layer exposes the top of the front interconnect structure; an interconnect structure located in the second dielectric layer, wherein the bottom of the interconnect structure contacts the top of the corresponding front interconnect structure; and an adhesion barrier layer located between the sidewall of the interconnect structure and the second dielectric layer.

[0006] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a first dielectric layer is formed on the substrate, and a front interconnect structure is formed in the first dielectric layer; forming a second dielectric layer covering the first dielectric layer and the front interconnect structure, wherein an opening is formed in the second dielectric layer exposing the top of the front interconnect structure; forming an adhesion barrier layer on the sidewall of the opening, wherein the adhesion barrier layer exposes the top of the front interconnect structure; and after forming the adhesion barrier layer, forming an interconnect structure in the opening, wherein the bottom of the interconnect structure contacts the top of the corresponding front interconnect structure.

[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0008] This invention provides a semiconductor structure comprising: a substrate on which a first dielectric layer is formed, wherein a front interconnect structure is formed; a second dielectric layer located on top of the first dielectric layer and the front interconnect structure, wherein the second dielectric layer exposes the top of the front interconnect structure; an interconnect structure located in the second dielectric layer, wherein the bottom of the interconnect structure contacts the top of the corresponding front interconnect structure; and an adhesion barrier layer located between the sidewall of the interconnect structure and the second dielectric layer. Because the adhesion barrier layer in this embodiment is located between the sidewall of the interconnect structure and the second dielectric layer, exposing the top of the front interconnect structure, and the bottom of the interconnect structure contacts the top of the corresponding front interconnect structure, there is no adhesion barrier layer at the bottom of the interconnect structure. This reduces the resistance of the interconnect structure, correspondingly improving the RC delay caused by resistance (R) and capacitance (C) in the semiconductor structure, thereby improving the electrical performance of the semiconductor structure.

[0009] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate, on which a first dielectric layer is formed, and a front interconnect structure is formed in the first dielectric layer; forming a second dielectric layer covering the first dielectric layer and the front interconnect structure, the second dielectric layer having an opening exposing the top of the front interconnect structure; forming an adhesion barrier layer on the sidewall of the opening, the adhesion barrier layer exposing the top of the front interconnect structure; and after forming the adhesion barrier layer, forming an interconnect structure in the opening, the bottom of the interconnect structure contacting the top of the corresponding front interconnect structure. Because the adhesion barrier layer in this embodiment is located between the sidewall of the interconnect structure and the second dielectric layer, exposing the top of the front interconnect structure, and the bottom of the interconnect structure contacting the top of the corresponding front interconnect structure, there is no adhesion barrier layer at the bottom of the interconnect structure. This reduces the contact resistance between the interconnect structure and the front interconnect structure, correspondingly improving the RC delay caused by resistance and capacitance in the semiconductor structure, thereby improving the electrical performance of the semiconductor structure.

[0010] In an optional embodiment, after forming the opening and before forming the adhesion barrier layer, the method further includes: performing a first modification treatment on the top of the front interconnect structure exposed by the opening to reduce the surface contact angle of the top of the front interconnect structure. In this embodiment, performing a first modification treatment on the top of the front interconnect structure exposed by the opening before forming the adhesion barrier layer reduces the surface contact angle of the top of the front interconnect structure, thereby reducing the probability of the adhesion barrier layer being deposited on the exposed top of the front interconnect structure during the subsequent adhesion barrier layer deposition process, and thus increasing the probability of the bottom of the interconnect structure contacting the top of the front interconnect structure.

[0011] In an optional embodiment, after forming the adhesion barrier layer and before forming the interconnect structure, the method further includes: performing a second modification treatment on the modified layer on the top of the exposed front interconnect structure to restore the modified layer to the original front interconnect structure. In this embodiment, performing a second modification treatment on the modified layer on the exposed top of the front interconnect structure after forming the adhesion barrier layer restores the modified layer to the original front interconnect structure, i.e., restoring the surface contact angle to the same level as the front interconnect structure. This increases the probability of material deposition onto the exposed top of the front interconnect structure during subsequent interconnect structure formation processes, thereby improving the contact effect between the bottom of the interconnect structure and the top of the front interconnect structure, and reducing the contact resistance between the interconnect structure and the front interconnect structure. Attached Figure Description

[0012] Figures 1 to 11 A schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure;

[0013] Figure 12 This is a schematic diagram of a semiconductor structure embodiment of the present invention;

[0014] Figures 13 to 26 This is a schematic diagram of the structure corresponding to each step in the embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0015] Currently, the performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a specific semiconductor structure and its formation method as an example. Figures 1 to 11 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0016] refer to Figure 1 A substrate (not shown) is provided, on which a first dielectric layer 11 is formed, and a front-layer interconnect structure 12 is formed in the first dielectric layer 11.

[0017] Continue to refer to Figure 1 A first stop layer 21 is formed covering the first dielectric layer 11 and the front interconnect structure 12; a second dielectric layer 13 is formed covering the first stop layer 21; a second stop layer 22 is formed covering the second dielectric layer 13; and a hard mask material layer 23A is formed covering the second stop layer 22.

[0018] refer to Figure 2 Using the top surface of the second stop layer 22 as the stop position, the hard mask material layer 23A is patterned to form a hard mask layer 23, and a groove 28 is formed in the hard mask layer 23 to expose the top surface of the second stop layer 22.

[0019] refer to Figure 3The groove 28 is graphically represented (e.g., Figure 2 The second stop layer 22 at the bottom (shown) has a groove 29 formed in the second stop layer 22 to expose the second medium layer 13. The opening size of the groove 29 is smaller than the opening size of the groove 28.

[0020] refer to Figure 4 After the trench 29 is formed, the second stop layer 22 and the second dielectric layer 13 are patterned along the groove 28 to form a first opening 30 in the second dielectric layer 13. The first opening 30 exposes the top of the stop layer 21. The first opening 30 includes an interconnect groove (not shown) and a through hole (not shown) located at the bottom of the interconnect groove.

[0021] refer to Figure 5 Remove the hard mask layer 23.

[0022] refer to Figure 6 The first stop layer 21 is patterned along the first opening 30 to form a second opening 31 that exposes the top of the front layer interconnect structure 12.

[0023] refer to Figure 7 A barrier layer 14 is formed on the sidewall and bottom of the second opening 31.

[0024] refer to Figure 8 A conformal adhesive layer 17 is formed on the barrier layer 14.

[0025] refer to Figure 9 A conformal seed layer 15 is formed on the adhesion layer 17.

[0026] refer to Figure 10 After the seed layer 15 is formed, an interconnect structure material layer 16A is formed in the second opening 31.

[0027] refer to Figure 11 The interconnect structure material layer 16A and the seed layer 15 are planarized to form the interconnect structure 16.

[0028] Research has found that, for example Figure 11 As shown, the barrier layer 14 and the adhesion layer 17 are located between the bottom of the interconnect structure 16 and the second dielectric layer 13. Therefore, the barrier layer 14 and the adhesion layer 17 are located between the interconnect structure 16 and the previous interconnect structure 12, thereby increasing the resistance of the interconnect structure 16, which in turn increases the RC delay caused by resistance and capacitance in the semiconductor structure, and thus reduces the electrical performance of the semiconductor structure.

[0029] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate on which a first dielectric layer is formed, wherein a front interconnect structure is formed in the first dielectric layer; a second dielectric layer located on top of the first dielectric layer and the front interconnect structure, wherein the second dielectric layer exposes the top of the front interconnect structure; an interconnect structure located in the second dielectric layer, wherein the bottom of the interconnect structure contacts the top of the corresponding front interconnect structure; and an adhesion barrier layer located between the sidewall of the interconnect structure and the second dielectric layer.

[0030] In the solution disclosed in the embodiments of the present invention, since the adhesion barrier layer is located between the sidewall of the interconnect structure and the second dielectric layer, exposing the top of the front interconnect structure, and the bottom of the interconnect structure is in contact with the top of the corresponding front interconnect structure, there is no adhesion barrier layer at the bottom of the interconnect structure, thereby reducing the resistance of the interconnect structure, correspondingly improving the RC delay caused by resistance and capacitance in the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0031] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] Figure 12 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0033] refer to Figure 12 The semiconductor structure includes: a substrate (not shown), on which a first dielectric layer 101 is formed, and a front interconnect structure 102 is formed in the first dielectric layer 101; a second dielectric layer 103 located on top of the first dielectric layer 101 and the front interconnect structure 102, and the second dielectric layer 103 exposing the top of the front interconnect structure 102; an interconnect structure 104 located in the second dielectric layer 103, the bottom of the interconnect structure 104 contacting the top of the corresponding front interconnect structure 102; and an adhesion barrier layer 105 located between the sidewall of the interconnect structure 104 and the second dielectric layer 103.

[0034] The substrate serves as a process platform for forming semiconductor structures. Depending on the specific process, the substrate includes a substrate (not shown) and functional structures formed on the substrate, such as semiconductor devices like MOS field-effect transistors, resistor structures, etc.

[0035] In this embodiment, the substrate includes a substrate. As an example, the substrate is a silicon substrate. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, and may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0036] The first dielectric layer 101 is used to achieve electrical isolation between adjacent front-layer interconnect structures 102.

[0037] In this embodiment, the material of the first dielectric layer 101 is an insulating material, including low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6), which can effectively reduce the parasitic capacitance between interconnect structures and thus reduce the RC delay of the device.

[0038] As an example, the material of the first dielectric layer 101 is a low-k dielectric material, such as black diamond (BD). In other embodiments, the material of the first dielectric layer may also be SiOCH.

[0039] The front interconnect structure 102 is used to make an electrical connection with the interconnect structure 104.

[0040] In this embodiment, the material of the front-layer interconnect structure 102 is copper. Copper has low resistivity, which helps reduce the RC delay of the device, and copper also has excellent electromigration resistance. In other embodiments, depending on actual process requirements, the material of the front-layer interconnect structure can also be a metal such as aluminum or tungsten.

[0041] The second dielectric layer 103 is used to provide a process platform for forming the interconnect structure 104 and also to insulate adjacent interconnect structures 104 from each other.

[0042] In this embodiment, the material of the second dielectric layer 103 is an insulating material, including low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6), which can effectively reduce the parasitic capacitance between interconnect structures and thus reduce the RC delay of the device.

[0043] As an example, the material of the second dielectric layer 103 is a low-k dielectric material, for example, the material of the second dielectric layer 103 is black diamond. In other embodiments, the material of the second dielectric layer may also be SiOCH.

[0044] Interconnection structure 104 is used to achieve electrical connection with the previous layer interconnection structure 102.

[0045] It should be noted that the material of interconnect structure 104 is the same as that of the preceding interconnect structure 102. In this embodiment, the material of interconnect structure 104 is copper. Copper has good electrical conductivity and low resistance, which is beneficial for obtaining an interconnect structure 104 with good conductivity.

[0046] In some embodiments, the material of interconnect structure 104 may be different from the material of the preceding interconnect structure 102. In other embodiments, depending on actual process requirements, the material of the interconnect structure may also be a metal such as aluminum or tungsten.

[0047] The interconnection structure 104 can be a single damascene structure or a dual damascene structure.

[0048] In this embodiment, the interconnect structure 104 includes an interconnect layer 104A and a via structure 104B located between the interconnect layer 104A and the previous interconnect structure 102.

[0049] Interconnect layer 104A is used to make electrical connections with via structure 104B.

[0050] The via structure 104B is used to connect the interconnect layer 104A and the front interconnect structure 102, thereby realizing the electrical connection between the interconnect layer 104A and the internal circuit of the semiconductor structure.

[0051] In this embodiment of the invention, the adhesion barrier layer 105 is located between the sidewall of the interconnect structure 104 and the second dielectric layer 103.

[0052] It should be noted that, since the adhesion barrier layer 105 is located between the sidewall of the interconnect structure 104 and the second dielectric layer 103, exposing the top of the front interconnect structure 102, and the bottom of the interconnect structure 104 is in contact with the top of the corresponding front interconnect structure 102, there is no adhesion barrier layer 105 at the bottom of the interconnect structure 104. This reduces the resistance of the interconnect structure 104, thereby improving the RC delay caused by resistance and capacitance in the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0053] In this embodiment, the adhesion barrier layer 105 includes: a barrier layer 105A, located between the sidewall of the interconnect structure 104 and the second dielectric layer 103, and exposing the top of the front interconnect structure 102; and an adhesion layer 105B, located between the sidewall of the interconnect structure 104 and the barrier layer 105A.

[0054] The barrier layer 105A serves to block the diffusion of metal ions in the interconnect structure 104.

[0055] In this embodiment, the material of the barrier layer 105A includes one or both of tantalum nitride and tantalum.

[0056] Specifically, tantalum nitride and tantalum materials can effectively block ion diffusion.

[0057] The adhesive layer 105B is used to improve the adhesion between the barrier layer 105A and the interconnect structure 104.

[0058] In this embodiment, the material of the adhesion layer 105B includes cobalt, molybdenum, ruthenium, tungsten, or zinc.

[0059] Specifically, cobalt, molybdenum, ruthenium, tungsten, and zinc all have low resistivity, which helps to reduce the resistance of the interconnect structure 104 and improve the performance of the semiconductor structure. At the same time, cobalt, molybdenum, ruthenium, tungsten, and zinc all have good wettability, which helps to form a uniform and pore-free interconnect structure 104 and improve the quality of the interconnect structure 104.

[0060] In this embodiment, the semiconductor structure further includes a bottom stop layer 106, located between the second dielectric layer 103 and the first dielectric layer 101, and between the second dielectric layer 103 and the front interconnect structure 102.

[0061] The top surface of the bottom stop layer 106 is used to define the etching stop position for etching the second dielectric layer 103.

[0062] In this embodiment, the material of the bottom stop layer 106 includes a low-k dielectric material. Specifically, a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9.

[0063] As an example, low-k dielectric materials include carbon-doped silicon dioxide or carbon-doped silicon nitride.

[0064] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 13 to 26 This is a schematic diagram of the structure corresponding to each step in the embodiment of the semiconductor structure formation method of the present invention.

[0065] refer to Figure 13 A substrate (not shown) is provided, on which a first dielectric layer 501 is formed, and a front-layer interconnect structure 502 is formed in the first dielectric layer 501.

[0066] The substrate serves as a process platform for forming semiconductor structures. Depending on the specific process, the substrate includes a substrate (not shown) and functional structures formed on the substrate, such as semiconductor devices like MOS field-effect transistors, resistor structures, etc.

[0067] In this embodiment, the substrate includes a substrate. As an example, the substrate is a silicon substrate. In other embodiments, the substrate material may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride, and may also be other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates.

[0068] The first dielectric layer 501 is used to achieve electrical isolation between adjacent front-layer interconnect structures 502.

[0069] In this embodiment, the material of the first dielectric layer 501 is an insulating material, including low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6), which can effectively reduce the parasitic capacitance between interconnect structures and thus reduce the RC delay of the device.

[0070] As an example, the material of the first dielectric layer 501 is a low-k dielectric material, for example, the material of the first dielectric layer 501 is black diamond. In other embodiments, the material of the first dielectric layer may also be SiOCH.

[0071] The front-end interconnect structure 502 is used to make electrical connections with the subsequently formed interconnect structure.

[0072] In this embodiment, the material of the front-layer interconnect structure 502 is copper. Copper has low resistivity, which helps reduce the RC delay of the device, and copper also has excellent electromigration resistance. In other embodiments, depending on actual process requirements, the material of the front-layer interconnect structure can also be a metal such as aluminum or tungsten.

[0073] Continue to refer to Figure 13 Before forming a second dielectric layer covering the first dielectric layer 501 and the front interconnect structure 502, the method of forming the semiconductor structure further includes forming a bottom stop layer 520 on top of the first dielectric layer 501 and the front interconnect structure 502.

[0074] The top surface of the bottom stop layer 520 is used to define the etching stop position for etching the second dielectric layer.

[0075] In this embodiment, the material of the bottom stop layer 520 includes a low-k dielectric material. Specifically, a low-k dielectric material refers to a dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9.

[0076] As an example, low-k dielectric materials include carbon-doped silicon oxide or carbon-doped silicon nitride.

[0077] refer to Figures 13 to 18A second dielectric layer 503 is formed covering the first dielectric layer 501 and the front interconnect structure 502, and an opening 510 is formed in the second dielectric layer 503 to expose the top of the front interconnect structure 502.

[0078] The second dielectric layer 503 is used to provide a process operation platform for the subsequent formation of interconnect structures, and also to ensure that adjacent interconnect structures are insulated from each other.

[0079] In this embodiment, the material of the second dielectric layer 503 is an insulating material, including low-k dielectric material (low-k dielectric material refers to dielectric material with a relative permittivity greater than or equal to 2.6 and less than or equal to 3.9) or ultra-low-k dielectric material (ultra-low-k dielectric material refers to dielectric material with a relative permittivity less than 2.6), which can effectively reduce the parasitic capacitance between interconnect structures and thus reduce the RC delay of the device.

[0080] As an example, the material of the second dielectric layer 503 is a low-k dielectric material, such as black diamond. In other embodiments, the material of the second dielectric layer may also be SiOCH.

[0081] The opening 510 is used to provide space for the subsequent formation of interconnect structures.

[0082] The steps for forming opening 510 are described in detail below with reference to the accompanying drawings.

[0083] refer to Figure 13 A top stop layer 521 is formed covering the second dielectric layer 503; a hard mask material layer 531A is formed covering the top stop layer 521; a first pattern definition layer 532 is formed covering the hard mask material layer 531A, and a groove (not shown) is formed in the first pattern definition layer 532 to expose the top of the hard mask material layer 531A.

[0084] It should be noted that the top surface of the top stop layer 521 is used to define the etching stop position of the hard mask material layer 531A; the hard mask material layer 531A is used to provide a process basis for the subsequent formation of the hard mask layer; and the first pattern definition layer 532 is used as a mask for the patterned hard mask material layer 531A.

[0085] In this embodiment, the material of the top stop layer 521 includes silicon carbide (SiOC).

[0086] In this embodiment, the material of the hard mask material layer 531A includes titanium nitride.

[0087] In this embodiment, the material of the first pattern definition layer 532 includes photoresist.

[0088] refer to Figure 14 and in conjunction with references Figure 13 Using the first pattern definition layer 532 as a mask and the top surface of the top stop layer 521 as the stop position, the hard mask material layer 531A is patterned to form the hard mask layer 531.

[0089] The hard mask layer 531 is used as a mask for subsequently forming an opening in the patterned second dielectric layer 503.

[0090] Specifically, a mask opening (not shown) is formed in the hard mask layer 531, which is used to define the location of the second trench to be formed subsequently.

[0091] refer to Figure 15 The top stop layer 521 at the bottom of the mask opening is graphically represented, and a first trench 513 is formed in the top stop layer 521 to expose the second dielectric layer 503.

[0092] The first trench 513 exposes the second dielectric layer 503, thereby preparing for subsequent etching of the second dielectric layer 503.

[0093] In this embodiment, the opening size of the first trench 513 is smaller than the opening size of the mask opening, so as to form a double damask type opening later.

[0094] Specifically, another graphic definition layer can be used to define the area that needs to be removed in the top stop layer 521 at the bottom of the mask opening. For example, the other graphic definition layer exposes the area that needs to be removed in the top stop layer 521 at the bottom of the mask opening and covers the remaining area.

[0095] refer to Figure 16 After forming the first trench 513, the second dielectric layer 503 is patterned along the mask opening, and a portion of the thickness of the second dielectric layer 503 is removed to form the second trench 511.

[0096] The second groove 511 is used as the initial opening for the subsequent formation of the opening.

[0097] It should be noted that the opening size of the first trench 513 is smaller than the opening size of the mask opening. That is, the bottom of the mask opening has a portion of the top stop layer 521. Therefore, the top stop layer 521 at the bottom of the mask opening needs to be removed first, and then the second dielectric layer 503 needs to be removed. Thus, a double damask-type opening can be formed subsequently.

[0098] refer to Figure 17 After forming the second trench 511, the hard mask layer 531 is removed.

[0099] refer to Figure 18A bottom stop layer 520 is patterned along the second trench 511 to form an opening 510 that penetrates the second dielectric layer 503 and the bottom stop layer 520, the bottom of which exposes the front layer interconnect structure 502.

[0100] Specifically, the opening 510 includes a second trench 511 and a through-hole (not shown) connected to the bottom of the second trench 511, the through-hole exposing the front layer interconnect structure 502. The second trench 511 is used to form interconnect lines, and the through-hole is used to form a through-hole structure.

[0101] refer to Figures 19 to 20 After forming the opening 510 and before forming the adhesion barrier layer, the method further includes: performing a first modification treatment on the top of the front interconnect structure 502 exposed by the opening 510 to reduce the surface contact angle of the top of the front interconnect structure 502.

[0102] It should be noted that, before forming the adhesion barrier layer, the top of the front interconnect structure 502 exposed by the opening 510 is subjected to a first modification treatment to reduce the surface contact angle of the top of the front interconnect structure 502. This reduces the probability of the adhesion barrier layer being deposited on the exposed top of the front interconnect structure 502 during the subsequent adhesion barrier layer deposition process, thereby increasing the probability of the bottom of the interconnect structure contacting the top of the front interconnect structure 502.

[0103] The step of performing a first modification treatment on the top of the front interconnect structure 502 exposed by the opening 510 includes: referring to Figure 19 The opening 510 is filled with a modified material layer 504A; continue referring to Figure 19 The modified material layer 504A is subjected to a heat treatment process, causing the modified material layer 504A to react with the top of the front interconnect structure 502, forming a modified layer 504 on the surface of the front interconnect structure 502. The surface contact angle of the modified layer 504 is smaller than the surface contact angle of the front interconnect structure 502. (Reference) Figure 20 Remove the remaining modified material layer 504A from the opening 510.

[0104] It should be noted that the heat treatment process of the modified material layer 504A will cause the modified material layer 504A to be adsorbed on the top of the front interconnect structure 502 and form an oxide layer of the front interconnect structure 502, thereby changing the dangling bonds on the surface of the front interconnect structure 502, making the surface of the front interconnect structure 502 hydrophobic, and thus reducing the surface contact angle of the top of the front interconnect structure 502.

[0105] In this embodiment, the modified material layer 504A is made of a self-assembled monolayer (SAM).

[0106] The SAM material can adjust the surface contact angle at the top of the front interconnect structure 502.

[0107] It should be noted that the modified material layer 504A includes SAM material. The SAM material has a simple formation process and is easy to remove, thereby improving the efficiency of the first modification treatment on the top of the front interconnect structure 502 while reducing damage to other film layers (e.g., the second dielectric layer 503).

[0108] Specifically, SAM materials can typically be formed and removed using photolithography. Therefore, the formation process of SAM materials is simple and they are easy to remove.

[0109] In this embodiment, the self-assembled monolayer material includes: dodecanethiol or a solution based on dodecanethiol. Specifically, the solution based on dodecanethiol is a composite solution based on dodecanethiol, that is, a composite solution with dodecanethiol as the main component.

[0110] Dodecyl mercaptan or solutions based on dodecyl mercaptan are common self-assembled monolayer materials, thus offering advantages such as low processing costs.

[0111] In this embodiment, the process of filling the modified material layer 504A includes a spin coating process.

[0112] The spin coating process can uniformly coat liquid or thin film materials onto a substrate, ensuring a consistent coating thickness. It can coat a large area of ​​substrate in a short time, improving productivity. Furthermore, the thickness of the resulting coating can be controlled by adjusting the spin coating process parameters. Therefore, a modified material layer of 504A with uniform thickness can be obtained.

[0113] In this embodiment, the heat treatment process is carried out in a nitrogen-containing gas atmosphere.

[0114] Specifically, using nitrogen as the gas in the heat treatment process has the advantage of low process cost.

[0115] As an example, the heat treatment process includes a baking process.

[0116] The parameters for the heat treatment process of the modified material layer 504A include: a process temperature of 100°C to 200°C and a process time of 1 min to 10 min.

[0117] It should be noted that the process temperature should not be too high or too low. If the process temperature is too high, the modified material layer 504A is prone to thermal deformation, resulting in poor quality of the oxide layer formed by the subsequent adsorption of the modified material layer 504A on the top of the previous interconnect structure 502, thus affecting the effect of changing the surface contact angle of the top of the previous interconnect structure 502. If the process temperature is too low, the activity of the modified material layer 504A is easily affected, resulting in poor quality of the oxide layer formed by the subsequent adsorption of the modified material layer 504A on the top of the previous interconnect structure 502, thus affecting the effect of changing the surface contact angle of the top of the previous interconnect structure 502. Therefore, in this embodiment, the process temperature is 100℃ to 200℃.

[0118] The process time should not be too long or too short. If the process time is too long, it will easily affect the efficiency of the manufacturing process, resulting in low production efficiency; if the process time is too short, it will easily affect the activity of the modified material layer 504A, resulting in poor quality of the oxide layer of the previous interconnect structure 502 formed by the subsequent adsorption of the modified material layer 504A on the top of the previous interconnect structure 502, thereby affecting the effect of changing the surface contact angle of the top of the previous interconnect structure 502. Therefore, in this embodiment, the process time is 1 min to 10 min.

[0119] In this embodiment, the modified material layer 504A in the opening 510 is removed by a wet cleaning process. The wet cleaning process effectively removes the modified material layer 504A from the opening 510 due to the fluidity of the solution, and it features low process cost and simple operation.

[0120] In this embodiment, the solution used in the wet cleaning process includes a propylene glycol methyl ether acetate (PGMEA) solution. The PGMEA solution has good dissolving power and easily removes the modified material layer 504A from the opening 510.

[0121] refer to Figures 21 to 22 An adhesion barrier layer 505 is formed on the sidewall of the opening 510, and the adhesion barrier layer 505 exposes the bottom of the opening 510.

[0122] It should be noted that, since the adhesion barrier layer 505 in this embodiment of the invention is located between the sidewall of the interconnect structure and the second dielectric layer 503, exposing the top of the front interconnect structure 502, and the bottom of the interconnect structure is in contact with the top of the corresponding front interconnect structure 502, there is no adhesion barrier layer 505 at the bottom of the interconnect structure, thereby reducing the contact resistance between the interconnect structure and the front interconnect structure 502, correspondingly improving the RC delay caused by resistance and capacitance in the semiconductor structure, and thus improving the electrical performance of the semiconductor structure.

[0123] In this embodiment, since the top of the front interconnect structure 502 exposed by the opening 510 is subjected to a first modification treatment before the adhesion barrier layer 505 is formed on the sidewall of the opening 510, in order to reduce the surface contact angle of the top of the front interconnect structure 502, the adhesion barrier layer 505 can be selectively deposited on the second dielectric layer 503 and the front interconnect structure 502, thereby reducing the probability of the adhesion barrier layer being deposited on the top of the front interconnect structure 502.

[0124] It should be noted that since the adhesion barrier layer 505 can be selectively deposited on the surface of the second dielectric layer 503, the step of removing the adhesion barrier layer 505 at the bottom of the opening 510 can be omitted, thereby avoiding damage to the front interconnect structure 502 or the adhesion barrier layer 505 located on the sidewall of the opening 510 caused by the step of removing the adhesion barrier layer 505 at the bottom of the opening 510.

[0125] Specifically, the steps for forming the adhesion barrier layer 505 include: (Refer to...) Figure 21 A barrier layer 506 is formed on the sidewall of the opening 510, and the barrier layer 506 exposes the bottom of the opening 510; Reference Figure 22 A conformal adhesive layer 507 is formed on the sidewall of the barrier layer 506.

[0126] In this embodiment, the fact that the barrier layer 506 exposes the bottom of the opening 510 specifically means that the barrier layer 506 exposes the top of the modified layer 504.

[0127] The barrier layer 506 serves to block the diffusion of metal ions in the subsequently formed interconnect structure.

[0128] In this embodiment, the barrier layer 506 is made of one or both of tantalum nitride and tantalum. Specifically, tantalum nitride and tantalum materials can effectively block ion diffusion.

[0129] The adhesion layer 507 is used to improve the adhesion between the barrier layer 506 and the subsequently formed interconnect structure. In this embodiment, the material of the adhesion layer 507 includes cobalt, molybdenum, ruthenium, tungsten, or zinc.

[0130] Specifically, cobalt, molybdenum, ruthenium, tungsten, and zinc all have low resistivity, which helps to reduce the resistance of the subsequently formed interconnect structure and improve the performance of the semiconductor structure. At the same time, cobalt, molybdenum, ruthenium, tungsten, and zinc all have good wettability, which helps to form a uniform and pore-free interconnect structure and improve the quality of the interconnect structure.

[0131] refer to Figure 23 and in conjunction with references Figure 22After forming the adhesion barrier layer 505 and before forming the interconnect structure, the method further includes: performing a second modification treatment on the modified layer 504 on the top of the front interconnect structure 502 exposed by the opening 510, for restoring the modified layer 504 to the front interconnect structure 502.

[0132] It should be noted that after forming the adhesion barrier layer 505, the modified layer 504 on the exposed top of the front interconnect structure 502 undergoes a second modification treatment to restore the modified layer 504 to the front interconnect structure 502, that is, to restore the surface contact angle to the surface contact angle of the front interconnect structure 502. This increases the probability of material deposition of the interconnect structure onto the exposed top of the front interconnect structure 502 during the subsequent interconnect structure formation process, thereby making the bottom of the interconnect structure contact the top of the front interconnect structure 502 and reducing the contact resistance between the interconnect structure and the front interconnect structure 502.

[0133] In this embodiment, the process of performing a second modification treatment on the modified layer 504 on the top of the front interconnect structure 502 exposed by the opening 510 includes a plasma treatment process.

[0134] It should be noted that the high-energy particles in the plasma treatment process interact with the atoms on the surface of the modified layer 504, thereby breaking the original valence bonds between the atoms of the modified layer 504 and forming active sites. These sites are conducive to the chemical bonding between the atoms on the surface of the modified layer 504 and the previous interconnect structure 502, thereby restoring the surface contact angle of the modified layer 504 to the surface contact angle of the previous interconnect structure 502.

[0135] The parameters of the plasma processing technology include: the plasma gas is a mixture of nitrogen and argon; the volume percentage of nitrogen is 4% to 25%; the process time is 10s to 60s; the pressure is 1000mTorr to 40000mTorr; and the power of the radio frequency power supply is 800W to 3500W.

[0136] In the plasma treatment process, nitrogen is used to activate the surface of the modified layer 504 while removing organic contaminants from the surface of the modified layer 504 without reacting with the material. Argon is an inert gas, which protects the modified layer 504 from oxidation or reduction reactions during the plasma treatment process. At the same time, argon can also be used to clean the surface of the modified layer 504 (e.g., to remove oxides, dust, etc. from the surface of the modified layer 504).

[0137] The volume ratio of nitrogen to argon in the plasma processing should not be too high or too low. If the volume ratio is too high, nitrogen will easily act as a nitrider, resulting in a thicker nitrided layer on top of the front interconnect structure 502, thus increasing its resistance. If the volume ratio is too low, the effect of restoring the modified layer 504 to the front interconnect structure 502 will be poor. Therefore, setting the volume ratio of nitrogen to argon in the plasma processing within a reasonable range is beneficial to improving the effect of the second modification treatment on the modified layer 504, thereby improving semiconductor performance. Therefore, in this embodiment, the volume ratio of nitrogen is 4% to 25%.

[0138] The process time in the plasma treatment process should not be too long or too short. If the process time is too long, nitrogen gas can easily perform nitriding, resulting in a thicker nitrided layer on the top of the front interconnect structure 502, which increases the resistance of the front interconnect structure 502. If the process time is too short, the modified layer 504 may not revert to the original front interconnect structure 502 effectively. Therefore, in this embodiment, the process time is 10 seconds to 60 seconds.

[0139] refer to Figures 24 to 26 After the adhesion barrier layer 505 is formed, an interconnect structure 508 is formed in the opening 510, and the bottom of the interconnect structure 508 contacts the top of the corresponding front interconnect structure 502.

[0140] Interconnect structure 508 is used to make electrical connections with the previous interconnect structure 502.

[0141] It should be noted that the material of interconnect structure 508 is the same as that of the preceding interconnect structure 502. In this embodiment, the material of interconnect structure 508 is copper. Copper has good electrical conductivity and low resistance, which is beneficial for obtaining interconnect structure 508 with good conductivity.

[0142] In some embodiments, the material of interconnect structure 508 may be different from the material of the preceding interconnect structure 502. In other embodiments, depending on actual process requirements, the material of the interconnect structure may also be a metal such as aluminum or tungsten.

[0143] The interconnect structure 508 can be a single damask structure or a double damask structure. In this embodiment, the interconnect structure 508 includes an interconnect layer 508A and a via structure 508B located between the interconnect layer 508A and the previous interconnect structure 502. The interconnect layer 508A is used to achieve electrical connection with the via structure 508B. The via structure 508B is used to connect the interconnect layer 508A and the previous interconnect structure 502, thereby realizing the electrical connection between the interconnect layer 508A and the internal circuitry of the semiconductor structure.

[0144] In this embodiment, the process of forming the interconnect structure 508 in the opening 510 includes an electroplating process.

[0145] The steps for forming the interconnect structure 508 are described in detail below with reference to the accompanying drawings.

[0146] refer to Figure 24 After the adhesion barrier layer 505 is formed and before the interconnection structure 508 is formed, the method further includes: forming a seed layer 509 at the top of the adhesion barrier layer 505 and the bottom of the opening 510.

[0147] Specifically, the seed layer 509 provides a uniform starting surface for the subsequent formation of interconnect structures, which helps to reduce the probability of defects such as voids and cracks in the subsequent interconnect structures, thereby improving the quality and reliability of the formed interconnect structures.

[0148] The material of the seed layer 509 is determined by the material of the interconnect structure 508. In this embodiment, the material of the seed layer 509 is copper. In other embodiments, the seed layer may also be made of other metal materials suitable for growing interconnect structures.

[0149] refer to Figure 25 After forming the seed layer 509, the opening 510 is filled with an interconnect structure material layer 508A.

[0150] Specifically, an interconnect structure material layer 508A is filled into the opening 510 using an electroplating process. The electroplating process enhances the bonding force between the formed interconnect structure material layer 508A and the seed layer 509, improving the adhesion of the interconnect structure material layer 508A. Simultaneously, the interconnect structure material layer 508A formed using the electroplating process exhibits high conductivity, thus improving the semiconductor structure performance.

[0151] refer to Figure 26 The interconnect structure material layer 508A is planarized to form the interconnect structure 508.

[0152] It should be noted that the planarization process of the interconnect structure material layer 508A helps to reduce the surface undulations in the interconnect structure 508 and improve the dimensional accuracy of the interconnect structure 508. At the same time, the planarization process of the interconnect structure material layer 508A helps to achieve better packaging quality and reduce stress and defects in the subsequent packaging process.

[0153] In this embodiment, the planarization process for the interconnect structure material layer 508A includes: performing a first planarization process (not shown) on the interconnect structure material layer 508A; after the first planarization process, performing a second planarization process on the remaining adhesion barrier layer 505 on the top of the second dielectric layer 503, with the remaining interconnect structure material layer 508A in the opening 510 serving as the interconnect structure 508.

[0154] Specifically, if a seed layer 509 is also formed in the opening 510, the remaining seed layer 509 and the interconnect structure material layer 508A in the opening 510 constitute the interconnect structure 508.

[0155] It should be noted that the semiconductor structure of the present invention can be formed by any of the forming methods of the foregoing embodiments, or by other forming methods. For the description of the semiconductor structure of the present invention, please refer to the relevant content in the foregoing forming methods.

[0156] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate on which a first dielectric layer is formed, wherein a front-layer interconnect structure is formed in the first dielectric layer; A second dielectric layer is located on top of the first dielectric layer and the front interconnect structure, and the second dielectric layer exposes the top of the front interconnect structure; An interconnect structure is located in the second dielectric layer, and the bottom of the interconnect structure is in contact with the top of the corresponding previous interconnect structure; An adhesion barrier layer is located between the sidewall of the interconnect structure and the second dielectric layer.

2. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a stop layer located between the second dielectric layer and the first dielectric layer, and between the second dielectric layer and the previous interconnect structure.

3. The semiconductor structure as described in claim 1, characterized in that, The adhesion barrier layer includes: a barrier layer located between the sidewall of the interconnect structure and the second dielectric layer, and exposing the top of the front interconnect structure; and an adhesion layer located between the sidewall of the interconnect structure and the barrier layer.

4. The semiconductor structure as described in claim 3, characterized in that, The barrier layer is made of one or both of tantalum nitride and tantalum.

5. The semiconductor structure as described in claim 3, characterized in that, The material of the adhesive layer includes cobalt, molybdenum, ruthenium, tungsten, or zinc.

6. The semiconductor structure as described in claim 1, characterized in that, The interconnect structure includes an interconnect layer and a via structure located between the interconnect layer and the previous interconnect structure.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a first dielectric layer is formed, and a front-layer interconnect structure is formed in the first dielectric layer; A second dielectric layer is formed to cover the first dielectric layer and the front interconnect structure, and an opening is formed in the second dielectric layer to expose the top of the front interconnect structure; An adhesion barrier layer is formed on the sidewall of the opening, and the adhesion barrier layer exposes the top of the front interconnect structure; After the adhesion barrier layer is formed, an interconnect structure is formed in the opening, with the bottom of the interconnect structure contacting the top of the corresponding front interconnect structure.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The process of forming the interconnect structure in the opening includes an electroplating process.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, After the opening is formed but before the adhesion barrier layer is formed, the method further includes: performing a first modification treatment on the top of the front interconnect structure exposed by the opening to reduce the surface contact angle of the top of the front interconnect structure.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of performing a first modification treatment on the top of the front interconnect structure exposed by the opening includes: A modified material layer is filled into the opening; The modified material layer is subjected to a heat treatment process to react with the top of the front interconnect structure, forming a modified layer on the surface of the front interconnect structure. The surface contact angle of the modified layer is smaller than the surface contact angle of the front interconnect structure. Remove the modified material layer from the opening.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The modified material layer comprises a self-assembled monolayer material.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The self-assembled monolayer material includes: dodecanethiol or a solution based on dodecanethiol.

13. The method for forming a semiconductor structure as described in claim 10, characterized in that, The modified material layer in the opening is removed by a wet cleaning process.

14. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process of filling the modified material layer includes a spin coating process.

15. The method for forming a semiconductor structure as described in claim 10, characterized in that, The heat treatment process is carried out in a nitrogen-containing gas atmosphere.

16. The method for forming a semiconductor structure as described in claim 10, characterized in that, The parameters for the heat treatment process of the modified material layer include: a process temperature of 100°C to 200°C and a process time of 1 min to 10 min.

17. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of forming an adhesion barrier layer includes: forming a barrier layer on the sidewall of the opening, wherein the barrier layer exposes the top of the front interconnect structure; and forming a conformal covering adhesion layer on the sidewall of the barrier layer.

18. The method for forming a semiconductor structure as described in claim 10, characterized in that, After forming the adhesion barrier layer and before forming the interconnect structure, the method further includes: performing a second modification treatment on the modified layer on top of the front interconnect structure exposed by the opening, for restoring the modified layer to the front interconnect structure.

19. The method for forming a semiconductor structure as described in claim 17, characterized in that, The process for modifying the modified layer on top of the front interconnect structure exposed by the opening includes a plasma treatment process.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The parameters of the plasma processing process include: the plasma gas is a mixture of nitrogen and argon; the nitrogen content is 4% to 25%; the process time is 10s to 60s; the pressure is 1000mTorr to 40000mTorr; and the power of the radio frequency power supply is 800W to 3500W.

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