Semiconductor device and method of manufacturing the same

Abstract

Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: a first semiconductor structure and a second semiconductor structure stacked along a first direction; the first semiconductor structure comprises: a first bonding layer, and a first conductive structure in the first bonding layer; the second semiconductor structure comprises: a second bonding layer, and a second conductive structure in the second bonding layer; one end of the first conductive structure is bonded to one end of the second conductive structure; wherein the semiconductor device further comprises: a first MIM structure in the first bonding layer, the first MIM structure being connected to the other end of the first conductive structure; and / or a second MIM structure in the second bonding layer, the second MIM structure being connected to the other end of the second conductive structure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] With the increasing demand for large data processing capability of integrated circuits, Moore's law is approaching the limit, and it is becoming more and more difficult to shrink the size of semiconductor devices. Three-dimensional integration technology has become an effective solution to continue to improve PPAC (performance, power, area, cost) in the post-Moore era. SUMMARY

[0003] Embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof; wherein the semiconductor device comprises: a first semiconductor structure and a second semiconductor structure stacked along a first direction; the first semiconductor structure comprises: a first bonding layer, and a first conductive structure in the first bonding layer; the second semiconductor structure comprises: a second bonding layer, and a second conductive structure in the second bonding layer; one end of the first conductive structure is bonded and connected to one end of the second conductive structure; wherein the semiconductor device further comprises: a first MIM structure in the first bonding layer, the first MIM structure being connected to the other end of the first conductive structure; and / or a second MIM structure in the second bonding layer, the second MIM structure being connected to the other end of the second conductive structure.

[0004] In some embodiments, the first bonding layer comprises one or more first MIM structures; and the second bonding layer comprises one or more second MIM structures.

[0005] In some embodiments, the first MIM structure and the second MIM structure each comprise a first electrode layer, a second electrode layer, and a dielectric layer between the first electrode layer and the second electrode layer.

[0006] In some embodiments, the semiconductor device further comprises: a first interconnection layer on a side of the first bonding layer away from the second bonding layer among opposite sides of the first bonding layer along the first direction, and a first interconnection structure in the first interconnection layer; and a second interconnection layer on a side of the second bonding layer away from the first bonding layer among opposite sides of the second bonding layer along the first direction, and a second interconnection structure in the second interconnection layer.

[0007] In some embodiments, when only the first MIM structure is included in the semiconductor device, a first electrode layer of the first MIM structure is connected with the first interconnection structure; a second electrode layer of the first MIM structure is connected with the other end of the first conductive structure; and the second conductive structure is directly connected with the second interconnection structure.

[0008] In some embodiments, when only the second MIM structure is included in the semiconductor device, a first electrode layer of the second MIM structure is connected with the second interconnection structure; a second electrode layer of the second MIM structure is connected with the other end of the second conductive structure; and the first conductive structure is directly connected with the first interconnection structure.

[0009] In some embodiments, when both the first MIM structure and the second MIM structure are included in the semiconductor device, a first electrode layer of the first MIM structure is connected with the first interconnection structure; a second electrode layer of the first MIM structure is connected with the other end of the first conductive structure; a first electrode layer of the second MIM structure is connected with the second interconnection structure; and a second electrode layer of the second MIM structure is connected with the other end of the second conductive structure.

[0010] In some embodiments, the semiconductor device further comprises: a third conductive structure penetrating through the first bonding layer, and a fourth conductive structure penetrating through the second bonding layer, the third conductive structure and the fourth conductive structure being bonded to each other; wherein the third conductive structure and the first conductive structure are electrically isolated from each other, and the fourth conductive structure and the second conductive structure are electrically isolated from each other.

[0011] In some embodiments, the semiconductor device further comprises: a third interconnection structure in the first interconnection layer, the third interconnection structure and the first interconnection structure being electrically isolated from each other; and a fourth interconnection structure in the second interconnection layer, the fourth interconnection structure and the second interconnection structure being electrically isolated from each other; wherein the third conductive structure is connected with the third interconnection structure, and the fourth conductive structure is connected with the fourth interconnection structure.

[0012] In some embodiments, the semiconductor device further comprises: a peripheral circuit, the peripheral circuit being located on a side of the first interconnection layer along the first direction, which is away from the first bonding layer; and a memory cell array, the memory cell array being located on a side of the second interconnection layer along the first direction, which is away from the second bonding layer.

[0013] In some embodiments, the semiconductor device further comprises: a fifth conductive structure in the first bonding layer, the fifth conductive structure connected with the first conductive structure; and a sixth conductive structure in the second bonding layer, the sixth conductive structure connected with the second conductive structure.

[0014] The embodiments of the present disclosure provide a method for manufacturing a semiconductor device, the method comprising: forming a first semiconductor structure; the first semiconductor structure comprising: a first bonding layer, and a first conductive structure in the first bonding layer; forming a second semiconductor structure; the second semiconductor structure comprising: a second bonding layer, and a second conductive structure in the second bonding layer; stacking the first semiconductor structure and the second semiconductor structure along a first direction, so that one end of the first conductive structure is bonded and connected with one end of the second conductive structure; wherein the method further comprises: forming a first MIM structure in the first bonding layer, the first MIM structure connected with the other end of the first conductive structure; and / or forming a second MIM structure in the second bonding layer, the second MIM structure connected with the other end of the second conductive structure.

[0015] In some embodiments, the method comprises: forming a first interconnection layer, and forming a first interconnection structure in the first interconnection layer; forming a first sub-bonding layer on one side of the first interconnection layer along the first direction; forming a first recess in the first sub-bonding layer, the first recess exposing the first interconnection structure; forming a first conductive layer in the first recess and on part of the surface of the first sub-bonding layer, forming a dielectric layer on the surface of the first conductive layer, and forming a second electrode layer on the surface of the dielectric layer, to form a first MIM structure.

[0016] In some embodiments, the method further comprises: forming a second sub-bonding layer on the first sub-bonding layer; forming a second recess in the second sub-bonding layer, the second recess penetrating through the second sub-bonding layer and exposing one end of the first MIM structure; forming a first conductive structure in the second recess, the first conductive structure connected with one end of the first MIM structure; wherein the first sub-bonding layer and the second sub-bonding layer constitute the first bonding layer.

[0017] In some embodiments, the method further comprises: forming a third recess in the first bonding layer; the third recess and the second recess are spaced apart from each other; forming a third conductive structure in the third recess; the third conductive structure and the first conductive structure are electrically isolated from each other.

[0018] In some embodiments, the method further comprises: forming a fourth recess in the first bonding layer; the fourth recess is in communication with the second recess; forming a fifth conductive structure in the fourth recess; the fifth conductive structure is connected with the first conductive structure.

[0019] In some embodiments, the forming the second semiconductor structure comprises: forming a second interconnection layer, and forming a second interconnection structure in the second interconnection layer; forming a third sub-bonding layer on one side of the second interconnection layer along the first direction; forming a fifth recess in the third sub-bonding layer, the fifth recess exposes the second interconnection structure; forming a first conductive layer in the fifth recess and on a part of the surface of the third sub-bonding layer, forming a dielectric layer on the surface of the first conductive layer, and forming a second electrode layer on the surface of the dielectric layer to form a second MIM structure.

[0020] In some embodiments, the method further comprises: forming a fourth sub-bonding layer on the third sub-bonding layer; forming a sixth recess in the fourth sub-bonding layer, the sixth recess exposes the second MIM structure on the part of the surface of the third sub-bonding layer; forming a second conductive structure in the sixth recess; the second conductive structure is connected with the second MIM structure; wherein the third sub-bonding layer and the fourth sub-bonding layer constitute the second bonding layer.

[0021] In some embodiments, the method further comprises: forming a seventh recess in the second bonding layer; the seventh recess and the sixth recess are spaced apart from each other; forming a fourth conductive structure in the seventh recess; the fourth conductive structure and the second conductive structure are electrically isolated from each other.

[0022] In some embodiments, the method further comprises: forming an eighth recess in the second bonding layer; the eighth recess is in communication with the fifth recess; forming a sixth conductive structure in the eighth recess; the sixth conductive structure is connected with the second conductive structure.

[0023] In this embodiment, by adding a first MIM structure to the first bonding layer, the utilization rate of the first bonding layer is improved, and / or by adding a second MIM structure to the second bonding layer, the utilization rate of the second bonding layer is improved, without requiring additional space occupied by the first semiconductor structure, the second semiconductor structure device region, or the substrate region. Furthermore, designing the MIM structure in the bonding layer, compared to designing it in the substrate, other dielectric layers, or passivation layers, reduces the space occupied by other device structures and metal interconnect structures, and reduces electrical interference or bridging risks between the MIM structure and other devices and metal interconnect structures, thereby increasing the utilization rate of the semiconductor device. Additionally, the first and second MIM structures can be connected using the conductive structures in their respective bonding layers, eliminating the need for additional design and addition of lead wires for the MIM structure, saving the process steps of "forming contact holes for the positive and negative terminals of the capacitor and connecting the capacitor to the circuit," without increasing the process difficulty. Moreover, the first and second MIM structures can resist voltage fluctuations, thus preventing the semiconductor device from being affected by unstable voltage signals and improving its reliability. Attached Figure Description

[0024] Figure 1 A schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Figure 1 ;

[0025] Figure 2 A schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Figure 2 ;

[0026] Figure 3 A schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Figure 3 ;

[0027] Figure 4 A schematic diagram of the manufacturing process of a semiconductor device provided in an embodiment of this disclosure;

[0028] Figure 5 This is a cross-sectional schematic diagram of a first functional layer provided in an embodiment of the present disclosure;

[0029] Figure 6 This is a schematic cross-sectional view of the formation of a first sub-bonding layer according to an embodiment of the present disclosure;

[0030] Figure 7 This is a cross-sectional schematic diagram of the formation of a first groove according to an embodiment of the present disclosure;

[0031] Figure 8 This is a cross-sectional schematic diagram of the formation of a first conductive material layer according to an embodiment of the present disclosure;

[0032] Figure 9A cross-sectional view of forming an insulating material layer is provided for an embodiment of the present disclosure.

[0033] Figure 10 A cross-sectional view of forming a first electrode layer is provided for an embodiment of the present disclosure.

[0034] Figure 11 A cross-sectional view of forming a second sub-bonding layer is provided for an embodiment of the present disclosure.

[0035] Figure 12 A cross-sectional view of planarizing the second sub-bonding layer is provided for an embodiment of the present disclosure.

[0036] Figure 13 A cross-sectional view of forming a third recess is provided for an embodiment of the present disclosure.

[0037] Figure 14 A cross-sectional view of forming a second recess is provided for an embodiment of the present disclosure.

[0038] Figure 15 A cross-sectional view of forming a first conductive structure is provided for an embodiment of the present disclosure.

[0039] Figure 16 A cross-sectional view of forming a fourth recess is provided for an embodiment of the present disclosure.

[0040] Figure 17 A cross-sectional view of forming a fifth conductive structure is provided for an embodiment of the present disclosure.

[0041] Figure 18 A cross-sectional view of bonding a first semiconductor structure and a second semiconductor structure is provided for an embodiment of the present disclosure.

[0042] In the drawings, which are not necessarily drawn to scale, like numerals describe substantially similar components throughout the several views. Like numerals having different letter suffixes can represent different instances of substantially similar components. The drawings illustrate generally, by way of example, various embodiments discussed herein. DETAILED DESCRIPTION

[0043] Exemplary embodiments of the present disclosure are described herein with reference to the accompanying drawings, which are not necessarily drawn to scale. The present disclosure can be implemented in various forms, and should not be limited to the specific embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0045] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0046] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0047] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0049] In order to enable a more detailed understanding of the features and technical content of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present disclosure.

[0050] It should be understood that in the bonding process of the wafer, the bonding technology has very high requirements on the flatness of the wafer surface. For example, in the bonding process of the first wafer and the second wafer, a bonding layer is usually formed on the side of the first wafer and the second wafer that is bonded and contacted, and then a chemical mechanical polishing (CMP) process is performed for planarization treatment to meet the requirements of the bonding technology on the flatness of the surfaces of the two wafers. In subsequent processes, bonding contacts and conductive structures are formed in the bonding layer, and the electrical connection of the two wafers is realized through the connection of the bonding contacts and the conductive structures in the two wafers. However, due to the limited area occupied by the bonding contacts and the conductive structures, the utilization rate of the bonding layer is low.

[0051] Therefore, in order to solve one or more of the above problems, the present disclosure provides a semiconductor device, which includes: a first semiconductor structure and a second semiconductor structure stacked along a first direction; the first semiconductor structure includes: a first bonding layer, and a first conductive structure in the first bonding layer; the second semiconductor structure includes: a second bonding layer, and a second conductive structure in the second bonding layer; one end of the first conductive structure is bonded and connected to one end of the second conductive structure; wherein the semiconductor device further includes: a first MIM structure in the first bonding layer, the first MIM structure being connected to the other end of the first conductive structure; and / or a second MIM structure in the second bonding layer, the second MIM structure being connected to the other end of the second conductive structure.

[0052] Thus, by adding the first MIM structure in the first bonding layer, the utilization of the first bonding layer is improved, and / or by adding the second MIM structure in the second bonding layer, the utilization of the second bonding layer is improved, without occupying additional space of the first semiconductor structure, the second semiconductor structure, and the substrate; and, by designing the MIM structure in the bonding layer, compared with designing the MIM structure in the substrate, other dielectric layer, or passivation layer, the space occupation of other device structures and metal interconnection structures can be reduced, and the electrical interference or bridging risk of the MIM structure with other devices and metal interconnection structures can be reduced, thereby increasing the utilization of the semiconductor device; in addition, the first MIM structure and the second MIM structure can be connected out through the conductive structure in the corresponding bonding layer, without the need to additionally design and add the lead-out wire of the MIM structure, thereby saving the process steps of “forming a contact hole for the positive and negative electrodes of the capacitor, and connecting the capacitor to the circuit”, without increasing the process difficulty. Furthermore, the first MIM structure and the second MIM structure can play a role in resisting voltage fluctuations, so that the influence of unstable voltage signals on the semiconductor device can be prevented, and the reliability of the semiconductor device can be improved.

[0053] To make the above-mentioned purposes, features and advantages of the present disclosure more obvious and easy to understand, specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Before introducing the semiconductor device shown in the drawings, the directions used in the following description are defined. Among them, the stacking direction of the semiconductor structure is defined as the first direction (i.e. the Z-axis direction), and the intersecting second direction (i.e. the X-axis direction) and the third direction (i.e. the Y-axis direction) are defined in the plane perpendicular to the first direction. In some embodiments, the first direction, the second direction and the third direction can be perpendicular to each other, i.e. the X-axis direction, the Y-axis direction and the Z-axis direction are perpendicular to each other.

[0054] Reference Figure 1 , Figure 1 A cross-sectional structure schematic diagram of a semiconductor device is exemplarily provided in the present disclosure. Figure 1 Cross-sectional schematic diagrams of three cases of the semiconductor device in the XZ plane are shown in FIGS. (a), (b) and (c). Among them, Figure 1 In FIG. (a) of the present disclosure, the first MIM structure 110 is arranged in the first bonding layer, and the second MIM structure is not arranged in the second bonding layer. Figure 1 In FIG. (b) of the present disclosure, the first MIM structure is not arranged in the first bonding layer, and the second MIM structure 210 is arranged in the second bonding layer. Figure 1 In FIG. (c) of the present disclosure, the first MIM structure 110 is arranged in the first bonding layer, and the second MIM structure 210 is arranged in the second bonding layer.

[0055] As Figure 1As shown, the semiconductor device can include a first semiconductor structure 100 and a second semiconductor structure 200, which are arranged in a stacked manner along the Z-axis direction. The first semiconductor structure 100 and the second semiconductor structure 200 can be connected to each other in a vertical stacked manner using a bonding technology. In this way, the planar size of the semiconductor device can be reduced, and the integration level can be improved. Here, the bonding technology, for example, includes a hybrid bonding connection (also referred to as a "metal / dielectric hybrid bonding connection"), which is a direct bonding technology, for example, forms a bond between surfaces without using an intermediate layer such as solder or adhesive, and can simultaneously obtain metal-metal bonding and dielectric-dielectric bonding. It should be noted that the "bonding" referred to in the present disclosure can be any suitable bonding technology, for example, hybrid bonding, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding, etc.

[0056] The first semiconductor structure 100 can include a first functional layer 102, in which a peripheral circuit and / or a memory cell array, etc. can be arranged. The peripheral circuit can include a plurality of CMOS transistors and control circuits related to the CMOS transistors, such as control logic, sense amplification circuit, row decoder, column decoder, data input / output buffer, driver, and read / write circuit, etc., wherein when the control logic receives a read / write operation command and address data, under the action of the control logic, the row decoder or the column decoder can apply a corresponding voltage generated from the driver to a corresponding bit line and word line based on the decoded address, to realize data reading or writing, etc., and interact with external devices through the data input / output buffer. The memory cell array can include a plurality of memory cells, which can be NAND memory cells, PCM memory cells, DRAM memory cells, etc. For ease of understanding, the following embodiments are exemplarily described with the peripheral circuit arranged in the first functional layer 102.

[0057] In other embodiments, the peripheral circuit can not be arranged in the first functional layer 102, but other circuits or devices can be arranged, which are not limited in the present disclosure. It should be understood that in the following embodiments, the content used to describe the peripheral circuit is only used to illustrate the present disclosure, and is not used to limit the scope of the present disclosure, unless specifically emphasized, in the embodiments of the present disclosure, the peripheral circuit can be replaced by other circuits or devices.

[0058] The first semiconductor structure 100 may further include a first interconnect layer 104, which is located on one side of the first functional layer 102 along the Z-axis. The first interconnect layer 104 has multiple interconnect structures, which are electrically isolated from each other, such as a first interconnect structure 112 and a third interconnect structure 114, etc., with the first interconnect structure 112 and the third interconnect structure 114 being electrically isolated from each other. The interconnect structures in the first interconnect layer 104 may include lateral wires and vias. These interconnect structures may be formed in one or more interlayer dielectric (ILD) layers. The constituent materials of the interconnect structures may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicides, or any combination thereof. The ILD layers in the first interconnect layer 104 may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. Here, the peripheral circuitry in the first functional layer 102 can be connected to the interconnect structures in the first interconnect layer 104 in any suitable manner.

[0059] The first semiconductor structure 100 may further include a first bonding layer 106, which is located on the side of the first interconnect layer 104 away from the first functional layer 102 along the Z-axis. The first bonding layer 106 has multiple conductive structures disposed therein, which are electrically isolated from each other; such as a first conductive structure 108, a third conductive structure 116, etc., where the first conductive structure 108 and the third conductive structure 116 are electrically isolated from each other. The conductive structures in the first bonding layer 106 may extend along the Z-axis for transmitting electrical signals. These conductive structures may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. Here, the interconnect structures in the first interconnect layer 104 may be connected to the conductive structures in the first bonding layer 106 in any suitable manner.

[0060] In some embodiments, such as Figure 1 As shown in Figures (a), (b), and (c), the third conductive structure 116 penetrates the first bonding layer 106 along the Z-axis. At the opposite ends of the third conductive structure 116 along the Z-axis, one end is connected to the third interconnect structure 114, and the other end can be connected to structures in other layers (such as the fourth conductive structure 216).

[0061] In some embodiments, such as Figure 1As shown in FIG. 1C, the first bonding layer 106 further includes a first MIM structure 110. The first MIM structure 110 can be connected to the first conductive structure 108 at one end along the Z-axis direction, and connected to the first interconnection structure 112 at the other end. In other words, the first MIM structure 110 is located between the first conductive structure 108 and the first interconnection structure 112. Here, the first MIM structure 110 is connected to the first conductive structure 108 at one end along the Z-axis direction, and connected to another structure in another layer (e.g., the second conductive structure 208) at the other end along the Z-axis direction.

[0062] In some embodiments, the first bonding layer 106 can include one or more first MIM structures 110, which can improve the compatibility of the first semiconductor structure.

[0063] In some embodiments, as shown in FIG. 1B, the first bonding layer 106 does not include the first MIM structure 110. In this case, the first conductive structure 108 can pass through the first bonding layer 106 along the Z-axis direction, and both ends of the first conductive structure 108 along the Z-axis direction can be connected to another structure in another layer, e.g., one end of the first conductive structure 108 along the Z-axis direction is connected to the second conductive structure 208, and the other end of the first conductive structure 108 along the Z-axis direction is connected to the first interconnection structure 112. Figure 1

[0064] In some embodiments, the first MIM structure 110 is a capacitor structure. Here, the first MIM structure 110 can include a first electrode layer, a second electrode layer, and a dielectric layer between the first electrode layer and the second electrode layer. The first electrode layer can be used as a lower electrode of the first MIM structure 110; the dielectric layer can be used as a dielectric of the first MIM structure 110; and the second electrode layer can be used as an upper electrode of the first MIM structure 110. For example, the first electrode layer and the second electrode layer can include, but are not limited to, titanium nitride. The dielectric layer can include a high-k material, which generally refers to a material with a dielectric constant higher than 3.9, and is usually significantly higher than this value. In some specific examples, the dielectric layer can include, but is not limited to, aluminum oxide (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc.

[0065] In some embodiments, the first MIM structure 110 can have various shapes, such as a cup-shaped capacitor CUP, a cylindrical capacitor CYL, and a pillar-shaped capacitor PIL, without limitation.

[0066] In some specific embodiments, referring to FIG. 1C, the first MIM structure 110 can be a cup-shaped capacitor CUP, and the first bonding layer 106 can include one or more cup-shaped capacitors CUP. Figure 1 ​In the (a) diagram in FIG. 11, when only the first MIM structure 110 is included in the semiconductor device, the first electrode layer of the first MIM structure 110 is connected with the first interconnection structure 112, and the second electrode layer of the first MIM structure 110 is connected with the other end of the first conductive structure 108. At this time, the second conductive structure 208 is directly connected with the second interconnection structure 212.

[0067] Based on this, in the embodiments of the present disclosure, the peripheral circuit can be coupled to the external device through the first interconnection structure 112, the first MIM structure 110, and the first conductive structure 108; and can also be coupled to the external device through the third interconnection structure 114 and the third conductive structure 116.

[0068] The second semiconductor structure 200 can include a second functional layer 202, and the second functional layer 202 can be provided with a peripheral circuit and / or a memory cell array, etc. The peripheral circuit and the memory cell array have been described above and will not be described here again. For the convenience of understanding, in the following embodiments, the second functional layer 202 is taken as an example to be provided with a memory cell array for illustrative description.

[0069] In other embodiments, the second functional layer 202 can also not be provided with a memory cell array, but be provided with other circuits or devices, which are not limited by the present disclosure. It should be understood that in the following embodiments, the content for describing the memory cell array is only used for illustrating the present disclosure, and is not used for limiting the scope of the present disclosure, and unless specifically emphasized, the memory cell array can be replaced by other circuits or devices in the embodiments of the present disclosure.

[0070] The second semiconductor structure 200 can also include a second interconnection layer 204 located on one side of the second functional layer 202 along the Z-axis direction. The second interconnection layer 204 is provided with a plurality of interconnection structures, and the plurality of interconnection structures are electrically isolated from each other, such as the second interconnection structure 212 and the fourth interconnection structure 214, which are electrically isolated from each other. The interconnection structures in the second interconnection layer 204 can include a lateral wire and a via, and the interconnection structures can be formed in one or more interlayer dielectric (ILD) layers. The constituent material of the interconnection structures can include a conductive material, which includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layer in the second interconnection layer 204 can include a dielectric material, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. Here, the memory cell array in the second functional layer 202 can be connected with the interconnection structures in the second interconnection layer 204 in any suitable manner.

[0071] The second semiconductor structure 200 can further include a second bonding layer 206 located at a side of the second interconnection layer 204 away from the second functional layer 202 along the Z-axis direction. The second bonding layer 206 is provided with a plurality of conductive structures electrically isolated from each other, such as the second conductive structure 208, the fourth conductive structure 216, and the like. Here, the second conductive structure 208 and the fourth conductive structure 216 are electrically isolated from each other. The conductive structures in the second bonding layer 206 can extend along the Z-axis direction for transmitting electrical signals, and can include a conductive material including but not limited to W, Co, Cu, Al, silicide, or any combination thereof. Here, the interconnection structures in the second interconnection layer 204 can be connected to the conductive structures in the second bonding layer 206 in any suitable manner.

[0072] In some embodiments, as shown in (a), (b), and (c) of FIG. 1, the fourth conductive structure 216 extends through the second bonding layer 206 along the Z-axis direction, and one end of the fourth conductive structure 216 along the Z-axis direction is connected to the fourth interconnection structure 214, and the other end can be connected to a structure in another layer, such as the third conductive structure 116. Figure 1

[0073] In some embodiments, as shown in (a) of FIG. 1, the second bonding layer 206 is not provided with the second MIM structure 210, and the second conductive structure 208 can extend through the second bonding layer 206 along the Z-axis direction. Both ends of the second conductive structure 208 along the Z-axis direction can be connected to a structure in another layer, such as one end of the second conductive structure 208 along the Z-axis direction being connected to the first conductive structure 108, and the other end being connected to the second interconnection structure 212. Figure 1

[0074] In some embodiments, as shown in (b) and (c) of FIG. 1, the second bonding layer 206 is further provided with the second MIM structure 210. One end of the second MIM structure 210 can be connected to one end of the second conductive structure 208 along the Z-axis direction, and the other end of the second MIM structure 210 can be connected to the second interconnection structure 212. In other words, the second MIM structure 210 is located between the second conductive structure 208 and the second interconnection structure 212. One end of the second conductive structure 208 along the Z-axis direction is connected to the second MIM structure, and the other end along the Z-axis direction can be connected to a structure in another layer, such as the first conductive structure 108. Figure 1 In some embodiments, the second bonding layer 206 can include one or more second MIM structures 210 to improve the compatibility of the second semiconductor structure.

[0075]

[0076] ​​​In some embodiments, the second MIM structure 210 is a capacitor structure. Here, the second MIM structure 210 may include a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer. The first electrode layer can be used as the lower electrode of the second MIM structure 210; the dielectric layer can be used as the dielectric of the second MIM structure 210; and the second electrode layer can be used as the upper electrode of the second MIM structure 210. Exemplarily, the constituent materials of both the first electrode layer and the second electrode layer include, but are not limited to, titanium nitride. The constituent materials of the dielectric layer include high-k dielectric materials, which generally refer to materials with a dielectric constant higher than 3.9, and are typically significantly higher than this value. In some specific examples, the constituent materials of the dielectric layer may include, but are not limited to, alumina (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc.

[0077] In some embodiments, the second MIM structure 210 may take on a variety of different shapes, such as a cup-shaped capacitor (CUP), a cylindrical capacitor (CYL), or a pillar-shaped capacitor (PIL), which are not limited in this disclosure.

[0078] In some specific embodiments, reference is made to Figure 1 In Figure (b), when the semiconductor device includes only the second MIM structure 210, the first electrode layer of the second MIM structure 210 is connected to the second interconnect structure 212; the second electrode layer of the second MIM structure is connected to the other end of the second conductive structure 208; at this time, the first conductive structure 108 is directly connected to the first interconnect structure 112.

[0079] In some specific embodiments, reference is made to Figure 1 In Figure (c), when the semiconductor device includes a first MIM structure 110 and a second MIM structure 210, the first electrode layer of the first MIM structure 110 is connected to the first interconnect structure 112; the second electrode layer of the first MIM structure 110 is connected to the other end of the first conductive structure 108; the first electrode layer of the second MIM structure 210 is connected to the second interconnect structure 212; and the second electrode layer of the second MIM structure 210 is connected to the other end of the second conductive structure 208.

[0080] Based on this, in this embodiment of the disclosure, the memory cell array can be coupled to external devices through the second interconnect structure 212, the second MIM structure 210, and the second conductive structure 208; or it can be coupled to external devices through the fourth interconnect structure 214 and the fourth conductive structure 216.

[0081] It is to be noted that after the first semiconductor structure 100 and the second semiconductor structure 200 are bonded, the first conductive structure 108 is bonded to the second conductive structure 208, and the third conductive structure 116 is bonded to the fourth conductive structure 216. The third conductive structure 116 is connected to the third interconnection structure 114, and the fourth conductive structure 216 is connected to the fourth interconnection structure 214.

[0082] That is, the peripheral circuit can be connected to the memory cell array through the third interconnection structure 114, the third conductive structure 116, the fourth conductive structure 216, and the fourth interconnection structure 214; can be connected to the memory cell array through the first interconnection structure 112, the first MIM structure 110, the first conductive structure 108, the second conductive structure 208, and the second interconnection structure 212; can be connected to the memory cell array through the first interconnection structure 112, the first conductive structure 108, the second conductive structure 208, the second MIM structure 210, and the second interconnection structure 212; and can be connected to the memory cell array through the first interconnection structure 112, the first MIM structure 110, the first conductive structure 108, the second conductive structure 208, the second MIM structure 210, and the second interconnection structure 212.

[0083] In some embodiments, the first semiconductor structure 100 can be a wafer, and the second semiconductor structure 200 can be a wafer, that is, Figure 1 The semiconductor device shown is a bonded stack of a wafer and a wafer (W2W).

[0084] In the above embodiments, the third interconnection structure, the third conductive structure, the fourth conductive structure, and the fourth interconnection structure are not connected to the first MIM structure and / or the second MIM structure in the communication path. In other embodiments, referring to Figure 2 , the communication path can also be connected to the first MIM structure and / or the second MIM structure.

[0085] In some embodiments, referring to Figure 2 , Figure 2 Another semiconductor device cross-sectional structure schematic diagram is provided as an example of the present disclosure. Figure 2 The cross-sectional schematic diagrams of three cases of the semiconductor device in the XZ plane are shown in FIGS. (a), (b), and (c) of the present disclosure. Among them, Figure 2 In FIG. (a) of the present disclosure, the first MIM structure 310 is arranged in the first bonding layer, and the second MIM structure is not arranged in the second bonding layer. Figure 2 In FIG. (b) of the present disclosure, the first MIM structure is not arranged in the first bonding layer, and the second MIM structure 410 is arranged in the second bonding layer. Figure 2The first bonding layer in the (c) diagram in the figure is provided with a first MIM structure 310, and the second bonding layer is provided with a second MIM structure 410.

[0086] Reference Figure 2 , the semiconductor device can include a first semiconductor structure 300 and a second semiconductor structure 400, the first semiconductor structure 300 and the second semiconductor structure 400 are stacked along the Z-axis direction. Among them, the first semiconductor structure 300 and the second semiconductor structure 400 can be connected to each other vertically stacked using the bonding technology mentioned in the foregoing. In this way, the planar size of the semiconductor device can be reduced, and the integration degree can be improved.

[0087] The first semiconductor structure 300 can include a first functional layer 302, and the first functional layer 302 can be provided with peripheral circuits and / or memory cell arrays, etc. For the sake of understanding, the following embodiments are exemplarily described by taking the first functional layer 302 provided with peripheral circuits as an example.

[0088] The first semiconductor structure 300 can further include a first interconnection layer 304 located on one side of the first functional layer 302 along the Z-axis direction. The first interconnection layer 304 is provided with a plurality of interconnection structures, and the plurality of interconnection structures are electrically isolated from each other, such as a first interconnection structure 312 and a third interconnection structure 314, which are electrically isolated from each other; The interconnection structure in the first interconnection layer 304 can include a lateral wire and a via, and the interconnection structure can be formed in one or more interlayer dielectric (ILD) layers, and the constituent material of the interconnection structure can include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide or any combination thereof. The ILD layer in the first interconnection layer 304 can include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric or any combination thereof. Here, the peripheral circuit in the first functional layer 302 can be connected to the interconnection structure in the first interconnection layer 304 in any suitable manner.

[0089] The first semiconductor structure 300 can further include a first bonding layer 306 located on one side of the first interconnection layer 304 along the Z-axis direction, away from the first functional layer 302. The first bonding layer 306 is provided with a plurality of conductive structures, such as a first conductive structure 308 and a fifth conductive structure 316, and here the first conductive structure 308 is connected to the fifth conductive structure 316. The conductive structure in the first bonding layer 306 can extend along the Z-axis direction for transmitting electrical signals, and the conductive structure can include a conductive material, including but not limited to W, Co, Cu, Al, silicide or any combination thereof. Here, the interconnection structure in the first interconnection layer 304 can be connected to the conductive structure in the first bonding layer 306 in any suitable manner.

[0090] In some embodiments, as shown in FIG. 1(a), FIG. 1(b) and FIG. 1(c), the fifth conductive structure 316 penetrates the first bonding layer 306 along the Z-axis direction; one end of the fifth conductive structure 316 along the Z-axis direction is connected with the third interconnection structure 314, and the other end can be connected with a structure (such as the sixth conductive structure 416) in other layers; one end of the fifth conductive structure 316 along the X-axis / Y-axis direction is connected with the first conductive structure 308. Figure 2 In some embodiments, as shown in FIG. 1(a) and FIG. 1(c), the first bonding layer 306 further comprises a first MIM structure 310; one end of the first MIM structure 310 can be connected with one end of the first conductive structure 308 along the Z-axis direction, and the other end of the first MIM structure 310 can be connected with the first interconnection structure 312. In other words, the first MIM structure 310 is located between the first conductive structure 308 and the first interconnection structure 312. One end of the first conductive structure 308 along the Z-axis direction is connected with the first MIM structure, and the other end along the Z-axis direction can be connected with a structure (such as the second conductive structure 408) in other layers. In the embodiments of the present disclosure, the first MIM structure 310 can be connected with the fifth conductive structure 316.

[0091] Figure 2 In some embodiments, the first bonding layer 306 can comprise one or more first MIM structures 310.

[0092] In some embodiments, as shown in FIG. 1(b), the first bonding layer 306 does not comprise the first MIM structure 310; at this time, one end of the first conductive structure 308 along the Z-axis direction is connected with the second conductive structure 408, and the other end can be connected with other interconnection structures (not shown in the figure). One end of the first conductive structure 308 along the X-axis / Y-axis direction is connected with the fifth conductive structure 316.

[0093] In some embodiments, as shown in FIG. 1(a), FIG. 1(b) and FIG. 1(c), the fifth conductive structure 316 penetrates the first bonding layer 306 along the Z-axis direction; one end of the fifth conductive structure 316 along the Z-axis direction is connected with the third interconnection structure 314, and the other end can be connected with a structure (such as the sixth conductive structure 416) in other layers; one end of the fifth conductive structure 316 along the X-axis / Y-axis direction is connected with the first conductive structure 308. Figure 2 In some embodiments, the first MIM structure 310 comprises a first electrode layer, a second electrode layer and a dielectric layer located between the first electrode layer and the second electrode layer. The first electrode layer can be used as a lower electrode of the first MIM structure 310; the dielectric layer can be used as a dielectric of the first MIM structure 310; and the second electrode layer can be used as an upper electrode of the first MIM structure 310.

[0094] In some specific embodiments, referring to FIG. 1(a), FIG. 1(b) and FIG. 1(c), the first bonding layer 306 can comprise one or more first MIM structures 310.

[0095] Figure 2 ​​In the (a) diagram in FIG. 11, when only the first MIM structure 310 is included in the semiconductor device, the first electrode layer of the first MIM structure 310 is connected with the first interconnection structure 312; the second electrode layer of the first MIM structure 310 is connected with the other end of the first conductive structure 308. At this time, the second conductive structure 408 is connected with the sixth conductive structure 416. Based on this, in the embodiments of the present disclosure, the peripheral circuit can be coupled to the external device through the first MIM structure 310.

[0096] The second semiconductor structure 400 can include a second functional layer 402, and the second functional layer 402 can be provided with a peripheral circuit and / or a memory cell array, etc. The peripheral circuit and the memory cell array have been described above and will not be described here again. For ease of understanding, in the following embodiments, the second functional layer 402 is taken as an example to be provided with a memory cell array for illustrative description.

[0097] The second semiconductor structure 400 can further include a second interconnection layer 404 located on one side of the second functional layer 402 along the Z-axis direction. The second interconnection layer 404 is provided with a plurality of interconnection structures, and the plurality of interconnection structures are electrically isolated from each other, such as the second interconnection structure 412 and the fourth interconnection structure 414, which are electrically isolated from each other; the interconnection structure in the second interconnection layer 404 can include a lateral wire and a via, and the interconnection structure can be formed in one or more interlayer dielectric (ILD) layers, and the constituent material of the interconnection structure can include a conductive material, which includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layer in the second interconnection layer 404 can include a dielectric material, which includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. Here, the memory cell array in the second functional layer 402 can be connected with the interconnection structure in the second interconnection layer 404 in any suitable manner.

[0098] The second semiconductor structure 400 can further include a second bonding layer 406 located on one side of the second interconnection layer 404 along the Z-axis direction, which is away from the second functional layer 402. The second bonding layer 406 is provided with a plurality of conductive structures, such as the second conductive structure 408 and the sixth conductive structure 416, and here, the second conductive structure 408 is connected with the sixth conductive structure 416. The conductive structure in the second bonding layer 406 can extend along the Z-axis direction for transmitting an electrical signal, and the conductive structure can include a conductive material, which includes but is not limited to W, Co, Cu, Al, silicide, or any combination thereof. Here, the interconnection structure in the second interconnection layer 404 can be connected with the conductive structure in the second bonding layer 406 in any suitable manner.

[0099] In some embodiments, as shown in FIG. 11, the first semiconductor structure 300 and the second semiconductor structure 400 can be connected through the first conductive structure 308 and the second conductive structure 408. Figure 2As shown in Figures (a), (b), and (c), the sixth conductive structure 416 penetrates the second bonding layer 406 along the Z-axis. At one end of the sixth conductive structure 416 along the Z-axis, it is connected to the fourth interconnect structure 414, and the other end can be connected to structures in other layers (such as the fifth conductive structure 316). At one end of the sixth conductive structure 416 along the X-axis / Y-axis, it is connected to the second conductive structure 408.

[0100] In some embodiments, such as Figure 2 As shown in Figure (a), the second MIM structure 410 is not provided in the second bonding layer 406. At this time, one end of the second conductive structure 408 is connected to the first conductive structure 308, and the other end is connected to the sixth conductive structure 416.

[0101] In some embodiments, such as Figure 2 As shown in Figures (b) and (c), a second MIM structure 410 is further provided in the second bonding layer 406. One end of the second MIM structure 410 can be connected to one end of the second conductive structure 408 along the Z-axis, and the other end of the second MIM structure 410 can be connected to the second interconnect structure 412. In other words, the second MIM structure 410 is located between the second conductive structure 408 and the second interconnect structure 412. The second conductive structure 408 is connected to the second MIM structure along the Z-axis, and the other end along the Z-axis can be connected to structures in other layers (such as the first conductive structure 308).

[0102] In some embodiments, the second bonding layer 406 may include one or more second MIM structures 410.

[0103] In some embodiments, the second MIM structure 410 includes a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer. The first electrode layer can be used as the lower electrode of the second MIM structure 410; the dielectric layer can be used as the dielectric of the second MIM structure 410; and the second electrode layer can be used as the upper electrode of the second MIM structure 410.

[0104] In some specific embodiments, reference is made to Figure 2 In Figure (b), when the semiconductor device includes only the second MIM structure 410, the first electrode layer of the second MIM structure 410 is connected to the second interconnect structure 412; the second electrode layer of the second MIM structure is connected to the other end of the second conductive structure 408; at this time, the first conductive structure 308 is directly connected to the fifth conductive structure 316.

[0105] In some specific embodiments, reference is made to Figure 2In the semiconductor device shown in FIG. 3C, when the first MIM structure 310 and the second MIM structure 410 are included in the semiconductor device, the first electrode layer of the first MIM structure 310 is connected with the first interconnection structure 312; the second electrode layer of the first MIM structure 310 is connected with the other end of the first conductive structure 308; the first electrode layer of the second MIM structure 410 is connected with the second interconnection structure 412; and the second electrode layer of the second MIM structure 410 is connected with the other end of the second conductive structure 408. Here, the first conductive structure 308 is further connected with the fifth conductive structure 316, and the second conductive structure 408 is connected with the sixth conductive structure 416. Based on this, in the embodiments of the present disclosure, the storage cell array can be coupled to the external device through the second MIM structure 410.

[0106] It should be noted that after the first semiconductor structure 300 and the second semiconductor structure 400 are bonded in stack, the first conductive structure 308 is bonded and connected with the second conductive structure 408, and the fifth conductive structure 316 is bonded and connected with the sixth conductive structure 416. The fifth conductive structure 316 is connected with the third interconnection structure 314, and the sixth conductive structure is connected with the fourth interconnection structure 414. In this way, the peripheral circuit can be connected to the storage cell array through various communication modes.

[0107] In some embodiments, the first semiconductor structure 300 can be a wafer, and the second semiconductor structure 400 can also be a wafer, i.e. Figure 1 The semiconductor device shown is a bonded stack of a wafer and a wafer (W2W).

[0108] It should be noted that, Figure 2 In the semiconductor device shown in FIG. 3C, the peripheral circuit can be connected to the storage cell array through the MIM structure, or can not be connected to the storage cell array through the MIM structure, so that the connection flexibility of the peripheral circuit can be improved. Figure 3In the semiconductor device shown in the figure, the peripheral circuit is connected to the memory cell array through the MIM structure, and the MIM structure can play a role in resisting voltage fluctuations, so that the semiconductor device can be prevented from being affected by unstable voltage signals and the like, and the reliability of the semiconductor device can be improved. On the other hand, the first and / or second MIM structure can be led out by using the first conductive structure and the second conductive structure, without the need for additional design and the addition of lead-out wires, without increasing the process difficulty. On the other hand, the MIM structure can be added in the bonding layer, the utilization rate of the bonding layer can be improved, and the utilization rate of the semiconductor device can be increased. Compared with the design of the MIM structure in the substrate device region, other dielectric layers or passivation layers, the MIM structure can reduce the space occupation of other device structures and metal interconnection structures, and reduce the electrical interference or bridging risk of the MIM capacitor structure and other devices and metal interconnection structures. In addition, due to the lower wiring density of the first conductive structure and the second conductive structure in the bonding interface relative to the substrate device region, other dielectric layers or passivation layers, and the higher layer height of the bonding layer relative to other dielectric layers or passivation layers, the same level MIM structure can be designed to have a larger charge storage capacity, so that the MIM structure can play a better role in resisting voltage fluctuations.

[0109] In some embodiments, reference is made to Figure 3 , Figure 3 Another semiconductor device cross-sectional structure diagram is provided as an example of the present disclosure. The semiconductor device can include a first semiconductor structure 600 and a plurality of second semiconductor structures 602, and the plurality of second semiconductor structures 602 are separated by an isolation structure 604. The isolation structure 604 can be any suitable material, such as an air gap, etc.

[0110] In some specific embodiments, the first semiconductor structure 600 can be a wafer (Wafer), and the second semiconductor structure 602 can be a chip (Chip), i.e. Figure 3 The semiconductor device shown is a bonded stack (C2W) of a wafer (Wafer) and a plurality of chips (Chip).

[0111] Reference is made to Figure 3 , Figure 3 Cross-sectional schematic diagrams of three cases of the semiconductor device in the XZ plane are shown in FIG. (a), FIG. (b) and FIG. (c). Among them, Figure 3 In FIG. (a) of the figure, the first bonding layer is provided with a first MIM structure 606, and the second bonding layer is not provided with a second MIM structure. Figure 3 In FIG. (b) of the figure, the first bonding layer is not provided with a first MIM structure, and the second bonding layer is provided with a second MIM structure 608. Figure 4 In FIG. (c) of the figure, the first bonding layer is provided with a first MIM structure 606, and the second bonding layer is provided with a second MIM structure 608.

[0112] Based on the above semiconductor device, the embodiment of the disclosure further provides a manufacturing method of a semiconductor device, Figure 4 The flow chart of the manufacturing method of the semiconductor device in the embodiment of the disclosure is shown in FIG. 5. Figure 4 As shown in the figure, the manufacturing method comprises the following steps:

[0113] Step S501: forming a first semiconductor structure; the first semiconductor structure comprises a first bonding layer and a first conductive structure in the first bonding layer.

[0114] Step S502: forming a second semiconductor structure; the second semiconductor structure comprises a second bonding layer and a second conductive structure in the second bonding layer.

[0115] Step S503: stacking the first semiconductor structure and the second semiconductor structure along a first direction to bond and connect one end of the first conductive structure with one end of the second conductive structure.

[0116] Step S504: the method further comprises: forming a first MIM structure in the first bonding layer, the first MIM structure being connected with the other end of the first conductive structure; and / or forming a second MIM structure in the second bonding layer, the second MIM structure being connected with the other end of the second conductive structure.

[0117] It should be understood that, Figure 4 The steps shown in the above embodiments are not exclusive, and other steps can be performed before, after or between any of the steps shown in the embodiments; Figures 5 to 18 The order of the steps shown in the above embodiments can be adjusted according to actual needs. Figures 4 to 18 The structure diagram of the manufacturing process of the semiconductor device provided by the embodiment of the disclosure is shown in FIG. 5. Figure 5 The manufacturing method of the semiconductor device provided by the embodiment of the disclosure is introduced.

[0118] In some embodiments, reference is made to Figure 5The method comprises: providing a first functional layer 701, and the first functional layer 701 is provided with a peripheral circuit or a memory cell array. The peripheral circuit can comprise a plurality of CMOS transistors and control circuits related to the CMOS transistors, such as control logic, sense amplification circuits, row decoders, column decoders, data input / output buffers, drivers, read / write circuits and the like. When the control logic receives a read / write operation command and address data, the row decoders or the column decoders can apply corresponding voltages generated from the drivers to corresponding bit lines and word lines based on the decoded address under the action of the control logic, so as to realize reading or writing of data, and interact with external devices through the data input / output buffers. The memory cell array can comprise a plurality of memory cells, which can be NAND memory cells, PCM memory cells, DRAM memory cells and the like. The method for forming the peripheral circuit or the memory cell array is relatively mature, and thus will not be described here.

[0119] In some embodiments, the peripheral circuit can also not be provided in the first functional layer, but other circuits or devices can be provided, which are not limited in the present disclosure. It should be understood that the following embodiments are only used for describing the peripheral circuit, and are not used for limiting the scope of the present disclosure, and unless otherwise emphasized, the peripheral circuit can be replaced by other circuits or devices in the embodiments of the present disclosure.

[0120] In some embodiments, reference is made to Figure 6The method further includes forming a first interconnect layer 702 on one side of the first functional layer 701 along the Z-axis direction. A plurality of interconnect structures, such as a first interconnect structure 703, a third interconnect structure 704, and the like, are formed in the first interconnect layer 702. The first interconnect structure 703 and the third interconnect structure 704 are electrically isolated from each other. The interconnect structures in the first interconnect layer 702 can include lateral wires and vias, which can be formed in one or more interlayer dielectric (ILD) layers, and the constituent materials of the interconnect structures can include conductive materials including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layers in the first interconnect layer 702 can include dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof. The method of forming the first interconnect layer 702 includes, but is not limited to, a deposition process including chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD) process, and the like.

[0121] In some embodiments, referring to Figure 7 The method further includes forming a first sub-bonding layer 705 on one side of the first interconnect layer along the Z-axis direction. The material of the first sub-bonding layer 705 includes, but is not limited to, silicon oxide. The method of forming the first sub-bonding layer 705 includes, but is not limited to, CVD, LPCVD, PECVD, PVD, ALD process, and the like.

[0122] In some embodiments, referring to Figure 8 The method further includes forming a first recess 706 in the first sub-bonding layer 705, the first recess 706 exposing the first interconnect structure 703. The method of forming the first recess 706 includes, but is not limited to, etching.

[0123] In some embodiments, referring to Figure 9, the method further comprises: forming a first conductive material layer 7071 on the surface of the first recess 706 and the first sub-bonding layer 705, forming a dielectric material layer 7072 on the surface of the first conductive material layer, and forming a second electrode material layer 7073 on the surface of the dielectric material layer 7072. The composition of the first electrode material layer and the second electrode material layer includes, but is not limited to, titanium nitride. The composition of the dielectric material layer includes a high dielectric constant (High-K) material, which generally refers to a material with a dielectric constant higher than 3.9, and is usually significantly higher than this value. In some examples, the composition of the dielectric material layer can include, but is not limited to, aluminum oxide (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc. The method of forming the first conductive material layer 7071, the dielectric material layer 7072 and the second electrode material layer 7073 includes, but is not limited to, CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0124] In some embodiments, referring to Figure 10 , the method further comprises: forming an insulating material layer 708 on the surface of the second electrode material layer 7073. The composition of the insulating material layer 708 includes, but is not limited to, silicon oxide. The method of forming the insulating material layer 708 includes, but is not limited to, CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0125] In some embodiments, referring to Figure 10 , the method further comprises: removing part of the first conductive material layer 7071 to form a first electrode layer 7074, removing part of the dielectric material layer 7072 to form a dielectric layer 7075, and removing part of the second electrode material layer 7073 to form a second electrode layer 7076. Here, the first electrode layer 7074, the dielectric layer 7075 and the second electrode layer 7076 constitute a first MIM structure. The first electrode layer can be used as the lower electrode of the first MIM structure; the dielectric layer can be used as the dielectric of the first MIM structure; and the second electrode layer can be used as the upper electrode of the first MIM structure.

[0126] Continuing to refer to Figure 11 , the method further comprises: removing part of the insulating material layer 708 to form an insulating layer 709. The insulating layer 709 covers the surface of the first MIM structure 707, and is used for isolation and protection of the first MIM structure. Here, the removal process includes, but is not limited to, etching.

[0127] In some embodiments, referring to Figure 12The method further includes forming a second sub-bonding layer 710 on the first sub-bonding layer 705, the second sub-bonding layer 710 covering the exposed first sub-bonding layer 705 and covering the insulating layer 709. The material of the second sub-bonding layer 710 can be the same as the material of the first sub-bonding layer 705, such as silicon oxide. The method of forming the second sub-bonding layer 710 includes but is not limited to CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0128] In some embodiments, referring to Figure 12 The method further includes performing a planarization process on the surface of the second sub-bonding layer 710. The planarization process includes but is not limited to a chemical mechanical polishing (CMP) process. Referring to Figure 13 The second sub-bonding layer 710 after the planarization process and the first sub-bonding layer 705 constitute a first bonding layer 711.

[0129] In some embodiments, referring to Figure 14 The method further includes forming a third recess 712 in the first bonding layer 711. The third recess 712 is located at one side of the first MIM structure 707 along the X-axis and / or Y-axis direction. The third recess 712 penetrates the first bonding layer 711 along the Z-axis direction. The method of forming the third recess 712 includes but is not limited to etching.

[0130] In some embodiments, referring to Figure 15 The method further includes forming a second recess 713 in the second sub-bonding layer 710, the second recess 713 penetrating the second sub-bonding layer 710 and the insulating layer 709 along the Z-axis direction and exposing one end of the first MIM structure 707. For example, the second recess 713 exposes the second electrode layer of the first MIM structure 707. The method of forming the second recess 713 includes but is not limited to etching. Here, the third recess 712 and the second recess 713 are isolated from each other. It should be noted that the formation sequence of the second recess 713 and the third recess 712 can be selected and set according to actual needs, and the present disclosure is not limited thereto.

[0131] In some embodiments, referring to Figure 15The method further includes forming a first conductive structure 714 in the second recess 713; the first conductive structure 714 is connected with one end of the first MIM structure 707, and the other end of the first MIM structure 707 is connected with the first interconnection structure 703. Specifically, the first conductive structure 714 is connected with the second electrode layer of the first MIM structure 707. The first electrode layer of the first MIM structure 707 is connected with the first interconnection structure 703. The material of the first conductive structure 714 includes but is not limited to W, Co, Cu, Al, silicide, or any combination thereof. The method of forming the first conductive structure 714 includes but is not limited to CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0132] With reference to the foregoing description of the first semiconductor structure 700, Figure 16 The method further includes forming a third conductive structure 715 in the third recess 712. The third conductive structure 715 penetrates the first bonding layer 711 along the Z-axis direction, and one end of the third conductive structure 715 is connected with the third interconnection structure 704. Here, the third conductive structure 715 is electrically isolated from the first conductive structure 714. The material of the third conductive structure 715 includes but is not limited to W, Co, Cu, Al, silicide, or any combination thereof. The method of forming the third conductive structure 715 includes but is not limited to CVD, LPCVD, PECVD, PVD, ALD process, etc. Here, the first conductive structure 714 and the third conductive structure 715 can be formed in the same process to save process flow and manufacturing time. They can also be formed in different processes to improve process reliability. In addition, if they are formed in different processes, the manufacturing sequence of the two can be selected and set according to actual conditions. In this way, the first semiconductor structure 700 is formed.

[0133] In other embodiments, with reference to the foregoing description of the first semiconductor structure 700, Figure 17 The method further includes forming a fourth recess 716 in the first bonding layer 711; the fourth recess 716 is in communication with the second recess 713; the method of forming the fourth recess 716 includes but is not limited to etching.

[0134] In some embodiments, with reference to the foregoing description of the first semiconductor structure 700, Figure 18 The method further includes forming a fifth conductive structure 717 in the fourth recess 716; the fifth conductive structure 717 is connected with the first conductive structure 714. Here, the first conductive structure 714 and the fifth conductive structure 717 can be formed in the same process to save process flow and manufacturing time.

[0135] In some embodiments, the method further includes providing a second functional layer, and the second functional layer is provided with a peripheral circuit or a memory cell array. The method of forming a peripheral circuit or a memory cell array is relatively mature, and will not be described here.

[0136] In other embodiments, the second functional layer can also not be provided with the array of memory cells, but other circuits or devices, which are not limited by the present disclosure. It should be understood that the following embodiments are used to describe the array of memory cells only for the purpose of illustrating the present disclosure, and are not used to limit the scope of the present disclosure, unless specifically emphasized. In the embodiments of the present disclosure, the array of memory cells can be replaced by other circuits or devices, unless specifically emphasized.

[0137] In some embodiments, the method further includes forming a second interconnect layer on one side of the second functional layer along the Z-axis direction. A plurality of interconnect structures, such as a second interconnect structure, a fourth interconnect structure, etc., are formed in the second interconnect layer. The second interconnect structure and the fourth interconnect structure are electrically isolated from each other. The interconnect structure in the second interconnect layer can include a lateral wire and a via, which can be formed in one or more interlayer dielectric (ILD) layers. The constituent material of the interconnect structure can include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layer in the first interconnect layer 702 can include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof.

[0138] The method of forming the second interconnect layer includes but is not limited to a deposition process, including CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0139] In some embodiments, the method further includes forming a third sub-bonding layer on one side of the first interconnect layer along the Z-axis direction. The material of the third sub-bonding layer includes but is not limited to silicon oxide. The method of forming the third sub-bonding layer includes but is not limited to CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0140] In some embodiments, the method further includes forming a fifth recess in the third sub-bonding layer, the fifth recess exposing the second interconnect structure. The method of forming the fifth recess includes but is not limited to etching.

[0141] In some embodiments, the method further comprises: forming a first conductive material layer on the surface of the fifth recess and the third sub-bonding layer, forming a dielectric material layer on the surface of the first conductive material layer, and forming a second electrode material layer on the surface of the dielectric material layer. The composition of the first electrode material layer and the second electrode material layer includes, but is not limited to, titanium nitride. The composition of the dielectric material layer includes a high-k material, which generally refers to a material with a dielectric constant higher than 3.9, and usually significantly higher than this value. In some specific examples, the composition of the dielectric material layer can include, but is not limited to, aluminum oxide (Al2O3), zirconium oxide (ZrO), hafnium oxide (HfO2), etc. The method of forming the first conductive material layer, the dielectric material layer, and the second electrode material layer includes, but is not limited to, CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0142] In some embodiments, the method further comprises: forming an insulating material layer on the surface of the second electrode material layer. The composition of the insulating material layer includes, but is not limited to, silicon oxide. The method of forming the insulating material layer includes, but is not limited to, CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0143] In some embodiments, the method further comprises: removing part of the first conductive material layer to form a first electrode layer, removing part of the dielectric material layer to form a dielectric layer, and removing part of the second electrode material layer to form a second electrode layer, where the first electrode layer, the dielectric layer, and the second electrode layer constitute a second MIM structure. The first electrode layer can be used as the lower electrode of the second MIM structure; the dielectric layer can be used as the dielectric of the second MIM structure; and the second electrode layer can be used as the upper electrode of the second MIM structure. The method further comprises: removing part of the insulating material layer to form an insulating layer. The insulating layer covers the surface of the second MIM structure and is used to isolate and protect the second MIM structure. Here, the removal process includes, but is not limited to, etching.

[0144] In some embodiments, the method further comprises: forming a fourth sub-bonding layer on the third sub-bonding layer, where the fourth sub-bonding layer covers the exposed third sub-bonding layer and covers the insulating layer. The material of the fourth sub-bonding layer can be the same as that of the third sub-bonding layer, such as silicon oxide. The method of forming the fourth sub-bonding layer includes, but is not limited to, CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0145] In some embodiments, the method further comprises: performing a planarization process on the surface of the fourth sub-bonding layer; here, the planarization process includes, but is not limited to, CMP. After the planarization process, the fourth sub-bonding layer and the third sub-bonding layer constitute a second bonding layer.

[0146] In some embodiments, the method further comprises forming a seventh recess in the second bonding layer. The seventh recess is located at one side of the second MIM structure along the X-axis and / or Y-axis direction. The seventh recess penetrates the second bonding layer along the Z-axis direction. The method of forming the seventh recess includes, but is not limited to, etching.

[0147] In some embodiments, the method further comprises forming a sixth recess in the fourth sub-bonding layer, the sixth recess penetrating the fourth sub-bonding layer and the insulating layer along the Z-axis direction and exposing one end of the second MIM structure; for example, the sixth recess exposes the second electrode layer of the second MIM structure. The method of forming the sixth recess includes, but is not limited to, etching. Here, the sixth recess and the seventh recess are isolated from each other. It should be noted that the formation sequence of the sixth recess and the seventh recess can be selected according to actual needs, and the present disclosure is not limited.

[0148] In some embodiments, the method further comprises forming a second conductive structure in the sixth recess; the second conductive structure is connected to one end of the second MIM structure; in particular, the second conductive structure is connected to the second electrode layer of the second MIM structure. The composition material of the second conductive structure includes, but is not limited to, W, Co, Cu, Al, silicide or any combination thereof. The method of forming the second conductive structure includes, but is not limited to, CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0149] The method further comprises forming a fourth conductive structure in the seventh recess. Here, the fourth conductive structure and the second conductive structure are electrically isolated from each other. The composition material of the fourth conductive structure includes, but is not limited to, W, Co, Cu, Al, silicide or any combination thereof. The method of forming the fourth conductive structure includes, but is not limited to, CVD, LPCVD, PECVD, PVD, ALD process, etc. In this way, the second semiconductor structure is formed.

[0150] In other embodiments, the method further comprises forming an eighth recess in the second bonding layer; the eighth recess communicates with the sixth recess; and forming a sixth conductive structure in the eighth recess; the sixth conductive structure is connected to the second conductive structure. The process of forming the eighth recess includes, but is not limited to, etching, and the method of forming the sixth conductive structure includes, but is not limited to, CVD, LPCVD, PECVD, PVD, ALD process, etc.

[0151] In some embodiments, with reference to Figure 18 , the method further comprises bonding connecting the first semiconductor structure 700 and the second semiconductor structure 800 along the Z-axis direction, so that one end of the first conductive structure is bonded connected to one end of the second conductive structure, and the third conductive structure is connected to the fourth conductive structure. It should be noted that Figure 18The first semiconductor structure 700 in the semiconductor device shown in FIG. 1 is provided with the first MIM structure 707, and the second semiconductor structure 800 is provided with the second MIM structure 718. In other embodiments of the semiconductor device, the first MIM structure can be provided only in the first semiconductor structure, or the second MIM structure can be provided only in the second semiconductor structure, which is not limited in the present disclosure.

[0152] In addition, ​ The semiconductor device shown in FIG. 1 includes a first conductive structure, a second conductive structure, a third conductive structure, and a fourth conductive structure, wherein the first conductive structure and the third conductive structure are electrically isolated from each other, and the second conductive structure and the fourth conductive structure are electrically isolated from each other. In other embodiments, the semiconductor device includes a first conductive structure, a second conductive structure, a fifth conductive structure, and a sixth conductive structure, wherein the first conductive structure is connected to the fifth conductive structure, and the second conductive structure is connected to the sixth conductive structure. The present disclosure is not limited in this regard.

[0153] It should be noted that "first", "second", and the like are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence. In addition, the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0154] The above is only a preferred embodiment of the present disclosure, and is not intended to limit the protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: A first semiconductor structure and a second semiconductor structure stacked along a first direction; The first semiconductor structure includes: a first bonding layer and a first conductive structure located in the first bonding layer. The first semiconductor structure includes a first functional layer, in which peripheral circuits and / or a memory cell array are disposed. The first semiconductor structure also includes a first interconnect layer. The second semiconductor structure includes: a second bonding layer, and a second conductive structure located in the second bonding layer. The second semiconductor structure includes a second functional layer, in which peripheral circuits and / or a memory cell array are disposed. The second semiconductor structure also includes a second interconnect layer. One end of the first conductive structure is bonded to one end of the second conductive structure. The semiconductor device further includes: a first MIM structure located in the first bonding layer, the first MIM structure being connected to the other end of the first conductive structure; and / or, a second MIM structure located in the second bonding layer, the second MIM structure being connected to the other end of the second conductive structure.

2. The semiconductor device according to claim 1, characterized in that, The first bonding layer includes one or more of the first MIM structures; The second bonding layer includes one or more of the second MIM structures.

3. The semiconductor device according to claim 1, characterized in that, Both the first MIM structure and the second MIM structure include a first electrode layer, a second electrode layer, and a dielectric layer located between the first electrode layer and the second electrode layer.

4. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes: a first interconnect structure located in the first interconnect layer; and a second interconnect structure located in the second interconnect layer; wherein the first functional layer is located on one side of the first interconnect layer along the first direction away from the first bonding layer; and the second functional layer is located on one side of the second interconnect layer along the first direction away from the second bonding layer.

5. The semiconductor device according to claim 4, characterized in that, When the semiconductor device includes only the first MIM structure, the first electrode layer of the first MIM structure is connected to the first interconnect structure; the second electrode layer of the first MIM structure is connected to the other end of the first conductive structure; and the second conductive structure is directly connected to the second interconnect structure.

6. The semiconductor device according to claim 4, characterized in that, When the semiconductor device includes only the second MIM structure, the first electrode layer of the second MIM structure is connected to the second interconnect structure; the second electrode layer of the second MIM structure is connected to the other end of the second conductive structure; and the first conductive structure is directly connected to the first interconnect structure.

7. The semiconductor device according to claim 4, characterized in that, When the semiconductor device includes the first MIM structure and the second MIM structure, the first electrode layer of the first MIM structure is connected to the first interconnect structure; the second electrode layer of the first MIM structure is connected to the other end of the first conductive structure; the first electrode layer of the second MIM structure is connected to the second interconnect structure; and the second electrode layer of the second MIM structure is connected to the other end of the second conductive structure.

8. The semiconductor device according to any one of claims 4 to 7, characterized in that, The semiconductor device further includes: A third conductive structure penetrating the first bonding layer and a fourth conductive structure penetrating the second bonding layer, wherein the third conductive structure and the fourth conductive structure are bonded together; wherein the third conductive structure is electrically isolated from the first conductive structure, and the fourth conductive structure is electrically isolated from the second conductive structure.

9. The semiconductor device according to claim 8, characterized in that, The semiconductor device further includes: a third interconnect structure located in the first interconnect layer, the third interconnect structure being electrically isolated from the first interconnect structure; and a fourth interconnect structure located in the second interconnect layer, the fourth interconnect structure being electrically isolated from the second interconnect structure. The third conductive structure is connected to the third interconnect structure, and the fourth conductive structure is connected to the fourth interconnect structure.

10. The semiconductor device according to claim 4, characterized in that, The peripheral circuit is located on one side of the first interconnect layer along the first direction, away from the first bonding layer; and the memory cell array is located on one side of the second interconnect layer along the first direction, away from the second bonding layer.

11. The semiconductor device according to any one of claims 1 to 3, characterized in that, The semiconductor device further includes: A fifth conductive structure located in the first bonding layer, the fifth conductive structure being connected to the first conductive structure; and a sixth conductive structure located in the second bonding layer, the sixth conductive structure being connected to the second conductive structure.

12. A method for manufacturing a semiconductor device, characterized in that, The method includes: A first semiconductor structure is formed; the first semiconductor structure includes: a first bonding layer and a first conductive structure located in the first bonding layer, the first semiconductor structure includes a first functional layer, the first functional layer is provided with peripheral circuits and / or a memory cell array, and the first semiconductor structure further includes a first interconnect layer; A second semiconductor structure is formed; the second semiconductor structure includes: a second bonding layer, and a second conductive structure located in the second bonding layer; the second semiconductor structure includes a second functional layer, in which peripheral circuits and / or a memory cell array are disposed; the second semiconductor structure further includes a second interconnect layer. The first semiconductor structure and the second semiconductor structure are stacked along a first direction so that one end of the first conductive structure is bonded to one end of the second conductive structure. The method further includes: forming a first MIM structure in the first bonding layer, wherein the first MIM structure is connected to the other end of the first conductive structure; and / or forming a second MIM structure in the second bonding layer, wherein the second MIM structure is connected to the other end of the second conductive structure.

13. The manufacturing method according to claim 12, characterized in that, The formation of the first semiconductor structure includes: A first interconnect structure is formed in the first interconnect layer; A first sub-bonding layer is formed on one side of the first interconnect layer along the first direction; A first groove is formed in the first sub-bonding layer, the first groove exposing the first interconnect structure; A first conductive layer is formed in the first groove and on a portion of the surface of the first sub-bonding layer, a dielectric layer is formed on the surface of the first conductive layer, and a second electrode layer is formed on the surface of the dielectric layer to form a first MIM structure.

14. The manufacturing method according to claim 13, characterized in that, The method further includes: A second sub-bonding layer is formed on the first sub-bonding layer; A second groove is formed in the second sub-bonding layer, penetrating the second sub-bonding layer, and the second groove exposes one end of the first MIM structure; A first conductive structure is formed in the second groove; the first conductive structure is connected to one end of the first MIM structure. The first sub-bonding layer and the second sub-bonding layer constitute the first bonding layer.

15. The manufacturing method according to claim 14, characterized in that, The method further includes: A third groove is formed in the first bonding layer; the third groove is spaced apart from the second groove. A third conductive structure is formed in the third groove; the third conductive structure is electrically isolated from the first conductive structure.

16. The manufacturing method according to claim 14, characterized in that, The method further includes: A fourth groove is formed in the first bonding layer; the fourth groove is connected to the second groove. A fifth conductive structure is formed in the fourth groove; the fifth conductive structure is connected to the first conductive structure.

17. The manufacturing method according to claim 12, characterized in that, The formation of the second semiconductor structure includes: A second interconnect structure is formed in the second interconnect layer; A third sub-bonding layer is formed on one side of the second interconnect layer along the first direction; A fifth groove is formed in the third sub-bonding layer, the fifth groove exposing the second interconnect structure; A first conductive layer is formed in the fifth groove and on a portion of the surface of the third sub-bonding layer. A dielectric layer is formed on the surface of the first conductive layer, and a second electrode layer is formed on the surface of the dielectric layer to form a second MIM structure.

18. The manufacturing method according to claim 17, characterized in that, The method further includes: A fourth sub-bonding layer is formed on the third sub-bonding layer; A sixth groove is formed in the fourth sub-bonding layer, the sixth groove exposing the second MIM structure located on a portion of the surface of the third sub-bonding layer; A second conductive structure is formed in the sixth groove; the second conductive structure is connected to the second MIM structure. The third sub-bond synthesis and the fourth sub-bonding layer constitute the second bonding layer.

19. The manufacturing method according to claim 18, characterized in that, The method further includes: A seventh groove is formed in the second bonding layer; the seventh groove is spaced apart from the sixth groove. A fourth conductive structure is formed in the seventh groove; the fourth conductive structure is electrically isolated from the second conductive structure.

20. The manufacturing method according to claim 19, characterized in that, The method further includes: An eighth groove is formed in the second bonding layer; the eighth groove communicates with the fifth groove. A sixth conductive structure is formed in the eighth groove; the sixth conductive structure is connected to the second conductive structure.

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