An acot control circuit for buck power supply

Abstract

The application discloses an ACOT control circuit for a BUCK power supply, comprising a SW node and an LDRV node of a BUCK circuit, wherein the SW node is a switch node connected with upper and lower power tubes in the BUCK circuit, and the LDRV node inputs a driving signal of the lower power tube of the BUCK circuit, further comprising a comparator, a second NMOS tube, a current generating resistor and a charging capacitor, wherein the SW node is connected with a negative input end of the comparator through the current generating resistor, the charging capacitor changes the voltage of the negative input end of the comparator through the second NMOS tube, and the second NMOS tube controls its switch through the signal input from the LDRV node; further comprising a follower, a charging resistor, a voltage dividing resistor and a current mirror, wherein the SW node is connected with a positive input end of the comparator through the voltage dividing resistor, the follower, the current mirror and the charging resistor in sequence.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an ACOT control circuit for a BUCK power supply. Background Technology

[0002] like Figure 1 As shown, the COT constant on-time control mode in the BUCK circuit has been widely used in switching power supply management chips due to its simple control mode and fast load response speed. However, because its working principle is based on a fixed on-time of the upper transistor, the chip frequency will change with the input voltage, resulting in poor EMC performance. The ACOT control mode was thus developed, which adaptively adjusts the on-time of the upper transistor (Ton) to keep the chip operating frequency relatively constant, thereby improving EMC performance. Summary of the Invention

[0003] In view of the above-mentioned shortcomings in the current integrated circuit technology field, the present invention provides an ACOT control circuit for BUCK power supply, which can obtain a power supply system with constant switching frequency, effectively improve the EMC characteristics of the system, and at the same time, errors in the circuit can be optimized by means of structural modification and replacement, further enabling the system frequency to match the set value.

[0004] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions:

[0005] An ACOT control circuit for a BUCK power supply includes an SW node and an LDRV node of the BUCK circuit. The SW node is a switching node connecting the upper and lower power transistors in the BUCK circuit. The LDRV node receives the drive signal of the lower power transistor of the BUCK circuit. The circuit also includes a comparator, a second NMOS transistor, a current generating resistor, and a charging capacitor. The SW node is connected to the negative input terminal of the comparator through the current generating resistor. The charging capacitor changes the voltage at the negative input terminal of the comparator through the second NMOS transistor. The second NMOS transistor controls its own switching through the signal input to the LDRV node. The circuit also includes a follower, a charging resistor, a voltage divider resistor, and a current mirror. The SW node is connected to the positive input terminal of the comparator in sequence through the voltage divider resistor, the follower, the current mirror, and the charging resistor.

[0006] According to one aspect of the present invention, the voltage divider resistor includes a first voltage divider resistor and a second voltage divider resistor, wherein the sum of the resistance of the first voltage divider resistor and the second voltage divider resistor is set as a fixed multiple of the resistance of the second voltage divider resistor.

[0007] According to one aspect of the invention, it further includes a first filter and a second filter connected together, the first filter and the second filter being connected between the voltage divider resistor and the follower.

[0008] According to one aspect of the present application, the follower comprises an amplifier, an external frequency selection resistor and a first NMOS transistor, the positive input terminal of the amplifier is connected to a voltage dividing resistor, the negative input terminal of the amplifier is connected to one end of the external frequency selection resistor, the other end of the external frequency selection resistor is connected to ground, the output terminal of the amplifier is connected to the gate of the first NMOS transistor, the source of the first NMOS transistor is connected to the external frequency selection resistor, and the drain of the first NMOS transistor is connected to a current mirror.

[0009] According to one aspect of the present application, the current mirror comprises a first PMOS transistor and a second PMOS transistor, the drain and gate of the first PMOS transistor are connected to each other, the drain is connected to the follower, and the gate is connected to the gate of the second PMOS transistor; the source of the first PMOS transistor and the source of the second PMOS transistor are connected to VDD, and the drain of the second PMOS transistor is connected to a charging resistor and the positive input terminal of a comparator.

[0010] According to one aspect of the present application, the number of the first PMOS transistor and the second PMOS transistor in parallel is set to a fixed value.

[0011] According to one aspect of the present application, one end of the charging resistor is connected to the current mirror and the positive input terminal of the comparator, and the other end is connected to ground.

[0012] According to one aspect of the present application, a third PMOS transistor is further included, the third PMOS transistor is used as an upper clamp, the gate of the third PMOS transistor is connected to the charging resistor, the drain is connected to ground, and the source is connected to the negative input terminal of the comparator.

[0013] According to one aspect of the present application, when the second NMOS transistor is turned off, the SW node charges the charging capacitor, the lower power transistor in the BUCK circuit is turned off, the upper power transistor is turned on, and the input voltage of the SW node is the input voltage of the BUCK circuit.

[0014] According to one aspect of the present application, when the second NMOS transistor is turned off, the voltage at the negative input terminal of the comparator slowly rises until it reaches the voltage at the positive input terminal of the comparator, the output of the comparator flips, and the signal outputted is finally controlled by a logic circuit to control the turn-on time of the upper power transistor.

[0015] The advantages of the embodiment of the present application: the SW node and the LDRV node of the BUCK circuit, the SW node is the switch node connected with the upper power tube and the lower power tube in the BUCK circuit, the LDRV node inputs the driving signal of the lower power tube of the BUCK circuit, further comprising a comparator, a second NMOS tube, a current generating resistor and a charging capacitor, the SW node is connected with the negative input end of the comparator through the current generating resistor, the charging capacitor changes the voltage of the negative input end of the comparator through the second NMOS tube, and the second NMOS tube controls its switch through the signal input from the LDRV node; further comprising a follower, a charging resistor, a voltage dividing resistor and a current mirror, the SW node is connected with the positive input end of the comparator through the voltage dividing resistor, the follower, the current mirror and the charging resistor in sequence, the power supply system with constant switching frequency can be obtained, the EMC characteristics of the system are effectively improved, and the error and the like in the circuit can be optimized through the structure modification replacement and the like, so that the system frequency is matched with the set value. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0017] Figure 1 The BUCK circuit overall block diagram of the ACOT control circuit for the BUCK power supply according to the present application;

[0018] Figure 2 The circuit structure schematic diagram of the ACOT control circuit for the BUCK power supply according to the present application. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the present application.

[0020] Embodiment one:

[0021] As Figure 2As shown, an ACOT control circuit for a BUCK power supply includes a SW node, an input voltage VDD, an LDRV node, a comparator COMP, a voltage dividing resistor, a filter, a follower, a current mirror, a charging resistor R0, a current generating resistor RX, a charging capacitor C0, a second NMOS transistor MN2 and a third PMOS transistor MP3. The SW node is a switch node connected to upper and lower power transistors in a BUCK circuit, and the LDRV node inputs a same-phase control signal for driving a lower power transistor in the BUCK circuit. The SW node is connected to the positive input terminal of the comparator COMP through the voltage dividing resistor, the filter, the follower and the current mirror in sequence.

[0022] The voltage dividing resistor includes a first voltage dividing resistor R1 and a second voltage dividing resistor R2; the filter includes a first filter and a second filter, the first filter includes a resistor R3 and a capacitor C1, and the second filter includes a resistor R4 and a capacitor C2; the follower includes an amplifier OP, a first NMOS transistor MN1 and an external frequency selection resistor RT; and the current mirror includes a first PMOS transistor MP1 and a second PMOS transistor MP2.

[0023] One end of the SW node is connected to the first voltage dividing resistor R1, the other end of the first voltage dividing resistor R1 is connected to the second voltage dividing resistor R2 and the resistor R3, and the other end of the second voltage dividing resistor R2 is connected to the ground. The ratio of the resistance value of the first voltage dividing resistor R1 plus the second voltage dividing resistor R2 to the resistance value of the second voltage dividing resistor R2 is set to n:1. The other end of the resistor R3 is connected to the capacitor C1 and the resistor R4, the other end of the resistor R4 is connected to the capacitor C2 and the positive input terminal of the amplifier OP, and the other ends of the capacitor C1 and the capacitor C2 are connected to the ground. The negative input terminal of the amplifier OP is connected to the external frequency selection resistor RT, the other end of the external frequency selection resistor RT is connected to the ground, the output terminal of the amplifier OP is connected to the gate of the first NMOS transistor MN1, the source of the first NMOS transistor MN1 is connected to the external frequency selection resistor RT, and the drain of the first NMOS transistor MN1 is connected to the drain of the first PMOS transistor MP1. The point where the positive input terminal of the amplifier OP is connected is set to A, and the point where the source of the first NMOS transistor MN1 is connected is set to B. The gate and the drain of the first PMOS transistor MP1 are connected to each other, the gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2, the source of the first PMOS transistor MP1 and the source of the second PMOS transistor MP2 are connected to the power supply VDD, the drain of the second PMOS transistor MP2 is connected to the positive input terminal of the comparator COMP and the charging resistor R0, and the number of the first PMOS transistor MP1 and the second PMOS transistor MP2 in parallel is set to m:1, that is, the current flowing through the drain of the first PMOS transistor MP1 is m times the current flowing through the second PMOS transistor MP2. The other end of the charging resistor R0 is connected to the ground, and the point where the positive input terminal of the comparator COMP is connected is set to C.

[0024] The SW node is connected to a current generating resistor RX, the other end of the current generating resistor RX is connected to the negative input terminal of a comparator COMP and a charging capacitor C0 respectively, the other end of the charging capacitor C0 is connected to the ground, and the negative input terminal of the comparator COMP is connected to a point set as D. The drain of a second NMOS transistor MN2 is connected to the negative input terminal of the comparator COMP, the source is connected to the ground, and the gate is connected to an LDRV node. The source of a third PMOS transistor MP3 is connected to the negative input terminal of the comparator COMP, the drain is connected to the ground, and the gate is connected to the drain of a second PMOS transistor MP2. The comparator COMP outputs a TON signal.

[0025] The SW node is divided by a first voltage dividing resistor R1 and a second voltage dividing resistor R2, and the resistance value of the first voltage dividing resistor R1 plus the second voltage dividing resistor R2 is n times the resistance value of the second voltage dividing resistor R2. After the voltage division, the voltage at point A is obtained through a second filter composed of a third resistor R3, a first capacitor C1, a fourth resistor R4 and a second capacitor C2. Since the SW is a switch node connected to the upper power transistor and the lower power transistor of the BUCK circuit, the voltage value after passing through the two-stage filter is the output voltage value VOUT set by the BUCK circuit, and the voltage at point A is VOUT / n after the resistance division by n times. The relationship between the output voltage and the input voltage of the BUCK circuit is . Wherein, D is the duty cycle. Therefore, the voltage at point A can be expressed as .

[0026] An amplifier OP, a first NMOS transistor MN1 and an external frequency selection resistor RT constitute a follower to transmit the voltage at point A to point B. Thus, the current flowing through the external frequency selection resistor RT is .

[0027] The current flowing through the charging resistor is m times the current mirror composed of the first PMOS transistor MP1 and the second PMOS transistor MP2, and the voltage at point C is .

[0028] For the comparator COMP, the voltage value at the positive input terminal is the voltage at point C, and the voltage at the negative input terminal is a triangular wave voltage signal obtained by charging and discharging the charging capacitor C0 controlled by the same phase control signal LDRV driven by the lower power transistor. The charging current is obtained by dividing the voltage at the SW node by the current generating resistor RX, and the SW node charges the charging capacitor C0 when the second NMOS transistor MN2 is off. At this time, the lower power transistor is off and the upper power transistor is on, and the SW voltage is the VIN voltage, so the charging current of the capacitor C0 is The voltage at point C is the input voltage of the positive input end of the comparator COMP, and the voltage at point D is slowly raised until it reaches the voltage at point C, the output of the comparator COMP flips, and the output TON signal finally controls the turn-on time of the upper power tube after subsequent logic circuits. Until the lower power tube is turned on, the corresponding second NMOS tube MN2 opens to pull down the voltage at point D to 0, and after the lower power tube is turned off, the voltage at point D is raised again to enter the next cycle and continuously control the upper power tube. Therefore, the actual turn-on time of the output signal TON, that is, the time for charging the voltage at point D on the capacitor to the voltage at point C, can be calculated by the formula . , wherein T is the chip operating frequency, which can be calculated by the above formula , and the overall chip frequency is , wherein n is the resistance multiple of the voltage dividing resistor, m is the current mirror multiple, R0 is the resistance value of the charging resistor, RX is the resistance value of the current generating resistor, and C is the capacitance value of the charging capacitor, all of which are fixed values. RT is the resistance value of the external frequency selection resistor, which can be adjusted and selected according to actual needs. The third PMOS tube MP3 is used as an upper clamp to avoid the voltage at point D from being too high above the voltage at point C. Through the above working principle introduction, it can be concluded that the frequency of the chip is only linearly controlled by the external frequency selection resistor and is irrelevant to the input voltage VIN of the BUCK circuit.

[0029] The advantages of the embodiment of the present application include a SW node and an LDRV node of a BUCK circuit, the SW node is a switch node connected between the upper power tube and the lower power tube in the BUCK circuit, the LDRV node inputs the lower power tube driving signal of the BUCK circuit, further including a comparator, a second NMOS tube, a current generating resistor and a charging capacitor, the SW node is connected to the negative input end of the comparator through the current generating resistor, the charging capacitor changes the voltage at the negative input end of the comparator through the second NMOS tube, and the second NMOS tube controls its own switch through the signal input from the LDRV node; further including a follower, a charging resistor, a voltage dividing resistor and a current mirror, the SW node is connected to the positive input end of the comparator through the voltage dividing resistor, the follower, the current mirror and the charging resistor in sequence, a power supply system with constant switching frequency can be obtained, the EMC characteristics of the system are effectively improved, and errors and the like in the circuit can be optimized through structure modification and replacement, further matching the system frequency with the set value.

[0030] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any changes or replacements that can be easily thought of by those skilled in the art within the technical range disclosed by the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An ACOT control circuit for a BUCK power supply, comprising a SW node and a LDRV node of a BUCK circuit, the SW node being a switch node connected to upper and lower power transistors in the BUCK circuit, the LDRV node inputting a lower power transistor drive signal of the BUCK circuit, characterized in that, The comparator, the second NMOS tube, the current generating resistor and the charging capacitor are further included, the SW node is connected with the negative input end of the comparator through the current generating resistor, the charging capacitor changes the voltage of the negative input end of the comparator through the second NMOS tube, the second NMOS tube controls the switch of itself through the signal inputted by the LDRV node; the follower, the charging resistor, the voltage dividing resistor and the current mirror are further included, the SW node is connected with the positive input end of the comparator through the voltage dividing resistor, the follower and the current mirror in sequence, one end of the charging resistor is connected with the positive input end of the comparator and the current mirror, and the other end is connected with the ground.

2. The ACOT control circuit for a BUCK power supply according to claim 1, wherein, The voltage dividing resistor includes the first voltage dividing resistor and the second voltage dividing resistor, and the resistance value of the first voltage dividing resistor plus the second voltage dividing resistor is set as a fixed multiple of the resistance value of the second voltage dividing resistor.

3. The ACOT control circuit for a BUCK power supply according to claim 1, wherein, The first filter and the second filter connected in sequence are further included, and the first filter and the second filter are connected between the voltage dividing resistor and the follower.

4. The ACOT control circuit for a BUCK power supply according to claim 1, wherein, The follower includes the amplifier, the external frequency selection resistor and the first NMOS tube, the positive input end of the amplifier is connected with the voltage dividing resistor, the negative input end is connected with one end of the external frequency selection resistor, the other end of the external frequency selection resistor is connected with the ground, the output end of the amplifier is connected with the gate of the first NMOS tube, the source of the first NMOS tube is connected with the external frequency selection resistor, and the drain of the first NMOS tube is connected with the current mirror.

5. The ACOT control circuit for a BUCK power supply according to claim 1, wherein, The current mirror includes the first PMOS tube and the second PMOS tube, the drain and the gate of the first PMOS tube are connected with each other, the drain is connected with the follower, and the gate is connected with the gate of the second PMOS tube; the source of the first PMOS tube and the source of the second PMOS tube are connected with VDD, and the drain of the second PMOS tube is connected with the charging resistor and the positive input end of the comparator.

6. The ACOT control circuit for a BUCK power supply according to claim 5, wherein, The number of the first PMOS tube and the second PMOS tube in parallel is set as a fixed value.

7. The ACOT control circuit for a BUCK power supply according to claim 1, wherein, The third PMOS tube is further included, the third PMOS tube is used as an upper clamp, the gate of the third PMOS tube is connected with the charging resistor, the drain is connected with the ground, and the source is connected with the negative input end of the comparator.

8. The ACOT control circuit for a BUCK power supply according to any one of claims 1 to 7, wherein, When the second NMOS tube is turned off, the SW node charges the charging capacitor, the lower power tube in the BUCK circuit is turned off, the upper power tube is turned on, and the input voltage of the SW node is the input voltage of the BUCK circuit.

9. The ACOT control circuit for a BUCK power supply according to claim 8, wherein, When the second NMOS tube is turned off, the voltage of the negative input end of the comparator slowly rises until the voltage of the positive input end of the comparator is reached, the output of the comparator flips, and the signal outputted finally controls the turn-on time of the upper power tube through the logic circuit.

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