Method for optimizing efficiency of dab converter, electronic device, and storage medium

Abstract

The application relates to the new energy technology field, in particular to a DAB converter efficiency optimization method, an electronic device and a storage medium. The method comprises the following steps: calculating an offset proportion coefficient and a first phase shift parameter in a heavy load mode, and a first phase shift parameter in a light load mode according to an output power reference value, a battery side voltage sampling value and a bus side voltage sampling value; determining a second phase shift parameter and a switching frequency in the heavy load mode according to the offset proportion coefficient and the first phase shift parameter in the heavy load mode, and determining a second phase shift parameter in the light load mode according to the first phase shift parameter in the light load mode; determining a current working mode based on the offset proportion coefficient in the heavy load mode and a preset dead zone proportion; and generating a driving signal of each power switch based on the first phase shift parameter, the second phase shift parameter and the switching frequency corresponding to the current working mode. The method improves the overall efficiency of the DAB converter under different load conditions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of new energy, in particular to an efficiency optimization method of a DAB converter, an electronic device and a storage medium. BACKGROUND

[0002] In recent years, low-voltage and high-capacity single-cell battery energy storage systems (BESS) gradually dominate the market due to their high cost-effectiveness and simple battery management system design. In order to realize efficient energy interaction with the power grid, single-cell BESS needs to be equipped with a high-voltage-ratio DC-DC converter and adopt a complex control strategy to raise its output voltage to a level compatible with the power grid, meeting the requirements of power grid access.

[0003] Dual active bridge (DAB) converters are widely used in modern energy conversion systems due to their excellent bidirectional energy transmission capability and inherent soft switching characteristics. However, in practical applications, DAB converters still face many challenges in maintaining high efficiency when operating under extreme voltage ratios.

[0004] Existing control strategies have obvious limitations when dealing with partial load operation of DAB converters. On the one hand, large circulating reactive power not only increases the energy loss of the system but also reduces the effectiveness of power transmission. On the other hand, the reduction of soft switching window makes it difficult for switching devices to switch under ideal zero-voltage conditions, resulting in increased switching loss. These two factors together significantly reduce the performance of DAB converters under partial load conditions, making it difficult to meet the growing demand for efficient and stable energy conversion. SUMMARY

[0005] Embodiments of the present application aim to provide an efficiency optimization method of a DAB converter, an electronic device and a storage medium to solve the problem of large energy loss in the control strategy of the DAB converter in the prior art.

[0006] To solve the above technical problems, the embodiments of the present application provide the following technical solutions:

[0007] According to a first aspect of the present application, an efficiency optimization method of a DAB converter is provided, the DAB converter adopts dual phase-shift control, and first and second phase-shift parameters are defined based on the dual phase-shift control mode, the first phase-shift parameter is the ratio of nVp pulse width to switching period, and the second phase-shift parameter is the ratio of the midpoint difference between the high-level pulse of Vs and nVp to the switching period, nVp is the normalized voltage of the primary side, and Vs is the output voltage of the transformer, the method comprising:

[0008] Step A: obtaining an output power reference value, a battery-side voltage sampling value and a bus-side voltage sampling value;

[0009] Step B: calculating, according to the output power reference value, the battery-side voltage sampling value and the bus-side voltage sampling value, a staggered proportion coefficient and the first phase shift parameter for achieving a first optimization target in a heavy load mode, and the first phase shift parameter for achieving a second optimization target in a light load mode, the staggered proportion coefficient being a ratio of a high level pulse starting point difference value of Vs and nVp to a pulse width of nVp;

[0010] Step C: determining, according to the staggered proportion coefficient and the first phase shift parameter in the heavy load mode, the second phase shift parameter and the switching frequency in the heavy load mode, and determining, according to the first phase shift parameter in the light load mode, the second phase shift parameter in the light load mode;

[0011] Step D: determining a current working mode based on the staggered proportion coefficient in the heavy load mode and a preset dead zone proportion;

[0012] Step E: generating a driving signal of each power switch based on the first phase shift parameter, the second phase shift parameter and the switching frequency corresponding to the current working mode, wherein the switching frequency of the DAB converter in the light load mode is a preset value.

[0013] Optionally, when the DAB converter is in the heavy load mode, the high level of nVp is partially staggered and partially overlapped with the high level of Vs, and when the DAB converter is in the light load mode, the high level of nVp is completely overlapped with the high level of Vs.

[0014] Optionally, the first optimization target is to minimize the backflow reactive power under the premise of ensuring that all power switches achieve zero voltage switching, and the second optimization target is to ensure that all power switches achieve zero voltage switching.

[0015] Optionally, the first phase shift parameter calculation formula for achieving the first optimization target in the heavy load mode is:

[0016]

[0017] The first phase shift parameter calculation formula for achieving the second optimization target in the light load mode is:

[0018]

[0019] wherein, is the first phase shift parameter in the heavy load mode, is the first phase shift parameter in the light load mode, is the output power reference value, a battery-side voltage sampling value, a voltage conversion ratio, a power transmission ratio, a bus-side voltage sampling value, a high-frequency transformer turn ratio, a reference switching frequency in a heavy load mode, a secondary side leakage inductance size, a switching frequency in a light load mode.

[0020] Optionally, the calculation formula of the staggered proportion coefficient for achieving the first optimization target in the heavy load mode is:

[0021]

[0022] wherein, the staggered proportion coefficient for achieving the first optimization target in the heavy load mode.

[0023] Optionally, the current working mode is determined based on the staggered proportion coefficient in the heavy load mode and a preset dead zone proportion, and the method comprises:

[0024] multiplying the staggered proportion coefficient in the heavy load mode and the first phase shift parameter in the heavy load mode to obtain a high level staggered proportion of Vs and nVp in the heavy load mode;

[0025] determining whether the high level staggered proportion is greater than twice the preset dead zone proportion, if yes, determining that the current working mode is the heavy load mode, and if no, determining that the current working mode is the light load mode.

[0026] Optionally, the calculation formula of the second phase shift parameter in the heavy load mode is:

[0027]

[0028] the calculation formula of the switching frequency in the heavy load mode is:

[0029]

[0030] the calculation formula of the second phase shift parameter in the light load mode is:

[0031]

[0032] wherein, the second phase shift parameter in the heavy load mode, the second phase shift parameter in the light load mode.

[0033] Optionally, the method further comprises, after the step B and before the step C:

[0034] acquire a bus side current sampling value, calculate a current error value according to the output power reference value, the bus side voltage sampling value and the bus side current sampling value;

[0035] obtain a correction value of the first phase shift parameter based on the current error value by using a proportional integral controller;

[0036] correct the first phase shift parameter in the heavy load mode and the first phase shift parameter in the light load mode based on the correction value respectively.

[0037] According to a second aspect of the present application, an electronic device is provided, comprising at least one processor and a memory connected with the at least one processor in communication, the memory storing instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method described above.

[0038] According to a third aspect of the present application, a computer storage medium is provided, the computer storage medium storing instructions or programs, when the instructions or programs are executed by at least one processor, the at least one processor executes the method described above.

[0039] The beneficial effects of the embodiments of the present application are: different from the prior art, in the embodiments of the present application, an efficiency optimization method of DAB converter is provided, the DAB converter adopts double phase shift control, and the first phase shift parameter and the second phase shift parameter are defined in advance based on the double phase shift control mode. The efficiency optimization method comprises the following steps: first, according to the output power reference value, the battery side voltage sampling value and the bus side voltage sampling value, the offset proportion coefficient, the first phase shift parameter in the heavy load mode for realizing the first optimization target and the first phase shift parameter in the light load mode for realizing the second optimization target are calculated, then the second phase shift parameter and the switching frequency in the heavy load mode are calculated according to the offset proportion coefficient and the first phase shift parameter in the heavy load mode, and the second phase shift parameter in the light load mode is calculated according to the first phase shift parameter in the light load mode; finally, the current working mode is determined based on the offset proportion coefficient in the heavy load mode and the preset dead zone proportion, and the driving signals of each power switch are generated based on the first phase shift parameter, the second phase shift parameter and the switching frequency corresponding to the current working mode. The method of the present application proposes a full range efficiency optimization control strategy for high step-up ratio DAB converter, in the heavy load mode, the system efficiency is improved by jointly optimizing the zero voltage switch and minimizing the backflow power; and in the light load mode, the zero voltage switch effect in the full range is focused on to ensure high efficiency performance. Overall, the method of the present application not only improves the overall efficiency of the DAB converter under different load conditions, but also ensures the economy and practicability of the system. BRIEF DESCRIPTION OF DRAWINGS

[0040] One or more embodiments are illustrated by way of example in the drawings in which like reference numerals indicate similar elements, and as such, the drawings should be considered for purposes of illustration only. The drawings are not necessarily drawn to scale, and the exemplary nature of the various drawings should not be considered limiting.

[0041] Figure 1 is a topological structure diagram of a high-voltage-ratio DAB converter provided by an embodiment of the present application;

[0042] Figure 2 is a schematic diagram of six working modes provided by an embodiment of the present application;

[0043] Figure 3 is a typical waveform diagram of mode B1 provided by an embodiment of the present application;

[0044] Figure 4 is a typical waveform diagram of mode C1 provided by an embodiment of the present application;

[0045] Figure 5 is a flowchart of an efficiency optimization method of a DAB converter provided by an embodiment of the present application;

[0046] Figure 6 is a block diagram of an optimized control strategy of a DAB converter provided by an embodiment of the present application;

[0047] Figure 7 is a simulation waveform diagram of the efficiency optimization method of the present application under various working conditions;

[0048] Figure 8 is Figure 7 a ZVS performance diagram corresponding to each working condition in the above table;

[0049] Figure 9 is a structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in connection with the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0051] In addition, the technical features involved in each of the embodiments of the present application described below can be combined with each other as long as there is no conflict.

[0052] It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases the steps shown or described may be executed in a different order than that shown here.

[0053] Please refer to Figure 1 , Figure 1 This is a topology diagram of a high boost ratio DAB converter provided in an embodiment of this application. For example... Figure 1 As shown, this high boost ratio DAB converter employs a symmetrical configuration, containing six power switches (S1-S6) to achieve bidirectional energy conversion between the low-voltage battery terminal and the high-voltage DC bus terminal. Specifically, the primary-side full-bridge circuit composed of power switches S1, S2, S3, and S4 is connected to the battery via an input capacitor (Cin), while the secondary-side hybrid network composed of power switches S5, S6, and capacitors C1 and C2 achieves voltage multiplication through capacitor switching operation. The drain-source voltages of power switches S1, S2, S3, S4, S5, and S6 are represented as Vds1, Vds2, Vds3, Vds4, Vds5, and Vds6, respectively. A high-frequency voltage converter with a turns ratio of 1:n is used to achieve electrical isolation and voltage conversion, wherein the magnetizing inductor ( The primary magnetic core excitation dynamics, secondary leakage inductance ( This DAB converter exhibits dominant power transfer characteristics. Compared to a symmetrical DAB converter with a full-bridge secondary side, its boost ratio is doubled. Figure 1 In this context, the reference directions of voltage and current indicate that power is transmitted from the current meter to the bus side, meaning the power transmission direction is positive.

[0054] Based on the topology of the DAB converter, its current equivalent circuit consists of nVp, A first-order linear circuit is formed by connecting Vp and Vs in series, where nVp is the normalized primary voltage, i.e., n times the primary voltage Vp of the transformer, and Vs is the transformer output voltage. In the embodiments of this application, the DAB converter adopts dual phase-shift control, which controls the shape and relative timing of the transformer primary voltage Vp and transformer secondary voltage Vs by controlling the inner phase shift angle between the primary leading bridge arm (i.e., S1 and S2) and the primary lagging bridge arm (i.e., S3 and S4), and the outer phase shift angle between the primary leading bridge arm and the secondary bridge arm (i.e., S5 and S6), thereby regulating the power flow.

[0055] Please refer to Figure 2 , Figure 2 These are schematic diagrams illustrating the six working modes provided in the embodiments of this application. For example... Figure 2As shown, according to the relative alignment of the high-level midpoint positions of nVp (blue three-level waveform) and Vs (red two-level waveform), the working modes of the DAB converter are divided into six modes A1, B1, C1, A2, B2 and C2. Among them, (a1) corresponds to mode A1; (b1) corresponds to mode B1; (c1) corresponds to mode C1; (a2) corresponds to mode A2; (b2) corresponds to mode B2; (c2) corresponds to mode C2. Specifically, in modes A1 and A2, the high-level pulses of nVp and Vs are completely staggered, in modes B1 and B2, the high-level pulses of nVp and Vs are partially staggered and partially overlapped, and in modes C1 and C2, the high-level pulses of nVp and Vs are completely overlapped. Further, in modes A1 / B1 / C1, the midpoint of the nVp high-level pulse leads the midpoint of the Vs high-level pulse, the voltage difference is positive, the power is transmitted in the positive direction, that is, the energy is transmitted from the low-voltage battery side to the high-voltage bus side; in modes A2 / B2 / C2, the midpoint of the nVp high-level pulse lags behind the midpoint of the Vs high-level pulse, the voltage difference is reversed, the power is transmitted in the reverse direction, that is, the energy is transmitted from the high-voltage bus side to the low-voltage battery side. The efficiency optimization method proposed in the present application switches between these modes by dynamically adjusting the midpoint offset and the high-level pulse width.

[0056] For the convenience of quantitative analysis, two intermediate variables are defined: a first phase shift parameter D1 and a second phase shift parameter D2. Among them, the first phase shift parameter D1 is the ratio of the nVp pulse width to the switching period Ts, that is, D1*Ts is equal to the duration of the nVp high-level pulse. The second phase shift parameter D2 is the ratio of the difference between the midpoint time of the Vs high-level pulse and the midpoint time of the nVp high-level pulse to the switching period, that is, D2*Ts is equal to the length of time that the nVp high-level pulse midpoint leads the Vs high-level pulse midpoint. If the nVp high-level pulse midpoint lags behind the midpoint of the Vs high-level pulse, D2*Ts takes a negative value. According to the definitions of D1 and D2, the relationship between D1 and D2 in the six modes is as shown in Table 1: Figure 2 It can be seen that the value range of D1 is 0 to 0.5, and the value range of D2 is -0.5 to 0.5. The relationship between D1 and D2 in the six modes is shown in Table 1:

[0057] Table 1

[0058]

[0059] It can be known through experiments that the output power ranges of mode A1 and A2 are the same as those of mode C1 and C2, but the current stress of mode A1 and A2 is higher. Therefore, mode A1 and A2 are generally avoided in actual control, and only switching is performed between mode B1, B2, C1 and C2. Taking mode B1 and C1 corresponding to power forward transmission as an example for analysis. Since the power transmission of the DAB converter is controlled by the outer shift phase angle of the primary and secondary voltages, when the DAB converter operates under a heavy load condition, in order to transmit more power, the high level of nVp and the high level of Vs must be staggered to increase the outer shift phase angle, that is, under the heavy load condition, the DAB converter operates in mode B1; and when the DAB converter operates under a light load condition, the transmission power is small, and the high level of nVp and the high level of Vs must be overlapped to reduce the outer shift phase angle, that is, under the light load condition, the DAB converter operates in mode C1. For the convenience of understanding, mode B1 is also called heavy load mode, and mode C1 is also called light load mode.

[0060] Please refer to Figure 3 , Figure 3 which is a typical waveform diagram of mode B1 provided by the embodiment of the present application. As shown in Figure 3 , the first three groups of waveforms are the conduction waveforms of power switches S1-S6, wherein S1, S4 and S5 correspond to red waveforms, S2, S3 and S6 correspond to blue waveforms, the fourth group of waveforms is the waveform of nVp and Vs (nVp is a blue waveform and Vs is a red waveform), the fifth group is the waveform of the instantaneous transmission current of the high-frequency transformer, and the sixth group of waveforms is the waveform of the instantaneous transmission power of the high-frequency transformer. It should be noted that Figure 3 ignores the dead time between the conduction and turn-off time of the two power switches in the same bridge arm. Based on the time marks in Figure 3 (for example, is the S1 conduction time, is the S4 conduction time, is the S5 conduction time, is the S2 conduction time, is the S3 conduction time, is the S6 conduction time, is the S1 conduction time of the next switching period), the corresponding relationship between D1, D2 and the power switch switching time under mode B1 is:

[0061] (1)

[0062] wherein, is a switching period, that is, to .

[0063] Considering the instantaneous transmission current The symmetry of the waveform in one switching cycle, the switching time of each mode B1 The calculation formula is as follows:

[0064] (2)

[0065] Wherein, is the low-voltage battery side voltage, is the high-voltage bus side voltage, is the secondary side leakage inductance, is the turn ratio of the high-frequency transformer, is the switching frequency under mode B1.

[0066] The instantaneous transmission power of the high-frequency transformer The output average power of a switching cycle under mode B1 is:

[0067] (3)

[0068] According to the value range of D1 and D2 under mode B1 described in Table 1, when D1=1 / 2 and D2=1 / 4, the output power reaches its maximum . Under heavy load conditions, the high-frequency current stress of the transformer is large, and the reflux reactive power is also large, therefore, the first optimization target corresponding to the B1 mode is to jointly optimize based on zero voltage switching (ZVS) and reflux reactive power, specifically, to minimize the reflux reactive power under the premise of ensuring that all power switches realize ZVS.

[0069] In order to realize ZVS, during the dead time before the power switch is turned on, the direction of the transformer current must be able to discharge the parasitic capacitance of the power switch (i.e. Coss1, Coss2, Coss3 and Coss4). According to the waveform of Figure 3 and formula (2), the ZVS conditions of S1 and S2 are:

[0070] that is (4)

[0071] The ZVS conditions of S3 and S4 are:

[0072] that is (5)

[0073] The ZVS conditions of S5 and S6 are:

[0074] that is (6)

[0075] Further, the minimum circulating reactive power is achieved under the ZVS condition. The circulating reactive power is the power circulating within the circuit but does not contribute to the effective power transfer, which corresponds to the shaded triangular region in the bottom right subplot of FIG. 3. While a certain amount of circulating power is necessary to achieve ZVS, excessive circulating power leads to additional conduction losses, thus reducing the overall efficiency. To suppress the circulating reactive power, the geometric area of the shaded region in FIG. 3 must be minimized. According to equations (2) and (3), the circulating reactive power Figure 3 Figure 3 Figure 3

[0076] (7)

[0077] Under heavy load conditions, the joint optimization of ZVS and circulating reactive power aims to balance the trade-off between the benefits and associated losses of ZVS. By optimizing the hardware parameter design of the DAB, the dominant constraint condition becomes the ZVS condition of the lagging arm switch under the ZVS conditions (4), (5), and (6). Specifically, satisfying inequality (5) automatically guarantees the satisfaction of inequalities (4) and (6). The first optimization objective can be transformed into minimizing equation (7) under the premise of satisfying inequality (5). Revisiting Figure 3 transitions from negative to positive values between t1 and t2. To model this behavior, a staggered duty ratio coefficient is introduced, satisfying Combining equation (1), we have:

[0078] (8)

[0079] Therefore, inequality (5) and equation (7) are transformed into the following inequality (9) and equation (10), respectively:

[0080] (9)

[0081] (10)

[0082] From this, the relationship between and the ZVS condition and circulating reactive power can be derived: when , the ZVS condition is satisfied, and , the circulating reactive power is minimized. The smaller the value of , the smaller the circulating reactive power. Based on the definition of , equation (3) can be rewritten as:​​​​​​​​

[0083] (11)

[0084] Further, a reference switching frequency is introduced, and the actual switching frequency varies with it as follows:

[0085] (12)

[0086] Therefore, formula (11) can be simplified as:

[0087] i.e. (13)

[0088] Formula (13) shows that when the variable switching frequency defined by formula (12) is applied, there is a linear relationship between the output power and D1. This simplifies the parameter tuning process of the feedback controller. Based on formula (13), the calculation formula for optimizing the minimum value of the backflow reactive power is:

[0089] (14)

[0090] Please refer to Figure 4 , Figure 4 is a typical waveform diagram of mode C1 provided by the embodiment of the application. As shown in Figure 4 , the first three groups of waveforms are the conduction waveforms of power switches S1-S6, wherein S1, S4 and S5 correspond to red waveforms, S2, S3 and S6 correspond to blue waveforms, the fourth group of waveforms is the waveform of nVp and Vs (nVp is a blue waveform and Vs is a red waveform), the fifth group is the waveform of the instantaneous transmission current of the high-frequency transformer, and the sixth group of waveforms is the waveform of the instantaneous transmission power of the high-frequency transformer. Similarly, Figure 4 , the dead time between the conduction and turn-off time of the two switches in the same bridge arm is also ignored. Based on the time marks in Figure 4 (e.g. is the S1 conduction time, is the S5 conduction time, is the S4 conduction time, is the S2 conduction time, is the S6 conduction time, is the S3 conduction time, is the S1 conduction time of the next switching period), the corresponding relationship between D1, D2 and the power switch switching time under mode C1 is as follows:

[0091] ​ (15)

[0092] where, is the switching period, i.e. the duration of .

[0093] The calculation formula of at each switching instant in mode C1 is as follows:

[0094] (16)

[0095] where, is the switching frequency under C1 mode.

[0096] Further, the output average power of the next switching period under mode C1 is:

[0097] (17)

[0098] According to the value range of D1 and D2 under mode C1 described in Table 1, when D1 = 1 / 4 and D2 = 1 / 8, the output power reaches its maximum value . It is worth noting that the maximum output power under mode C1 is half of that under mode B1, therefore, the DAB converter operates in mode C1 under light load conditions. Under light load conditions, the high-frequency current stress of the transformer is low, the circulating reactive power and conduction loss are at a low level. In this case, the power loss is mainly dominated by the switching loss. Therefore, the second optimization goal corresponding to mode C1 is to ensure ZVS for all power switches.

[0099] According to the waveform of Figure 4 and formula (16), the ZVS conditions for S1 and S2 are:

[0100] i.e. (18)

[0101] The ZVS conditions for S3 and S4 are:

[0102] i.e. (19)

[0103] The ZVS conditions for S5 and S6 are:

[0104] i.e. (20)

[0105] In order to simplify the derivation process of the ZVS conditions, the voltage conversion ratio and the power transmission ratio , which is defined as follows:

[0106] (21)

[0107] By optimizing the hardware parameter design of the DAB converter, the ZVS condition (18) can be naturally established. In combination with formula (19), formula (20) and formula (17), the ZVS condition can be re-expressed in the form of , and D1:

[0108] (22)

[0109] In the control, in order to simultaneously satisfy the two ZVS conditions, D1 is set to the average value of the upper and lower limit values of formula (22):

[0110] (23)

[0111] Please refer to Figure 5 , Figure 5 is a flowchart of an efficiency optimization method of a DAB converter provided by an embodiment of the present application. The method is applied to a DAB converter with the topology structure shown in Figure 1 , which adopts double-phase-shift control. The method comprises the following steps:

[0112] In step S501, an output power reference value, a battery-side voltage sampling value and a bus-side voltage sampling value are obtained.

[0113] In an embodiment, a first voltage sampling device is arranged at the battery side of the DAB converter, and a second voltage sampling device is arranged at the bus side of the DAB converter. The first voltage sampling device is used to collect a low-voltage battery-side voltage sampling value in real time to obtain the battery-side voltage sampling value, and the second voltage sampling device is used to collect a high-voltage bus-side voltage sampling value in real time to obtain the bus-side voltage sampling value.

[0114] In step S502, a staggered duty ratio coefficient for achieving a first optimization target in a heavy load mode, a first phase-shift parameter in the heavy load mode and a first phase-shift parameter for achieving a second optimization target in a light load mode are calculated according to the output power reference value, the battery-side voltage sampling value and the bus-side voltage sampling value.

[0115] The control mode of the DAB converter includes single-phase-shift control, double-phase-shift control, triple-phase-shift control and other modes. Among them, the double-phase-shift control controls the shape and relative timing of the transformer primary voltage vp and the transformer secondary voltage vs by controlling the inner phase-shift angle between the primary side leading bridge arm and the primary side lagging bridge arm, and the outer phase-shift angle between the primary side leading bridge arm and the secondary bridge arm.

[0116] For the convenience of quantitative analysis, two intermediate variables are defined: a first phase shift parameter D1 and a second phase shift parameter D2. The first phase shift parameter D1 is the ratio of the nVp pulse width to the switching period Ts, that is, D1*Ts is equal to the nVp pulse width. The second phase shift parameter D2 is the ratio of the midpoint difference between the high-level pulse of Vs and the high-level pulse of nVp to the switching period, that is, D2*Ts is equal to the time length in which the midpoint of the high-level pulse of nVp leads the midpoint of the high-level pulse of Vs.

[0117] Based on the foregoing analysis, it can be known that when the power is transmitted in the positive direction, the candidate operating modes of the DAB converter are the B1 mode (that is, the heavy load mode) and the C1 mode (that is, the light load mode). In the heavy load mode, the nVp high level and the Vs high level are partially staggered and partially overlapped, and in the light load mode, the nVp high level and the Vs high level are completely overlapped. The staggered proportion coefficient is the ratio of the starting point difference between the high-level pulse of Vs and the high-level pulse of nVp to the nVp pulse width. For example, when the staggered proportion coefficient is 0.5, the nVp high level and the Vs high level are completely overlapped. Figure 3 Therefore, there are .

[0118] In the heavy load operating condition, the high-frequency current stress of the transformer is large, and the reflux reactive power is also large. In an embodiment, the first optimization target is the joint optimization based on the ZVS and the reflux reactive power, specifically, the reflux reactive power is minimized under the premise of ensuring that all power switches achieve ZVS.

[0119] In the light load operating condition, the high-frequency current stress of the transformer is low, and the reflux reactive power and the conduction loss are both at a low level. In this case, the power loss is mainly dominated by the switching loss. In an embodiment, the second optimization target is to ensure that all power switches achieve ZVS.

[0120] Based on the foregoing analysis of Figure 3 , the output power Pout in formula (14) is replaced by the output power reference value, and the calculation formula of the staggered proportion coefficient for achieving the first optimization target in the heavy load mode is obtained:

[0121] (24)

[0122] wherein, is the staggered proportion coefficient for achieving the first optimization target in the heavy load mode, is the output power reference value, is the size of the secondary side equivalent leakage inductance, is the battery side voltage sampling value, is the bus side voltage sampling value, is the turn ratio of the high-frequency transformer, ​​​​​The reference switching frequency in the heavy load mode is a preset value.

[0123] Based on the analysis of the foregoing Figure 4 , the output power in formula (13) is replaced by the output power reference value, and a calculation formula of the first phase shift parameter for achieving the first optimization target in the heavy load mode is obtained.

[0124] (25)

[0125] Further, the output power in formula (21) is replaced by the output power reference value, and in combination with formula (23), a calculation formula of the first phase shift parameter for achieving the second optimization target in the light load mode is obtained.

[0126] (26)

[0127] wherein, the switching frequency in the light load mode is a preset value, the voltage conversion ratio is, and the power transmission ratio is.

[0128] In step S503, the second phase shift parameter and the switching frequency in the heavy load mode are calculated according to the staggered duty ratio coefficient and the first phase shift parameter in the heavy load mode, and the second phase shift parameter in the light load mode is calculated according to the first phase shift parameter in the light load mode.

[0129] Specifically, based on the foregoing formula (8), a calculation formula of the second phase shift parameter in the heavy load mode is obtained.

[0130] (27)

[0131] Based on the foregoing formula (12), a calculation formula of the switching frequency in the heavy load mode is obtained.

[0132] (28)

[0133] Based on the analysis of the foregoing Figure 4 , the output power in formula (17) is replaced by the output power reference value, and a calculation formula of the second phase shift parameter in the light load mode is obtained.

[0134] (29)

[0135] ​​​Step S504, determining the current working mode based on the staggered proportion coefficient in the heavy load mode and the preset dead zone proportion.

[0136] Specifically, the staggered proportion coefficient in the heavy load mode is multiplied by the first phase shift parameter in the heavy load mode to obtain the high level staggered proportion of Vs and nVp in the heavy load mode, i.e., high level staggered proportion = (1 - staggered proportion coefficient) * first phase shift parameter. Then, it is determined whether the high level staggered proportion is greater than twice the preset dead zone proportion. If yes, the current working mode is determined as the heavy load mode. If no, the current working mode is determined as the light load mode.

[0137] Step S505, generating the driving signal of each power switch based on the first phase shift parameter, the second phase shift parameter and the switching frequency corresponding to the current working mode.

[0138] In an embodiment, the specific implementation steps of step S505 include: first calculating the inner phase shift angle and the outer phase shift angle in the current working mode based on the first phase shift parameter and the second phase shift parameter in the current working mode, and then generating the driving signal of each power switch based on the inner phase shift angle, the outer phase shift angle and the switching frequency in the current working mode. Specifically, according to Figure 3 and Figure 4 , the calculation formula of the inner phase shift angle and the outer phase shift angle in the current working mode is:

[0139] (28)

[0140] wherein, is the inner phase shift angle, is the outer phase shift angle, , are the first phase shift parameter and the second phase shift parameter in the current working mode, respectively.

[0141] In an embodiment, after step S502 and before step S503, it further includes: obtaining the bus side current sampling value, calculating the current error value according to the output power reference value, the bus side voltage sampling value and the bus side current sampling value; obtaining the correction value of the first phase shift parameter based on the current error value using a proportional integral controller; and correcting the first phase shift parameter in the heavy load mode and the light load mode based on the correction value, respectively. Specifically, first, the bus side current sampling value is obtained, the current reference value is calculated according to the output power reference value and the bus side voltage sampling value, and the current error value can be calculated based on the current reference value and the bus side current sampling value; then, the correction value of the first phase shift parameter is obtained based on the current error value using a proportional integral controller; finally, the first phase shift parameter in the heavy load mode and the light load mode calculated in step S502 is added with the correction value to obtain the corrected first phase shift parameter in the heavy load mode and the light load mode, respectively.

[0142] In the practical application of the control strategy, it is essential to maintain system stability and optimize performance under different load conditions. To prevent instability caused by switching between different feedback control loops, a unified feedback control strategy is proposed. The strategy dynamically adjusts parameters based on real-time measurements of the output power reference value , battery-side voltage sampling value , bus-side voltage sampling value , and bus-side current sampling value , ensuring optimal performance in all operating modes without changing the structure of the basic control loop.

[0143] Please refer to Figure 6 , Figure 6 for the DAB converter optimization control strategy diagram provided by the embodiments of the present application. As shown in Figure 6 , the optimization control strategy includes the following steps: Step 1, calculate the staggered ratio coefficient in heavy load mode according to the output power reference value , battery-side voltage sampling value , bus-side voltage sampling value , and formula (24); calculate the feedforward control output in heavy load mode (i.e., the feedforward output of the first phase shift parameter in heavy load mode) according to the output power reference value , battery-side voltage sampling value , bus-side voltage sampling value , and formula (25); calculate the feedforward control output in light load mode (i.e., the feedforward output of the first phase shift parameter in light load mode) according to the output power reference value , battery-side voltage sampling value , bus-side voltage sampling value . Step 2, calculate the bus current error according to the output power reference value , high-voltage bus-side voltage sampling value , bus current sampling value , and get the feedback output through the PI controller (i.e., the correction value of the first phase shift parameter). Step 3, add the feedforward control output in heavy load mode and the feedback output to get the compensated first phase shift parameter in heavy load mode; add the feedforward control output in light load mode and the feedback output to get the compensated first phase shift parameter in light load mode. Step 4, according to the compensated first phase shift parameter , the second phase-shift parameter in the heavy load mode is calculated according to formula (27) and formula (28) , the switching frequency ; the second phase-shift parameter in the light load mode is calculated according to the compensated first phase-shift parameter and formula (29) . Step 5, it is judged whether the following condition is met: if yes, the drive signals of the power switches are generated based on the first phase-shift parameter , the second phase-shift parameter and the switching frequency in the heavy load mode; if no, the drive signals of the power switches are generated based on the first phase-shift parameter , the second phase-shift parameter and the switching frequency in the light load mode. Wherein, the preset dead zone ratio is a preset value.

[0144] Please refer to Figure 7 , Figure 7 is a typical waveform diagram of the efficiency optimization method provided by the embodiment of the application under various working conditions. As shown in Figure 7 , (a1), (a2) and (a3) respectively show the waveforms of the low-voltage battery-side voltage sampling value = 20V, the output power reference value = 100W, 300W and 500W; (b1), (b2) and (b3) respectively show the waveforms of the low-voltage battery-side voltage sampling value = 25V, the output power reference value = 100W, 300W and 500W. As can be seen from Figure 7 , the waveforms under various working conditions all show stable running states, and the ripples of voltage and current are extremely small at a low power level. With the increase of the output power reference value, the ripples slightly rise, indicating that the system can maintain stability even under high load conditions.

[0145] Wherein, in the light load mode (mode C1), the constant frequency 50 kHz is maintained; in the heavy load mode (mode B1), the reference switching frequency is set to 600 kHz. According to formula (12), when k = 0.2, the effective switching frequency range is 300 kHz to 400 kHz.

[0146] In the simulation experiment, the DAB runs in the light load mode (corresponding to = 100W and 300W Figure 7 ​​In (a1), (a2), (b1), and (b2), a constant frequency of 50 kHz is maintained, and the return reactive power is relatively high to ensure that all switches achieve complete ZVS. The DAB operates at the output power reference value. When the power is 500W, it runs in heavy load mode (corresponding to) Figure 7 In equations (a3) ​​and (b3), the reference switching frequency is set to 600 kHz. According to equation (12), when k=0.2, the effective switching frequency range is 300 kHz to 400 kHz. By jointly optimizing ZVS and return reactive power, the return reactive power in heavy load mode is controlled within a low range, significantly improving the efficiency of DAB.

[0147] Please refer to Figure 8 , Figure 8 yes Figure 7 ZVS performance diagrams for various operating conditions. (Example) Figure 8 As shown, (a1), (a2), and (a3) ​​respectively display the sampled values ​​of the low-voltage battery side voltage. =20V, Output Power Reference Value The waveforms of the drive signals of switches S1, S4, and S5 and their drain-source voltage (Vds) are shown for 100W, 300W, and 500W respectively; (b1), (b2), and (b3) show the sampled values ​​of the low-voltage battery side voltage respectively. =25V, Output Power Reference Value The waveforms of the drive signals for switches S1, S4, and S5 and their drain-source voltage (Vds) are shown for 100W, 300W, and 500W. ZVS was achieved stably in all test scenarios, demonstrating that Vds drops to zero before the switch is turned on, effectively reducing switching losses. This performance remained stable regardless of changes in battery voltage or output power reference values.

[0148] The efficiency optimization method of the DAB converter provided by the embodiment of the application adopts double phase-shifting control, and the first phase-shifting parameter and the second phase-shifting parameter are defined in advance based on the double phase-shifting control mode. The efficiency optimization method comprises the following steps: first, the off-set proportion coefficient for achieving the first optimization target in the heavy load mode, the first phase-shifting parameter in the heavy load mode, and the first phase-shifting parameter for achieving the second optimization target in the light load mode are calculated according to the output power reference value, the battery-side voltage sampling value and the bus-side voltage sampling value; then, the second phase-shifting parameter in the heavy load mode and the switching frequency are calculated according to the off-set proportion coefficient and the first phase-shifting parameter in the heavy load mode, and the second phase-shifting parameter in the light load mode is calculated according to the first phase-shifting parameter in the light load mode; finally, the current working mode is determined based on the off-set proportion coefficient in the heavy load mode and the preset dead zone proportion, and the drive signal of each power switch is generated based on the first phase-shifting parameter, the second phase-shifting parameter and the switching frequency corresponding to the current working mode. The method provided by the application proposes a full-range efficiency optimization control strategy for the high step-up ratio DAB converter. In the heavy load mode, the system efficiency is improved by jointly optimizing the zero voltage switching and minimizing the backflow power; and in the light load mode, the zero voltage switching effect in the full range is optimized to ensure high efficiency performance. Overall, the method provided by the application not only improves the overall efficiency of the DAB converter under different load conditions, but also ensures the economy and practicability of the system.

[0149] According to the embodiment of the application, an electronic device is provided, such as Figure 9 The electronic device 100 can include a processor 10, a communication interface 30, a memory 20 and a communication bus, wherein the processor 10, the communication interface 30 and the memory 20 complete communication with each other through the communication bus. The processor 10 can invoke the logical instructions in the memory 20 to execute the efficiency optimization method of the DAB converter described above.

[0150] In addition, the logical instructions in the memory 20 described above can be implemented in the form of a software function unit and sold or used as an independent product, and can be stored in several computer readable storage media. Based on such understanding, the technical solutions of the application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the efficiency optimization method of the DAB converter. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0151] According to the embodiments of the present application, a computer readable storage medium is provided, which is of the type described above, and stores a computer program, when the computer program is executed by a processor, the processor executes the steps of the efficiency optimization method of the DAB converter described above.

[0152] Through the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be implemented by means of software plus a general hardware platform, and of course, can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part that contributes to the related art, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions to cause a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0153] The above is merely specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application. Therefore, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for efficiency optimization of a DAB converter, characterized by, The DAB converter adopts double phase-shift control, and first phase-shift parameters and second phase-shift parameters are defined based on the double phase-shift control mode, the first phase-shift parameters are ratios of nVp pulse widths to switching periods, and the second phase-shift parameters are ratios of midpoint difference values of high-level pulses of Vs and nVp to the switching periods, the nVp is a primary side normalized voltage, and the Vs is a transformer output voltage, and the method comprises the following steps: Step A: obtaining an output power reference value, a battery side voltage sampling value and a bus side voltage sampling value; Step B: calculating, according to the output power reference value, the battery side voltage sampling value and the bus side voltage sampling value, an offset ratio coefficient for achieving a first optimization target in a heavy load mode and the first phase-shift parameters in the heavy load mode, and the first phase-shift parameters in a light load mode for achieving a second optimization target, the offset ratio coefficient being a ratio of a high-level pulse starting point difference value of Vs and nVp to an nVp pulse width; Step C: determining, according to the offset ratio coefficient and the first phase-shift parameters in the heavy load mode, the second phase-shift parameters and a switching frequency in the heavy load mode, and determining, according to the first phase-shift parameters in the light load mode, the second phase-shift parameters in the light load mode; Step D: determining a current working mode based on the offset ratio coefficient in the heavy load mode and a preset dead zone ratio; Step E: generating a driving signal of each power switch based on the first phase-shift parameters, the second phase-shift parameters and the switching frequency corresponding to the current working mode, wherein the switching frequency of the DAB converter in the light load mode is a preset value.

2. The method of claim 1, wherein, The nVp high level and the Vs high level are partially offset and partially overlapped when the DAB converter is in the heavy load mode, and the nVp high level and the Vs high level are completely overlapped when the DAB converter is in the light load mode.

3. The method of claim 1, wherein, The first optimization target is to minimize the backflow reactive power under the premise of ensuring that all power switches achieve zero voltage switching, and the second optimization target is to ensure that all power switches achieve zero voltage switching.

4. The method of claim 1, wherein, The first phase-shift parameter calculation formula for achieving the first optimization target in the heavy load mode is: The first phase-shift parameter calculation formula for achieving the second optimization target in the light load mode is: wherein, is the first phase shift parameter in heavy load mode, is the first phase shift parameter in light load mode, is the output power reference value, is the battery side voltage sampling value, is the voltage conversion ratio, is the power transfer ratio, is the bus side voltage sampling value, is the turns ratio of the high frequency transformer, is the reference switching frequency in heavy load mode, is the secondary side leakage inductance size, is the switching frequency in light load mode.

5. The method of claim 4, wherein, The offset ratio coefficient calculation formula for achieving the first optimization target in the heavy load mode is: wherein, is the offset ratio coefficient for achieving the first optimization target in the heavy load mode.

6. The method of claim 5, wherein, The determination of the current working mode based on the offset ratio coefficient in the heavy load mode and the preset dead zone ratio comprises the following steps: Multiplying the offset ratio coefficient in the heavy load mode and the first phase-shift parameters in the heavy load mode to obtain a high-level offset ratio of Vs and nVp in the heavy load mode; Determining whether the high-level offset ratio is greater than twice the preset dead zone ratio, if yes, determining that the current working mode is the heavy load mode, and if no, determining that the current working mode is the light load mode.

7. The method of claim 5, wherein, The second phase-shift parameter calculation formula in the heavy load mode is: The switching frequency calculation formula in the heavy load mode is: The second phase-shift parameter calculation formula in the light load mode is: wherein is the second phase shift parameter in heavy load mode, is the second phase shift parameter in light load mode.

8. The method according to any one of claims 1 to 7, characterized in that, The step B is followed by the step C, and the step C is followed by the step D. Obtaining a bus-side current sampling value, and calculating a current error value according to the output power reference value, the bus-side voltage sampling value and the bus-side current sampling value; Obtaining a bus-side current sampling value, and calculating a current error value according to the output power reference value, the bus-side voltage sampling value and the bus-side current sampling value; Obtaining a bus-side current sampling value, and calculating a current error value according to the output power reference value, the bus-side voltage sampling value and the bus-side current sampling value; 9. An electronic device, comprising: The computer storage medium stores instructions or programs, when the instructions or programs are executed by at least one processor, the at least one processor executes the method as any one of claims 1 to 8.

10. A computer storage medium, characterized in that The computer storage medium stores instructions or programs, when the instructions or programs are executed by at least one processor, the at least one processor executes the method as any one of claims 1 to 8.

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