Push-pull inverter and electronic device
By adding a third and fourth switching transistor in the push-pull inverter, a low-impedance freewheeling path is provided for the center-tapped transformer current, solving the problems of high switching losses and switching transistor breakdown risk in traditional push-pull inverters in low-voltage, high-current applications, and achieving soft switching and efficiency improvement of the switching transistor.
Patent Information
- Application Number
- CN202510978470.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-15
- Publication Date
- 2025-11-11
AI Technical Summary
Traditional push-pull inverters suffer from high switching losses and the risk of switching transistor breakdown in low-voltage, high-current applications. This is mainly because the transformer current lacks a low-impedance freewheeling path after the switching transistor is turned off, resulting in leakage inductance energy that cannot be discharged, leading to high-frequency oscillations and voltage spikes.
In push-pull inverters, a third and a fourth switching transistor are added to provide a low-impedance freewheeling path for the center-tapped transformer current. Soft switching is achieved by controlling the drive signal of the switching transistors, thereby reducing high-frequency oscillations and voltage spikes.
By providing a low-impedance freewheeling path, switching losses are reduced, the risk of transistor breakdown is decreased, soft switching of the transistor is achieved, and the efficiency and reliability of the inverter are improved.
Smart Images
Figure CN120934366A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of AC-DC conversion technology, specifically to a push-pull inverter and electronic equipment. Background Technology
[0002] In existing technologies, common micro-inverter solutions all adopt a full-bridge structure. In a full-bridge structure, the current must flow through two switching transistors, resulting in significant conduction losses. This disadvantage is particularly pronounced in low-voltage, high-current micro-inverter applications. In a push-pull structure, although the current flows through only one switching transistor, and the conduction loss is half that of the full-bridge structure, the traditional push-pull structure cannot achieve soft switching of the switching transistors, resulting in significant switching losses. Furthermore, the traditional push-pull structure only includes two switching transistors, achieving voltage reduction by directly adjusting the duty cycles of the two transistors. However, this results in a state where both transistors are off. When the transistors are off, the transformer current lacks a low-impedance freewheeling path, and the energy from the leakage inductance cannot be released. This leads to high-frequency oscillations and voltage spikes at the parasitic capacitance of the switching transistors, which greatly increases switching losses and the risk of transistor breakdown. Summary of the Invention
[0003] To address the aforementioned problems, this application proposes a push-pull inverter and electronic equipment, which aims to solve these problems.
[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is: to provide a push-pull inverter, which includes an inverter circuit, a center-tapped transformer, and a rectifier circuit. The inverter circuit is coupled to the primary side of the center-tapped transformer and is used to convert the input DC power into AC power. The rectifier circuit is coupled to the secondary side of the center-tapped transformer and is used to realize AC power grid connection. The inverter circuit includes a first switch, a second switch, a third switch, and a fourth switch connected in series. The first path terminal of the first switch and the first path terminal of the second switch are used to connect to the DC power supply. The second path terminal of the first switch is connected to the first path terminal of the third switch and the first end of the primary side of the center-tapped transformer. The second path terminal of the second switch is connected to the first path terminal of the fourth switch and the second end of the primary side of the center-tapped transformer. The second path terminal of the third switch and the second path terminal of the fourth switch are connected. The second path terminals of the third switch and the fourth switch are both source or drain terminals.
[0005] The first and second terminals of the first and second switching transistors are the source terminals, and the second and second terminals of the first and second switching transistors are the drain terminals. The inverter circuit also includes a DC power supply, the negative terminal of which is connected to the source terminals of the first and second switching transistors, and the positive terminal of which is connected to the center tap of the primary side of the center-tapped transformer.
[0006] The drive signals of the first and fourth switching transistors are complementary, as are the drive signals of the second and third switching transistors; and the center lines of the drive signals of the first and third switching transistors are aligned, as are the center lines of the drive signals of the second and fourth switching transistors.
[0007] The first switch, the second switch, the third switch, and the fourth switch include N-type metal-oxide-semiconductor field-effect transistors, gallium nitride switch transistors, or insulated-gate bipolar transistors with anti-parallel diodes.
[0008] The third and fourth switching transistors are configured as bidirectional gallium nitride switching transistors.
[0009] The rectifier circuit includes a first inductor, a fifth, sixth, seventh, and eighth switching transistors, a first capacitor, a second capacitor, an output capacitor, and a filter circuit. The source of the fifth switching transistor is connected to the source of the sixth switching transistor, the drain of the sixth switching transistor is connected to the drain of the seventh switching transistor, and the source of the seventh switching transistor is connected to the source of the eighth switching transistor. The drain of the fifth switching transistor is connected to the first terminal of the first capacitor and the first terminal of the output capacitor, respectively. The drain of the eighth switching transistor is connected to the first terminal of the second capacitor and the second terminal of the output capacitor, respectively. The second terminal of the first capacitor is connected to the second terminal of the second capacitor. The first terminal of the first inductor is connected to the first terminal of the secondary side of the center-tapped transformer, and the second terminal of the first inductor is connected to the junction of the drains of the sixth and seventh switching transistors. The second terminal of the secondary side of the center-tapped transformer is connected to the junction of the second terminals of the first and second capacitors. The input terminal of the filter circuit is connected in parallel across the output capacitor, and the output terminal of the filter circuit is connected to the power grid.
[0010] Specifically, when the grid voltage is positive, the sixth and eighth switches are always on, the fifth and seventh switches are switched at high frequency, and the drive signals of the fifth and seventh switches are complementary, with the drive signal of the fifth switch being phase-shifted relative to the rising edge of the drive signal of the third switch; when the grid voltage is negative, the fifth and seventh switches are always on, the sixth and eighth switches are switched at high frequency, and the drive signals of the sixth and eighth switches are complementary, with the drive signal of the eighth switch being phase-shifted relative to the rising edge of the drive signal of the third switch.
[0011] The half-cycle switching period when the grid voltage is positive includes seven sequential time periods. In the first time period, the second, fourth, and seventh switches are turned on, the current in the first inductor on the secondary side of the center-tapped transformer is negative, the current on the primary side of the center-tapped transformer flows through the center-tapped transformer and the second switch, and the current on the secondary side of the center-tapped transformer flows through the first inductor, the center-tapped transformer, and then through the seventh switch to reach the second capacitor. In the second time period, the second switch is turned off, and the current in the center-tapped transformer freewheels through the body diodes of the fourth and third switches. In the third time period, the third switch is soft-turned on, and the current in the first inductor rises. In the fourth time period, the fourth switch is turned off, and the primary current of the center-tapped transformer forces the body diode of the first switch to conduct. In the fifth time period, the first switch is soft-turned on, and the current of the first inductor continues to rise and crosses zero. In the sixth time period, the seventh switch is turned off, and the current of the first inductor forces the body diode of the fifth switch to conduct. In the seventh time period, the fifth switch is soft-turned on. In response to the fact that twice the product of the DC power supply voltage and the turns ratio of the center-tapped transformer is less than the grid voltage, the current of the first inductor decreases. In response to the fact that twice the product of the DC power supply voltage and the turns ratio of the center-tapped transformer is greater than the grid voltage, the current of the first inductor increases.
[0012] The primary-side duty cycle is defined as the time during which the first and third switches are simultaneously on, relative to the rising edge of the third switch's drive signal. The secondary-side shift ratio is defined as the phase shift time of the drive signal of the fifth or eighth switch relative to the rising edge of the drive signal of the third switch, relative to the rising edge of the drive signal of the third switch. When the secondary-side shift ratio remains constant, the primary-side duty cycle is reduced to enable the push-pull inverter to perform a step-down function. When the primary-side duty cycle remains constant, the secondary-side shift ratio is increased before the extreme point to enable the push-pull inverter to perform a step-up function.
[0013] To solve the above-mentioned technical problems, another technical solution adopted in this application is to provide an electronic device that includes any of the above-mentioned push-pull inverters.
[0014] The beneficial effects of this application are as follows: Unlike the prior art, the push-pull inverter of this application includes an inverter circuit, a center-tapped transformer, and a rectifier circuit. The inverter circuit is coupled to the primary side of the center-tapped transformer and is used to convert the input DC power into AC power. The rectifier circuit is coupled to the secondary side of the center-tapped transformer and is used to realize AC power grid connection. The inverter circuit includes a first switch, a second switch, a third switch, and a fourth switch connected in series. The first path terminal of the first switch and the first path terminal of the second switch are used to connect to the DC power supply. The second path terminal of the first switch is connected to the first path terminal of the third switch and the first end of the primary side of the center-tapped transformer. The second path terminal of the second switch is connected to the first path terminal of the fourth switch and the second end of the primary side of the center-tapped transformer. The second path terminal of the third switch is connected to the second path terminal of the fourth switch. The second path terminal of the third switch and the second path terminal of the fourth switch are both source or drain terminals. By means of the above method, the push-pull inverter of this application adds a third and a fourth switching transistor, which can provide a low-impedance freewheeling path for the center-tapped transformer current, reduce high-frequency oscillations and voltage spikes, and thus reduce switching losses. Attached Figure Description
[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the technical solutions of this application.
[0016] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the push-pull inverter provided in this application;
[0017] Figure 2 This is a schematic diagram of the circuit structure of an embodiment of the inverter circuit provided in this application;
[0018] Figure 3 This is a schematic diagram of the circuit structure of an embodiment of the inverter circuit provided in this application;
[0019] Figure 4 This is a schematic diagram of the ideal waveform of an ideal embodiment of the push-pull inverter provided in this application;
[0020] Figure 5 This is a schematic diagram of the control waveform of an embodiment of the rectifier circuit provided in this application;
[0021] Figure 6 This is a schematic diagram of the push-pull inverter provided in this application during half a switching cycle when the grid voltage is positive;
[0022] Figure 7 This is a schematic diagram of the variation curve of a per-unit power embodiment provided in this application;
[0023] Figure 8This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application. Detailed Implementation
[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0025] In existing technologies, common micro-inverter solutions all adopt a full-bridge structure. In a full-bridge structure, the current must flow through two switching transistors, resulting in significant conduction losses. This disadvantage is particularly pronounced in low-voltage, high-current micro-inverter applications. In a push-pull structure, although the current flows through only one switching transistor, and the conduction loss is half that of the full-bridge structure, the traditional push-pull structure cannot achieve soft switching of the switching transistors, resulting in significant switching losses. Furthermore, the traditional push-pull structure only includes two switching transistors, achieving voltage reduction by directly adjusting the duty cycles of the two transistors. However, this results in a state where both transistors are off. When the transistors are off, the transformer current lacks a low-impedance freewheeling path, and the energy from the leakage inductance cannot be released. This leads to high-frequency oscillations and voltage spikes at the parasitic capacitance of the switching transistors, which greatly increases switching losses and the risk of transistor breakdown.
[0026] To address the aforementioned issues, this application first proposes a push-pull inverter. Please refer to [link / reference needed]. Figure 1 , Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the push-pull inverter provided in this application. Figure 1 As shown, the push-pull inverter 100 of this embodiment includes an inverter circuit 10, a center-tapped transformer 20, and a rectifier circuit 30.
[0027] The inverter circuit 10 is coupled to the primary side of the center-tapped transformer 20 to convert the input DC power into AC power. The rectifier circuit 30 is coupled to the secondary side of the center-tapped transformer 20 to achieve AC power grid connection. The inverter circuit 10 includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4 connected in series. The first path terminal of the first switch S1 and the first path terminal of the second switch S2 are connected to the DC power supply Vin. The second path terminal of the first switch S1 is connected to the first path terminal of the third switch S3 and the first end of the primary side of the center-tapped transformer 20. The second path terminal of the second switch S2 is connected to the first path terminal of the fourth switch S4 and the second end of the primary side of the center-tapped transformer 20. The second path terminal of the third switch S3 is connected to the second path terminal of the fourth switch S4.
[0028] In this embodiment, as Figure 1 As shown, the second terminal of the third switch S3 and the second terminal of the fourth switch S4 are both sources. The first terminal of the third switch S3 and the first terminal of the fourth switch S4 are both drains.
[0029] In other embodiments, please refer to Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of an embodiment of the inverter circuit provided in this application. Figure 2 As shown, in this embodiment, the second terminal of the third switch S3 and the second terminal of the fourth switch S4 are both drains. The first terminal of the third switch S3 and the first terminal of the fourth switch S4 are both sources.
[0030] As mentioned earlier, the traditional push-pull structure achieves voltage reduction by directly adjusting the duty cycle of the two switching transistors. However, when the switching transistors are turned off, the current in the center-tapped transformer 20 lacks a low-impedance freewheeling path, and the energy of the leakage inductance cannot be discharged. This results in high-frequency oscillations and voltage spikes in the parasitic capacitance of the switching transistors, which greatly increases switching losses and the risk of transistor breakdown. In this application, a third switching transistor S3 and a fourth switching transistor S4 are added. When the first switching transistor S1 or the second switching transistor S2 is turned off, the current in the center-tapped transformer 20 can freewheel through the third switching transistor S3 and the fourth switching transistor S4 connected to it, thereby providing a low-impedance freewheeling path for the current in the center-tapped transformer 20, reducing high-frequency oscillations and voltage spikes, and further reducing switching losses.
[0031] Unlike existing technologies, the push-pull inverter 100 of this application includes an inverter circuit 10, a center-tapped transformer 20, and a rectifier circuit 30. The inverter circuit 10 is coupled to the primary side of the center-tapped transformer 20 to convert the input DC power into AC power. The rectifier circuit 30 is coupled to the secondary side of the center-tapped transformer 20 to enable AC power grid connection. The inverter circuit 10 includes a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4 connected in series. The first path terminal and the second path terminal of the first switch S1 are connected in series. The first terminal of switch S2 is connected to the DC power supply Vin. The second terminal of the first switch S1 is connected to the first terminal of the third switch S3 and the first terminal of the primary winding of the center-tapped transformer 20. The second terminal of the second switch S2 is connected to the first terminal of the fourth switch S4 and the second terminal of the primary winding of the center-tapped transformer 20. The second terminal of the third switch S3 is connected to the second terminal of the fourth switch S4. Both the second terminals of the third switch S3 and the fourth switch S4 are source or drain terminals. Through this method, the push-pull inverter 100 of this application adds a third switch S3 and a fourth switch S4, which can provide a low-impedance freewheeling path for the current in the center-tapped transformer 20, reducing high-frequency oscillations and voltage spikes, thereby reducing switching losses.
[0032] Optionally, such as Figure 1 and Figure 2 As shown, the first terminal of the first switch S1 and the first terminal of the second switch S2 are the sources, and the second terminals of the first switch S1 and the second terminal of the second switch S2 are the drains. Furthermore, in this embodiment, the inverter circuit 10 also includes a DC power supply Vin. The negative terminal of the DC power supply Vin is connected to the source of the first switch S1 and the source of the second switch S2, and the positive terminal of the DC power supply Vin is connected to the center tap O of the primary side of the center-tapped transformer 20.
[0033] In this embodiment, the transformer of the push-pull inverter 100 is generally configured as a center-tapped transformer 20. The center-tapped transformer 20 is a transformer with a special structure, having a center tap O in the middle of the primary winding. Due to the presence of the center tap O, when one part of the primary winding is energized, the other part is de-energized; when one part of the primary winding is energized, an induced current is generated in the secondary winding, thereby driving the load. When the other part of the primary winding is energized, the direction of the induced current changes, thus achieving the effect of alternately driving the load. Therefore, to achieve the purpose of alternately driving the load, the positive terminal of the DC power supply Vin needs to be connected to the center tap O of the primary winding of the center-tapped transformer 20 in the push-pull inverter 100.
[0034] Optionally, based on the above embodiments, in this embodiment, the first switch S1, the second switch S2, the third switch S3 and the fourth switch include an N-type metal-oxide-semiconductor field-effect transistor, a gallium nitride switch or an insulated-gate bipolar transistor with an anti-parallel diode.
[0035] In this embodiment, the first switch S1, the second switch S2, the third switch S3, and the fourth switch can be any one of an N-type metal-oxide-semiconductor field-effect transistor, a gallium nitride switch, or an insulated-gate bipolar transistor with an anti-parallel diode. In other embodiments, the first switch S1, the second switch S2, the third switch S3, and the fourth switch can also be N-type silicon carbide metal-oxide-semiconductor field-effect transistors.
[0036] Optionally, please refer to Figure 3 , Figure 3 This is a schematic diagram of the circuit structure of an embodiment of the inverter circuit provided in this application. In this embodiment, the third switch S3 and the fourth switch S4 are configured as bidirectional gallium nitride switches.
[0037] In this embodiment, the third switch S3 and the fourth switch S4 can be configured as bidirectional gallium nitride (GaN) switches. By configuring the third switch S3 and the fourth switch as bidirectional GaN switches in this embodiment, a monolithic integrated design can be achieved, realizing bidirectional voltage blocking and bidirectional current conduction, replacing... Figure 1 and Figure 2 The third switch S3 and the fourth switch S4 are connected "back to back" in the embodiment, which simplifies the circuit design and reduces the number of components and system cost.
[0038] Optionally, such as Figure 1As shown, the rectifier circuit 30 in this embodiment includes a first inductor Lr, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a first capacitor Co1, a second capacitor Co2, an output capacitor Co, and a filter circuit 31; wherein, the source of the fifth switch S5 is connected to the source of the sixth switch S6, the drain of the sixth switch S6 is connected to the drain of the seventh switch S7, the source of the seventh switch S7 is connected to the source of the eighth switch S8, the drain of the fifth switch S5 is connected to the first terminal of the first capacitor Co1 and the first terminal of the output capacitor Co, and the drain of the eighth switch S8 is connected to the first terminal of the first capacitor Co1 and the first terminal of the output capacitor Co. The first terminal of the first capacitor Co1 is connected to the first terminal of the second capacitor Co2 and the second terminal of the output capacitor Co, respectively. The second terminal of the first capacitor Co1 is connected to the second terminal of the second capacitor Co2. The first terminal of the first inductor Lr is connected to the first terminal of the secondary side of the center-tapped transformer 20. The second terminal of the first inductor Lr is connected to the connection between the drain of the sixth switch S6 and the drain of the seventh switch S7. The second terminal of the secondary side of the center-tapped transformer 20 is connected to the connection between the second terminal of the first capacitor Co1 and the second terminal of the second capacitor Co2. The input terminal of the filter circuit 31 is connected in parallel across the two terminals of the output capacitor Co. The output terminal of the filter circuit 31 is connected to the power grid.
[0039] In this embodiment, the filter circuit 31 includes a filter inductor Lg and a filter capacitor Cg. The first end of the output capacitor Co is connected to the first end of the filter inductor Lg, the second end of the filter inductor Lg is connected to the first end of the filter capacitor Cg, the second end of the filter capacitor Cg is connected to the second end of the output capacitor Co, and the two ends of the filter capacitor Cg are connected in parallel to the power grid.
[0040] In this embodiment, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 can also be any one of an N-type metal-oxide-semiconductor field-effect transistor, a gallium nitride switch, or an insulated-gate bipolar transistor with an anti-parallel diode.
[0041] In other embodiments, the first capacitor Co1 and the second capacitor Co2 can be replaced with resonant capacitors, so that the current waveform is close to a sine wave, further reducing losses.
[0042] Optionally, please refer to Figure 4 , Figure 4 This is a schematic diagram of an ideal waveform of an ideal embodiment of the push-pull inverter provided in this application. Figure 4 As shown, based on the above embodiments, in this embodiment, when the push-pull inverter 100 is operating ideally, the drive signals of the first switch S1 and the fourth switch S4 are complementary, and the drive signals of the second switch S2 and the third switch S3 are complementary; and the center lines of the drive signals of the first switch S1 and the third switch S3 are aligned, and the center lines of the drive signals of the second switch S2 and the fourth switch S4 are aligned.
[0043] In this embodiment, the complementary relationship between the two switches means that in a circuit, two switches with the same parameters operate in a complementary manner, that is, when one switch is on, the other switch is off, and vice versa. That is, when the first switch S1 is on, the fourth switch S4 is off, and when the first switch S1 is off, the fourth switch S4 is on; similarly, the second switch S2 and the third switch S3 are controlled in the same way.
[0044] Optionally, please refer to Figure 5 , Figure 5 This is a schematic diagram of the control waveform of an embodiment of the rectifier circuit provided in this application. Figure 4 and Figure 5 As shown, based on the above embodiment, in this embodiment, when the push-pull inverter 100 is operating ideally, when the grid voltage is positive, the sixth switch S6 and the eighth switch S8 are always on, the fifth switch S5 and the seventh switch S7 are switched at high frequency, and the drive signals of the fifth switch S5 and the seventh switch S7 are complementary, with the drive signal of the fifth switch S5 phase-shifted relative to the rising edge of the drive signal of the third switch S3; when the grid voltage is negative, the fifth switch S5 and the seventh switch S7 are always on, the sixth switch S6 and the eighth switch S8 are switched at high frequency, and the drive signals of the sixth switch S6 and the eighth switch S8 are complementary, with the drive signal of the eighth switch S8 phase-shifted relative to the rising edge of the drive signal of the third switch S3.
[0045] In this embodiment, as Figure 4 and Figure 5 As shown, in this embodiment, the push-pull inverter 100 uses duty cycle control for all switches on the primary side of the center-tapped transformer 20, while all switches on the secondary side of the center-tapped transformer 20 are phase-shifted relative to the primary side. Figure 5 The value in the table represents the primary side duty cycle, which is the ratio of the time during which the first switch S1 and the third switch S3 are simultaneously turned on to the total time of the entire switching cycle. Figure 5 D in s It is expressed as the secondary side shift ratio, which is the ratio of the phase shift time of the driving signal of the fifth switch S5 or the eighth switch S8 relative to the rising edge of the driving signal of the third switch S3 to the entire switching cycle.
[0046] Optionally, please refer to Figure 1 , Figure 4 and Figure 6 , Figure 6 This is a schematic diagram of the push-pull inverter provided in this application during half a switching cycle when the grid voltage is positive. In this embodiment, the half switching cycle when the grid voltage is positive includes seven sequential time periods.
[0047] like Figure 6 As shown in (a), during the first time period (i.e. before t0), the second switch S2, the fourth switch S4, and the seventh switch S7 are turned on. The inductance current iL of the first inductor Lr on the secondary side of the center-tapped transformer 20 is negative. The current ip on the primary side of the center-tapped transformer 20 flows through the center-tapped transformer 20 and the second switch S2. The inductance current iL on the secondary side of the center-tapped transformer 20 flows through the first inductor Lr, the center-tapped transformer 20, and then through the seventh switch S7 to reach the second capacitor Co2.
[0048] like Figure 6 As shown in (b), during the second time period (i.e., t0~t1), the second switch S2 is turned off, and the current ip on the primary side of the center tap transformer 20 freewheels through the body diodes of the fourth switch S4 and the third switch S3.
[0049] like Figure 6 As shown in (c), during the third time period (i.e., t1~t2), the third switch S3 achieves soft turn-on, and the inductor current iL of the first inductor Lr rises. At this time, the slope of the change of the inductor current iL of the first inductor Lr is as shown in formula (1):
[0050]
[0051] in, V represents the slope of the transformation of the inductor current iL of the first inductor Lr. g Represented as grid voltage, L r This is represented by the inductance value of the first inductor, Lr.
[0052] like Figure 6 As shown in (d), during the fourth time period (i.e., t2 to t3), the fourth switch S4 is turned off, and the primary current ip of the center tap transformer 20 forces the body diode of the first switch S1 to turn on.
[0053] like Figure 6 As shown in (e), during the fifth time period (i.e., t3~t4), the first switch S1 is soft-turned on, and the inductor current iL of the first inductor Lr continues to rise and crosses zero. At this time, the slope of the change of the inductor current iL of the first inductor Lr is as shown in formula (2):
[0054]
[0055] in, V represents the slope of the transformation of the inductor current iL of the first inductor Lr. g Represented as grid voltage, L r V is represented by the inductance value of the first inductor Lr; inThe voltage is represented as the DC power supply Vin, and n represents the turns ratio of the center-tapped transformer 20.
[0056] As Figure 6 shown in (f) of [], in the sixth time period (i.e., t4 to t5), the seventh switch tube S7 is turned off, and the inductor current iL of the first inductor Lr forces the body diode of the fifth switch tube S5 to conduct.
[0057] As Figure 6 shown in (g) of [], in the seventh time period (i.e., t5 to t6), the fifth switch tube S5 is softly turned on. At this time, within the seventh time period, the conversion slope of the inductor current iL of the first inductor Lr is as shown in formula (3):
[0058]
[0059] Among them, represents the conversion slope of the inductor current iL of the first inductor Lr, V g represents the grid voltage, L r represents the inductance value of the first inductor Lr; V in The voltage is represented as the DC power supply Vin, and n represents the turns ratio of the center-tapped transformer 20.
[0060] When 2nV in < Vg, the inductor current iL of the first inductor Lr shows a decreasing state; when 2nV in > Vg, the inductor current iL of the first inductor Lr shows an increasing state.
[0061] That is, in this embodiment, in response to the fact that twice the product of the voltage of the DC power supply Vin and the turns ratio of the center-tapped transformer 20 is less than the grid voltage, the current of the first inductor Lr shows a decreasing state; in response to the fact that twice the product of the voltage of the DC power supply Vin and the turns ratio of the center-tapped transformer 20 is greater than the grid voltage, the current of the first inductor Lr shows an increasing state.
[0062] In this embodiment, within half of the switching period when the grid voltage is negative, the working principle and mode of the push-pull inverter 100 are similar to those described above. When the grid voltage is negative, at this time, the fifth switch tube S5 and the seventh switch tube S7 are always on, the sixth switch tube S6 and the eighth switch tube S8 are switched at a high frequency, and the drive signals of the sixth switch tube S6 and the eighth switch tube S8 are complementary. The drive signal of the eighth switch tube S8 is phase-shifted relative to the rising edge of the drive signal of the third switch tube S3, and the remaining control waveforms are the same as those Figure 4 shown.
[0063] The push-pull inverter 100 of this embodiment can create a zero level on the primary side of the center-tapped transformer 20 through the above control to achieve voltage reduction, and realize soft switching of the switching transistor, which can further reduce switching losses.
[0064] Optionally, in this embodiment, the time during which the first switch S1 and the third switch S3 are simultaneously turned on is equal to the primary-side duty cycle D during the entire switching cycle. p The phase shift time of the drive signal of the fifth switch S5 or the eighth switch S8 relative to the rising edge of the drive signal of the third switch S3 accounts for a portion of the entire switching cycle as a fraction of the secondary side shift time compared to D. s Compared to D, in the secondary side shift s While keeping it unchanged, reduce the duty cycle D of the original side. p To enable the push-pull inverter 100 to achieve the step-down function; at the primary-side duty cycle D p When kept constant, increasing the secondary side shift before the extreme point compared to D s This enables the push-pull inverter 100 to achieve a boost function.
[0065] In this embodiment, according to the primary side duty cycle D mentioned above... s Compared to secondary edge shifting, D p The relative magnitudes of the values can be used to derive the power expression for the push-pull inverter 100, as shown in formula (4):
[0066]
[0067] In this embodiment, formula (4) can also be normalized, that is, by dividing both sides of the equation (4) by P. n To obtain the per-unit power expression for the push-pull inverter 100. Where P n As shown in formula (5), the per-unit power expression of the push-pull inverter 100 is shown in formula (6):
[0068]
[0069] In formulas (4) to (6) above, P o (D p D s P represents the power of the push-pull inverter 100. o.u (D p D s D represents the per-unit power of the push-pull inverter 100. p Compared to the secondary edge shift described above, d s V represents the primary-side duty cycle as described above. g Represented as grid voltage, L r V is represented by the inductance value of the first inductor Lr;in The voltage represented by Vin is the DC power supply voltage, n represents the turns ratio of the center-tapped transformer 20, and f is the voltage of the DC power supply. s This represents the switching frequency of the push-pull inverter 100.
[0070] Please see Figure 7 , Figure 7 This is a schematic diagram of the variation curve of a per-unit power embodiment provided in this application. Figure 7 As shown, the horizontal axis of the coordinate system represents the secondary side shift compared to D. s The vertical axis represents the normalized power. Figure 7 There are 3 curves, representing the primary side duty cycle D. p When the values are 0.3, 0.4, and 0.5, the per-unit power increases with the shift of the secondary side compared to D. s The curve showing the change in the primary side duty cycle D. Comparing the three curves, we can see that the primary side duty cycle D... p The smaller the value, the smaller the per-unit power. If a resistor is connected to the output, the smaller the power, the lower the voltage across the resistor. Therefore, the push-pull inverter 100 of this application has a step-down capability. Similarly, comparing the same curve, before the extreme point, when the secondary side shifts relative to D... s The larger the voltage, the higher the per-unit power. If a resistor is connected to the output, the higher the power, the higher the voltage across the resistor. Therefore, the push-pull inverter 100 of this application has a boost capability. The push-pull inverter 100 of this application with boost and step-up capabilities can be applied in the field of DC to AC conversion to adapt to a wide voltage range with sinusoidal output voltage.
[0071] Optionally, this application further proposes an electrical appliance; please refer to [link to relevant documentation]. Figure 8 , Figure 8 This is a schematic diagram of the structure of an embodiment of the electronic device provided in this application. Figure 8 As shown, the electronic device 200 of this embodiment includes the push-pull inverter 100 of any of the above embodiments.
[0072] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A push-pull inverter, characterized in that, It includes an inverter circuit, a center-tapped transformer, and a rectifier circuit. The inverter circuit is coupled to the primary side of the center-tapped transformer to convert the input DC power into AC power. The rectifier circuit is coupled to the secondary side of the center-tapped transformer to enable the AC power to be connected to the grid. The inverter circuit includes a first switch, a second switch, a third switch, and a fourth switch connected in series. The first path terminal of the first switch and the first path terminal of the second switch are used to connect to a DC power supply. The second path terminal of the first switch is connected to the first path terminal of the third switch and the first end of the primary winding of the center-tapped transformer. The second path terminal of the second switch is connected to the first path terminal of the fourth switch and the second end of the primary winding of the center-tapped transformer. The second path terminal of the third switch is connected to the second path terminal of the fourth switch. The second path terminals of the third switch and the fourth switch are both source or drain terminals.
2. The push-pull inverter according to claim 1, characterized in that, The first path terminal of the first switch and the first path terminal of the second switch are the source terminals, and the second path terminal of the first switch and the second path terminal of the second switch are the drain terminals; the inverter circuit also includes a DC power supply, the negative terminal of the DC power supply is connected to the source terminals of the first switch and the second switch, and the positive terminal of the DC power supply is connected to the center tap of the primary side of the center tap transformer.
3. The push-pull inverter according to claim 2, characterized in that, The drive signals of the first and fourth switches are complementary, and the drive signals of the second and third switches are complementary; and the center lines of the drive signals of the first and third switches are aligned, and the center lines of the drive signals of the second and fourth switches are aligned.
4. The push-pull inverter according to claim 1, characterized in that, The first switch, the second switch, the third switch, and the fourth switch include N-type metal-oxide-semiconductor field-effect transistors, gallium nitride switch transistors, or insulated-gate bipolar transistors with anti-parallel diodes.
5. The push-pull inverter according to claim 1, characterized in that, The third and fourth switching transistors are configured as bidirectional gallium nitride switching transistors.
6. The push-pull inverter according to claim 1, characterized in that, The rectifier circuit includes a first inductor, a fifth switching transistor, a sixth switching transistor, a seventh switching transistor, an eighth switching transistor, a first capacitor, a second capacitor, an output capacitor, and a filter circuit. In this configuration, the source of the fifth switching transistor is connected to the source of the sixth switching transistor, the drain of the sixth switching transistor is connected to the drain of the seventh switching transistor, and the source of the seventh switching transistor is connected to the source of the eighth switching transistor. The drain of the fifth switching transistor is connected to the first terminal of the first capacitor and the first terminal of the output capacitor, respectively. The drain of the eighth switching transistor is connected to the first terminal of the second capacitor and the second terminal of the output capacitor, respectively. The second terminal of the first capacitor is connected to the second terminal of the second capacitor. The first terminal of the first inductor is connected to the first terminal of the secondary side of the center-tapped transformer, and the second terminal of the first inductor is connected to the connection point between the drains of the sixth and seventh switching transistors. The second terminal of the secondary side of the center-tapped transformer is connected to the connection point between the second terminals of the first and second capacitors. The input terminal of the filter circuit is connected in parallel across the two ends of the output capacitor, and the output terminal of the filter circuit is connected to the power grid.
7. The push-pull inverter according to claim 6, characterized in that, When the grid voltage is positive, the sixth and eighth switches are always on, the fifth and seventh switches are switched at high frequency, and the drive signals of the fifth and seventh switches are complementary. The drive signal of the fifth switch is phase-shifted relative to the rising edge of the drive signal of the third switch. When the grid voltage is negative, the fifth and seventh switches are always on, the sixth and eighth switches are switched at high frequency, and the drive signals of the sixth and eighth switches are complementary. The drive signal of the eighth switch is phase-shifted relative to the rising edge of the drive signal of the third switch.
8. The push-pull inverter according to claim 6, characterized in that, The half-switching cycle when the grid voltage is positive includes seven sequential time periods. During the first time period, the second switch, the fourth switch, and the seventh switch are turned on. The current direction of the first inductor on the secondary side of the center tap transformer is negative. The current on the primary side of the center tap transformer flows through the center tap transformer and the second switch. The current on the secondary side of the center tap transformer flows through the first inductor, the center tap transformer, and then through the seventh switch to reach the second capacitor. During the second time period, the second switch is turned off, and the current of the center tap transformer freewheels through the body diodes of the fourth switch and the third switch. During the third time period, the third switch is soft-turned on, and the current in the first inductor increases. During the fourth time period, the fourth switch is turned off, and the primary current of the center tap transformer forces the body diode of the first switch to turn on. During the fifth time period, the first switch is soft-turned on, and the current in the first inductor continues to rise and crosses zero. During the sixth time period, the seventh switch is turned off, and the current in the first inductor forces the body diode of the fifth switch to turn on. During the seventh time period, the fifth switch is soft-turned on. In response to the fact that twice the product of the DC power supply voltage and the turns ratio of the center-tapped transformer is less than the grid voltage, the current of the first inductor decreases. In response to the fact that twice the product of the DC power supply voltage and the turns ratio of the center-tapped transformer is greater than the grid voltage, the current of the first inductor increases.
9. The push-pull inverter according to claim 6, characterized in that, The time during which the first and third switches are simultaneously turned on is the primary side duty cycle of the entire switching cycle, and the phase shift time of the driving signal of the fifth or eighth switch relative to the rising edge of the driving signal of the third switch is the secondary side phase shift time of the entire switching cycle. While keeping the secondary-side shift ratio constant, the primary-side duty cycle is reduced to enable the push-pull inverter to perform a step-down function; While keeping the primary duty cycle constant, the secondary shift ratio is increased before the extreme point to enable the push-pull inverter to achieve a boost function.
10. An electronic device, characterized in that, Includes the push-pull inverter as described in any one of claims 1-9.