Anti-skew circuit and method of operation for one or more anti-skew stages

Abstract

An anti-skew circuit and method of operation for one or more anti-skew stages. The anti-skew circuit includes one or more anti-skew stages. Each of the one or more anti-skew stages is configured to adjust a transition edge of a signal and includes: a single inverter; the head end is used for coupling a first power supply voltage to the single inverter; the pin end is used for coupling a second power supply voltage to the single phase inverter; a capacitor coupled to an output of the single inverter; and a switching circuit coupled between the output of the single inverter and the capacitor.

Description

Technical Field

[0001] One embodiment disclosed herein relates to an anti-skew circuit and its operation method, and more particularly to an adaptive anti-skew circuit and its operation method. Background Technology

[0002] Various types of 3D / 2.5D integrated circuit (IC) interfaces exist. For example, Universal Chiplet Interconnect Express (UCIe) is an interface standard that can support data rates up to 32 Gb / s. Such high-speed interfaces may include anti-skew circuitry to ensure signal synchronization and alignment within the interface. Summary of the Invention

[0003] One embodiment of this disclosure provides an anti-skew circuit comprising one or more anti-skew stages. Each of the one or more anti-skew stages is used to adjust the transition edge of a signal and includes a single inverter, a header, a pin, a capacitor, and a switching circuit. The header is used to couple a first power supply voltage to the single inverter. The pin is used to couple a second power supply voltage to the single inverter. The capacitor is coupled to the output of the single inverter. The switching circuit is coupled between the output of the single inverter and the capacitor.

[0004] Another embodiment of some embodiments disclosed herein provides an anti-skew circuit comprising one or more anti-skew stages. The one or more anti-skew stages are included in the data path of at least one of a transmitter or receiver. Each of the one or more anti-skew stages includes an inverter having an input and an output, a header, a pin, a capacitor, and a switching circuit. The input is used to receive a signal, and the output is used to provide an updated version of the signal with adjusted transition edges. The header is used to selectively couple a first power supply voltage to the inverter. The pin is used to selectively couple a second power supply voltage to the inverter. The capacitor is coupled to the output of the inverter. The switching circuit is coupled between the output of the inverter and the capacitor.

[0005] Another embodiment of some embodiments disclosed herein provides a method of operation for one or more anti-skew stages, which are included in the data channel of at least one of a transmitter or receiver. The method of operation includes the following steps: receiving a signal from the input of an inverter; selectively coupling a first power supply voltage to the inverter, at least in part based on the signal; selectively coupling a second power supply voltage to the inverter, at least in part based on the signal; and providing an updated version of the signal with adjusted transition edges from the output of the inverter. Attached Figure Description

[0006] The features of one embodiment disclosed herein are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In practice, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1A These are schematic diagrams of example circuits according to some embodiments;

[0008] Figure 1B Based on some embodiments and Figure 1A A schematic diagram of the waveforms associated with the circuit;

[0009] Figure 1C Based on some embodiments and Figure 1A A schematic diagram of the waveforms associated with the circuit;

[0010] Figure 2 These are schematic diagrams of example circuits according to some embodiments;

[0011] Figure 3 These are schematic diagrams of example circuits according to some embodiments;

[0012] Figure 4 These are schematic diagrams of example circuits according to some embodiments;

[0013] Figure 5 These are schematic diagrams of example circuits according to some embodiments;

[0014] Figure 6 These are schematic diagrams of example circuits according to some embodiments;

[0015] Figure 7 This is a flowchart of an example method for operating a circuit according to some embodiments.

[0016] [Symbol Explanation]

[0017] 100: Example Circuit

[0018] 150A: Signal

[0019] 150B: Signal

[0020] 190A: First Edge

[0021] 190B: Second Edge

[0022] 190C: Third Edge

[0023] 191A: First Edge

[0024] 191B: Second Edge

[0025] 191C: Third Edge

[0026] 200: Example Circuit

[0027] 210: Inverter

[0028] 220: Head end

[0029] 230: Foot end

[0030] 240: Variable Capacitor

[0031] 250: Capacitor

[0032] 260: Switching circuit

[0033] 270: Buffer circuit

[0034] 300-1: First Circuit

[0035] 300-K: The k-th circuit

[0036] 300: Example Circuit

[0037] 400: Example Circuit

[0038] 410: Circuit

[0039] 415: Matching delay wiring

[0040] 420, I_RXDATA[63:0]: Data channel

[0041] 430: Deserializer

[0042] 500: Example Circuit

[0043] 510: Circuit

[0044] 520: Time Tree

[0045] 530: Serializer

[0046] 600: Example Circuit

[0047] 610: Inverter

[0048] 620: Head end

[0049] 625: First Current Source / First Calibration Circuit

[0050] 626: First Current Source

[0051] 627: First Switch

[0052] 628: Second Switch

[0053] 630: Foot end

[0054] 635: Second calibration circuit

[0055] 636: Second Current Source

[0056] 637: First Switch

[0057] 638: Second Switch

[0058] 640: Variable Capacitor

[0059] 700: Method

[0060] 710: Operation

[0061] 720: Operation

[0062] 730: Operation

[0063] 740: Operation

[0064] I_TXDATA[63:0]: Data channel

[0065] IN: Input

[0066] OUT: Output

[0067] I REFN Current source

[0068] I REFP Current source

[0069] uBump: Bump structure Detailed Implementation

[0070] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify one embodiment of this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of an embodiment of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0071] Additionally, spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” “top,” “bottom,” and similar terms, may be used herein for ease of description to describe the relationship between one or more elements or features illustrated in the figures and another. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0072] Generally, per-channel anti-skew circuitry is a component of IC interfaces, such as Universal Chiplet Interconnect Express (UCIe) interfaces, to ensure data path anti-skewness, for example, meeting tolerance requirements for different speeds at a maximum anti-skew step resolution of 16 mUI. Design specifications, including correction range and resolution, can vary depending on the operating data rate. To achieve a wider correction range while maintaining fine resolution, additional tuning stages can be added. For example, anti-skew stage units can be cascaded to extend the correction range for lower-speed applications. To achieve a k× tuning range, k× stages can be cascaded. However, this approach is accompanied by significant cost in terms of power and area, which is unacceptable for high-efficiency and energy-saving UCIe interface designs. For the above example of cascading k× stages, the cost is at least k times higher in terms of power and area. Furthermore, such designs that do not implement the techniques disclosed herein may not have sufficient rise / fall times, which can cause inter-symbol interference (ISI).

[0073] The techniques disclosed herein provide a circuit comprising one or more anti-skew stages. Each of the one or more anti-skew stages can be used to adjust the transition edge of a signal based on a first power supply voltage coupled to a headend and a second power supply voltage coupled to a footer. In some embodiments, each of the one or more anti-skew stages may include an inverter having an input and an output. The input can be used to receive a signal, and the output can be used to provide an updated version of the signal with adjusted transition edges based on the first power supply voltage coupled to the headend and the second power supply voltage coupled to the footer. In some embodiments, the headend may selectively couple the first power supply voltage to the inverter, and the footer may selectively couple the second power supply voltage to the inverter. In some embodiments, a capacitor may be coupled to the output of the inverter, and a switching circuit may be coupled between the output of the inverter and the capacitor. In some embodiments, the techniques disclosed herein may include additional structures for speed control drives to extend the tuning range. For example, a driver unit such as a speed control adjustable driver may be added. Process voltage temperature (PVT) calibration structures or circuitry may be additionally coupled. Additional switching units, such as transmission door switches, can be added.

[0074] The techniques disclosed herein provide adaptive anti-skew circuitry for various speed data links (e.g., various data rates: 4 / 8 / 12 / 16 / 24 / 32Gb / s) in IC interfaces (e.g., UCIe interfaces). These techniques allow anti-skew circuitry to support different data rate operation requirements while achieving improved tuning efficiency (e.g., at least twice as much) and finer resolution, along with reduced power and area (e.g., improved power, performance, and area (PPA)). Furthermore, for lower-speed operating applications, the techniques disclosed herein allow for slower rise / fall times without causing ISI problems. Additionally, problems caused by PVT variations can be prevented through the inclusion of PVT calibration structures or circuits. The techniques disclosed herein provide a novel, simple, and cost-effective solution for designing adaptive anti-skew circuitry in receivers and / or transmitters. In some embodiments, the techniques disclosed herein can be used in other applications, including but not limited to various die-to-die interfaces such as 3D IC applications, bandwidth on wafer (BoW), advanced interconnect bridge (AIB), high bandwidth memory (HBM), etc.

[0075] Figure 1AThis is a schematic diagram of an example circuit 100 according to some embodiments. In some embodiments, circuit 100 may be a circuit component or stage. For example, circuit 100 may be or include one or more anti-skew stages. Circuit 100 may include circuit components, including but not limited to inverters, headers, pins, capacitors, switching circuits, etc. Figure 1A The illustration shows a non-limiting example of circuit 100. In some embodiments, circuit 100 is compared to... Figure 1A The illustrations or descriptions shown in the text Figure 1A The description may include more, fewer, or different components.

[0076] In some embodiments, circuit 100 includes: a single inverter; a header for coupling a first power supply voltage to the single inverter; a pin for coupling a second power supply voltage to the single inverter; a capacitor coupled to the output of the single inverter; and a switching circuit coupled between the output of the single inverter and the capacitor. In some embodiments, circuit 100 may be included in the data path of at least one of a transmitter or a receiver. Circuit 100 may include an inverter having an input and an output, and the inverter may be configured such that the input receives a signal and the output provides an updated version of the signal with adjusted transition edges. Circuit 100 may include: a header for selectively coupling a first power supply voltage to the inverter; a pin for selectively coupling a second power supply voltage to the inverter; a capacitor coupled to the output of the inverter; and a switching circuit coupled between the output of the inverter and the capacitor.

[0077] Circuit 100 can be used to adjust the transition edge of the signal. Figure 1B Based on some embodiments and Figure 1A A schematic diagram of the example waveform associated with circuit 100. Figure 1C Based on some embodiments and Figure 1A A schematic diagram of the example waveforms associated with circuit 100. More specifically, Figure 1B The diagram illustrates a circuit 100 with adjusted transition edges designed for high-speed operation, capable of outputting a signal 150A. Figure 1C The diagram illustrates a circuit 100 with adjusted transition edges that can output a signal 150B for low-speed operation. (Example:) Figure 1B As illustrated, circuit 100 can adjust the transition edge of signal 150A via a tuning range ΔT. For example... Figure 1C As shown in the diagram, circuit 100 can adjust the transition edge of signal 150B through a tuning range of 4×ΔT.

[0078] Figure 2This is a schematic diagram of an example circuit 200 according to some embodiments. In some embodiments, circuit 200 may be substantially similar to or have the features of circuit 100. In some embodiments, circuit 200 includes an inverter 210, a head terminal 220, a foot terminal 230, and a variable capacitor 240. In some embodiments, variable capacitor 240 may include capacitor 250 and switching circuit 260. Figure 2 The illustration is a non-limiting example of circuit 200. In some embodiments, circuit 200 is compared to... Figure 2 The illustrations or descriptions shown in the text Figure 2 The description may include more, fewer, or different components.

[0079] In some embodiments, circuit 200 may be an anti-skew stage for adjusting the transition edge of a signal. Circuit 200 may include a single inverter, such as inverter 210. Inverter 210 may include an input IN for receiving a signal (e.g., a logic state, its voltage, etc.). Inverter 210 may include an output OUT for providing an updated version of the signal with adjusted transition edges. In some embodiments, such as Figure 2 As illustrated, inverter 210 may be coupled to head terminal 220 and pin terminal 230 such that head terminal 220 and pin terminal 230 can provide a power supply voltage. In some embodiments, inverter 210 may output an updated version of a power supply voltage signal based on at least one of head terminal 220 and pin terminal 230. In some embodiments, inverter 210 may include a semiconductor device, such as a metal-oxide-semiconductor (MOS) transistor. For example, inverter 210 may include n-type MOS (NMOS) and p-type MOS (PMOS) transistors.

[0080] Circuit 200 may include a header 220. Header 220 may be used to couple a first power supply voltage to inverter 210. In some embodiments, the first power supply voltage may be a positive voltage rail (VDD). In some embodiments, header 220 may include N PMOS transistors. In some embodiments, header 220 may selectively couple the first power supply voltage to inverter 210. For example, a first number of the coupled N NMOS transistors may be in a logic high state "H", while a second number of the coupled N PMOS transistors may be in a logic low state "L". In some instances, header 220 may selectively couple the first power supply voltage to inverter 210 at least in part based on a signal received from input IN. For example, a first number of the N PMOS transistors in header 220 may be turned on, the first number being determined based on the signal received from input IN.

[0081] Circuit 200 may include pin 230. Pin 230 may be used to couple a second power supply voltage to inverter 210. In some embodiments, the second power supply voltage may be a ground reference (GND) or a voltage level reference point in circuit 200. In some embodiments, pin 230 may include N NMOS transistors. In some embodiments, pin 230 may selectively couple the second power supply voltage to inverter 210. For example, a first number of the coupled N NMOS transistors may be in a logic high state "H", while a second number of the coupled N NMOS transistors may be in a logic low state "L". In some instances, pin 230 may selectively couple the second power supply voltage to inverter 210 at least in part based on a signal received from input IN. For example, a second number of the N NMOS transistors at pin 230 may be turned on, the second number being determined based on the signal received from input IN.

[0082] In some embodiments, the header 220 and the pin 230 may be alternately turned on. For example, N PMOS transistors of the header 220 and N NMOS transistors of the pin 230 may be alternately turned on. The inverter 210 may be used to alternately couple to a first power supply voltage from the N PMOS transistors of the header 220 and a second power supply voltage from the N NMOS transistors of the pin 230. In some embodiments, the first number of PMOS transistors to be turned on in the header 220 and the second number of NMOS transistors to be turned on in the pin 230 may be the same. For example, the same number of PMOS transistors in the header 220 and NMOS transistors in the pin 230 may be in a logic high state "H" (and / or a logic low state "L"). In some embodiments, the first number and the second number may correspond to the adjustment range of the signal transition edge. For example, when the first number and the second number are larger (or smaller), the tuning range of the signal transition edge may be larger. In some embodiments, when the first number of PMOS transistors at the head end 220 and the NMOS transistors at the pin end 230 are in a logic high state, the circuit 200 can provide an updated version of the signal with a first adjusted transition edge (e.g., Figure 1B The first edge 190A or Figure 1C The first edge 191A in the circuit). When the second number of PMOS transistors at the head end 220 and the NMOS transistors at the foot end 230 are in a logic high state, the circuit 200 can provide an updated version of the signal with a second adjustment transition edge (e.g., Figure 1B The second edge 190B or Figure 1CThe second edge 191B in the circuit). When the third number of PMOS transistors at the head end 220 and the NMOS transistors at the foot end 230 are in a logic high state, the circuit 200 can provide an updated version of the signal with a third adjustment transition edge (e.g., Figure 1C The third edge 190C or Figure 1C (The third edge 191C in the middle). In some embodiments, the head end 220 and the foot end 230 may be programmable, and / or reconfigurable to allow for a variety of adjustable transition edges. For example, by making the head end 220 and the foot end 230 programmable, the anti-skew buffer drive strength can be adjusted according to speed requirements.

[0083] Circuit 200 may include a variable capacitor 240 coupled to the output OUT of inverter 210. In some embodiments, the variable capacitor 240 may include a MOS capacitor, a passive capacitor, or a combination thereof. For example, the variable capacitor 240 may include a capacitor 250, which may be or include a MOS capacitor, a passive capacitor, or a combination thereof.

[0084] In some embodiments, the variable capacitor 240 may include a switching circuit 260. In some embodiments, the switching circuit 260 may be coupled between the output of the inverter 210 and the capacitor 250. In some embodiments, the switching circuit 260 may include a transmission gate or be used as a transmission gate. For example, when the head end 220 includes N PMOS transistors and / or the foot end 230 includes N NMOS transistors, the variable capacitor 240 may include 2 M A variable capacitor 240, and a switching circuit 260 may include 2 MA transmission gate. In some embodiments, the switching circuit 260 (and / or the transmission gate) may include a MOS transistor. For example, the switching circuit 260 may include a PMOS transistor and an NMOS transistor. This can provide improved capacitor charging / discharging efficiency, thereby allowing sufficient rise / fall times. In some embodiments, the number of transmission gates to be activated corresponds to the adjustment resolution of the signal transition edge. For example, the circuit 200 may be configured to adjust the signal transition edge with an adjustment resolution corresponding to the number of transmission gates. In some embodiments, when a transmission gate is activated, the gate is turned on and allows a signal (e.g., the output of inverter 210) to pass through. When a transmission gate is deactivated, the gate can block the signal. In some embodiments, the switching circuit 260 may be used to adjust the delay and / or skew of the output signal from inverter 210. In some embodiments, the switching circuit 260 (and / or the transmission gate) may be used to adjust the timing of the signal by selectively introducing a delay. For example, the timing of the signal through the switching circuit 260 may be adjusted by selectively enabling or disabling the gate. In some embodiments, each of the transmission gates in the switching circuit 260 can be used to introduce different amounts of delay, thereby finely tuning the timing of the signal with high precision (e.g., finer resolution).

[0085] In some embodiments, circuit 200 may be coupled to or include a capacitor connected to or included in buffer circuit 270. In some embodiments, buffer circuit 270 may provide impedance matching, signal amplification, etc., without changing the logic level of the output of inverter 210 (e.g., an updated version of the signal). For example, buffer circuit 270 may filter out noise, enhance signal stability, etc.

[0086] Figure 3 This is a schematic diagram of an example circuit 300 according to some embodiments. Circuit 300 may include first circuits 300-1, ..., k-th circuits 300-K, where k can be any integer. In some embodiments, each of the first circuits 300-1, ..., k-th circuits 300-K may be substantially similar to or have features of circuits 100, 200, etc. In some embodiments, each of the first circuits 300-1, ..., k-th circuits 300-K may be used to adjust the transition edges of a signal. Figure 3 The illustration shows a non-limiting example of circuit 300. In some embodiments, circuit 300 is compared to... Figure 3 The illustrations or descriptions shown in the text Figure 3 The description may include more, fewer, or different components.

[0087] By incorporating multiple stage units, such as first circuit 300-1, ..., k-th circuit 300-K, the design challenges in meeting the requirements for improved speed anti-skew tuning range can be relaxed. In some embodiments, the same speed adjustment can be applied to each of the first circuit 300-1, ..., k-th circuit 300-K to achieve a wider correction range during lower speed operation without causing ISI problems. For example, to avoid ISI problems at 32Gb / s, multiple stage units (e.g., first circuit 300-1, ..., k-th circuit 300-K) can be combined to obtain sufficient rise / fall times while meeting the minimum correction range (e.g., K×2) for a 32Gb / s design. M (Step-by-step) requirements.

[0088] In some embodiments, such as Figure 3 As illustrated, the first circuits 300-1, ..., k-th circuits 300-K may be included in a unit circuit, a unit stage (e.g., an anti-skew stage), etc. In some embodiments, the first circuits 300-1, ..., k-th circuits 300-K may be connected in series, in parallel, or in a combination of series and parallel and / or coupled to each other. In some embodiments, each of the first circuits 300-1, ..., k-th circuits 300-K can be used to adjust the transition edge of the signal in the corresponding circuit, stage, etc. In some embodiments, each of the first circuits 300-1, ..., k-th circuits 300-K can be used to provide different adjustments to the transition edge. For example, a first number of MOS transistors may be activated in the first circuit 300-1, and a second number of MOS transistors may be activated in the k-th circuit 300-K. Based on the coupled circuits (e.g., the first circuits 300-1, ..., k-th circuits 300-K), the output signal of the circuit can be modulated in various ways.

[0089] Figure 4 This is a schematic diagram of an example circuit 400 according to some embodiments. More specifically, circuit 400 may be a receiver circuit. In some embodiments, circuit 400 is a UCIe receiver. Circuit 400 may include various components, including but not limited to a data channel 420 (e.g., I_RXDATA[63:0]), a bump structure (e.g., uBump), an amplifier, circuit 410, matched delay wiring 415, a D flip-flop (DFF), and a deserializer 430, etc. In some embodiments, circuit 410 may be substantially similar to or have the characteristics of circuits 100, 200, 300, etc. That is, anti-skew circuitry disclosed herein (e.g., circuits 100, 200, 300, etc.) may be included in the receiver. Figure 4As illustrated, in some embodiments, one or more anti-skew stages (e.g., included in or in circuit 410) may be included in circuit 400 and operatively coupled between data channel 420 and deserializer 430. In some embodiments, circuit 410 may be used to adjust the transition edge of a signal in circuit 400. For example, circuit 410 may receive a signal as input from data channel 420 and provide deserializer 430 with an updated version of the signal having adjusted transition edges. In some embodiments, circuit 410 may provide an updated version of the signal to a matching delay line 415, which circuit 410 may insert into the data path to match the clock path delay. Figure 4 The illustration shows a non-limiting example of circuit 400. In some embodiments, circuit 400 is compared to... Figure 4 The illustrations or descriptions shown in the text Figure 4 The description may include more, fewer, or different components.

[0090] Figure 5 This is a schematic diagram of an example circuit 500 according to some embodiments. More specifically, circuit 500 may be a transmitter circuit. In some embodiments, circuit 500 is a UCIe transmitter. Circuit 500 may include various components, including but not limited to a sequencer 530, a driver, a bump structure (e.g., uBump), a data channel (e.g., I_TXDATA[63:0]), circuit 510, clock tree 520, etc. In some embodiments, clock tree 520 may include clock tree synthesis (CTS), a phase interpolator (PI) and digital clock manager (DCC), a delay-locked loop (DLL), a phase-locked loop (PLL), etc. In some embodiments, circuit 510 may be substantially similar to or have the features of circuits 100, 200, 300, etc. That is, the anti-skew circuits disclosed herein (e.g., circuit 100, circuit 200, circuit 300, etc.) may be included in the transmitter. Figure 5 As illustrated, in some embodiments, one or more anti-skew stages (e.g., included in circuit 510 or circuit 510) may be included in circuit 500 and operatively coupled between sequencer 530 and clock tree 520. In some embodiments, circuit 510 may be used to adjust the transition edges of signals in circuit 500. For example, circuit 510 may receive a signal as input from clock tree 520 and provide sequencer 530 with an updated version of the signal having adjusted transition edges. Figure 5The illustration is a non-limiting example of circuit 500. In some embodiments, circuit 500 is compared to... Figure 5 The illustrations or descriptions shown in the text Figure 5 The description may include more, fewer, or different components.

[0091] In some embodiments, the anti-skew circuitry disclosed herein (e.g., circuit 100, circuit 200, circuit 300, etc.) may be included in a corresponding data channel among a plurality of data channels operatively inserted between the transmitter and the receiver. For example, the circuitry may receive a signal from the transmitter as input and provide the receiver with an updated version of the signal having adjusted transition edges. By thus inserting the circuitry and aligning timing characteristics, compatibility between the transmitter and receiver can be improved. For example, the circuitry inserted between the transmitter and receiver may even enable effective communication between the transmitter and receiver with different timing requirements or capabilities.

[0092] Figure 6 This is a schematic diagram of an example circuit 600 according to some embodiments. Circuit 600 includes an inverter 610, a header 620, a pin 630, and a variable capacitor 640. In some embodiments, circuit 600 may be substantially similar to or have features of circuit 200, etc. For example, inverter 610, header 620, pin 630, and variable capacitor 640 may be substantially similar to or have features of inverter 210, header 220, pin 230, and variable capacitor 240, respectively. In some embodiments, circuit 600 may additionally include a first calibration circuit 625 and a second calibration circuit 635. For example, the first calibration circuit 625 may be included in or coupled to header 620. The second calibration circuit 635 may be included in or coupled to pin 630. Figure 6 The illustration shows a non-limiting example of circuit 600. In some embodiments, circuit 600 is compared to... Figure 6 The illustrations or descriptions shown in the text Figure 6 The description may include more, fewer, or different components.

[0093] In some embodiments, the head end 620 may be coupled to or include the following: a first current source 626 (e.g., I...). REFP N first switches 627, each of which is used to selectively couple a first power supply voltage (e.g., VDD) to headend 620; and N second switches 628, each of which is used to selectively couple a first current source 626 to headend 620. In some embodiments, when headend 620 includes N PMOS transistors (e.g., ... <0> ,…, <n-1>When N first switches 627 (e.g., ENB_P) are used, <0> ,…,ENB_P <n-1>Each of the N second switches 628 (e.g., EN_P) can be selectively coupled to a first supply voltage to a corresponding one of the PMOS transistors, and the N second switches 628 (e.g., EN_P) can be selectively coupled to a first supply voltage to a corresponding one of the PMOS transistors. <0> ,…,EN_P <n-1>Each of the first current source 626 can be selectively coupled to a corresponding one of the PMOS transistors.

[0094] In some embodiments, pin 630 may be coupled to or include the following: a second current source 636 (e.g., I...). REFN N first switches 637, each of which is used to selectively couple a second power supply voltage (e.g., VSS) to pin 630; and N second switches 638, each of which is used to selectively couple a second current source 636 to pin 630. In some embodiments, when pin 630 includes N NMOS transistors (e.g., ... <0> ,…, <n-1>When N first switches 637 (e.g., ENB_P) are used, <0> ,…,ENB_P <n-1>Each of the N second switches 638 can be selectively coupled to a second power supply voltage to a corresponding one of the NMOS transistors, and the N second switches 638 (e.g., EN_P) <0> ,…,EN_P <n-1>Each of the two current sources 636 can be selectively coupled to a corresponding one of the NMOS transistors.

[0095] In some embodiments, the first current source 626 can provide current source I. REFP Furthermore, the second current source 636 can provide current source I. REFN This results in a constant current bias (e.g., I). REFN / I REFP It can provide up to 600 kW of current. For example, I REFP and I REFN However, it is constant. This situation allows the drive strength to be unaffected by PVT variations.

[0096] Figure 7 This is a flowchart of an example method 700 for operating a circuit according to some embodiments. Method 700 may be performed by one or more components of circuits 100, 200, 300, 400, 500, 600, etc. In some embodiments, method 700 is performed by other entities. In some embodiments, method 700 is compared to... Figure 7 The diagram may include more, fewer, or different operations.

[0097] In short, method 700 can begin with operation 710, which receives a signal from the output of the inverter. Method 700 can continue with operation 720, which selectively couples a first power supply voltage to the inverter. Method 700 can continue with operation 730, which selectively couples a second power supply voltage to the inverter. Method 700 can continue with operation 740, which provides an updated version of the signal with adjusted transition edges from the output of the inverter.

[0098] Method 700 may be initiated by operation 710, which receives a signal at the output of an inverter. At operation 710, the inverter (e.g., inverter 210) may receive a signal via its input. In some embodiments, the inverter is part of one or more anti-skew stages included in a receiver (e.g., circuitry 400). In some embodiments, the inverter is part of one or more anti-skew stages included in a transmitter (e.g., circuitry 500).

[0099] Method 700 may continue with operation 720, selectively coupling a first supply voltage to the inverter. At operation 720, a header (e.g., header 220) may couple the first supply voltage to the inverter. Method 700 may simultaneously perform or continue with operation 730, selectively coupling a second supply voltage to the inverter. At operation 730, a pin (e.g., pin 230) may couple the second supply voltage to the inverter. In some embodiments, method 700 may include: turning on a first number of p-type metal-oxide-semiconductor (PMOS) transistors to selectively couple the first supply voltage to the inverter, and turning on a second number of n-type metal-oxide-semiconductor (NMOS) transistors to selectively couple the second supply voltage to the inverter. In some embodiments, the first number and the second number are the same. In some embodiments, method 700 may include alternately turning on PMOS transistors and NMOS transistors. In some embodiments, the first number of PMOS transistors to be turned on and the second number of NMOS transistors to be turned on are the same, and both numbers correspond to the adjustment range of the signal transition edge (e.g., Figure 1B Edges 190A, 190B, and 190C in the middle, and Figure 1C (Edges 191A, 191B and 191C in the middle).

[0100] Method 700 may continue with operation 740, which provides an updated version of the signal (e.g., signal 150A, signal 150B, etc.) with adjusted transition edges from the output of the inverter. At operation 740, in some embodiments, method 700 may include receiving a signal from a receiver's data channel (e.g., data channel 420) and providing an updated version of the signal with adjusted transition edges to a deserializer (e.g., deserializer 430). At operation 740, in some embodiments, method 700 may include receiving a signal from a transmitter's clock tree (e.g., clock tree 520) and providing an updated version of the signal with adjusted transition edges to a sequencer (e.g., sequencer 530).

[0101] In one embodiment of this disclosure, a circuit is disclosed. The circuit includes one or more anti-skew stages. Each of the one or more anti-skew stages is used to adjust a transition edge of a signal and includes: a single inverter; a header for coupling a first power supply voltage to the single inverter; a pin for coupling a second power supply voltage to the single inverter; a capacitor coupled to an output of the single inverter; and a switching circuit coupled between the output of the single inverter and the capacitor.

[0102] In some embodiments, the head end includes N p-type metal-oxide-semiconductor transistors, and the foot end includes N n-type metal-oxide-semiconductor transistors.

[0103] In some embodiments, a single inverter is used to alternately couple to a first power supply voltage from N p-type metal-oxide-semiconductor transistors and a second power supply voltage from N n-type metal-oxide-semiconductor transistors.

[0104] In some embodiments, N corresponds to the adjustment range of the signal transition edge.

[0105] In some embodiments, the switching circuit includes 2 M One transmission gate.

[0106] In some embodiments, each of one or more anti-skew stages is configured to adjust the transition edge of the signal by adjusting the resolution, the adjusted resolution corresponding to the number of these transmission gates.

[0107] In some embodiments, one or more anti-skew stages are included in the transmitter and operatively coupled between the clock tree and the sequencer.

[0108] In some embodiments, one or more anti-skew stages are included in the receiver and operatively coupled between the data channel and the deserializer.

[0109] In some embodiments, one or more anti-skew stages are included in corresponding data channels of a plurality of data channels operatively inserted between the transmitter and the receiver.

[0110] In some embodiments, the head end includes N p-type metal-oxide-semiconductor transistors, a first current source, N first switches each selectively configured to couple a first power supply voltage to a corresponding p-type metal-oxide-semiconductor transistor among the p-type metal-oxide-semiconductor transistors, and N second switches each selectively couple the first current source to a corresponding p-type metal-oxide-semiconductor transistor among the p-type metal-oxide-semiconductor transistors. The pin end includes N n-type metal-oxide-semiconductor transistors, a second current source, N third switches each selectively couple a second power supply voltage to a corresponding n-type metal-oxide-semiconductor transistor among the n-type metal-oxide-semiconductor transistors, and N fourth switches each selectively couple a second current source to a corresponding n-type metal-oxide-semiconductor transistor among the n-type metal-oxide-semiconductor transistors.

[0111] In another embodiment of this disclosure, a circuit is disclosed. The circuit includes one or more anti-skew stages included in a data channel of at least one of a transmitter or a receiver. Each of the one or more anti-skew stages includes an inverter having an input and an output. The input is used to receive a signal, and the output is used to provide an updated version of the signal having an adjusted transition edge. Each of the one or more anti-skew stages includes: a header for selectively coupling a first power supply voltage to the inverter; a pin for selectively coupling a second power supply voltage to the inverter; a capacitor coupled to the output of the inverter; and a switching circuit coupled between the output of the inverter and the capacitor.

[0112] In some embodiments, the head end includes N p-type metal-oxide-semiconductor transistors, and the foot end includes N n-type metal-oxide-semiconductor transistors, and the inverter is used to alternately couple to a first power supply voltage from the N p-type metal-oxide-semiconductor transistors and a second power supply voltage from the N n-type metal-oxide-semiconductor transistors.

[0113] In some embodiments, N corresponds to an adjustment range of the transition edge of the signal.

[0114] In some embodiments, the switching circuit includes 2 M A number of transmission gates, wherein one or more anti-skew stages are configured to provide an updated version of the signal with adjusted transition edges at an adjusted resolution corresponding to the number of transmission gates.

[0115] In some embodiments, one or more anti-skew stages are included in the transmitter and operatively coupled between the clock tree and the sequencer.

[0116] In some embodiments, one or more anti-skew stages are included in the receiver and operatively coupled between the data channel and the deserializer.

[0117] In some embodiments, one or more anti-skew stages are included in corresponding data channels of a plurality of data channels operatively inserted between the transmitter and the receiver.

[0118] In another embodiment of this disclosure, a method for operating one or more anti-skew stages is disclosed, the one or more anti-skew stages being included in a data channel of at least one of a transmitter or a receiver. The method includes: receiving a signal from an input of an inverter; selectively coupling a first power supply voltage to the inverter, at least in part based on the signal; selectively coupling a second power supply voltage to the inverter, at least in part based on the signal; and providing an updated version of the signal having an adjusted transition edge from an output of the inverter.

[0119] In some embodiments, the method of operation further includes the following steps: Turning on a first number of p-type metal-oxide-semiconductor transistors to selectively couple a first power supply voltage to the inverter, the first number being determined based on a signal. Turning on a second number of n-type metal-oxide-semiconductor transistors to selectively couple the second power supply voltage to the inverter, the second number being determined based on the signal. The first number and the second number are the same.

[0120] In some embodiments, the method of operation further includes the following steps: alternately turning on the p-type metal-oxide-semiconductor transistors and the n-type metal-oxide-semiconductor transistors.

[0121] As used herein, the terms "about" and "approximately" generally indicate a given number of values ​​that may vary based on a particular technology node associated with the target semiconductor device. Based on a particular technology node, the subject "about" may indicate a given number of values ​​that may vary within, for example, 10% to 30% of the value (e.g., +10%, ±20%, or ±30%).

[0122] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of one embodiment of this disclosure. Those skilled in the art will understand that one embodiment of this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of one embodiment of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of one embodiment of this disclosure.

Claims

1. An anti-skew circuit, characterized in that, Include: One or more anti-skew levels; Each of the one or more anti-skew stages is used to adjust a transition edge of a signal and includes: A single inverter; One end is used to couple a first power supply voltage to the single inverter; One pin is used to couple a second power supply voltage to the single inverter; A capacitor coupled to an output of the single inverter; and A switching circuit is coupled between the output of the single inverter and the capacitor.

2. The anti-skew circuit as described in claim 1, characterized in that, The head end includes N p-type metal-oxide-semiconductor transistors, and the foot end includes N n-type metal-oxide-semiconductor transistors.

3. The anti-skew circuit as described in claim 2, characterized in that, The single inverter is used to alternately couple to the first power supply voltage from the N p-type metal-oxide-semiconductor transistors and the second power supply voltage from the N n-type metal-oxide-semiconductor transistors.

4. The anti-skew circuit as described in claim 3, characterized in that, N corresponds to an adjustment range for the transition edge of the signal.

5. The anti-skew circuit as described in claim 1, characterized in that, The one or more anti-skew stages are included in a transmitter and are operatively coupled between a clock tree and a sequencer.

6. The anti-skew circuit as described in claim 1, characterized in that, The one or more anti-skew stages are included in a receiver and operatively coupled between a data channel and a deserializer.

7. The anti-skew circuit as described in claim 1, characterized in that, The one or more anti-skew stages are included in a corresponding data channel of a plurality of data channels operatively inserted between a transmitter and a receiver.

8. An anti-skew circuit, characterized in that, Include: One or more anti-skew stages are included in a data channel of at least one of a transmitter or a receiver; Each of the one or more anti-skew levels includes: An inverter having an input and an output, wherein the input is used to receive a signal and the output is used to provide an updated version of the signal having an adjusted transition edge; One end is used to selectively couple a first power supply voltage to the inverter; One pin is used to selectively couple a second power supply voltage to the inverter; A capacitor coupled to the output of the inverter; and A switching circuit is coupled between the output of the inverter and the capacitor.

9. The anti-skew circuit as described in claim 8, characterized in that, The switching circuit includes 2 M A transmission gate, wherein the one or more anti-skew stages are configured to provide the updated version of the signal with the adjusted transition edge at an adjusted resolution corresponding to a number of transmission gates.

10. An operating method for one or more anti-skew stages, characterized in that, The one or more anti-skew stages are included in a data channel of at least one of a transmitter or a receiver, and the operation method includes the following steps: A signal is received from one input of an inverter; At least in part, a first power supply voltage is selectively coupled to the inverter based on this signal; At least in part, a second power supply voltage is selectively coupled to the inverter based on this signal; and An updated version of the signal with an adjusted transition edge is provided by one output of the inverter.

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