Voltage-controlled oscillator and phase-locked loop

Abstract

The invention discloses a voltage-controlled oscillator and a phase-locked loop, and the voltage-controlled oscillator comprises an auxiliary current source unit which is coupled with a voltage-controlled oscillation structure and is suitable for providing initial starting current for the voltage-controlled oscillator; the main control current source unit is suitable for receiving the control voltage output by the pre-stage filter and outputting an adjustment control current corresponding to the control voltage; and the voltage-controlled oscillation structure is suitable for receiving the initial control current and the adjustment control current and outputting an oscillation clock signal with an oscillation frequency corresponding to the control current, and the control current is the sum of the initial control current and the adjustment control current. According to the technical scheme, the convergence speed of the voltage-controlled oscillation structure can be increased, and then the locking speed of the phase-locked loop can be increased.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a voltage-controlled oscillator and a phase-locked loop. Background Technology

[0002] With the development of modern microelectronics technology, the clock speed and performance of microprocessors and workstation systems have improved, placing increasingly higher demands on the design of system clock generation circuits. Phase-locked loops (PLLs), as a commonly used design technique, are widely applied in system-on-chips (SoCs) to construct clock generation circuits.

[0003] A phase-locked loop (PLL) typically includes a phase-frequency detector, a charge pump, a loop filter, and a voltage-controlled oscillator (VCO). It generally achieves rapid locking of the PLL by employing complex circuitry to process the control voltage (Vc) of the VCO. This is accomplished by pre-estimating the frequency range the PLL will lock onto, comparing it with the current control voltage, calculating the corresponding starting voltage for each VCO frequency, and then directly applying the appropriate voltage value. This allows the entire PLL to quickly converge within the corresponding operating frequency band.

[0004] However, the convergence speed of the oscillation clock signal output by the current voltage-controlled oscillator still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a voltage-controlled oscillator, module and related equipment to improve the convergence speed of the oscillation clock signal output by the voltage-controlled oscillator, which in turn helps to improve the locking speed of the phase-locked loop.

[0006] To address the above problems, embodiments of the present invention provide a voltage-controlled oscillator, comprising:

[0007] An auxiliary current source unit, coupled to the voltage-controlled oscillator structure, is adapted to provide the voltage-controlled oscillator with an initial start-up current;

[0008] The main control current source unit is adapted to receive the control voltage output from the pre-stage filter and output an adjustment control current corresponding to the control voltage.

[0009] A voltage-controlled oscillator structure is adapted to receive the initial control current and the adjustment control current, and output an oscillation clock signal having an oscillation frequency corresponding to the control current, wherein the control current is the sum of the initial control current and the adjustment control current.

[0010] Optionally, the auxiliary current source unit includes a first current mirror module and a first current source transistor coupled to each other:

[0011] The first current mirror module is adapted to generate a first mirror current;

[0012] The first current source transistor is adapted to provide a first mirror current to the voltage-controlled oscillator structure.

[0013] Optionally, the first current mirror module includes a first PMOS transistor, a first NMOS transistor, and a first resistor;

[0014] The gate and drain terminals of the first PMOS transistor are coupled to the first terminal of the first resistor, and the source terminal of the first PMOS transistor is used to receive an analog power supply voltage signal.

[0015] The gate terminal of the first NMOS transistor is used to receive a first enable signal, the source terminal of the first NMOS transistor is used to receive an analog ground voltage signal, and the drain terminal of the first NMOS transistor is coupled to the second terminal of the first resistor.

[0016] Optionally, the first current source transistor includes a second PMOS transistor;

[0017] The gate of the second PMOS transistor is coupled to the first current mirror module, the source of the second PMOS transistor is used to receive the analog power supply voltage signal, and the drain of the second PMOS transistor is coupled to the voltage-controlled oscillator structure.

[0018] Optionally, the first current source transistor may be one or more.

[0019] Optionally, the number of the first current source transistors is multiple;

[0020] The auxiliary current source unit further includes: a control module, adapted to acquire the starting current of the required frequency band; and based on the starting current, to generate a corresponding control signal to the plurality of first current source transistors, so that a corresponding number of the first current source transistors among the plurality of first current source transistors are turned on.

[0021] Optionally, the main control current source unit is coupled to a second current mirror module and a second current source transistor:

[0022] The second current mirror module is adapted to generate a second mirror current based on the control voltage output by the pre-stage filter;

[0023] The second current source transistor is adapted to provide the second mirror current as the adjustment control current to the voltage-controlled oscillator structure.

[0024] Optionally, the second current mirror module includes a third PMOS transistor, a second NMOS transistor, a third NMOS transistor, and a second resistor;

[0025] The gate and drain of the third PMOS transistor are coupled to the drain of the second NMOS transistor, and the source of the third PMOS transistor is used to receive an analog power supply voltage signal.

[0026] The gate terminal of the second NMOS transistor is used for the control voltage output of the pre-stage filter, and the source terminal of the second NMOS transistor is coupled to the first terminal of the second resistor.

[0027] The gate terminal of the third NMOS transistor is used to receive the second enable signal, the source terminal of the third NMOS transistor is used to receive the analog ground voltage signal, and the drain terminal of the third NMOS transistor is coupled to the second terminal of the second resistor.

[0028] Optionally, the second current source transistor includes a fourth PMOS transistor;

[0029] The gate of the fourth PMOS transistor is coupled to the second current mirror module, the source of the fourth PMOS transistor is used to receive the analog power supply voltage signal, and the drain of the fourth PMOS transistor is coupled to the voltage-controlled oscillator structure.

[0030] Optionally, the voltage-controlled oscillator structure includes an odd number of cascaded single-ended voltage-controlled oscillator structures or an even number of cascaded differential oscillator structures.

[0031] Optionally, if the count value of the clock cycle counter of the voltage-controlled oscillator structure is N*FvcoFref±1 within N clock cycles of the reference clock signal, and the phase-locked loop to which the voltage-controlled oscillator belongs enters a locked state, then the locking accuracy of the voltage-controlled oscillator is N*FrefFvco, and the locking time of the voltage-controlled oscillator is NFref; where Fref represents the reference clock frequency of the reference clock signal, and Fvco represents the locking frequency of the voltage-controlled oscillator structure.

[0032] Accordingly, embodiments of the present invention also provide a phase-locked loop, including a voltage-controlled oscillator as described in any of the preceding claims.

[0033] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0034] This invention provides a voltage-controlled oscillator (VCO), comprising: an auxiliary current source unit coupled to the VCO structure, adapted to provide an initial start-up current for the VCO; a main control current source unit adapted to receive a control voltage output from a pre-stage filter and output an adjustment control current corresponding to the control voltage; and a VCO structure adapted to receive the initial control current and the adjustment control current, and output an oscillation clock signal having an oscillation frequency corresponding to the control current, wherein the control current is the sum of the initial control current and the adjustment control current.

[0035] In the voltage-controlled oscillator of this embodiment, an auxiliary current source unit is used to provide the starting current for the voltage-controlled oscillator, so that the voltage-controlled oscillator structure can converge from the oscillation frequency corresponding to the starting current to the required locking frequency, rather than from zero to the required locking frequency. Therefore, the convergence speed of the clock signal output by the voltage-controlled oscillator structure can be accelerated, which helps to improve the locking speed of the phase-locked loop. Attached Figure Description

[0036] Figure 1 This is a schematic diagram of the frame structure of an embodiment of the voltage-controlled oscillator provided by the technical solution of the present invention;

[0037] Figure 2 This is a circuit diagram of an embodiment of the voltage-controlled oscillator provided by the technical solution of the present invention;

[0038] Figure 3 This is a schematic diagram comparing the convergence time of an existing voltage-controlled oscillator with that of the voltage-controlled oscillator provided by the present invention.

[0039] Figure 4 This is a circuit diagram of another embodiment of the voltage-controlled oscillator provided by the technical solution of the present invention. Detailed Implementation

[0040] As can be seen from the background technology, the convergence speed of the clock signal output by the current voltage-controlled oscillator structure still needs to be improved.

[0041] To address the aforementioned technical problem, embodiments of the present invention provide a voltage-controlled oscillator (VCO), comprising: an auxiliary current source unit coupled to the VCO structure, adapted to provide an initial start-up current for the VCO; a main control current source unit adapted to receive a control voltage output from a pre-stage filter and output an adjustment control current corresponding to the control voltage; and a VCO structure adapted to receive the initial control current and the adjustment control current, and output an oscillation clock signal having an oscillation frequency corresponding to the control current, wherein the control current is the sum of the initial control current and the adjustment control current.

[0042] In the voltage-controlled oscillator of this embodiment, an auxiliary current source unit is used to provide the starting current for the voltage-controlled oscillator, so that the voltage-controlled oscillator structure can converge from the oscillation frequency corresponding to the starting current to the required locking frequency, rather than from zero to the required locking frequency. Therefore, the convergence speed of the clock signal output by the voltage-controlled oscillator structure can be accelerated, which helps to improve the locking speed of the phase-locked loop.

[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figure 1 This diagram shows a schematic frame structure of an embodiment of the voltage-controlled oscillator provided by the present invention. Figure 2 A circuit diagram of an embodiment of the voltage-controlled oscillator provided by the technical solution of the present invention is shown.

[0045] Reference Figure 1 and Figure 2 A voltage-controlled oscillator includes an auxiliary current source unit 110, a main control current source unit 120, and a voltage-controlled oscillator structure 130. The auxiliary current source unit 110 and the main control current source unit 120 are respectively coupled to the voltage-controlled oscillator structure 130.

[0046] In this embodiment, the auxiliary current source unit 110 has an enable terminal, a power input terminal, and an output terminal. The enable terminal of the auxiliary current source unit 110 receives a first enable signal EN1, the power input terminal receives an analog power supply voltage signal AVDD, and the output terminal is coupled to the voltage-controlled oscillator structure 130. The auxiliary current source unit 110 provides an initial startup current to the voltage-controlled oscillator structure 130.

[0047] In this embodiment, the auxiliary current source unit 110 includes a first current mirror module 111 and a first current source transistor 112 that are coupled to each other.

[0048] In this embodiment, the first current mirror module 111 has an enable terminal, a power input terminal, and an output terminal. The enable terminal of the first current mirror module 111 serves as the enable terminal of the auxiliary current source unit 110 or is coupled to the enable terminal of the auxiliary current source unit 110, and is used to receive a first enable signal EN1. The power input terminal of the first current mirror module 111 serves as the power input terminal of the auxiliary current source unit 110 or is coupled to the power input terminal of the auxiliary current source unit 110, and is used to receive an analog power supply voltage signal AVDD. The output terminal of the first current mirror module 111 is coupled to the first current source transistor 112. The first current mirror module 111 is used to generate a first mirror current.

[0049] Specifically, the first current mirror module 111 includes a first PMOS transistor MP1, a first NMOS transistor MN1, and a first resistor R1. The gate and drain of the first PMOS transistor MP1 are coupled to a first terminal of the first resistor R1, and the source of the first PMOS transistor MP1 is used to receive the analog power supply voltage signal AVDD. The gate of the first NMOS transistor MN1 is used to receive the first enable signal EN1, and the source of the first NMOS transistor MN1 is used to receive the analog ground voltage signal AVSS. The drain of the first NMOS transistor MN1 is coupled to a second terminal of the first resistor R1. The first resistor R1 can be composed of a single resistive element, or it can be composed of resistive elements connected in series and / or in parallel; this is not limited here.

[0050] In other embodiments, the first current mirror module can also be implemented using other structures with the same function, which are not limited here.

[0051] In this embodiment, the first current source transistor 112 has a control terminal, a first conducting terminal, and a second conducting terminal. The control terminal of the first current source transistor 112 is coupled to the output terminal of the first current mirror module 111. The first conducting terminal of the first current source transistor 112 is used to receive the analog power supply voltage signal AVDD. The second conducting terminal of the first current source transistor 112 is coupled to the voltage-controlled oscillator structure 130. The first current source transistor 112 is used to provide a first mirrored current to the voltage-controlled oscillator structure 130.

[0052] Specifically, the first current source transistor 112 includes a second PMOS transistor MP2. The gate of the second PMOS transistor MP2 is coupled to the first current mirror module 111, the source of the second PMOS transistor MP2 is used to receive the analog power supply voltage signal AVDD, and the drain of the second PMOS transistor MP2 is coupled to the voltage-controlled oscillator structure 130.

[0053] Depending on actual needs, there may be one or more first current source transistors 112. Specifically, the number of first current source transistors 112 is related to the initial startup current. It can be understood that, with the first mirror current provided by the first current mirror module 111 remaining constant, the larger the initial startup current provided to the voltage-controlled oscillator structure 130, the more first current source transistors 112 there will be; the smaller the initial startup current provided to the voltage-controlled oscillator structure 130, the fewer first current source transistors 112 there will be.

[0054] In this embodiment, the main control current source unit 120 has an enable terminal, a voltage input terminal, a power input terminal, and an output terminal. The enable terminal of the main control current source unit 120 receives a second enable signal EN2; the voltage input terminal receives the control voltage VC output from the pre-stage filter; the power input terminal receives the analog power supply voltage signal AVDD; and the output terminal is coupled to the voltage-controlled oscillator structure 130. The main control current source unit 120 receives the control voltage VC output from the pre-stage filter and outputs an adjustment control current corresponding to the control voltage VC.

[0055] Specifically, the main control current source unit 120 includes a second current mirror module 121 and a second current source transistor 122. The second current mirror module 121 and the second current source transistor 122 are coupled to each other.

[0056] The second current mirror module 121 has an enable terminal, a voltage input terminal, a power input terminal, and an output terminal. The enable terminal of the second current mirror module 121 receives a second enable signal EN2; the voltage input terminal receives the control voltage VC output from the pre-stage filter; the power input terminal receives the analog power supply voltage signal AVDD; and the output terminal is coupled to the voltage-controlled oscillator structure 130. The second current mirror module 121 generates a second mirrored current based on the control voltage VC output from the pre-stage filter.

[0057] In this embodiment, the second current mirror module 121 includes a third PMOS transistor MP3, a second NMOS transistor MN2, a third NMOS transistor MN3, and a second resistor R2. The gate and drain of the third PMOS transistor MP3 are coupled to the drain of the second NMOS transistor MN2, and the source of the third PMOS transistor MP3 is used to receive the analog power supply voltage signal AVDD. The gate of the second NMOS transistor MN2 is used for the control voltage VC output by the pre-stage filter, and the source of the second NMOS transistor MN2 is coupled to the first terminal of the second resistor R2. The gate of the third NMOS transistor MN3 is used to receive the second enable signal EN2, the source of the third NMOS transistor MN3 is used to receive the analog ground voltage signal AVDD, and the drain of the third NMOS transistor MN3 is coupled to the second terminal of the second resistor R2.

[0058] In other embodiments, the second current mirror module can also be implemented using other structures with the same function. Those skilled in the art can set it according to actual needs, and no limitation is made here.

[0059] In this embodiment, the second current source transistor 122 has a control terminal, a first conducting terminal, and a second conducting terminal. The control terminal of the second current source transistor 122 is coupled to the output terminal of the second current mirror module 121. The first conducting terminal of the second current source transistor 122 is used to receive the analog power supply voltage signal AVDD, and the second conducting terminal of the second current source transistor 122 is coupled to the voltage-controlled oscillator structure 130. The second current source transistor 122 is used to provide the second mirrored current as the adjustment control current to the voltage-controlled oscillator structure 130.

[0060] In this embodiment, the second current source transistor 122 includes a fourth PMOS transistor MP4. The gate of the fourth PMOS transistor MP4 is coupled to the second current mirror module 121, the source of the fourth PMOS transistor MP4 is used to receive the analog power supply voltage signal AVDD, and the drain of the fourth PMOS transistor MP4 is coupled to the voltage-controlled oscillator structure 130.

[0061] In other embodiments, the second current source transistor can also be implemented using other structures with the same function. Those skilled in the art can select according to actual needs, and no restrictions are imposed here.

[0062] The voltage-controlled oscillator structure 130 has a control terminal, a ground terminal, an input terminal, and an output terminal. The control terminal of the voltage-controlled oscillator structure 130 is coupled to the auxiliary current source unit 110 and the main control current source unit 120. The ground terminal of the voltage-controlled oscillator structure 130 is used to receive the analog ground voltage signal AVSS. The input terminal of the voltage-controlled oscillator structure 130 is coupled to its output terminal. The voltage-controlled oscillator structure 130 receives the initial control current and the adjustment control current, and outputs an oscillation clock signal with an oscillation frequency corresponding to the control current, wherein the control current is the sum of the initial control current and the adjustment control current.

[0063] In this embodiment, the voltage-controlled oscillator structure 130 includes an odd number of cascaded single-ended voltage-controlled oscillator structures 130a.

[0064] In other embodiments, the voltage-controlled oscillator structure can also be an even number of cascaded differential oscillator structures. Those skilled in the art can set it according to actual needs, and there are no restrictions here.

[0065] The working principle of the voltage-controlled oscillator in the above embodiments will be described below.

[0066] Reference Figures 1 to 2In this embodiment, in the auxiliary current source unit 110, the first enable signal EN1 is a high-level signal, and the first NMOS transistor MN1 in the first current mirror module 111 is turned on, so that the current path containing the first PMOS transistor MP1, the first resistor R1 and the first NMOS transistor MN1 is turned on, generating a first mirror current and inputting it to the first current source transistor 112, that is, the second PMOS transistor MP2. The second PMOS transistor MP2 then provides the first mirror current generated by the first current mirror module 111 to the control terminal of the voltage-controlled oscillator structure 130.

[0067] The first mirror current generated by the auxiliary current source unit 110 is related to the voltage value of the analog power supply voltage signal AVDD, the resistance value of the first resistor R1, the voltage value of the first enable signal EN1, the gate-source voltage value of the first NMOS transistor MN1, and the gate-source voltage value of the first PMOS transistor MP1.

[0068] The current input to the voltage-controlled oscillator structure 130 from each first current source transistor 112 is the first mirror current I. mir1 When there are multiple second PMOS transistors MP2, the auxiliary current source unit 110 provides the starting current to the voltage-controlled oscillator structure 130 as (Q*I) mir1 ), where Q represents the number of second PMOS transistors MP2 in the auxiliary current source unit 110.

[0069] In the main control current source unit 120, when the second enable signal EN2 and the control voltage VC output by the pre-stage filter are at a high level, the second NMOS transistor MN2 and the third NMOS transistor MN3 in the second current mirror module 121 are both turned on, so that the current path containing the third PMOS transistor MP3, the second NMOS transistor MN2, the third NMOS transistor MN3 and the second resistor R2 is turned on, generating a second mirror current and inputting it into the second current source transistor 122, that is, the fourth PMOS transistor MP4.

[0070] The second mirror current generated by the main control current source unit 120 is related to the voltage value of the control voltage VC output by the pre-stage filter, the voltage value of the second enable signal EN2, the gate-source voltage value of the second NMOS transistor MN2, and the resistance value of the second resistor R2. Specifically, the second mirror current generated by the main control current source unit 120 can be calculated using the following formula:

[0071]

[0072] Among them, I mir2 V represents the second mirror current. MN3V represents the gate-source voltage value of the second NMOS transistor MN2. EN2 r2 represents the voltage value of the second enable signal EN2, and r2 represents the resistance value of the second resistor R2.

[0073] As described above, the control current input to the voltage-controlled oscillator structure 130 is:

[0074] I C =(N*I mir1 )+I mir2 (2)

[0075] Among them, I C This represents the control current input to the voltage-controlled oscillator structure 130.

[0076] Accordingly, the voltage-controlled oscillator structure 130 receives the control current I. C This generates an oscillation clock signal with a corresponding oscillation frequency.

[0077] Combining formulas (1) to (2), it can be seen that when the starting current output of the auxiliary current source unit 110 remains unchanged, the oscillation clock frequency of the oscillation clock signal output by the voltage-controlled oscillator structure 130 can be adjusted by adjusting the control voltage VC output by the pre-stage filter, so that the oscillation clock frequency of the oscillation clock signal output by the voltage-controlled oscillator structure 130 converges to the locked frequency.

[0078] Those skilled in the art will understand that the initial value of the oscillation frequency of the oscillation clock signal output by the voltage-controlled oscillator in this embodiment of the invention is determined by the initial start-up current output by the auxiliary current source unit 110. In other words, the oscillation clock signal output by the voltage-controlled oscillator converges towards the locked frequency from the initial oscillation frequency corresponding to the initial start-up current output by the auxiliary current source unit 110. Compared with converging from the initial oscillation frequency starting from zero towards the locked frequency, this can accelerate the convergence speed of the oscillation clock signal output by the voltage-controlled oscillator.

[0079] See Figure 3 The diagram illustrates a comparison of the convergence time of a conventional voltage-controlled oscillator (VCO) with that of the VCO in this embodiment. Figure 3 (a) It can be seen that the convergence time of the oscillation clock signal output by an existing voltage-controlled oscillator is 12 microseconds (μs), while from Figure 3 (b) It can be seen that the convergence time of the oscillation clock signal output by the voltage-controlled oscillator in this embodiment is only 8μs, which significantly improves the convergence speed of the voltage-controlled oscillator.

[0080] Furthermore, the oscillation clock signal output by the voltage-controlled oscillator converges from the starting oscillation frequency corresponding to the starting current output by the auxiliary current source unit 110 towards the lock frequency. By setting the starting current output by the auxiliary current source unit 110, the starting oscillation frequency of the oscillation clock signal output by the voltage-controlled oscillator can be set to be higher than the lock frequency, thereby enabling the oscillation clock signal of the voltage-controlled oscillator to converge from a higher starting oscillation frequency to a lower preset lock frequency; or, the starting oscillation frequency of the oscillation clock signal output by the voltage-controlled oscillator can be set to be lower than the lock frequency, thereby enabling the oscillation clock signal of the voltage-controlled oscillator to converge from a lower starting oscillation frequency to a higher preset lock frequency, realizing a bidirectional convergence process from high frequency to low frequency and from low frequency to high frequency.

[0081] Furthermore, if the locking accuracy of the phase-locked loop is ±M parts per million (ppm), the reference clock frequency of the reference clock signal is Fref, the locking frequency of the voltage-controlled oscillator is Fvco, and the oscillation clock frequency of the voltage-controlled oscillator before entering the locked state is Fvco_real, then the phase-locked loop satisfies the following condition when entering the locked state:

[0082]

[0083] but:

[0084] Fvco_real=(1±M)*Fvco (4)

[0085] If the count value of the clock cycle counter of the voltage-controlled oscillator is within N reference clock cycles of the reference clock signal... The phase-locked loop (PLL) enters the locked state under the following conditions:

[0086]

[0087] but:

[0088]

[0089] From the above formulas (5) and (7), we can obtain:

[0090]

[0091] but:

[0092]

[0093] Therefore, when the number of clock cycles N of the reference clock signal is constant, the locking accuracy of the voltage-controlled oscillator is N*FrefFvco, and the locking time is NFref.

[0094] For example, if the ratio of the lock frequency of the oscillation clock signal output by the voltage-controlled oscillator to the reference clock frequency of the reference clock signal is N*FrefFvco, which is 16 to 31, and the reference clock frequency Fref of the reference clock signal is 51.6 to 200 MHz, and the number of clock cycles N of the reference clock signal is 512, then the lock accuracy of the voltage-controlled oscillator is 122.1 ppm to 63.0 ppm, and the lock time is 9.92 μs to 2.56 μs.

[0095] Figure 4 A circuit diagram of a second embodiment of the voltage-controlled oscillator according to the present invention is shown. The similarities between this embodiment and the previous embodiments will not be repeated here. Reference Figure 4 The difference between this embodiment and the previous embodiment is that in this embodiment, there are multiple first current source transistors 112 in the auxiliary current source unit 110, and the multiple first current source transistors 112 are respectively coupled to the control module (not shown) through corresponding switches SW.

[0096] Accordingly, when the number of the first current source transistors 112 in the auxiliary current source unit 110 is P, the control unit 140 controls 1 to P of the N switches SW to turn on, thereby providing I to the voltage-controlled oscillator structure 130. mir1 To (P*I) mir1 The starting current is determined to meet the different starting current requirements of the voltage-controlled oscillator for different frequency ranges. Here, P represents the number of the first current source transistors 112 in the auxiliary current source unit 110.

[0097] Accordingly, embodiments of the present invention also provide a phase-locked loop, including the voltage-controlled oscillator provided in the embodiments of the present invention. The voltage-controlled oscillator is described in the foregoing embodiments and will not be repeated here.

[0098] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is accorded the widest scope consistent with the principles and novel features disclosed herein.

[0099] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A voltage-controlled oscillator, characterized in that, include: An auxiliary current source unit, coupled to the voltage-controlled oscillator structure, is adapted to provide the voltage-controlled oscillator with an initial start-up current; The main control current source unit is adapted to receive the control voltage output from the pre-stage filter and output an adjustment control current corresponding to the control voltage. A voltage-controlled oscillator structure is adapted to receive the initial control current and the adjustment control current, and output an oscillation clock signal having an oscillation frequency corresponding to the control current, wherein the control current is the sum of the initial control current and the adjustment control current.

2. The voltage-controlled oscillator as described in claim 1, characterized in that, The auxiliary current source unit includes a first current mirror module and a first current source transistor that are coupled to each other. The first current mirror module is adapted to generate a first mirror current; The first current source transistor is adapted to provide a first mirror current to the voltage-controlled oscillator structure.

3. The voltage-controlled oscillator as described in claim 2, characterized in that, The first current mirror module includes a first PMOS transistor, a first NMOS transistor, and a first resistor; The gate and drain terminals of the first PMOS transistor are coupled to the first terminal of the first resistor, and the source terminal of the first PMOS transistor is used to receive an analog power supply voltage signal. The gate terminal of the first NMOS transistor is used to receive a first enable signal, the source terminal of the first NMOS transistor is used to receive an analog ground voltage signal, and the drain terminal of the first NMOS transistor is coupled to the second terminal of the first resistor.

4. The voltage-controlled oscillator as described in claim 2, characterized in that, The first current source transistor includes a second PMOS transistor; The gate of the second PMOS transistor is coupled to the first current mirror module, the source of the second PMOS transistor is used to receive the analog power supply voltage signal, and the drain of the second PMOS transistor is coupled to the voltage-controlled oscillator structure.

5. The voltage-controlled oscillator as described in claim 2, characterized in that, The first current source transistor can be one or more.

6. The voltage-controlled oscillator as described in claim 2, characterized in that, The number of the first current source transistors is multiple; The auxiliary current source unit further includes: a control module, adapted to acquire the starting current of the required frequency band; and based on the starting current, to generate a corresponding control signal to the plurality of first current source transistors, so that a corresponding number of the first current source transistors among the plurality of first current source transistors are turned on.

7. The voltage-controlled oscillator as described in any one of claims 1 to 6, characterized in that, The main control current source unit is mutually coupled to the second current mirror module and the second current source transistor: The second current mirror module is adapted to generate a second mirror current based on the control voltage output by the pre-stage filter; The second current source transistor is adapted to provide the second mirror current as the adjustment control current to the voltage-controlled oscillator structure.

8. The voltage-controlled oscillator as described in claim 7, characterized in that, The second current mirror module includes a third PMOS transistor, a second NMOS transistor, a third NMOS transistor, and a second resistor; The gate and drain of the third PMOS transistor are coupled to the drain of the second NMOS transistor, and the source of the third PMOS transistor is used to receive an analog power supply voltage signal. The gate terminal of the second NMOS transistor is used for the control voltage output of the pre-stage filter, and the source terminal of the second NMOS transistor is coupled to the first terminal of the second resistor. The gate terminal of the third NMOS transistor is used to receive the second enable signal, the source terminal of the third NMOS transistor is used to receive the analog ground voltage signal, and the drain terminal of the third NMOS transistor is coupled to the second terminal of the second resistor.

9. The voltage-controlled oscillator as described in claim 7, characterized in that, The second current source transistor includes a fourth PMOS transistor; The gate of the fourth PMOS transistor is coupled to the second current mirror module, the source of the fourth PMOS transistor is used to receive an analog power supply voltage signal, and the drain of the fourth PMOS transistor is coupled to the voltage-controlled oscillator structure.

10. The voltage-controlled oscillator as described in claim 1, characterized in that, The voltage-controlled oscillator structure includes an odd number of cascaded single-ended voltage-controlled oscillator structures or an even number of cascaded differential oscillator structures.

11. The voltage-controlled oscillator as described in claim 1, characterized in that, If the count value of the clock cycle counter of the voltage-controlled oscillator structure is N*FvcoFref±1 within N clock cycles of the reference clock signal, and the phase-locked loop to which the voltage-controlled oscillator belongs enters the locked state, then the locking accuracy of the voltage-controlled oscillator is N*FrefFvco, and the locking time of the voltage-controlled oscillator is NFref; where Fref represents the reference clock frequency of the reference clock signal, and Fvco represents the locking frequency of the voltage-controlled oscillator structure.

12. A phase-locked loop, characterized in that, Includes the voltage-controlled oscillator as described in any one of claims 1 to 11.

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