Method and system for transmitting a digital signal

Abstract

The present invention relates to a digital signal transmission system and method for serializing data generated by two or more independent data sources into a single bitstream with enhanced robustness against skew, jitter, phase drift and alignment error. The system includes a first circuit, a second circuit, and a serialization module. The first circuit includes a first parallel conversion circuit and a first synchronization circuit coupled to the first parallel conversion circuit. The second circuit includes a second parallel conversion circuit, a second latch coupled to the second parallel conversion circuit, and a second synchronization circuit coupled to the second latch.

Description

Cross-references to related applications

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 645,057, filed May 9, 2024, entitled “METHOD AND SYSTEM FORTRANSMITTING DIGITAL SIGNALS,” the disclosure of which is incorporated herein by reference in its entirety. Background Technology

[0002] Serialization of data from two data sources has been performed in various applications, including data communication applications. As an example, time-division multiplexing can be used to multiplex data from two data sources to output a serialized data stream.

[0003] Despite the progress made in these serialization technologies, there is still a need in the field for improved methods and systems related to data serialization. Summary of the Invention

[0004] This invention generally relates to digital signal transmission technology, and more specifically, to methods and systems for serializing data generated from two or more independent data sources into a single bitstream, exhibiting enhanced robustness against skew, jitter, phase drift, and alignment errors. As an example only, embodiments of the invention serialize data from two different data sources (e.g., a D-PHY video data bitstream) into a single serial bitstream. The Mobile Industry Processor Interface (MIPI) standard defines three physical (PHY) layer specifications: MIPID-PHY, M-PHY, and C-PHY. The MIPID-PHY and C-PHY physical layers support camera and display applications. The "D" in D-PHY originates from the Roman numeral 500, reflecting the historical communication speed of 500 Mbps for D-PHY.

[0005] A system of one or more computers may be configured to perform specific operations or actions by means of software, firmware, hardware, or combinations thereof installed on the system, which in operation cause or enable the system to perform actions.

[0006] One general aspect includes a data processing circuit. The data processing circuit includes a first circuit and a second circuit. The first circuit includes a first parallel conversion circuit and a first synchronization circuit coupled to the first parallel conversion circuit. The first parallel conversion circuit may include a first serial-to-parallel distributor, a first clock divider having a division ratio m, and a first D-type flip-flop (D-FF). The second circuit may include a second parallel conversion circuit, a second latch coupled to the second parallel conversion circuit, and a second synchronization circuit coupled to the second latch. The second parallel conversion circuit includes a second serial-to-parallel distributor, a second clock divider having a division ratio m, and a second D-FF. The circuit may also include a serialization module coupled to the first and second synchronization circuits.

[0007] The implementation may include one or more of the following features. In the data processing circuit, the first circuit may further include a first latch coupled to a first parallel conversion circuit and a first clock divider, and a first synchronization circuit coupled to the first latch. A first serial-to-parallel distributor and a first clock distributor are coupled to a first source, and a first D-FF is coupled to the first serial-to-parallel distributor and the first clock distributor. The first serial-to-parallel distributor or a second serial-to-parallel distributor may include an n-bit shift register.

[0008] One general aspect includes a method for serializing data. The method further includes receiving first serial data (D1a) and a first clock signal (CK1) from a first source. The data also includes receiving second serial data (D2a) and a second clock signal (CK2) from a second source, parallelizing the first serial data to generate a first parallel signal (D1c), parallelizing the second serial data to generate a second parallel signal (D2c), and latching the first parallel signal using a first enable signal (ENN1) to generate a first latched signal (D1d). The method further includes latching the second parallel signal using a second enable signal (ENN2) to generate a second latched signal (D2d). The method may further include synchronizing the first latched signal and the second latched signal to generate a first synchronization signal (D1e) and a second synchronization signal (D2e). The method may further include serializing the first synchronization signal and the second synchronization signal to generate a serial bit stream.

[0009] Implementations may include one or more of the following features. Parallelizing first serial data includes: sampling the first serial data with a first clock signal and deserializing the first serial data into a first packet of n-bit signals; and synchronizing the first packet of n-bit signals to a first divided clock signal, wherein the first divided clock signal is derived from the first clock signal by a first clock divider. Parallelizing second serial data includes: sampling second serial data with a second clock signal and deserializing the second serial data into a second n-bit signal; and synchronizing the second n-bit signal to a second divided clock signal, wherein the second divided clock signal is derived from the second clock signal by a second clock divider. The first serial data may include serial data from at least two data channels, and the second serial data may include serial data from at least two data channels. Parallelization may include parallelizing the first serial data and the second serial data; latching may include latching a second parallel signal for each data channel; synchronization may include synchronizing a first parallel signal for each data channel and synchronizing a second latch signal for each data channel; and serialization may include serializing a first synchronization signal for each data channel and a second synchronization signal for each data channel to generate a serial bit stream. The serial bit stream includes a first synchronization signal, a second synchronization signal, and one or more additional signals. Attached Figure Description

[0010] This disclosure is described in conjunction with the accompanying drawings.

[0011] Figure 1 A system for serializing data generated using two independent clocks and a data source into a single bit stream, according to an embodiment of the present invention, is shown.

[0012] Figure 2A The waveform of a second frequency-divided clock signal that lags behind the first frequency-divided clock signal is shown according to an embodiment of the present invention.

[0013] Figure 2B The waveform of a second frequency-divided clock signal that leads the first frequency-divided clock signal is shown according to an embodiment of the present invention.

[0014] Figure 3 A system with a latch is shown for serializing data generated using two independent clocks and a data source into a single bit stream according to an embodiment of the present invention.

[0015] Figure 4 An alternative system according to an embodiment of the present invention is shown for serializing data generated using two independent clocks and data sources, as well as other signals, into a single bit stream.

[0016] Figure 5 It shows Figure 4 One embodiment of the system shown is in which each source has two signal channels.

[0017] Figure 6 This is a simplified flowchart illustrating a method for serializing data according to an embodiment of the present invention.

[0018] In the accompanying drawings, similar parts and / or features may have the same reference numerals. Furthermore, various parts of the same type can be distinguished by adding a dash and a second reference numeral after the reference numeral to differentiate similar parts. If only the first reference numeral is used in the specification, the description applies to any similar part having the same first reference numeral, regardless of the second reference numeral. Detailed Implementation

[0019] The following description provides only one or more preferred exemplary embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of one or more preferred exemplary embodiments will provide those skilled in the art with an advantageous description for implementing the preferred exemplary embodiments. It should be understood that various changes may be made to the function and arrangement of the elements without departing from the spirit and scope set forth in the appended claims.

[0020] In digital systems, such as digital video systems, especially those requiring high bandwidth and reliability, such as high-definition video streaming or video conferencing, data is typically transmitted across multiple channels or interconnects. However, transmitting video data across disparate channels presents challenges, particularly necessitating multi-interconnect frameworks rather than the more efficient single-interconnect system. Aggregator FPGAs can be used to decode and evaluate video data to perform aggregation, forcing two inputs to a single output video aggregator bridge. However, this solution is complex and leads to a significant increase in area, power consumption, and cost.

[0021] In environments involving serialized data transmission from two or more independent sources, conventional strategies involve individually serializing the data from each source. However, this conventional approach requires a multi-interconnect framework rather than a more efficient single-interconnect system. This requirement not only increases the space allocation within the system architecture but also significantly raises the associated costs. This cost increase is particularly pronounced in scenarios involving optical interconnects, where the necessity for additional components, including but not limited to additional lasers, photodiodes, and optical fibers, becomes unavoidable.

[0022] An alternative solution could involve utilizing a dedicated aggregator FPGA designed specifically for dual-camera configurations, which decodes and evaluates video data to perform aggregation. However, this system is overly complex and results in a significant increase in area, power consumption, and cost. For example, this approach may not be most efficient for dual-camera setups with equal bit rates (same video resolution), such as those used in stereo or 3D applications. The complexity and resource requirements of managing two independent video streams through such an aggregator may outweigh the benefits, especially when applications require synchronizing and aligning video frames with minimal latency. Therefore, while aggregator FPGAs offer a technically viable solution for integrating multiple video sources, their practical application may be limited to scenarios where the increased complexity and resource requirements justify the need for advanced processing or integration capabilities that simpler systems cannot provide.

[0023] Embodiments of the present invention seek to address the aforementioned challenges by providing novel systems and methods for serializing two or more digital streams, which are capable of dynamically compensating for arbitrary skew, large jitter and phase drift, and misalignment issues, thereby ensuring high-quality serialization of two or more digital streams even under varying environmental conditions, while providing a system at a limited cost.

[0024] Figure 1 A system for serializing data generated using two independent clocks and a data source into a single bit stream, according to an embodiment of the present invention, is shown. Figure 1 As shown, system 100 includes data processing circuitry 105, a first source 111, and a second source 121. Data processing circuitry 105 includes a first circuit 110 connecting the first source 111 to serialization module 130 and a second circuit 120 connecting the second source 121 to serialization module 130. Serialization module 130 may be a multiplexer, shift register, digital signal processor (DSP), application-specific integrated circuit (ASIC), etc.

[0025] The first source 111 and the second source 121 can be various data sources, including image sensors, cameras, microphones, etc. Each of the first source 111 and the second source 121 generates an independent bit stream, such as two video data streams, and the independent bit streams are combined to form a single serial bit stream. The serial bit stream can then be transmitted to another electronic or optoelectronic system using a serial link (such as optical fiber, or an electrical conductor such as copper wire).

[0026] The first source 111 and the second source 121 operate at the same bit rate. As an example, two cameras used in a 3D stereo camera system (e.g., a 3D visual camera system) can operate at a common bit rate to generate stereo video data. While the first source 111 and the second source 121 can operate at the same bit rate, these sources may exhibit characteristics such as skewness and jitter. In some embodiments, the first source 111 and the second source 121 utilize two separate chips, each with its own internal phase-locked loop (PLL), which is relatively slow and roughly multiplied by the input reference frequency to achieve a higher frequency in the output data stream. Additionally, the first source 111 and the second source 121 may have been commanded to activate at different times. Therefore, although they typically operate at the same average frequency, their alignment can vary significantly, especially during the startup phase. Furthermore, while the phase relationship with the input clock can be kept consistent, it can still change during operation because the two cameras do not receive exactly the same copy of the image. The first source 111 could originate from the camera on the left and the second source 121 could originate from another camera on the right, causing one camera to receive more light and the other less, resulting in signal differences. These differences can translate into voltage variations, which then affect the feedback mechanism. It has been observed that these variations can cause shifts of several unit intervals in the high-speed data stream. Therefore, although the long-term average frequency of the cameras may be the same, there may be short-term fluctuations, with the data stream shifting forward or backward by several bits per second. This can result in a shift of several bits in the bitstream before returning to the original alignment.

[0027] The first circuit 110 is configured to connect the first source 111 to the serialization module 130. The first circuit 110 is configured to receive first serial data D1a and a first clock signal CK1 from the first source 111 and generate a first synchronization signal D1e to the serialization module 130. Although the first serial data D1a is shown as a single data channel, it will be apparent to those skilled in the art that the first serial data D1a represents multiple data channels, such as four or six data channels. In an embodiment utilizing four data channels generated by the first source 111, the first serial data D1a will represent four data channels output by the first source 111 together with the first clock signal CK1. As will be apparent to those skilled in the art, the number of first serial-to-parallel distributors 112 and the number of first D-type flip-flops (D-FF) 114 will correspond to the number of data channels generated by the first source 111.

[0028] The first circuit 110 includes a first parallel conversion circuit 151, which may also be referred to as a stage 1 serial-to-parallel conversion circuit, operable to convert serial data generated by the first source 111 into parallel data, and a first synchronization circuit 153, which may also be referred to as a stage 3 synchronization circuit, both of which will be described more fully below.

[0029] The first parallel conversion circuit 151 includes a first serial-to-parallel distributor 112, a first clock divider 113, and a first D-FF 114. The first serial-to-parallel distributor 112 can be an N-bit shift register, demultiplexer, etc. The division ratio of the first clock divider 113 is M1. The first serial-to-parallel distributor 112 is configured to receive first serial data D1a and a first clock signal CK1, and output a first N-bit signal D1b, where N is a positive integer. The first clock divider 113 is configured to receive the first clock signal CK1 and output a first divided clock signal CK1div. The first D-FF 114 is configured to receive the first N-bit signal D1b and the first divided clock signal CK1div, and output a first parallel signal D1c. The division ratio M1 of the first clock divider can be the same as or different from the size N of the first serial-to-parallel distributor 112. As described above, although in Figure 1 The diagram shows a first serial-to-parallel distributor 112 and a first D-FF 114, but the number of first serial-to-parallel distributors 112 and the number of first D-FFs 114 will correspond to the number of data channels generated by the first source 111. Therefore, the first parallel signal D1c at the output of the first parallel conversion circuit 151 represents the conversion of a one-bit signal (i.e., the first serial data D1a at a predetermined bit rate) into an N-bit parallel signal characterized by a bit rate lower than the predetermined bit rate. Therefore, as described more fully below, the embodiment enables the alignment of the first latch signal D1d and the second latch signal D2d at a lower rate than that corresponding to the initial serial data stream, thereby reducing system requirements.

[0030] The first synchronization circuit 153 includes a third D-FF 116. The third D-FF 116 is configured to receive a first parallel signal D1c and a first frequency-divided clock signal CK1div, and output a first synchronization signal D1e to the serialization module 130.

[0031] The first circuit 110 further includes a first latch 115 connected between the first parallel conversion circuit 151 and the first synchronization circuit 153. In some embodiments, the first latch 115 is optional. When the first latch 115 is used, it is configured to receive a first parallel signal D1c and a first enable signal ENN1. The first synchronization circuit 153 is configured to receive a first latch signal D1d and a first divided clock signal CK1div, and output a first synchronization signal D1e to the serialization module 130. The first enable signal ENN1 may be the first divided clock signal CK1div.

[0032] The second circuit 120 is configured to connect the second source 121 to the serialization module 130. The second circuit 120 is configured to receive the second serial data D2a and the second clock signal CK2 from the second source 121, and output the second synchronization signal D2e to the serialization module 130. The second circuit 120 includes a second parallel conversion circuit 152, a second latch 125, and a second synchronization circuit 154.

[0033] The second parallel conversion circuit 152 includes a second serial-to-parallel distributor 122, a second clock divider 123, and a second D-FF 124. The division ratio of the second clock divider 123 is M2, where M2 is a positive integer. The second serial-to-parallel distributor 122 includes one of an N-bit shift register or a demultiplexer. The second serial-to-parallel distributor 122 is configured to receive a second serial data D2a and a second clock signal CK2, and output a second N-bit signal D2b. The second clock divider 123 is configured to receive the second clock signal CK2 and output a second divided clock signal CK2div. The second D-FF 124 is configured to receive the second N-bit signal D2b and the second divided clock signal CK2div, and output a second parallel signal D2c to a second latch. The second latch 125 is configured to receive the second parallel signal D2c and a second enable signal ENN2, and output a second latch signal D2d. The second latch 125 introduces a delay or data transmission (in transparent operation mode), as described more fully herein. The second latch 125 may delay the second parallel signal D2c to provide the second latch signal D2d in a delayed manner that aligns (i.e., time-aligns) the first parallel signal D1c or the first latch signal D1d with the second latch signal D2d. Otherwise, the second latch 125 provides the second latch signal D2d without delay via the second parallel signal D2c. The division ratio M2 of the second clock divider 123 may be the same as or different from the size N of the second serial-to-parallel distributor 122. The division ratio M2 of the second clock divider 123 may be the same as the division ratio M1 of the first clock divider 113.

[0034] The second synchronization circuit 154 includes a fourth digital flip-flop (D-FF) 126. The fourth D-FF 126 is configured to receive a second latch signal D2d and a first divided clock signal CK2div, and output a first synchronization signal D2e to the serialization module 130.

[0035] The serialization module 130 is configured to receive a first synchronization signal D1e and a second synchronization signal D2e, and output a serial bit stream. The serialization module 130 can be any multiplexer / serializer circuit.

[0036] The data processing circuit 105 may further include an alignment monitor 141. The alignment monitor 141 is configured to monitor a first divided clock signal CK1div and a second divided clock signal CK2div to identify the phase difference between them, and then control the second divided clock signal CK2div to align it with the first divided clock signal CK1div. The alignment monitor 141 is used to monitor skew between the first divided clock signal CK1div and the second divided clock signal CK2div, and can trigger (re)alignment of the second clock divider 123 by synchronizing the state of the second clock divider 123 to the state of the first clock divider 113. This can be done at least once (e.g., during startup) to start from a desired (e.g., optimal) position and provide maximum jitter tolerance. Reference Figure 2A Once the first divided clock signal CK1div and the second divided clock signal CK2div are aligned, the rising edges of these divided clock signals will appear at the same time.

[0037] The data processing circuit 105 also includes a phase detector 142 and an enable generator 143. The phase detector 142 is configured to identify the phase difference between the first divided clock signal CK1div and the second divided clock signal CK2div. The enable generator 143 is configured to receive the second divided clock signal CK2div and the phase difference CK2divLate from the phase detector 142, and output a second enable signal ENN2 to the second latch 125.

[0038] In an embodiment where the system includes both a first latch 115 and a second latch 125, the first latch 115 and the second latch 125 are configured to receive a first parallel signal D1c and a second parallel signal D2c to output a first latched signal D1d and a second latched signal D2d. The first parallel signal D1c is latched by a first enable signal ENN1, and the second parallel signal D2c is latched by a second enable signal ENN2.

[0039] For the entire alignment and serialization process, the first source 111 is considered the master source. The corresponding first enable signal ENN1 requires no special adjustment; therefore, the first divider signal CK1div can be used as the first enable signal ENN1. The first enable signal ENN1 is derived from the first divider clock signal CK1div.

[0040] By dynamically adjusting the second enable signal ENN2, the data from the second source 121 (source 2) is aligned with the data from the first source 111 (source 1). To do this, a phase detector is used to determine whether the second divided clock signal CK2div leads or lags the first divided clock signal CK1div. (See also: ...) Figure 2A As discussed, if the second divider clock signal CK2div is lagging, the latch is set (e.g., immediately set) to its transparent mode, allowing data to pass through the second parallel signal D2c without further delay. On the other hand, as regarding... Figure 2B As discussed, if the second divided clock signal CK2div (and therefore the second parallel signal D2c) is leading, a second enable signal ENN2 that delays the second parallel signal D2c is generated. Since this decision (whether to lag or lead) is made within each second divided clock signal CK2div period, the system is able to tolerate significant jitter between the first and second divided clock signals, between the first and second divided clock signals CK1div and the second divided clock signal CK2div, and therefore also handle significant jitter between the original clock signals CK1 and CK2.

[0041] In this embodiment, the data processing circuit 105 may further include a phase detector 142 and an enable generator 143. The phase detector 142 is configured to identify the phase difference between the first divided clock signal CK1div and the second divided clock signal CK2div, and generate a second divided clock lag signal CK2divlate to the enable generator 143. The enable generator 143 receives the second divided clock signal CK2div and the second divided clock lag signal CK2divlate from the phase detector 142, and outputs a second enable signal ENN2 to the second latch 125. The second enable signal ENN2 is derived from the second divided clock signal CK2div and the second divided clock lag signal CK2divlate. The second divided clock lag signal CK2divlate should be understood as representing the lead and lag relationship between the clock signals.

[0042] The first synchronization circuit 153 is configured to directly synchronize the first parallel signal D1c. The second parallel signal D2c is controlled to be aligned with the first parallel signal D1c by latching the second parallel signal D2c with the second enable signal ENN2 from the phase detector 142 and the enable generator 143.

[0043] During the synchronization of the first latch signal D1d and the second latch signal D2d to output the first synchronization signal D1e and the second synchronization signal D2e, both the first latch signal D1d and the second latch signal D2d can be synchronized by the first frequency divider clock signal CK1div.

[0044] In some embodiments, the second divided clock signal CK2div can be realigned by an alignment monitor 141 that monitors the first divided clock signal CK1div and the second divided clock signal CK2div. The alignment monitor 141 can continuously monitor the phase difference between the first divided clock signal CK1div and the second divided clock signal CK2div, and then, when the phase difference becomes too large, trigger the realignment of the second clock divider 123 to reset it to a predetermined (e.g., optimal) position.

[0045] In some data transmissions, such realignment can lead to transient data corruption (e.g., a few bits may be sent twice or only the data from source 2 may be deleted). However, in the case of data with a blanking phase, such as D-PHY video data, this realignment can be performed during each blanking phase (during which no actual video data is transmitted). Since these blanking phases are frequent (e.g., after each video line), the methods and systems described herein can be used to perform realignment during these blanking phases and maintain high (e.g., maximum) drift and / or jitter tolerances during operation. The system implementations described herein enhance robustness to common signal transmission challenges, thereby improving reliability, reducing error rates, and facilitating smoother and more efficient data communication between interconnected components or systems. Through experimentation, the inventors have determined that even phase drift exceeding + / - N*UI is acceptable, as long as the drift between blanking phases remains below this value. Here, UI = 1-bit time interval of the first serial data D1a and the second serial data D2a.

[0046] like Figure 1As shown, in stage 1, data is sampled by its corresponding clock. This ensures that the data is read using the optimal sampling point provided by the source. Furthermore, each of the first and second serial bit streams (first serial data D1a and second serial data D2a) is deserialized into N-bit packets. At this time, the N-bit packets (first N-bit signal D1b and second N-bit signal D2b) are synchronously output to the first divided clock signal CK1div and the second divided clock signal CK2div, respectively. The first divided clock signal CK1div and the second divided clock signal CK2div are derived from the first clock signal CK1 and the second clock signal CK2 by one or two suitable clock dividers (first clock divider 113 and second clock divider 123). The dividers may have a division ratio of M. M may be equal to or not equal to N. M may be equal to N / 2. N is the width of the first serial-to-parallel divider 112 and the second serial-to-parallel divider 122.

[0047] In stage 2, the optional first latch and second latch can either pass data (transparent latching) or delay data based on the applied enable signals ENN1 and / or ENN2 (active low enable). By selecting appropriate enable signals (ENN1, ENN2), the skew between the first latch signal D1d and the second latch signal D2d can be modified compared to the skew that exists between the first parallel signal D1c and the second parallel signal D2c.

[0048] In stage 3, the aforementioned skew adjustment between the data lines enables the sampling of both the first latch signal D1d and the second latch signal D2d using the same clock signal, generating the first synchronization signal D1e and the second synchronization signal D2e. These synchronization signals can then be serialized using conventional multiplexer / serializer circuitry.

[0049] When two or more digital streams are transmitted through different data channels, these channels experience differential skew and phase drift. These inconsistencies can arise from a variety of factors, including temperature fluctuations, variations in power supply voltage, or inherent differences in the transmission medium. Such variations can lead to misalignment of video frames, resulting in degraded video quality, artifacts, or loss of synchronization between the transmitted and received video streams. Embodiments of the present invention demonstrate robustness in operating effectively in environments characterized by large jitter and phase drift between two data sources. Based on empirical analysis of real-world clocks and data sources such as image sensors, the inventors have observed that relative jitter (which refers to the variability of the time interval between data packets or signals) can be substantial between the two sources. This variability poses challenges to maintaining data integrity and synchronization, thus requiring advanced system design to mitigate these effects. Embodiments of the present invention are also designed to accommodate phase drift and significant time misalignment / skew between signals from two different data sources.

[0050] As described herein, embodiments of the invention dynamically adjust and compensate for misalignment / skew, jitter, and phase drift. In doing so, the system described herein maintains high fidelity during data acquisition and processing, ensuring data integrity and accuracy even in the face of significant skew, jitter, and phase drift.

[0051] Figure 2A The waveform of a second frequency-divided clock signal that lags behind the first frequency-divided clock signal is shown according to an embodiment of the present invention. Figure 2B The waveform of a second divided clock signal, which leads the first divided clock signal, is shown according to an embodiment of the present invention. For Figure 2A and Figure 2B The waveform shown uses a Double Data Rate (DDR) clock and has an output quantity N = 6. This can be referred to as the 1 to N (demultiplexer) ratio of the first serial-to-parallel distributor, for example, a 1 to 4 demultiplexer. Both the first serial-to-parallel distributor 112 and the second serial-to-parallel distributor 122 have an output quantity N = 6. The division ratios M1 and M2 of the first clock divider 113 and the second clock divider 123 are both 3. Therefore, in Figure 2A In the example shown, the first serial data D1a is represented by a six-bit serial bitstream, and the second serial data D2a is also represented by a six-bit serial bitstream. However, these values ​​are merely exemplary, and the division ratios M1 and M2, the number of outputs N, and the clock rate are not limited to these exemplary values, and other values ​​may be used. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0052] Figure 2A and Figure 2BThe waveforms shown demonstrate the system's ability to handle jitter and phase drift up to + / - N*UI. In practice, the actual jitter / drift tolerance may be slightly smaller than this value due to the set-and-hold times used by the D-FFs and latches. Increasing the value of N can reduce the operating speed of system components and can enhance system tolerance by increasing timing margins, including handling larger input skew and input jitter (e.g., dynamic skew and jitter) between data sources. However, increasing the value of N will also increase the complexity and area utilized by the system, as the number of the first serial-to-parallel distributor 112 and the first D-FF 114, as well as the number of the second serial-to-parallel distributor 122 and the second D-FF 124 (and the number of latches discussed herein) also increase.

[0053] refer to Figure 1 and Figure 2A The six-bit serial bitstream represented by the first serial data D1a is switched to the first serial-to-parallel distributor 112 via the rising and falling edges of the first clock signal CK1. Therefore, after three clock cycles, as... Figure 2A As shown, a first parallel signal D1c comprising six bits is provided. Similarly, a six-bit serial bitstream represented by a second serial signal D2a is switched to the second serial-to-parallel distributor 122 via the rising and falling edges of the second clock signal CK2. Therefore, after three clock cycles, a second parallel signal D2c comprising six bits is provided, as shown. Figure 2A As shown. The time overlap between the first parallel signal D1c and the second parallel signal D2c is... Figure 2A The time τ represents the time between t3 and t4.

[0054] refer to Figure 2A This illustrates an example where the second divided clock signal CK2div lags behind the first divided clock signal CK1div. Figure 2A As shown, due to the skew between the divided clock signals, the rising edge of the first divided clock signal CK1div occurs at time t1, while the rising edge of the second divided clock signal CK2div occurs at time t2. In this case, the phase detector 142 sets the second divided clock hysteresis signal CK2divLate to coincide with the rising edge of the second divided clock signal CK2div to zero, indicating that the second latch signal D2d should pass through the second latch 125 without delay. This is achieved by setting the second enable signal ENN2 to coincide with the rising edge of CK2div to zero. Therefore, as... Figure 2A As shown, the second latch signal D2d is output by the second latch 125 at time t2, and it coincides with the second parallel signal D2c. Therefore, the first latch signal D1d and the second latch signal D2d overlap during time τ1. Figure 1As shown, both the third D-FF 116 and the fourth D-FF are enabled by CK1div. The result is as follows: Figure 2A As shown, the first synchronization signal D1e and the second synchronization signal D2e are aligned with and synchronized with the rising edge of the first frequency divider clock signal CK1div at time t4.

[0055] As discussed more fully below, embodiments of the invention are robust in applications where the skew between the first parallel signal D1c and the second parallel signal D2c is within the range of + / - N*UI (where UI = 1 bit). Figure 2A As shown, the skew between the first parallel signal D1c and the second parallel signal D2c is less than 6UI. Since the time interval between the first parallel signal D1c and the second parallel signal D2c is equal to 6UI, the skew is less than the time interval, resulting in time overlap between the first parallel signal D1c and the second parallel signal D2c.

[0056] refer to Figure 2B This illustrates an example where the second divided clock signal CK2div leads the first divided clock signal CK1div. Figure 2B As mentioned above, due to the skew between the frequency-divided clock signals, the rising edge of the second frequency-divided clock signal CK2div occurs at time t. 1' The rising edge of the first divided clock signal CK1div occurs at time t. 2' Therefore, as Figure 2B As shown, the output of the second parallel signal D2c by the second D-FF 124 occurs at time t. 1' Its time is determined by the first D-FF 114 at time t. 2’ Before the output of the first parallel signal D1c. In this case, the phase detector 142 will be at time t 3' Setting the second divider clock hysteresis signal CK2divLate to zero causes the second latch signal D2d to also be zero at time t. 3' Output by the second latch 125. As a result, compared to when the second parallel signal D2c and the first parallel signal D1c are aligned, at time t... 3' The output second latch signal D2d is related to time t 4' The output first latch signal D1d is more closely aligned (i.e., has reduced skew). Therefore, the second latch signal D2d and the first latch signal D1d overlap during time τ'. Figure 1 As shown, both the third D-FF 116 and the fourth D-FF are enabled by CK1div. The result is as follows: Figure 2B As shown, the first synchronization signal D1e and the second synchronization signal D2e at time t 5' It is aligned with and synchronized with the rising edge of the first divided clock signal CK1div.

[0057] Compare Figure 2A and Figure 2B The overlap between the first parallel signal D1c and the second parallel signal D2c remains within the range of + / -N*UI, i.e., between -N*UI and zero, because the second parallel signal D2c leads the first parallel signal D1c. Therefore, embodiments of the present invention provide a system capable of synchronizing signals over a skew range from -N*UI to +N*UI, i.e., + / -N*UI.

[0058] The system includes only the second latch and does not include, for example, Figure 3 In the embodiment of the first latch shown, when the second divided clock signal CK2div lags behind, for example, the phase detector 142 detects that the second divided clock signal CK2div lags behind the first divided clock signal CK1div, resulting in a delayed second parallel signal D2c, the second enable signal ENN2 immediately sets the second latch 125 to its transparent mode, so that the second parallel signal D2c can pass through the second latch 125 without further delay. Therefore, the second parallel signal D2c is modified into the second latch signal D2d.

[0059] In such Figure 1 In the embodiment shown that includes both a first latch and a second latch, the skew between the first latch signal D1d and the second latch signal D2d can also be modified by the first latch 115 and the second latch 125, compared to the skew that exists between the first parallel signal D1c and the second parallel signal D2c.

[0060] During the synchronization step, the first latch signal D1d and the second latch signal D2d are synchronized by the third D-FF 116 and the fourth D-FF 126, both of which are based on the first divided clock signal CK1div. Therefore, the first latch signal D1d and the second latch signal D2d are synchronized to become the first synchronization signal D1e and the second synchronization signal D2e, respectively.

[0061] Figure 2A The digital timing diagram of the above circuit is shown when the phase detector detects a hysteresis in the second clock divider signal CK2div. In this specific diagram, Figure 2AThe first serial data D1a and the second serial data D2a shown are both six-bit packets. However, this is just an example, and the number of bits in a packet is not limited to 6. In the parallelization step, the six-bit packets of the first serial data D1a and the second serial data D2a are synchronously output to the first parallel signal D1c and the second parallel signal D2c, respectively. This is accomplished using a first divided clock CK1div for the first serial data D1a and a second divided clock CK2div for the second serial data D2a.

[0062] As mentioned above, Figure 2B A digital timing diagram of the circuit described above is shown when the phase detector detects that the second divided clock signal CK2div is ahead. In addition to the discussion above, when the second divided clock signal CK2div is ahead, causing the second parallel signal D2c to be ahead, the system generates a second enable signal ENN2 that delays the second parallel signal D2c. The second latch 125 is set (e.g., immediately set) to its delayed mode, such that the second parallel signal D2c can be delayed through the second latch. Therefore, the second parallel signal D2c is modified into a second latched signal D2d. The skew between the first latched signal D1d (or D1c, excluding the first latch 115) and the second latched signal D2d can be modified compared to the skew that exists between the first parallel signal D1c and the second parallel signal D2c.

[0063] In this particular graph, Figure 2B The first serial data D1a and the second serial data D2a shown are both six-bit blocks. However, this is merely an example, and the number of bits in a block is not limited to six bits.

[0064] During the parallelization of the six-bit block first serial data D1a and second serial data D2a, both the first serial data D1a and the second serial data D2a are synchronously output in combination with the first divided clock signal CK1div and the second divided clock signal CK2div, respectively, as the first parallel signal D1c and the second parallel signal D2c. When the second divided clock signal CK2div appears ahead, causing the second parallel signal D2c to appear ahead, a second enable signal ENN2 is generated that delays the second parallel signal D2c. Then, the second latch 125 is set (e.g., immediately set) to its delay mode, so that the second parallel signal D2c can be delayed through the second latch. Therefore, the second parallel signal D2c is modified into the second latch signal D2d. The skew between the first latch signal D1d (e.g., the first parallel signal D1c if the first latch 115 is not included) and the second latch signal D2d can be modified compared to the skew that exists between the first parallel signal D1c and the second parallel signal D2c. During the synchronization process, both the first latch signal D1d and the second latch signal D2d are synchronized by the first divided clock signal CK1div. Then, the first latch signal D1d and the second latch signal D2d are synchronized into the first synchronization signal D1e and the second synchronization signal D2e.

[0065] As described in the embodiments of the present invention and as follows Figure 1 The significant advantage of the method shown for serializing data from two different sources lies in its area- and power-efficient implementation. This efficiency not only helps reduce or minimize the system's physical footprint and energy consumption but also enhances its compatibility with low-cost CMOS technologies. By leveraging this solution, developers can achieve a delicate balance between performance, efficiency, and cost, making it ideal for a variety of applications that provide reliable data serialization from multiple sources.

[0066] Furthermore, the versatility of the methods and systems described herein can be extended to their compatibility with both Single Data Rate (SDR) and Double Data Rate (DDR) clocks. This adaptability allows embodiments of the invention to cater to a wide range of applications, from traditional SDR environments prioritizing simplicity and cost-effectiveness to more advanced DDR scenarios achieving higher throughput and efficiency. For SDR applications, M can be equal to N (M = N). For DDR applications, M can be equal to N / 2 (M = N / 2). N is typically a multiple of 2 (e.g., ...). Figure 2A and Figure 2B (Example waveforms are shown in the image), but not limited to multiples of 2. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0067] Figure 3A system with a latch is shown for serializing data generated using two independent clocks and a data source into a single bit stream according to an embodiment of the present invention. Figure 3 The system 300 shown is Figure 1 The system 100 shown shares common elements. Therefore, regarding Figure 1 The description provided for the system 100 shown can be appropriately applied to Figure 3 The system 300 shown.

[0068] refer to Figure 3 The data processing circuit 305 utilizes only the second latch 125 (i.e., in this embodiment, it does not utilize the first circuit 310). Figure 1 The first latch 115 shown is shown, and all other components can be connected to it. Figure 1 The components shown are the same.

[0069] exist Figure 3 In the embodiment shown where system 300 utilizes only the second latch and not the first latch, a source (source 1) is considered the master source, and for the master source, the entire alignment and serialization process and the intermediate latch (first latch 115) of stage 2 can be skipped.

[0070] Compared to existing solutions for these problems, which typically involve complex hardware setups or extensive calibration processes that may be prohibitively expensive and unable to dynamically adapt to changing conditions, embodiments of the present invention offer better performance in changing operating environments.

[0071] Figure 4 An alternative system according to an embodiment of the present invention is shown for serializing data generated using two independent clocks and data sources, as well as other signals, into a single bit stream. Figure 4 The system 400 shown is Figure 1 The system 100 shown shares common elements. Therefore, regarding Figure 1 The description provided for the system 100 shown can be appropriately applied to Figure 4 The system shown is 400.

[0072] although Figure 1 The serialization module 130 shown only reuses the first synchronization signal D1e and the second synchronization signal D2e, but this is not necessary for embodiments of the present invention. Figure 4In the alternative embodiment shown, in addition to the first synchronization signal D1e and the second synchronization signal D2e, the serialization module 430 also multiplexes additional signals (i.e., any other signals 401 to be transmitted) with the first synchronization signal D1e and the second synchronization signal D2e. Therefore, the serialization module 430 is configured to receive the first synchronization signal D1e, the second synchronization signal D2e, and the other signals to be transmitted, and output a serial bit stream including all of these signals. The serialization module 430 can be any suitable multiplexer / serializer circuit.

[0073] Figure 5 It shows Figure 4 One embodiment of the system shown depicts each source having two signal channels. Although Figure 1 This illustrates that first serial data D1a and second serial data D2a, generated by first source 111 and second source 121, are each provided in a single data channel, but serial data can be generated in multiple data channels. Figure 5 In the illustrated embodiment, the first source 511 uses two data channels to output the first serial data D1a: the first serial channel data D1a-1 and the second serial channel data D1a-2, and the second source 521 outputs the second serial data D2a, which includes the third serial channel data D2a-1 and the fourth serial channel data D2a-2.

[0074] like Figure 5 As shown, system 500 includes data processing circuitry 505, a first source 511, and a second source 521. Data processing circuitry 505 includes a first circuit 510 connecting the first source 511 to serialization module 530 and a second circuit 520 connecting the second source 521 to serialization module 530. Serialization module 530 can be a multiplexer, shift register, digital signal processor (DSP), application-specific integrated circuit (ASIC), etc.

[0075] The first source 511 and the second source 521 can be various data sources, including image sensors or cameras. The first source 511 and the second source 521 generate independent bit streams, with each source generating two bit streams, for example, in a stereo camera application using two cameras with the same resolution. The four bit streams are combined to form a single serial bit stream. The serial bit stream can then be transmitted to another electronic or optoelectronic system using a serial link (e.g., optical fiber, or an electrical conductor such as copper wire).

[0076] The first source 511 and the second source 521 operate at the same bit rate. As mentioned above, although the first source 511 and the second source 521 can operate at the same bit rate, these sources may have characteristics such as skewness and jitter.

[0077] The first circuit 510 is configured to connect a first source 511 to a serialization module 530. The first source 511 generates a bitstream comprising two channels: first serial channel data D1a-1 and second serial channel data D1a-2, both of which are output along with a first clock signal CK1. The first circuit 510 is configured to receive the first serial channel data D1a-1 and the second serial channel data D1a-2, along with the first clock signal CK1, from the first source 511, and generate a first channel synchronization signal D1e-1 and a second channel synchronization signal D1e-2 to the serialization module 530. In addition to the first serial-to-parallel distributor 112 and the first D-FF 114, a first channel serial-to-parallel distributor 512(b) (also referred to as a third serial-to-parallel distributor) and a first channel D-FF 514(b) (also referred to as a fifth D-FF) are included to correspond to the number of data channels generated by the first source 511.

[0078] The first circuit 510 includes a first parallel conversion circuit 551, which may also be referred to as a stage 1 serial-to-parallel conversion circuit, operable to convert serial data generated by the first source 511 into parallel data, and a first synchronization circuit 553, which may also be referred to as a stage 3 synchronization circuit, both of which will be described more fully below.

[0079] The first parallel conversion circuit 551 includes a first serial-to-parallel distributor 112, a first-channel serial-to-parallel distributor 512(b), a first clock divider 113, a first D-FF 114, and a first-channel D-FF 514(b). The first serial-to-parallel distributor 112 and the first-channel serial-to-parallel distributor 512(b) can be N-bit shift registers or demultiplexers, etc. The division ratio of the first clock divider 113 is M1. The first serial-to-parallel distributor 112 is configured to receive first serial data D1a-1 and a first clock signal CK1, and output a first-channel N-bit signal D1b-1, where N is a positive integer. The first-channel serial-to-parallel distributor 512(b) is configured to receive first serial data D1a-2 and a first clock signal CK1, and output a second-channel N-bit signal D1b-2. The first clock divider 113 is configured to receive the first clock signal CK1 and output a first divided clock signal CK1div. The first D-FF 114 is configured to receive the first channel N-bit signal D1b-1 and the first divided clock signal CK1div, and output the first channel parallel signal D1c-1. The first channel D-FF 514(b) is configured to receive the second channel N-bit signal D1b-2 and the first divided clock signal CK1div, and output the second channel parallel signal D1c-2. The division ratio M1 of the first clock divider can be the same as or different from the size N of the first serial-to-parallel distributor 112. The first serial-to-parallel distributor 112, the first channel serial-to-parallel distributor 512(b), the first D-FF 114, and the first channel D-FF 514(b) can be similar to... Figure 1 and Figure 4 The serial-to-parallel distributor and D-FF are shown. Therefore, the first channel parallel signal D1c-1 and the second channel parallel signal D1c-2 at the output of the first parallel conversion circuit 551 represent the conversion of a one-bit signal (i.e., the first channel serial data D1a-1 and the second channel serial data D1a-2 at a predetermined bit rate) into an N-bit parallel signal, characterized by a bit rate lower than the predetermined bit rate. Therefore, as described more fully below, the embodiment enables the alignment of the first channel latch signal D1d-1, the second channel latch signal D1d-2, the third channel latch signal D2d-1, and the fourth channel latch signal D2d-2 at a lower rate than that corresponding to the initial serial data stream, thereby reducing system requirements.

[0080] The first synchronization circuit 553 includes a third D-FF 116 and a third channel D-FF 516(b). The third D-FF 116 and the third channel D-FF 516(b) are configured to receive the first channel parallel signal D1c-1, the second channel parallel signal D1c-2 and the first frequency division clock signal CK1div, and output the first channel synchronization signal D1e-1 and the second channel synchronization signal D1e-2 to the serialization module 530.

[0081] The first circuit 510 may further include a first latch 115 and a first channel latch 515(b) connected between the first parallel conversion circuit 551 and the first synchronization circuit 553. In some embodiments, the first latch 115 is optional. When the first latch 115 and the first channel latch 515(b) are used, the first latch 115 and the first channel latch 515(b) are configured to receive a first channel parallel signal D1c-1 and a second channel parallel signal D1c-2, as well as a first enable signal ENN1, and generate a first channel latch signal D1d-1 and a second channel latch signal D1d-2. The first synchronization circuit 553 is configured to receive the first channel latch signal D1d-1 and the second channel latch signal D1d-2, as well as a first frequency divider clock signal CK1div, and output a first channel synchronization signal D1e-1 and a second channel synchronization signal D1e-2 to the serialization module 530. The first enable signal ENN1 may be the first frequency divider clock signal CK1div.

[0082] The second circuit 520 is configured to connect the second source 521 to the serialization module 530. The second circuit 520 is configured to receive third channel serial data D2a-1, fourth channel serial data D2a-2, and a second clock signal CK2 from the second source 521, and output a third synchronization signal D2e-1 and a fourth synchronization signal D2e-2 to the serialization module 530. The second circuit 520 includes a second parallel conversion circuit 552, a second latch 125, a second channel latch 525(b), and a second synchronization circuit 554.

[0083] The second parallel conversion circuit 552 includes a second serial-to-parallel distributor 122, a second-channel serial-to-parallel distributor 522(b), a second clock divider 123, a second D-FF 124, and a second-channel D-FF 524(b). The division ratio of the second clock divider 123 is M2, where M2 is a positive integer. Each of the second serial-to-parallel distributor 122 and the second-channel serial-to-parallel distributor 522(b) may include an N-bit shift register or a demultiplexer, etc. The second serial-to-parallel distributor 122 and the second-channel serial-to-parallel distributor 522(b) are configured to receive third-channel serial data D2a-1, fourth-channel serial data D2a-2, and a second clock signal CK2, and generate a third-channel N-bit signal D2b-1 and a fourth-channel N-bit signal D2b-2. The second clock divider 123 is configured to receive the second clock signal CK2 and output a second divided clock signal CK2div. The second D-FF 124 and the second channel D-FF 524(b) are configured to receive the third channel N-bit signal D2b-1, the fourth channel N-bit signal D2b-2, and the second divider clock signal CK2div, and output the third channel parallel signal D2c-1 and the fourth channel parallel signal D2c-2 to the second latch 125 and the second channel latch 525(b). The second latch 125 and the second channel latch 525(b) are configured to receive the third channel parallel signal D2c-1, the fourth channel parallel signal D2c-2, and the second enable signal ENN2, and output the third channel latch signal D2d-1 and the fourth channel latch signal D2d-2. The second latch 125 and the second channel D-FF 524(b) introduce delays or pass-through data (in transparent operation mode), as described more fully herein. The second latch 125 and the second channel D-FF 524(b) can delay the third channel parallel signal D2c-1 and the fourth channel parallel signal D2c-2 in a delay manner that allows the first channel parallel signal D1c-1 and the second channel parallel signal D1c-2, or the first channel latch signal D1d-1 and the second channel latch signal D1d-2, to be aligned (i.e., time-aligned) with the third channel latch signal D2d-1 and the fourth channel latch signal D2d-2. Otherwise, the second latch 125 provides the third channel latch signal D2d-1 without delay via the third channel parallel signal D2c-1. The second channel latch 525(b) provides the fourth channel latch signal D2d-2 without delay via the fourth channel parallel signal D2c-2. The division ratio M2 of the second clock divider 123 can be the same as or different from the size N of the second serial-to-parallel divider 122 and the second channel serial-to-parallel divider 522(b). The division ratio M2 of the second clock divider 123 can be the same as the division ratio M1 of the first clock divider 113.

[0084] The second synchronization circuit 554 includes a fourth D-FF 126 and a fourth channel D-FF 526(b). The fourth D-FF 126 and the fourth channel D-FF 526(b) are configured to receive the third channel latch signal D2d-1, the fourth channel latch signal D2d-2 and the first frequency divider clock signal CK2div, and output the third channel synchronization signal D2e-1 and the fourth channel synchronization signal D2e-2 to the serialization module 530.

[0085] The serialization module 530 is configured to receive the first channel synchronization signal D1e-1, the second channel synchronization signal D1e-2, the third channel synchronization signal D2e-1, and the fourth channel synchronization signal D2e-2, and output a serial bit stream. The serialization module 530 can be any multiplexer / serializer circuit.

[0086] Figure 5 The system 500 shown is with Figure 1 The system 100 shown and Figure 4 The system 400 shown shares common elements, alignment monitor 141, phase detector 142, enable generator 143, and any other signals 401 to be transmitted. Therefore, regarding... Figure 1 and Figure 4 The descriptions provided for systems 100 and 400 shown can be appropriately applied to... Figure 5 The system 500 shown is shown.

[0087] Figure 6 This is a simplified flowchart illustrating a method for serializing data according to an embodiment of the present invention. Method 600 includes receiving first serial data and a first clock signal from a first source (610), and receiving second serial data and a second clock signal from a second source (612). The method further includes parallelizing the first serial data to generate a first parallel signal (614), and parallelizing the second serial data to generate a second parallel signal (616). In some embodiments, parallelizing the first serial data includes: sampling the first serial data with a first clock signal and deserializing the first serial data into a first packet of N-bit signals; and synchronizing the first packet of N-bit signals to a first divided clock signal, wherein the first divided clock signal is derived from the first clock signal by a first clock divider. Furthermore, parallelizing the second serial data may include: sampling the second serial data with a second clock signal and deserializing the second serial data into a second N-bit signal; and synchronizing the second N-bit signal to a second divided clock signal, wherein the second divided clock signal is derived from the second clock signal by a second clock divider.

[0088] The method further includes: latching a first parallel signal using a first enable signal to generate a first latch signal (618), and latching a second parallel signal using a second enable signal to generate a second latch signal (620). In some embodiments, the second enable signal is derived from a second divided clock signal and a second divided clock hysteresis signal. The second divided clock hysteresis signal may be defined by the time difference between the first divided clock signal and the second divided clock signal. The first enable signal may be equal to the first divided clock signal.

[0089] Furthermore, the method includes: synchronizing a first latch signal and a second latch signal to generate a first synchronization signal and a second synchronization signal (622), and serializing the first synchronization signal and the second synchronization signal to generate a serial bit stream (624). Synchronizing the first parallel signal may include: synchronizing the first parallel signal with a first divided clock signal, and synchronizing the second latch signal may include: synchronizing the second latch signal with a first divided clock signal. Latching the first parallel signal may be performed before synchronizing the first parallel signal. The method may also include: realigning the second divided clock signal to align with the first divided clock signal. Furthermore, in some embodiments, the method includes: detecting a phase delay between the first divided clock signal and the second divided clock signal, and generating the second latch signal based on the phase delay.

[0090] The first serial data may include serial data from at least two data channels, and the second serial data may include serial data from at least two data channels. In these embodiments, parallelization includes parallelizing the first serial data and the second serial data; latching includes latching a second parallel signal for each data channel; synchronization includes synchronizing the first parallel signal for each data channel and synchronizing the second latch signal for each data channel; and serialization includes serializing the first synchronization signal and the second synchronization signal for each data channel to generate a serial bit stream. In some alternative embodiments, the method includes serializing one or more additional signals, wherein the serial bit stream includes the first synchronization signal, the second synchronization signal, and the one or more additional signals.

[0091] It should be understood that Figure 6 The specific steps shown provide a particular method for serializing data according to one embodiment of the present invention. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments of the invention may perform the steps outlined above in a different order. Furthermore, Figure 6 A single step shown may include multiple sub-steps, which may be executed in various orders suitable for that single step. Furthermore, depending on the specific application, additional steps may be added or removed. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0092] In one embodiment, the system addresses the aforementioned challenges of transmitting from two video data sources (although a greater number of video sources could be utilized), individually and dynamically compensating for arbitrary skew and phase drift, as well as misalignment issues, thereby ensuring high-quality video transmission even under varying environmental conditions. The system may include two cameras, such as... Figure 1 The diagram shows the data processing circuitry and transmission cable. Two cameras can be dual-channel video transmission units, responsible for encoding and transmitting video data on two separate channels. The data processing circuitry is configured to dynamically adjust the timing and alignment of the data channels based on real-time feedback, effectively mitigating the effects of jitter, skew, phase drift, and misalignment. The data processing circuitry manages the integrity of the video data transmitted on the dual channels. Each video channel operates independently, transmitting a serial bitstream of first serial data D1a and second serial data D2a, with corresponding clock lines: first clock signal CK1 and second clock signal CK2. The data processing circuitry detects and quantifies any skew or phase drift between channels attributed to temperature variations, power supply voltage instability, or other external factors. The data processing circuitry serializes the adjusted dual channels into a serial bitstream to the transmission cable. This system serializes two data sources into a single data stream, reducing the number of channels required (cost / area savings) compared to solutions that must transmit data from two sources separately.

[0093] The data is not limited to video data as described in the foregoing embodiments. The data stream includes different types of data, such as visual, audio, and binary information encoded using encoding methods (e.g., MPEG, JPEG, H.264 for video data; PCM, AAC for audio data; other relevant encodings for computer data). The data includes digital signals formatted according to specific communication protocols or standards suitable for transmission via different types of cables (e.g., coaxial cable, fiber optic cable, HDMI cable, USB cable). This output configuration is designed for seamless integration with applications or systems (e.g., broadcast systems, networked computing environments, multimedia display systems) to facilitate real-time or buffered transmission of high-quality data streams.

[0094] The data processing circuitry is cleverly designed to manage significant timing misalignment or skew between two different data sources by accommodating arbitrary levels of skew in their data and clock signals, even when both utilize the same reference clock. This skew can be caused by factors such as signal propagation delays, differences in circuit path lengths, or variations in processing speed, leading to misalignment between the transmitted data and the clock signal. The system's robust architecture employs advanced algorithms and synchronization mechanisms to ensure data integrity and synchronization, effectively handling large skews between data sources.

[0095] Furthermore, this system can operate in environments with significant jitter and phase drift between data sources. Empirical analysis of real clocks and data sources (such as image sensors) has shown significant variations in the time intervals between data packets or signals, posing challenges to data integrity and synchronization. This system is tolerant of phase drift, which can be caused by external factors such as temperature fluctuations or power supply voltage variations, leading to changes in propagation delay. By dynamically adjusting to compensate for both jitter and phase drift, the system maintains high data fidelity, ensuring data integrity and accuracy despite these challenges.

[0096] Another advanced feature of this system is its automatic detection and subsequent realignment of misalignments, ensuring operational continuity even under dynamic conditions. It autonomously identifies and corrects data stream alignment deviations caused by skew variations or drift, minimizing the need for manual intervention and enhancing system reliability and efficiency. For video data, automatic realignment during the blanking phase increases tolerance to drift between data sources without corrupting the video data.

[0097] The system is compatible with multiple clocking technologies, including both Single Data Rate (SDR) and Double Data Rate (DDR) clocks, allowing for seamless integration into a wide range of technological environments, from traditional setups requiring simple data transfer rates to more advanced applications demanding higher throughput and efficiency.

[0098] Designed for power and area efficiency, this system is the desired (e.g., optimal) choice for integration into systems prioritizing resource conservation and compactness, particularly beneficial in the context of low-cost CMOS technology. This efficiency reduces manufacturing costs and aligns with industry trends toward sustainable and economically viable electronic solutions, fostering the development of high-performance, cost-effective, and environmentally friendly electronics. The design goes beyond simply accommodating two sources and can be modified to support multiple data sources, not just a binary configuration. This scalability allows for a wider range of applications and more complex data integration scenarios where data from numerous sources needs to be serialized and processed efficiently. By not limiting the system to just two inputs, embodiments of the invention open up possibilities for broader and more versatile data processing capabilities, catering to the growing need for systems capable of managing data from the increasingly diverse arrays of sensors, devices, and information streams in today's interconnected digital environments.

[0099] The various features described herein (e.g., methods, apparatus, computer-readable media, etc.) can be implemented using combinations of dedicated components, programmable processors, and / or other programmable devices. Some processes described herein can be implemented on the same processor or on different processors. Some components are described as being configured to perform certain operations, which can be achieved, for example, by designing electronic circuits, by programming programmable electronic circuits (e.g., microprocessors), or combinations thereof. Furthermore, while the embodiments described above may refer to specific hardware and software components, those skilled in the art will understand that different combinations of hardware and / or software components can also be used, and specific operations described as being implemented in hardware can be implemented in software, and vice versa.

[0100] Details are set forth in the foregoing description to provide an understanding of the embodiments. However, it should be understood that these embodiments may be practiced without some of these specific details. In some instances, well-known circuits, processes, algorithms, structures, and techniques are not shown in the figures.

[0101] Although the principles of this disclosure have been described above in conjunction with specific apparatus and methods, it should be understood that this description is by way of example only and is not intended to limit the scope of this disclosure. The embodiments were chosen and described to explain the principles and practical application, enabling others skilled in the art to utilize the invention in various embodiments and make various modifications to suit a particular intended use. It should be understood that this description is intended to cover modifications and equivalents.

[0102] Furthermore, it should be noted that embodiments can be described as processes depicted as operation diagrams, flowcharts, data flow diagrams, structure diagrams, or block diagrams. Although flowcharts can describe operations as sequential processes, many operations can be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed, but may have additional steps not included in the diagram. A process can correspond to a method, function, process, subroutine, subroutine, etc.

[0103] Unless otherwise indicated, the expressions “one,” “an,” or “the” are intended to mean “one or more.”

[0104] The specific details of a particular embodiment may be combined in any suitable manner without departing from the spirit and scope of the embodiments of the invention. However, other embodiments of the invention may relate to specific embodiments relating to each individual aspect or a particular combination of these individual aspects.

[0105] The foregoing description of embodiments of the present invention is provided for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the invention to the precise forms described, and many modifications and variations are possible in light of the above teachings. The embodiments were chosen and described to explain the principles of the invention and its practical application, thereby enabling others skilled in the art to utilize the invention in various embodiments and make various modifications to suit a particular intended use.

Claims

1. A data processing circuit, comprising: The first circuit includes: The first parallel conversion circuit includes: First serial-to-parallel distributor; The first clock divider has a division ratio M; and The first type D flip-flop (D-FF); and The first synchronization circuit, coupled to the first parallel conversion circuit, and The second circuit includes: The second parallel conversion circuit includes: Second serial-to-parallel distributor; The second clock divider has a division ratio M; and Second D-FF; A second latch, coupled to the second parallel conversion circuit; and A second synchronization circuit, coupled to the second latch; and A serialization module, which is coupled to the first synchronization circuit and the second synchronization circuit.

2. The data processing circuit according to claim 1, wherein, The first circuit further includes a first latch, which is coupled to the first parallel conversion circuit and the first clock divider, and the first synchronization circuit is coupled to the first latch.

3. The data processing circuit according to claim 2, wherein, The first latch signal of the first latch is equal to the first divided clock signal of the first clock divider.

4. The data processing circuit according to claim 1, wherein, The first serial-to-parallel distributor and the first clock distributor are coupled to the first source, and the first D-FF is coupled to the first serial-to-parallel distributor and the first clock distributor.

5. The data processing circuit according to claim 4, wherein, The first source includes at least one of a camera, a microphone, or a sensor.

6. The data processing circuit according to claim 4, wherein, The first parallel conversion circuit further includes: A third serial-to-parallel distributor, coupled to the first source; and The fifth D-FF is coupled to the third serial-to-parallel distributor and the first clock distributor.

7. The data processing circuit according to claim 1, wherein, The first serial-to-parallel distributor or the second serial-to-parallel distributor includes an N-bit shift register.

8. The data processing circuit according to claim 7, wherein, The frequency division ratio M is equal to N or N / 2.

9. The data processing circuit according to claim 1, wherein, The first serial-to-parallel allocator or the second serial-to-parallel allocator includes a demultiplexer.

10. The data processing circuit of claim 1 further includes an alignment monitor coupled to the first clock divider and the second clock divider.

11. The data processing circuit according to claim 1, further comprising: A phase detector coupled to the first clock divider and the second clock divider; as well as An enable generator, which is coupled to the phase detector and the second clock divider; The second latch is coupled to the enable generator.

12. The data processing circuit according to claim 1, wherein, The first synchronization circuit further includes a third D-FF, wherein the third D-FF is coupled to the first D-FF and the first clock divider, and the serialization module is coupled to the third D-FF.

13. A method for serializing data, the method comprising: Receive first serial data and a first clock signal from a first source; Receive second serial data and second clock signal from the second source; Parallelize the first serial data to generate a first parallel signal; Parallelize the second serial data to generate a second parallel signal; The first enable signal is used to latch the first parallel signal to generate the first latch signal; The second enable signal is used to latch the second parallel signal to generate the second latch signal; Synchronize the first latch signal and the second latch signal to generate a first synchronization signal and a second synchronization signal; and The first synchronization signal and the second synchronization signal are serialized to generate a serial bit stream.

14. The method of claim 13, wherein: Parallelizing the first serial data includes: The first serial data is sampled using the first clock signal, and the first serial data is deserialized into a first packet of N-bit signals; and The first group of the N-bit signal is synchronized with a first frequency-divided clock signal, wherein the first frequency-divided clock signal is derived from the first clock signal by a first clock divider; and Parallelizing the second serial data includes: The second serial data is sampled using the second clock signal, and the second serial data is deserialized into a second N-bit signal; and The second N-bit signal is synchronized to a second divided clock signal, wherein the second divided clock signal is derived from the second clock signal by a second clock divider.

15. The method for serializing data according to claim 14, wherein, The second enable signal is derived from the second divided clock signal and the second divided clock hysteresis signal, wherein the second divided clock hysteresis signal includes the time difference between the first divided clock signal and the second divided clock signal.

16. The method for serializing data according to claim 14, wherein, Synchronizing the first parallel signal includes synchronizing the first parallel signal using a first frequency-divided clock signal, and synchronizing the second latch signal includes synchronizing the second latch signal using a first frequency-divided clock signal.

17. The method for serializing data according to claim 14, wherein, Latching the first parallel signal is performed before synchronizing the first parallel signal.

18. The method for serializing data according to claim 17, wherein, The first enable signal is equal to the first frequency divider clock signal.

19. The method for serializing data according to claim 14, further comprising: Realign the second divided clock signal to align it with the first divided clock signal.

20. The method for serializing data according to claim 14, further comprising: Detect the phase delay between the first frequency-divided clock signal and the second frequency-divided clock signal; as well as The second latch signal is generated based on the phase delay.

21. The method for serializing data according to claim 13, wherein: The first serial data includes serial data from at least two data channels, and the second serial data includes serial data from at least two data channels; Parallelization includes parallelizing the first serial data and the second serial data; Latching includes latching the second parallel signal for each data channel; Synchronization includes synchronizing the first parallel signal of each data channel and synchronizing the second latch signal of each data channel; and Serialization includes serializing a first synchronization signal and a second synchronization signal for each data channel to generate the serial bit stream.

22. The method for serializing data according to claim 13, further comprising serializing one or more additional signals, wherein, The serial bit stream includes the first synchronization signal, the second synchronization signal, and the one or more additional signals.

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