Programmable integrated transceiver applied to X wave band

Abstract

The invention belongs to the technical field of integrated transceivers, and particularly relates to a programmable integrated transceiver applied to an X wave band, which comprises a down-conversion unit used for down-converting a 9.6 + / -0.3 GHz radio frequency signal to a 1.1 + / -0.3 GHz intermediate frequency signal, an up-conversion unit used for up-converting the 1.1 + / -0.3 GHz intermediate frequency signal to a 9.6 + / -0.3 GHz radio frequency signal, a clock and frequency synthesizer unit, and an X-waveband integrated transceiver. The control module is used for providing 8.5 GHz local oscillation signals to the down-conversion unit and the up-conversion unit, the calibration switch unit is used for realizing equal-amplitude and equal-phase connection between ANT1 and ANT2 ports and a calibration output port, and the control module is used for controlling gain or attenuation through an RS422 serial port. According to the invention, high-precision frequency conversion of 9.6 + / -0.3 GHz and 1.1 + / -0.3 GHz can be realized, the instantaneous bandwidth reaches 600MHz, and the broadband requirement is met; the isolation degree of transceiving and transmitting channels is larger than or equal to 70 dB, and interference is effectively reduced.

Description

Technical Field

[0001] This invention belongs to the field of integrated transceiver technology, specifically relating to an integrated transceiver for X-band programmable applications. Background Technology

[0002] In the fields of modern communication, radar, remote sensing and other radio frequency technologies, the X-band (8-12GHz) is widely used in satellite communication, weather radar, aerospace measurement and control and other scenarios due to its advantages such as moderate bandwidth, strong anti-interference ability and small equipment size. As the core component of the X-band system, the radio frequency integrated transceiver undertakes key functions such as receiving, frequency conversion, transmission and signal processing of radio frequency signals. Its performance directly determines the communication quality, detection accuracy and stability of the entire system.

[0003] As application demands continue to upgrade, existing X-band RF integrated transceivers are gradually revealing the following technical bottlenecks:

[0004] Traditional integrated transceivers often employ fixed-gain downconversion modules, which struggle to adapt to wide dynamic range (e.g., -50 to +10 dBm) RF input signals, leading to signal saturation or excessive noise. Upconversion modules, on the other hand, have low transmit power adjustment accuracy and insufficient harmonic and spurious suppression capabilities (typically only -40 to -50 dBc), resulting in severe signal interference and impacting communication or detection accuracy. Furthermore, some devices have narrow instantaneous bandwidth (mostly below 300 MHz), failing to meet the demands of broadband signal transmission.

[0005] For systems with multiple transmission channels, the amplitude consistency between transmission channels of existing equipment is mostly above ±2dB, the phase consistency is above ±15°, and the drift with temperature changes is obvious (e.g., power stability ≥2dB within the operating temperature range). This makes it difficult to meet the requirements of scenarios with high channel synchronization requirements, such as phased array radar and multi-beam communication. In addition, the isolation between transmit and receive channels is insufficient (often below 60dB), which easily generates transmit and receive interference, resulting in a decrease in receiver sensitivity.

[0006] The clock modules of existing sub-units mostly rely on a single external reference signal (such as only supporting 10MHz or 100MHz), lacking the ability to adaptively switch between internal and external references. When the external reference signal is interrupted, the system is prone to losing lock. The calibration function is mostly open-loop calibration, which makes it difficult to compensate for channel phase difference in real time, and the calibration accuracy is low (the phase difference is mostly above ±5°), which cannot meet the requirements of high-precision measurement or beamforming.

[0007] Traditional equipment often adopts a multi-module discrete design, resulting in a large size (mostly 3U and above chassis) and a variety of interface types, which is not conducive to system integration. The power module has poor compatibility, with some equipment only supporting DC power supply and lacking direct adaptation to AC220V mains power, which limits its application in civilian or general scenarios. At the same time, the electromagnetic compatibility (EMC) and heat dissipation design are not perfect, which leads to a decrease in the stability of the equipment in complex electromagnetic environments.

[0008] To address the aforementioned issues, there is an urgent need for an X-band RF integrated transceiver with high integration, excellent frequency conversion performance, good channel consistency, and flexible and reliable clock and calibration mechanisms, in order to meet the technical requirements of modern communications, radar, and other fields for wide bandwidth, high precision, and high stability. Summary of the Invention

[0009] The purpose of this invention is to provide an integrated transceiver for X-band programmable applications, capable of high-precision frequency conversion between 9.6±0.3GHz and 1.1±0.3GHz, with an instantaneous bandwidth of 600MHz, meeting wideband requirements; the isolation between the transmit and receive channels is ≥70dB, effectively reducing interference; the amplitude consistency of the dual transmit channels is ≤1dB, the phase consistency is ≤10°, and the phase difference stability is ≤3°, demonstrating excellent channel synchronization; the clock supports adaptive switching between 10MHz / 100MHz internal and external references, with an output accuracy of ±0.1ppm; the phase difference of the calibration switch is ≤±3°, ensuring calibration accuracy; it adopts a 2U chassis integrated design, supports AC220V power supply, and features high integration and strong adaptability.

[0010] The specific technical solution adopted by this invention is as follows:

[0011] An integrated transceiver for X-band programmable applications, comprising:

[0012] The downconversion unit is used to downconvert a 9.6±0.3GHz radio frequency signal to a 1.1±0.3GHz intermediate frequency signal;

[0013] The upconversion unit is used to upconvert the 1.1±0.3GHz intermediate frequency signal to a 9.6±0.3GHz radio frequency signal;

[0014] The clock and frequency synthesizer unit provides an 8.5GHz local oscillator signal to the downconverter and upconverter units, and supports adaptive switching of 10MHz / 100MHz external reference clock;

[0015] The calibration switch unit enables equal amplitude and phase connection between the ANT1 and ANT2 ports and the calibration output port;

[0016] The control module controls the gain or attenuation via RS422 serial port and controls the pulse modulation switch via TTL differential port;

[0017] The power module converts AC220V to DC+12V and DC-5V for power supply.

[0018] The downconverter unit is connected in sequence to a limiter, a switch, a switched filter bank, a bandpass filter, a mixer, an intermediate frequency amplifier, a digitally controlled attenuator, and a low-pass filter.

[0019] The upconversion unit includes two channels, each channel being connected in sequence to a temperature-compensated attenuator, an intermediate frequency amplifier, a digitally controlled attenuator, a mixer, a bandpass filter, two stages of digitally controlled attenuators, and an output switch.

[0020] The clock and frequency synthesizer unit includes:

[0021] The external reference detection module determines the presence status of 10MHz and 100MHz external reference signals;

[0022] The phase-locked loop module generates an 8.5GHz local oscillator signal with a 100MHz signal as a reference.

[0023] The frequency divider module divides a 100MHz signal into a 10MHz clock signal.

[0024] The power divider module outputs four 100MHz clock channels.

[0025] In the calibration switch unit, the phase difference between ANT1 and the calibration port is ensured. Phase difference between ANT2 and calibration port satisfy

[0026] The pulse modulation switch control interface of the control module includes:

[0027] Receive switch control terminal;

[0028] Transmit channel 1 switch control terminal;

[0029] Transmission Channel 2 switch control terminal.

[0030] This integrated transceiver connects to the transceiver channel via a circulator to achieve full-duplex transmission and reception, and simplex transmission and reception when the jumper is disconnected.

[0031] The integrated transceiver is housed in a 2U-19 inch chassis, and the power module has a built-in AC220V filter.

[0032] The technical effects achieved by this invention are as follows:

[0033] This invention provides one channel for receiving frequencies from 9.6±0.3GHz to 1.1±0.3GHz with downconversion and power regulation, input filtering, and input limiter functions; and two channels for transmitting frequencies from 1.1±0.3GHz to 9.6±0.3GHz.

[0034] It features 0.3GHz upconversion and power regulation, an instantaneous bandwidth of 600MHz, and non-invertable spectrum. The upconversion channels 1 and 2 for receiving and transmitting are connected to a shared port of the circulator via an external jumper, enabling full-duplex transmission and reception. By disconnecting the external jumper, simplex transmission and reception are achieved. The receiving and transmitting channels share a local oscillator and have internal and external reference adaptive functions. It can select and switch between 10MHz and 100MHz external reference clocks and has a closed-loop calibration function for switching the receiving and transmitting channels. The phase difference between each channel output port and the calibration output port is within ±3°. The receiving and transmitting channels have switch control gating functions, module current detection, internal and external reference detection, and reporting via serial port query. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the overall principle of the present invention;

[0036] Figure 2 This is a block diagram of the downconverter unit in this invention;

[0037] Figure 3 This is a block diagram of the upconversion unit in this invention;

[0038] Figure 4 This is a simulation diagram of the link when the upconversion unit link does not attenuate in this invention;

[0039] Figure 5 This is a graph showing the isolation degree of the link simulation device in this invention;

[0040] Figure 6 This is a block diagram of the intermediate frequency synthesizer unit of this invention;

[0041] Figure 7 This is a diagram of the 200MHz-15GHz low-noise frequency synthesizer device in this invention.

[0042] Figure 8 This is a block diagram of the calibration switch principle in this invention;

[0043] Figure 9 This is a block diagram of the control module in this invention;

[0044] Figure 10 This is a block diagram of the power module principle in this invention;

[0045] Figure 11 This is a block diagram illustrating the principle of the integrated transceiver power module in this invention. Detailed Implementation

[0046] To make the objectives and advantages of this invention clearer, the invention will be specifically described below with reference to embodiments. It should be understood that the following text is merely used to describe one or more specific embodiments of the invention and does not strictly limit the scope of protection specifically claimed by the invention.

[0047] like Figures 1-11 As shown, an integrated transceiver for X-band programmable applications includes:

[0048] The downconversion unit is used to downconvert a 9.6±0.3GHz radio frequency signal to a 1.1±0.3GHz intermediate frequency signal;

[0049] See appendix Figure 2 The downconverter unit is connected in sequence to a limiter, a switch, a switched filter bank, a bandpass filter, a mixer, an intermediate frequency amplifier, a digitally controlled attenuator, and a low-pass filter;

[0050] The principle of the downconverter unit is as follows: Figure 2 As shown: The 9.6GHz radio frequency signal is limited by a limiter, controlled by a switch, and switched with the calibration input signal via a switch. After being switched by a switching filter bank to the amplifier and the direct signal, it is filtered by a bandpass filter and mixed with the local oscillator LO: 8.5GHz to obtain a signal with a center frequency of 1.1GHz and a bandwidth of 0.6GHz. This signal is then filtered, amplified, controlled by a digitally controlled attenuator, filtered by a low-pass filter, and output.

[0051] The upconversion unit is used to upconvert the 1.1±0.3GHz intermediate frequency signal to a 9.6±0.3GHz radio frequency signal;

[0052] See appendix Figure 3 The upconverter unit includes two channels, each of which is connected in sequence to a temperature-compensated attenuator, an intermediate frequency amplifier, a digitally controlled attenuator, a mixer, a bandpass filter, two stages of digitally controlled attenuators, and an output switch;

[0053] Furthermore, the two channels operate on the same principle. We will take one of the channels as an example to illustrate its principle.

[0054] The intermediate frequency (IF) signal with a center frequency of 1.1 GHz and a bandwidth of ±0.3 GHz is controlled by a temperature-compensated attenuator, amplified by an amplifier, controlled by a digitally controlled attenuator, and mixed with the local oscillator (LO) signal of 8.5 GHz to obtain an radio frequency (RF) signal with a center frequency of 9.6 GHz and a bandwidth of ±0.3 GHz. This signal is then filtered by a bandpass filter, controlled by two stages of digitally controlled attenuators, and finally output after being controlled by a switch.

[0055] The power modulation switch is used to control the power supply to the transmitter amplifier;

[0056] The link simulation when the upconversion unit link does not attenuate is shown in the attached figure. Figure 4 As shown;

[0057] From the appendix Figure 4The link simulation shows that the link gain is 14dB, the noise figure is 15.3dB, and the instantaneous bandwidth is 600MHz. Therefore, the link noise floor is ≤-174dBm / Hz+14dB+15.3dB+87.7dB=-57dBm / Hz.

[0058] The final stage switch of the transmit link is ISW-0018ST, and the device isolation curve is attached. Figure 5 As shown, the isolation within the frequency band used is ≥50dB;

[0059] According to previous project tests, the isolation of the circulator between the transceiver links is ≥20dB. Therefore, when the receiving unit is working, the final stage switch of the transmitting unit link is open. At this time, the noise floor of the transmitting unit is ≤-57dBm / Hz-50dB-20dB=-127dBm / Hz.

[0060] The clock and frequency synthesizer unit provides an 8.5GHz local oscillator signal to the downconverter and upconverter units, and supports adaptive switching of 10MHz / 100MHz external reference clock;

[0061] See appendix Figure 6 The clock and frequency synthesizer unit includes:

[0062] The external reference detection module determines the presence status of 10MHz and 100MHz external reference signals;

[0063] The phase-locked loop module generates an 8.5GHz local oscillator signal with a 100MHz signal as a reference.

[0064] The frequency divider module divides a 100MHz signal into a 10MHz clock signal.

[0065] The power divider module outputs four 100MHz clock channels;

[0066] The working principle of the frequency synthesizer is as follows:

[0067] A coupling-detector structure is designed at the external reference input terminal to determine whether there is an external reference signal input.

[0068] When an external reference signal is input, the 10MHz and 100MHz external reference input signals are switched via single and double switches; when no reference signal is input, the internal 100MHz crystal oscillator operates.

[0069] Furthermore, the 100MHz signal is split into three paths by a power divider:

[0070] a. One path serves as the reference signal for the 8.5GHz phase-locked loop. The signal obtained from the phase-locked loop is divided into three paths by a power divider. These paths are then attenuated by attenuators and amplified by amplifiers, and used as the local oscillator (LO) for the up-conversion and down-conversion units at 8.5GHz.

[0071] b. One path is divided by a frequency divider, filtered and amplified to serve as a 10MHz clock signal;

[0072] c. One channel is divided into four channels by a power divider, and each channel is amplified and filtered to serve as a 100MHz clock signal.

[0073] This design uses a 200MHz–15GHz low-noise frequency synthesizer as the phase-locked source. Component datasheet is attached. Figure 7 As shown;

[0074] The calibration switch unit enables equal amplitude and phase connection between the ANT1 and ANT2 ports and the calibration output port;

[0075] See appendix Figure 8 In the calibration switch unit, ensure that the phase difference φ1 between ANT1 and the calibration port and the phase difference φ2 between ANT2 and the calibration port satisfy |φ1-φ2|≤±3°;

[0076] The principle design of the calibration switch is attached. Figure 8 As shown, the design of the ANT1 to calibration output circuit is exactly the same as that of the ANT2 to calibration output circuit, and the cable connection length is also the same to ensure that the ANT1 and ANT2 to calibration output channels have equal amplitude and equal phase functions.

[0077] The control module controls the gain or attenuation via RS422 serial port and controls the pulse modulation switch via TTL differential port;

[0078] See appendix Figure 9 The pulse modulation switch control interface of the control module includes:

[0079] Receive switch control terminal;

[0080] Transmit channel 1 switch control terminal;

[0081] Transmission Channel 2 switch control terminal;

[0082] The external module communicates with the control module via an RS422 serial port to control the amplitude of the frequency converter and the calibration between the transceiver and receiver. The pulse modulation level directly controls the modulation switch in the link;

[0083] The power module converts AC220V to DC+12V and DC-5V for power supply.

[0084] The principle of the power module is shown in the attached figure. Figure 10As shown, the chassis is powered by AC220V and outputs DC+12V and DC-5V voltages through the internal power module. The DC+12V directly powers the active devices, or the DC+5V voltage is regulated by a voltage regulator to power the active devices. Power control is controlled by RS422 serial port, and the transmit / receive channel pulse modulation switch control is controlled by differential port (TTL 5V level).

[0085] See appendix Figure 11 The integrated transceiver is housed in a 2U-19 inch chassis, and the power module has a built-in AC220V filter.

[0086] The interface definition of the X-band RF integrated transceiver is shown in Table 1 below:

[0087]

[0088]

[0089] Table 1 above lists the interfaces of the X-band RF integrated transceiver.

[0090] This integrated transceiver connects to the transceiver channel via a circulator to achieve full-duplex transmission and reception, and simplex transmission and reception when the jumper is disconnected.

[0091] The beneficial effects of this X-band RF integrated transceiver are as follows:

[0092] It features one receiving channel with downconversion and power adjustment from 9.6±0.3GHz to 1.1±0.3GHz, input filtering, and input limiter functions; and two transmitting channels with upconversion and power adjustment from 1.1±0.3GHz to 9.6±0.3GHz, with an instantaneous bandwidth of 600MHz and a non-invertable spectrum. The receiving and transmitting upconversion channels 1 and 2 are connected to a shared port via an external jumper, enabling full-duplex transmission and reception. Disconnecting the external jumper enables simplex transmission and reception. The transmitting and receiving channels share a local oscillator and feature adaptive internal and external reference functions. It allows selection and switching between 10MHz and 100MHz external reference clocks and provides closed-loop calibration for transmitting and receiving channel switching. The phase difference between each channel's output port and the calibration output port is within ±3°. The receiving and transmitting channels have switch control and selection functions, and it features module current detection, internal and external reference detection, and reports via serial port query.

[0093] The following are the numerical values ​​of the technical specifications for a specific embodiment:

[0094] The technical specifications for this downconverter are as follows:

[0095] Number of RF input channels: 1;

[0096] Down-conversion RF input frequency: 9.6±0.3GHz;

[0097] Number of intermediate frequency output channels: 1;

[0098] Down-conversion intermediate frequency output frequency: 1.1±0.3GHz;

[0099] Down-conversion RF input burn-out protection power (continuous wave): ≤2W;

[0100] Downconversion RF input power range: -50 to +10 dBm

[0101] Down-conversion gain control range: -10 to +50 dB;

[0102] Down-conversion attenuation step: 0.25dB;

[0103] Attenuation accuracy: ±0.5dB;

[0104] In-band group delay ripple: ≤6ns;

[0105] Down-conversion RF input noise figure: ≤8dB;

[0106] Down-conversion intermediate frequency output P-1: ≤+10dBm;

[0107] Down-conversion intermediate frequency output power: 0±1dBm;

[0108] Instantaneous band flatness: ≤2dB;

[0109] Downconversion intermediate frequency output spurious signals: ≤-55dBc; (Pout=0dBm);

[0110] Downconverter intermediate frequency output harmonics: ≤-55dBc; (Pout=0dBm);

[0111] Isolation from the upconverter channel: ≥70dB;

[0112] Pulse modulation switch response time: ≤1µs;

[0113] Power stability: ≤1.5dB (within the operating temperature range);

[0114] ≤0.3dB (tested for 2 hours at room temperature after reaching temperature equilibrium);

[0115] Phase stability: 3° (tested for 2 hours after reaching temperature equilibrium at room temperature).

[0116] The technical specifications of the up-conversion unit are as follows:

[0117] Number of intermediate frequency input channels: 2;

[0118] Intermediate frequency input range: 1.1±0.3GHz;

[0119] Intermediate frequency input power: -14±1dBm;

[0120] Intermediate frequency input filter suppression: ≥40dBc@1.6~3GHz;

[0121] Number of RF output channels: 2;

[0122] Up-conversion transmission frequency range: 9.6±0.3GHz;

[0123] Up-conversion RF transmit power: -60~0dBm;

[0124] Output P-1: ≥13dBm;

[0125] Up-conversion RF output step: 0.25dB;

[0126] Attenuation accuracy: ±0.5dB;

[0127] Harmonic suppression: ≤-55dBc (0dBm for RF output);

[0128] In-band group delay ripple: ≤6ns;

[0129] Transmit / receive isolation: ≥70dB;

[0130] Inter-channel isolation: ≥70dB

[0131] Instantaneous band flatness: ≤2dB;

[0132] Phase noise: ≤-80dBc / Hz@100Hz, -100dBc / Hz@1KHz, -110dBc / Hz@10KHz; Emit noise floor: ≤-125dBm / Hz@Pout=-60dBm;

[0133] Pulse modulation switch response time: ≤1µs;

[0134] Power stability: ≤1.5dB (within the operating temperature range);

[0135] ≤0.3dB (tested for 2 hours at room temperature after reaching temperature equilibrium);

[0136] Phase stability: ≤3° (tested for 2 hours after reaching temperature equilibrium at room temperature);

[0137] Amplitude consistency between transmission channels: ≤1dB;

[0138] Phase consistency between transmission channels: ≤10°; (cannot span cycles)

[0139] Phase difference φ1 between ANT1 and calibration port and phase difference φ2 between ANT2 and calibration port: |φ1-φ2|≤±3°; Phase difference stability between transmission channels:≤3° (tested for 4 hours after power-on for half an hour);

[0140] Amplitude difference stability between transmission channels: ≤0.5dB (tested for 4 hours after power-on for half an hour);

[0141] Inter-channel delay: ≤100ps;

[0142] Frequency generation accuracy: better than ±10kHz.

[0143] The technical specifications of this clock module are as follows:

[0144] A: Synchronous clock input:

[0145] External reference input frequencies: 100MHz and 10MHz (one of each, not operating simultaneously);

[0146] External reference input power: 3±5dBm;

[0147] B: Synchronous clock output:

[0148] Output 100M clock; Number of output channels: 4;

[0149] Output 100MHz clock accuracy: ±0.1ppm;

[0150] 100MHz clock output stability in seconds: ≤2E-11 (free operation, no external reference); 100MHz clock output power: 7~10dBm;

[0151] Output phase noise: ≤-155dBc@1kHz; 100MHz clock output

[0152] Output spurious signal at 100MHz clock speed: ≤-65dBc;

[0153] Output 100MHz clock with harmonics ≤-50dBc;

[0154] Output 10MHz clock; Number of output channels: 1;

[0155] Output clock accuracy: ±0.1ppm (10MHz);

[0156] Output 10MHz clock; Output power: 7–10dBm;

[0157] Output phase noise: ≤-145dBc@1kHz; 10MHz clock output

[0158] Output spurious signal at 10MHz clock speed: ≤-65dBc;

[0159] Output 10MHz clock with harmonics ≤-50dBc;

[0160] The antenna technical specifications are as follows:

[0161] Antenna polarization: linear polarization;

[0162] Quantity: 2;

[0163] Antenna gain: ≥2dBi;

[0164] Antenna frequency: X (9.6GHz);

[0165] Antenna bandwidth: ≥600MHz.

[0166] The above description is merely a preferred embodiment of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention. Structures, devices, and operating methods not specifically described or explained in this invention are implemented according to conventional methods in the art unless otherwise specified or limited.

Claims

1. An integrated transceiver for X-band programmable applications, characterized in that, include: The downconversion unit is used to downconvert a 9.6±0.3GHz radio frequency signal to a 1.1±0.3GHz intermediate frequency signal; The upconversion unit is used to upconvert the 1.1±0.3GHz intermediate frequency signal to a 9.6±0.3GHz radio frequency signal; The clock and frequency synthesizer unit provides an 8.5GHz local oscillator signal to the downconverter and upconverter units, and supports adaptive switching of 10MHz / 100MHz external reference clock; The calibration switch unit enables equal amplitude and phase connection between the ANT1 and ANT2 ports and the calibration output port; The control module controls the gain or attenuation via RS422 serial port and controls the pulse modulation switch via TTL differential port; The power module converts AC220V to DC+12V and DC-5V for power supply.

2. The integrated transceiver according to claim 1, characterized in that: The downconverter unit is connected in sequence to a limiter, a switch, a switched filter bank, a bandpass filter, a mixer, an intermediate frequency amplifier, a digitally controlled attenuator, and a low-pass filter.

3. The integrated transceiver according to claim 1, characterized in that: The upconversion unit includes two channels, each channel being connected in sequence to a temperature-compensated attenuator, an intermediate frequency amplifier, a digitally controlled attenuator, a mixer, a bandpass filter, two stages of digitally controlled attenuators, and an output switch.

4. The integrated transceiver according to claim 1, characterized in that: The clock and frequency synthesizer unit includes: The external reference detection module determines the presence status of 10MHz and 100MHz external reference signals; The phase-locked loop module generates an 8.5GHz local oscillator signal with a 100MHz signal as a reference. The frequency divider module divides a 100MHz signal into a 10MHz clock signal. The power divider module outputs four 100MHz clock channels.

5. The integrated transceiver according to claim 1, characterized in that: In the calibration switch unit, the phase difference φ1 between ANT1 and the calibration port and the phase difference φ2 between ANT2 and the calibration port are ensured to satisfy |φ1-φ2|≤±3°.

6. The integrated transceiver according to claim 1, characterized in that: The pulse modulation switch control interface of the control module includes: Receive switch control terminal; Transmit channel 1 switch control terminal; Transmission Channel 2 switch control terminal.

7. The integrated transceiver according to claim 1, characterized in that: This integrated transceiver connects to the transceiver channel via a circulator to achieve full-duplex transmission and reception, and simplex transmission and reception when the jumper is disconnected.

8. The integrated transceiver according to claim 1, characterized in that: The integrated transceiver is housed in a 2U-19 inch chassis, and the power module has a built-in AC220V filter.

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