Improved e1 link ptp time serving device

Abstract

The application relates to an improved E1 link PTP timing device. The device selects a PSoC processor, a CPU at the PS end of the processor runs a PTP protocol, an AXI 1G / 2.5G Ethernet Subsystem IP core responsible for processing MAC of the Ethernet is used in the BD, a PTP message transceiving processing module communicates with a GMII interface and a GMII interface of the IP core; an E1 transceiving processing module completes HDB3 encoding and decoding and mutual conversion between serial data and parallel data, and full-time slot transmission of Ethernet data of the PTP message on the E1 link. The logic resource of PL is used in the PSoC processor to optimize the hardware design of the E1 link PTP timing, and the processor transceives the PTP message without using a physical Ethernet interface, so that the influence of transceiving delay uncertainty of the PHY chip on the timing accuracy is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of precise timing, in particular to an improved E1 link PTP timing device. BACKGROUND

[0002] In the field of time and frequency timing, there are many timing methods, such as Beidou satellite timing, direct current B (DC), optical fiber B code, NTP network, long wave, short wave timing, etc. Any timing method needs to consider the timing accuracy index, and the higher the timing accuracy, the better the application prospect. E1 link PTP (Precision Time Protocol) timing is also a common timing method, which is an E1 link carrying PTP service data and complying with IEEE 1588 V2 protocol. Timing accuracy is an important index of E1 link PTP timing, and the requirement of timing accuracy is also constantly improving. Currently, the E1 link PTP timing index is usually better than ≤10us in the early stage to currently usually better than ≤1us.

[0003] The current E1 link PTP timing method is shown in Figure 1 At present, the hardware mainly adopts IEEE 1588v2 scheme based on ARM processor and protocol converter, and the protocol function is simple to implement, but the E1 link PTP timing accuracy is limited by the hardware implementation scheme, and the timing accuracy is difficult to improve. The hardware design has limitations in improving the timing accuracy.

[0004] The software mainly runs 1588v2 software on the protocol stack or operating system, adopts the existing E1 protocol converter principle, and when sending PTP message data packet, the ARM processor sends the PTP message data packet to the protocol converter through the Ethernet interface. The protocol converter realizes the conversion of the PTP message data packet from the Ethernet packet to the E1 link. When receiving the PTP message data packet, the protocol converter receives the PTP message data packet from the E1 link and then converts it into an Ethernet data packet to send to the ARM processor. The ARM processor receives the PTP message data packet and performs corresponding software processing and time synchronization calculation. The local clock adopts a common 65.536MHz crystal oscillator, which is divided by the FPGA of the protocol converter to provide a 2.048MHz frequency for the E1 transceiver control module. The local clock is also used for PTP message timestamp correction or generating the required timestamp of the PTP message, and the local clock is adjusted and aligned by the external time reference 1PPS signal.

[0005] The PTP timing of the E1 link adopts a mature protocol converter for bidirectional conversion of E1 interface and Ethernet interface data, uses the mature PTP network timing technology of the ARM processor, and can realize the PTP timing of the E1 link through the Ethernet interface connection of the ARM processor and the Ethernet interface of the protocol converter. However, the transmission rate of the E1 line is only 2.048 Mbit / s, and is fixed rate transmission, while the transmission rate of the Ethernet port is 1000 / 100 / 10 Mbit / s, and the data transmission of the Ethernet interface has intermittence and burstiness. When the PTP Ethernet data packet is transmitted through the E1 link, the data transmission rate is not matched, which will cause the time slot to be random when the PTP data packet is transmitted through the E1 link, and the time interval of the time slot is 3.91us. According to the PTP protocol principle, the time slot randomness is equivalent to the network delay with uncertainty, and the delay jitter through the protocol converter is in the microsecond level, which will seriously affect the timing accuracy of the PTP, far exceeding the technical index that the PTP timing accuracy of the E1 link is better than ≤1us. According to the PTP protocol principle, the closer the PTP message timestamp is to the hardware bottom layer, the higher the PTP timing accuracy will be. The current conventional E1 link PTP timing timestamp position is in the MAC layer of the ARM processor or the physical layer of the PHY chip, or in the application layer, and there is no timestamp in the E1 link transceiver hardware bottom layer, which affects the E1 link PTP timing accuracy.

[0006] The current conventional E1 link PTP timing device generally uses a quartz crystal 65.536M as a frequency source to provide a timing function of the signal. The frequency of the crystal oscillator is greatly affected by aging and temperature change, and the timing will produce a large error, which also affects the timing accuracy.

[0007] The conventional E1 master timing device adopts the method of giving the 1PPS time reference to the local clock. The method of synchronizing the time reference of the E1 master timing device is to update the nanosecond count value of the local time according to the clock frequency on the rising edge of the 1PPS time reference. First, the adjustment accuracy of the local time is limited by the clock frequency, and second, the 1PPS time reference also has jitter. By constantly adjusting the count value to align the 1PPS time reference every second, the adjustment accuracy of the local clock is not high enough or jitter is generated, which also affects the E1 timing accuracy. This synchronization method used in the E1 slave timing device also affects the timing accuracy, and the timing accuracy test of the E1 master-slave timing device is not direct enough.

[0008] The conventional E1 time service device is connected with an E1 protocol converter through Ethernet, and both the time service device and the protocol converter use a PHY chip. The PHY chip is applied in both the E1 time service device and the E1 protocol converter, and the delay uncertainty of one PHY chip will bring an influence of 20-70 nanoseconds. There are totally four PHY chips on the link of the E1 master time service device and the E1 slave time service device, and from the nanosecond level time service precision, the multiple PHY chips in the hardware circuit of the E1 time service will greatly influence the time service precision.

[0009] On the basis of the protocol converter technology, when the PTP data packet is converted and sent from the Ethernet to the E1 link, firstly, the Ethernet PTP packet needs to be identified and analyzed, the sending delay t1 of the PTP event message for calculating the link delay in the protocol converter is measured, then the time stamp T1 is adjusted to (T1+t1) according to the time stamp carried by the event message in the delay request response mechanism. This technology can only eliminate the influence of the protocol converter on the time service precision, and cannot improve the PTP time service precision of the E1 link. The ARM processor runs the PTP protocol, and even if the IEEE 1588v2 is implemented by marking the time stamp at the physical layer, the time stamp recording is very accurate, but the two PHY chips are connected through the Ethernet, and the delay jitter between the two PHY chips cannot be eliminated, and the chip has an influence of several tens of nanoseconds on the time service precision. When the PTP data packet is forwarded and received from the E1 link to the Ethernet, the time delay t2 of the received E1 data packet to the Ethernet forwarding needs to be measured, and the time stamp of the PTP event message needs to be adjusted to (T2-t2). The E1 link PTP time service adopts the protocol converter technology, and the measurement and correction of the delay in the protocol converter have improved and enhanced the time service precision in the microsecond level, but for the nanosecond level time service precision, the master device and the slave device are connected through two protocol converter hardware, the hardware delay jitter in the protocol converter, and the measurement precision and error in the protocol converter are all not conducive to the improvement of the time service precision. From the nanosecond level time service precision, the improvement of the E1 link PTP time service precision is the main problem to be solved in the present application. SUMMARY

[0010] Therefore, it is necessary to provide an improved E1 link PTP time service device in view of the above technical problems.

[0011] An improved E1 link PTP time service device, comprising a PSoC processor, a clock driving module and an E1 interface module.

[0012] The PL end of the PSoC processor is configured to measure a time difference between a 1PPS time reference and a PTP 1588 clock to obtain a time difference measurement result, to take a reference clock multiplied by a PLL as a reference of the PTP 1588 clock, to establish the PTP 1588 clock according to the reference of the PTP 1588 clock and the 1PPS time reference, to receive and transmit Ethernet data of a PTP protocol message by using an AXI 1G / 2.5G Ethernet Subsystem IP core, and to convert Ethernet data of the PTP protocol message and E1 link data to each other by using a PTP packet transceiving module and an E1 encoding and decoding processing module, and to re-time stamp and record a time stamp of a transceived PTP message in the E1 encoding and decoding processing module according to the PTP 1588 clock.

[0013] The ARM processor at the PS end of the PSoC processor is configured to run a PTP protocol, to receive PTP protocol data by using an AXI 1G / 2.5G Ethernet Subsystem IP core of a MAC of Ethernet, and to communicate with the PL end by using an AXI4_Lite bus, and a DDR3 memory controller at the PS end of the PSoC processor is configured to receive and store a TOD input and transmit the TOD input to the ARM processor.

[0014] The clock driving module is configured to drive and output the PTP 1588 clock.

[0015] The E1 interface module is configured to receive and transmit E1 link data.

[0016] In one of the embodiments, the apparatus further comprises an external PLL frequency multiplication module, a constant temperature crystal oscillator, a level conversion module, and a DAC module.

[0017] The ARM processor at the PS end of the PSoC processor is connected with the DAC module, the DAC module is connected with a voltage control end of the constant temperature crystal oscillator, an output end of the constant temperature crystal oscillator is connected with the level conversion module, and the level conversion module is connected with the external PLL frequency multiplication module.

[0018] The PLL frequency multiplication module is configured to provide a working clock for the PL end of the PSoC processor and to provide a reference clock.

[0019] In one of the embodiments, the PL end of the PSoC processor comprises a 1PPS time difference measurement IP core, an internal PLL frequency multiplication IP core, a PTP 1588 clock IP core with an AXI4_Lite bus interface, and a protocol conversion IP core.

[0020] 1PPS time difference measurement IP core, used for time difference measurement on 1PPS time reference and PTP1588 clock, obtaining time difference measurement result, and transmitting the time difference measurement result to the ARM processor of the PS end through the AXI4_Lite bus.

[0021] Internal PLL frequency multiplication IP core, used for PLL frequency multiplication on the output of the external PLL frequency multiplication module as the reference of the PTP1588 clock, and transmitting the reference of the PTP1588 clock to the PTP1588 clock IP core.

[0022] PTP1588 clock IP core, used for establishing the PTP1588 clock according to the reference of the PTP1588 clock and the 1PPS time reference.

[0023] Protocol conversion IP core, used for communicating with the AXI 1G / 2.5G Ethernet Subsystem IP core through the GMII interface, receiving and transmitting the data of the E1 link through the E1 interface, and converting the PTP protocol data packet between the MAC and the E1 protocol, encapsulating the Ethernet data of the PTP message into the preset format of the serial interface data when transmitting the Ethernet data, and realizing the full-time slot transmission of the Ethernet data of the PTP message on the E1 link.

[0024] The ARM processor of the PS end of the PSoC processor is further used for adjusting and compensating the PTP1588 clock IP core.

[0025] In one embodiment, the specific steps of the ARM processor of the PS end of the PSoC processor for adjusting and compensating the PTP1588 clock IP core include:

[0026] In the initial stage of the power-on of the device, the ARM processor of the PS end of the PSoC processor directly adjusts and modifies the second field of the PTP1588 clock IP core through the AXI4_Lite bus.

[0027] After the device is stable, the ARM processor of the PS end of the PSoC processor reads the time difference measurement result from the 1PPS time difference measurement IP core through the AXI4_Lite bus, and compensates and adjusts the nanosecond field of the PTP1588 clock IP core through the AXI4_Lite bus according to the time difference measurement result.

[0028] According to the time difference measurement result, the constant temperature crystal oscillator is tamed through the EMIO control DAC module and finally through the PID algorithm, and the compensation of the nanosecond decimal field of the PTP1588 clock IP core is realized.

[0029] In one embodiment, the protocol conversion IP core includes a PTP message transceiving processing module and an E1 encoding and decoding processing module.

[0030] When sending the Ethernet data packet:

[0031] The Ethernet data packet received from the AXI 1G / 2.5G Ethernet Subsystem IP core through the GMII interface is parsed by the PTP message transceiving processing module and the E1 coding and decoding processing module to obtain the data of the HDB3 code, the event message satisfying the PTP protocol type is re-timestamped according to the PTP 1588 clock in the E1 coding and decoding processing module, the CRC32 check is recalculated after the timestamping, and the timestamp is stored in the PTP 1588 clock register; the sending timestamp of the PTP event message is read by the PS end ARM processor of the PSoC processor through the AXI4_Lite bus, and then the data of the HDB3 code is sent to the E1 link through the E1 interface module.

[0032] When receiving the Ethernet data packet:

[0033] The E1 coding and decoding processing module receives the data of the HDB3 code from the E1 interface module, parses the PTP event message, records the receiving time of the event message according to the PTP 1588 clock, and registers the receiving time in the PTP 1588 clock register; the receiving timestamp of the PTP event message is read by the PS end ARM processor through the AXI4_Lite bus, and the parsed Ethernet packet data is sent from the serial data to the parallel data to the PTP message transceiving processing module buffer by the E1 coding and decoding processing module, and then the Ethernet packet data is sent to the AXI 1G / 2.5G Ethernet Subsystem IP core by the PTP message transceiving processing module.

[0034] In one embodiment, the serial interface data of the preset format is: a frame front flag code, an Ethernet frame, and a frame rear flag code.

[0035] The Ethernet frame includes: an HDLC frame header, an Ethernet frame start delimiter, a destination address, a source address, a protocol type, PTP message data, a CRC32 check, and an HDLC frame header.

[0036] The frame front flag code and the frame rear flag code are not allowed to appear inside the frame; and the 0-bit insertion method is adopted.

[0037] In one embodiment, the constant temperature crystal oscillator is a constant temperature crystal oscillator with a frequency stability of 10MHz in the order of E-12.

[0038] In one embodiment, the external PLL frequency multiplication module includes a first PLL frequency multiplication module and a second PLL frequency multiplication module.

[0039] The first PLL frequency multiplication module is used for multiplying the signal output by the constant temperature crystal oscillator into a first frequency signal, and providing a working clock for a protocol conversion IP core.

[0040] The second PLL frequency multiplication module is used for multiplying the signal output by the constant temperature crystal oscillator into a second frequency signal, transmitting the second frequency information to a 1PPS time difference measurement IP core as a working clock, and transmitting the second frequency information to an internal PLL frequency multiplication IP core as a reference clock.

[0041] In one of the embodiments, when the device is a master time device: the 1PPS time reference is the standard time information input from the TOD.

[0042] When the device is a slave time device: the 1PPS time reference is output from the 1PPS of the master time device.

[0043] The improved E1 link PTP time device, by selecting a PSoC processor, the CPU at the PS end of the processor runs the PTP protocol, an AXI 1G / 2.5G Ethernet Subsystem IP core responsible for processing the MAC of the Ethernet is used in the BD, and the PTP message transceiver processing module communicates with the GMII interface of the IP core through the GMII interface; the E1 transceiver processing module completes HDB3 encoding and decoding and mutual conversion between serial data and parallel data, and sends the Ethernet data of the PTP message in the full time slot of the E1 link. The logic resource of the PL inside the PSoC processor optimizes the hardware design of the E1 link PTP time device, and the processor transceiver PTP message does not use a physical Ethernet interface, reducing the influence of the transceiver delay uncertainty of the PHY chip on the time accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 It is a principle block diagram of the existing E1 link PTP time device;

[0045] Figure 2 It is a structure block diagram of the improved E1 link PTP time device in one of the embodiments;

[0046] Figure 3 It is a principle block diagram of the improved E1 link PTP time device in another embodiment;

[0047] Figure 4 It is a PTP 1588 clock generation and use schematic diagram in another embodiment;

[0048] Figure 5 It is a PTP 1588 clock time composition schematic diagram in another embodiment;

[0049] Figure 6 It is an E1 link PTP time accuracy system test system schematic diagram in another embodiment;

[0050] Figure 7 Synchronization accuracy diagram of E1 master time device in another embodiment;

[0051] Figure 8 Timing accuracy diagram of E1 master-slave clock device in another embodiment. DETAILED DESCRIPTION

[0052] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0053] E1 link PTP timing is transmitted through 1588v2 protocol, PTP data packets of Ethernet on E1 link, so that E1 master-slave timing device can realize frequency synchronization and phase synchronization. To improve the E1 link PTP timing accuracy, first of all, the precision of E1 master timing device and time reference synchronization needs to be solved. The E1 master timing device uses PTP timing, and the higher the synchronization accuracy of the E1 master timing device and the time reference is, the higher the timing accuracy will be. Then, the influence of the non-fixed time slot of PTP message on the timing accuracy needs to be solved, and the influence of the nanosecond level delay jitter of the hardware device of the conventional device on the timing accuracy also needs to be solved.

[0054] There are three key points to improve the E1 link PTP timing accuracy. The first point is to count the master-slave time deviation through PTP message protocol, to realize the frequency synchronization between the master and the slave, to establish PTP1588 clock in the FPGA inside the PSoC processor PL end, to improve the synchronization accuracy of PTP1588 clock and 1PPS time reference, and the synchronization accuracy of the master-slave clock within a second. The second point is to solve the influence of the link delay jitter on the timing accuracy caused by the mismatch between the Ethernet data packet of PTP message and the 2M link transmission rate when the IEEE 1588v2 protocol is running in the PS end ARM processor. The third point is to reduce the influence of the timing accuracy caused by the device delay uncertainty.

[0055] In one embodiment, as shown in Figure 2 an improved E1 link PTP timing device is provided, which comprises a PSoC processor 10, a clock driving module 20 and an E1 interface module 30.

[0056] The PL end of the PSoC processor 10 is used for time difference measurement on a 1PPS time reference and a PTP 1588 clock, to obtain a time difference measurement result; is also used for multiplying a reference clock by PLL to serve as a reference of the PTP 1588 clock, and establishing the PTP 1588 clock according to the reference of the PTP 1588 clock and the 1PPS time reference; is also used for receiving and transmitting Ethernet data of a PTP protocol message by using an AXI 1G / 2.5G Ethernet Subsystem IP core, and converting Ethernet data of the PTP protocol message and E1 link data to each other by using a PTP packet transceiving module and an E1 encoding and decoding processing module, and re-timestamping and recording the time stamp of the received and transmitted PTP message in the E1 encoding and decoding processing module according to the PTP 1588 clock.

[0057] Specifically, the PTP 1588 clock established in the PL end of the PSoC processor 10 is used for time stamping the PTP message in the E1 transceiving module, and the time stamping is at the E1 serial data transceiving layer, so as to reduce the influence of device time delay uncertainty and further improve the E1 link PTP time service precision.

[0058] The 1PPS output by the PTP 1588 clock and the 1PPS time reference of the standard time are measured by using the FPGA logic resource of the PSoC processor 10, the TDC measurement result is used to tame the constant temperature crystal oscillator, the synchronization precision of the E1 time service master clock and the time reference is improved, and the E1 link PTP time service precision can be improved by improving the E1 time service master clock synchronization precision and the PTP 1588 clock adjustment precision.

[0059] The ARM processor of the PS end of the PSoC processor 10 is used for running the PTP protocol, receiving PTP protocol data by using the AXI 1G / 2.5G Ethernet Subsystem IP core of the MAC of the Ethernet; is also used for communicating with the PL end through the AXI4_Lite bus, and the DDR3 memory controller of the PS end of the PSoC processor is used for receiving and storing the TOD input and transmitting the TOD input to the ARM processor.

[0060] The clock driving module 20 is used for driving and outputting the PTP 1588 clock.

[0061] The E1 interface module 30 is used for receiving and transmitting E1 link data.

[0062] Specifically, PTP is a protocol for time synchronization over a network, and the implementation of PTP network time service technology by ARM processors is very mature. To improve the PTP time service accuracy of the E1 link, without changing the conditions under which IEEE 1588v2 runs on ARM processors through the lwip protocol stack or the operating system, the hardware needs to be optimized and designed to reduce the impact of the uncertainty of device delay on the time service accuracy. The improvements in the hardware design include: (1) selecting a PSoC processor, running IEEE 1588v2 on the ARM processor of the PS end of the PSoC processor 10, without modifying the 1588v2 software, and receiving and sending PTP protocol packet data through the MAC (Media Access Control) media access control sublayer protocol. (2) calling the AXI 1G / 2.5G Ethernet Subsystem IP core in the Block Design of the PSoC processor 10, which implements the hardware function of the Ethernet MAC, and the physical interface is selected as the GMII interface. (3) fixing the rate of the MAC on the lwip protocol stack or the operating system to 1000Mbit / s, using a 125MHz clock, and the MAC data is an 8bit byte data stream, which facilitates the subsequent parallel-serial conversion of the Ethernet PTP data packet and the E1 link data. (4) designing a GMII interface and an E1 interface protocol conversion function module on the PL end, the GMII interface of the protocol conversion function module is connected with the AXI 1G / 2.5G Ethernet Subsystem IP core, and the E1 interface module is used for the reception and processing of 2M data.

[0063] Compared with using a dedicated ARM processor and an FPGA chip, the PSoC processor 10 can integrate the processing and complete the conversion of the PTP protocol data packet between the MAC and the E1 protocol on the PL end. This hardware design method is very convenient for processing cross-clock domain data transmission. The PTP message reception and processing module receives and sends Ethernet data of the PTP protocol packet through the GMII interface from the AXI 1G / 2.5G Ethernet Subsystem IP core, optimizes the hardware design of the Ethernet interface PHY chip, and reduces the impact of the uncertainty of the PHY chip delay on the time service accuracy.

[0064] In the improved E1 link PTP timing device, the device selects a PSoC processor, a CPU at a PS end of the processor runs a PTP protocol, an AXI 1G / 2.5G Ethernet Subsystem IP core responsible for processing a MAC of Ethernet is used in the BD, a PTP message transceiving processing module communicates with a GMII interface of the IP core through the GMII interface; an E1 transceiving processing module completes HDB3 encoding and decoding and mutual conversion between serial data and parallel data, and sends Ethernet data of the PTP message in full time slots of the E1 link. The PSoC processor uses a logic resource of a PL inside the PSoC processor to optimize hardware design of the E1 link PTP timing, and the processor transceives the PTP message without using a physical Ethernet interface, thereby reducing influence of transceiving delay uncertainty of a PHY chip on timing accuracy.

[0065] In one of the embodiments, as Figure 3 The device further comprises an external PLL frequency multiplication module, a constant temperature crystal oscillator, a level conversion module and a DAC module.

[0066] The PS end ARM processor of the PSoC processor is connected with the DAC module, the DAC module is connected with a voltage control end of the constant temperature crystal oscillator, an output end of the constant temperature crystal oscillator is connected with the level conversion module, and the level conversion module is connected with the external PLL frequency multiplication module.

[0067] The PLL frequency multiplication module is used to provide a working clock for a PL end of the PSoC processor and to provide a reference clock.

[0068] Specifically, the constant temperature crystal oscillator is multiplied to 65.536MHz to provide a stable low-jitter clock for E1 encoding and decoding, and the constant temperature crystal oscillator is multiplied to 125MHz to provide a clock for the PTP message transceiving processing module.

[0069] The constant temperature crystal oscillator with a frequency stability of E-12 provides a frequency reference for the PTP1588 clock through external frequency multiplication and PLL frequency multiplication inside the PSoC processor, a high-stability and high-precision PTP1588 clock is established inside the FPGA, and a high-resolution time stamp is provided for the PTP message.

[0070] The E1 timing master adjusts a master-slave time deviation of the PTP1588 clock through an AXI4-lite bus, the second-in-second deviation is improved by compensating the PTP1588 clock and taming the constant temperature crystal oscillator, and synchronization accuracy of the E1 timing master-slave clock is improved, under the condition that the E1 link transmission is short and delay is symmetrical, a long-time running index can be better than ≤100ns, which is much higher than a requirement of the E1 link PTP timing accuracy in the industry.

[0071] In one of the embodiments, as Figure 3As shown, the PL end of the PSoC processor includes: a 1PPS time difference measurement IP core, an internal PLL frequency multiplication IP core, a PTP1588 clock IP core with an AXI4_Lite bus interface, and a protocol conversion IP core.

[0072] The 1PPS time difference measurement IP core is configured to perform time difference measurement on a 1PPS time reference and a PTP1588 clock, obtain a time difference measurement result, and transmit the time difference measurement result to the ARM processor at the PS end via an AXI4_Lite bus interface.

[0073] The internal PLL frequency multiplication IP core is configured to perform PLL frequency multiplication on an output of an external PLL frequency multiplication module and use the output as a reference of the PTP1588 clock, and transmit the reference of the PTP1588 clock to the PTP1588 clock IP core.

[0074] The PTP1588 clock IP core is configured to establish a PTP1588 clock based on the reference of the PTP1588 clock and the 1PPS time reference.

[0075] The protocol conversion IP core is configured to communicate with the AXI 1G / 2.5G Ethernet Subsystem IP core via a GMII interface, receive and transmit data of an E1 link via an E1 interface, and convert PTP protocol data packets between MAC and E1 protocols, encapsulate Ethernet data of the PTP protocol data packets into serial interface data in a preset format, and implement full-time slot transmission of the Ethernet data of the PTP protocol data packets on the E1 link.

[0076] The ARM processor at the PS end of the PSoC processor is further configured to adjust and compensate the PTP1588 clock IP core.

[0077] Specifically, the high-precision 1PPS time difference measurement at the PL end tames the oven-controlled crystal oscillator, and the short stability of the oven-controlled crystal oscillator is used to establish a high-precision and low-jitter PTP1588 clock. The ARM processor at the PS end directly adjusts and modifies the PTP1588 clock in the second domain via an AXI4_Lite bus, compensates the nanosecond domain for time difference, and uses the tamed oven-controlled crystal oscillator to synchronize the master clock and the slave clock in the nanosecond domain that exceeds the compensation precision. The establishment of the PTP1588 clock at the PL end further improves the synchronization precision and time service precision of the E1 time service device.

[0078] In one embodiment, the specific steps of the ARM processor at the PS end of the PSoC processor for adjusting and compensating the PTP1588 clock IP core include:

[0079] In the initial stage of the device power-on, the ARM processor of the PS end of the PSoC processor directly adjusts and modifies the second domain of the PTP1588 clock IP core through the AXI4_Lite bus.

[0080] After the device works stably, the ARM processor of the PS end of the PSoC processor reads the time difference measurement result from the 1PPS time difference measurement IP core through the AXI4_Lite bus, and compensates and adjusts the nanosecond of the PTP1588 clock IP core according to the time difference measurement result through the AXI4_Lite bus.

[0081] According to the time difference measurement result, the constant temperature crystal oscillator is tamed through the EMIO control DAC module and finally through the PID algorithm, and the compensation of the nanosecond fractional domain of the PTP1588 clock IP core is performed.

[0082] Specifically, to improve the PTP time service precision of the E1 link, a high-precision PTP1588 clock needs to be established for the processing of the PTP message timestamp. The frequency source of the PTP1588 clock needs to consider the frequency stability and the clock jitter, and the PTP1588 clock also needs to solve the synchronization precision with the time reference. If the synchronization precision with the time reference is not accurate enough, it will also affect the time service precision. The generation and use of the PTP1588 clock are as shown in Figure 4 The frequency stability of the constant temperature crystal oscillator is in the order of E-12 10MHz, which is used as the frequency source of the E1 time service device. The 10M output of the constant temperature crystal oscillator is multiplied to 125MHz through the external PLL, and the 125MHz is multiplied to 400MHz through the internal PLL clock IP core in the PL end, which is used as the reference of the PTP1588 clock. The generation and use method of the PTP1588 clock of the E1 master time service device is as follows: (1) the IP core for 1PPS time difference measurement is designed in the PL end through the AXI4_Lite bus interface. The 1PPS time difference measurement adopts the time interval measurement (TDC) method, which is used to measure the second deviation of the 1PPS output by the PTP1588 clock and the 1PPS time reference. (2) the PTP1588 clock IP core is designed in the PL end through the AXI4_Lite bus interface, and the port output is provided to the E1 transceiver processing module, which is used for the PTP message timestamp processing of the E1 transceiver processing module. (3) the PTP1588 clock time adopts 48-bit second domain, 32-bit nanosecond domain and nanosecond fractional domain, as shown in Figure 5 The composition of the PTP1588 clock time is shown in

[0083] In the initial stage of the E1 time service device power-on, the PS end ARM processor converts the standard time information input from the TOD into the total seconds of the coordinated universal time UTC after the rising edge of the 1PPS time reference, and directly adjusts the second field of the PTP1588 clock IP core through the AXI4_Lite bus. After the subsequent E1 time service device works stably, only the value of the second field register read through the AXI4_Lite bus is compared with the standard time, and the value of the IP core second field register is re-adjusted when the second changes. The PS end ARM processor reads the deviation value of the PTP1588 clock and the 1PPS time reference second from the 1PPS time difference measurement IP core through the AXI4_Lite bus, and then compensates and adjusts the nanosecond field of the PTP1588 clock IP core through the AXI4_Lite bus. The frequency reference of the PTP1588 clock is 400MHz, and the nanosecond field compensation and adjustment accuracy is 2.5 nanoseconds. The measurement accuracy of the 1PPS time difference measurement IP core can reach 50 picoseconds, and the nanosecond decimal field adjustment is that the PS end ARM processor controls the DAC module through the EMIO, and finally the constant temperature crystal oscillator is tamed and controlled through the PID algorithm, so that the 1PPS signal output by the PTP1588 clock and the 1PPS time reference signal realize nanosecond-level time synchronization. After the E1 master time service device PTP1588 clock is precisely synchronized with the standard time, the subsequent tame constant temperature crystal oscillator can reduce the direct adjustment of the PTP1588 clock.

[0084] In one of the embodiments, the protocol conversion IP core includes a PTP message transceiving processing module and an E1 encoding and decoding processing module.

[0085] When sending an Ethernet data packet:

[0086] The Ethernet data packet received from the AXI 1G / 2.5G Ethernet Subsystem IP core through the GMII interface is parsed by the PTP message transceiving processing module and the E1 encoding and decoding processing module to obtain the data of the HDB3 code. The PTP event message meeting the PTP protocol type is re-timestamped according to the PTP1588 clock in the E1 encoding and decoding processing module. After the timestamping, the CRC32 check is recalculated, and the timestamp is stored in the PTP1588 clock register. The PS end ARM processor of the PSoC processor reads the sending timestamp of the PTP event message through the AXI4_Lite bus, and then sends the data of the HDB3 code to the E1 link through the E1 interface module.

[0087] When receiving an Ethernet data packet:

[0088] The E1 codec processing module receives HDB3 code data from the E1 interface module. It parses the PTP event message, records the reception time of the event message according to the PTP1588 clock, and stores the reception time in the PTP1588 clock register. The PS-side ARM processor reads the reception timestamp of the PTP event message via the AXI4_Lite bus. The E1 codec processing module restores the parsed Ethernet packet data from serial data to parallel data and sends it to the PTP message transceiver processing module's buffer. Then, the PTP message transceiver processing module sends the Ethernet packet data to the AXI 1G / 2.5G Ethernet Subsystem IP core.

[0089] In one embodiment, the serial interface data in the preset format is: a pre-frame flag, an Ethernet frame, and a post-frame flag.

[0090] An Ethernet frame includes: an HDLC frame header, an Ethernet frame start delimiter, a destination address, a source address, a protocol type, PTP message data, a CRC32 checksum, and an HDLC frame header.

[0091] Pre-frame and post-frame flags are not allowed to appear within a frame; they are implemented using 0-bit insertion.

[0092] Specifically, IEEE 1588v2 runs on the lwip protocol stack or operating system at the PS end. Without modifying the software operating mechanism, it requires the conversion between Ethernet frame format data and the E1 protocol. During protocol conversion, the data transmission rate of the Ethernet frame format does not match the E1 link rate. This rate mismatch will cause link latency jitter. A one-slot deviation on the link will result in a 3.91µs delay. Uncertainty: A clock jitter of 2.048MHz produces 488 nanoseconds. Jitter is addressed by the PTP protocol through calculation of link latency. Uncertainty and jitter exist, which greatly affect the accuracy of time synchronization. When PTP message data is encapsulated into Ethernet packets for transmission and reception on the E1 link, in order to reduce the impact of link delay jitter caused by the random transmission time slots of PTP messages on the E1 link and to make the most of the effective bandwidth of E1, PTP messages are transmitted in all time slots of E1. The data transmission format of the E1 link is shown in Table 1.

[0093] Table 1 E1 Link Transmission Data Format

[0094]

[0095] The PTP message data on the lwip protocol stack or operating system of the PS end is processed in the Ethernet frame format, and when the Ethernet data is sent from the AXI 1G / 2.5G Ethernet Subsystem IP core, the Ethernet data sent by the IP core is converted into serial interface data meeting the E1 communication through the PTP packet transceiving module and the E1 coding and decoding processing module. The serial data meets the high-level data link control (HDLC) protocol, and each frame has a flag code 0x7E at the front and the rear, which is used for indicating the start and termination of the frame and synchronizing the frame. The flag code is not allowed to appear in the frame to avoid ambiguity. In order to ensure the uniqueness of the flag code and take into account the transparency of the data in the frame, the 0-bit insertion method can be used to solve the problem. The 0-bit insertion method is simple in principle and is very suitable for hardware implementation. When the Ethernet data packet is sent, the PTP packet transceiving module analyzes the Ethernet packet, re-timestamps the event message meeting the PTP protocol type according to the PTP 1588 clock, recalculates the CRC32 check after the timestamping, and stores the timestamp in the PTP 1588 clock register. The PS end ARM processor can read the sending timestamp of the PTP event message through the AXI4_Lite bus, and then send the HDB3 code data to the E1 link through the E1 interface circuit. When the Ethernet data packet is received, the E1 coding and decoding processing module receives the HDB3 code data from the E1 interface circuit, analyzes the PTP event message, records the receiving time of the event message according to the PTP 1588 clock, stores the receiving time in the PTP 1588 clock register, and the PS end ARM processor can read the receiving timestamp of the PTP event message through the AXI4_Lite bus. The E1 coding and decoding processing module sends the analyzed Ethernet packet data from the serial data to the parallel data to the PTP message transceiving processing module buffer, and then sends the Ethernet packet data to the AXI 1G / 2.5G Ethernet Subsystem IP core. By sending the Ethernet data of the PTP message in the full time slot of the E1 link, the coding and decoding of the E1 link re-timestamps and records the timestamp of the transceived PTP message according to the PTP 1588 clock, which solves the influence of the fixed and jittered transmission link delay of the PTP protocol layer to the HDB3 code transceiving position, and further improves the PTP timing precision of the E1 link.

[0096] In one of the embodiments, the constant temperature crystal oscillator is a constant temperature crystal oscillator with a frequency stability of 10MHz at the order of E-12.

[0097] In one of the embodiments, the external PLL frequency multiplication module includes a first PLL frequency multiplication module and a second PLL frequency multiplication module.

[0098] The first PLL frequency multiplier module is used to multiply the signal output from the temperature-controlled crystal oscillator to a first frequency signal, providing a working clock for the protocol conversion IP core.

[0099] The second PLL frequency multiplier module is used to multiply the signal output by the temperature-controlled crystal oscillator to a second frequency signal, and transmit the second frequency information to the 1PPS time difference measurement IP core as a working clock. It also transmits the second frequency information to the internal PLL frequency multiplier IP core as a reference clock.

[0100] In one embodiment, when the device is the main time synchronization device: the 1PPS time base is standard time information input from the TOD.

[0101] When the device is a slave timekeeping device: the 1PPS time reference is output from the master timekeeping device.

[0102] Specifically, the E1 slave clock generation and usage method of the PTP1588 timing device is similar to that of the master timing device, except that the TOD input is converted into the master-slave time deviation value counted through the PTP protocol. The second and nanosecond domains of the PTP1588 clock IP core can be directly adjusted via the AXI4_Lite bus. For the part exceeding the nanosecond domain compensation accuracy, a PID algorithm is used to discipline the temperature-controlled crystal oscillator to achieve nanosecond-level time synchronization.

[0103] In a verification embodiment, a test system is constructed to test and verify the E1 link PTP timing accuracy. The constructed E1 link PTP timing accuracy test system is as follows: Figure 6 As shown, the 1PPS clock output of the PTP1588 of the E1 timing device is output externally through the BNC interface, which is very convenient for testing the timing accuracy and synchronization accuracy.

[0104] (1) The pulse distribution amplifier distributes and amplifies the 1PPS time base to 16 outputs. The channel consistency of the pulse distribution amplifier output is better than ≤30ps. One of them is used as the external reference 1PPS input of the 16-channel time interval counter, and the other is used as the 1PPS time base input of the master clock.

[0105] (2) The E1 timing master clock device acquires the standard time through the TOD input, and then the software adjusts the local time of the PTP1588 clock according to the standard time. Using the 1PPS time reference output by the distribution amplifier, the software adjusts the synchronization accuracy between the 1PPS output of the PTP1588 clock and the 1PPS time reference. The phase difference between the 1PPS output of the PTP1588 clock of the E1 timing master clock device and the 1PPS time reference of the standard time is as follows: Figure 7As shown, the phase difference test result (standard deviation: 6.23 ns) is the synchronization accuracy of the E1 time service master clock device and the 1PPS time reference of the standard time.

[0106] (3) The 16-channel time interval counter has a measurement accuracy of ≤50 ps, a channel consistency of ≤50 ps, a measurement resolution of 1 ps, and an external reference 10 MHz input used as the frequency source input of the counter to improve the measurement accuracy. The 1PPS of the PTP1588 clock output of the E1 time service master clock device can be observed and measured through the 16-channel time interval counter. The phase difference between the 1PPS of the PTP1588 clock output of the E1 time service master clock device and the 1PPS time reference of the standard time is tested, and the phase difference test result is the synchronization accuracy of the E1 time service master clock device and the 1PPS time reference of the standard time. The synchronization accuracy of the E1 master time service device is as shown in Figure 7 Meanwhile, the 1PPS of the PTP1588 clock output of the E1 time service slave clock device is connected to the counter, and the phase difference of the 1PPS of the PTP1588 clock output of the E1 time service master-slave clock device can be observed and measured through the counter. The phase difference test result (standard deviation: 45.23 ns) is the time synchronization accuracy of the E1 time service master-slave clock device, and the time service accuracy of the E1 master-slave clock device is as shown in Figure 8 .

[0107] (4) The SyncEdge time-frequency synchronization analyzer is used to test whether the time of the master-slave clock is synchronized, and can determine whether the E1 link PTP time service is working normally.

[0108] By modifying the configuration of the E1 time service device to the E2E mode delay mechanism and the Ethernet message encapsulation mode, the one-step method is used to measure the master-slave time service accuracy of the E1 time service device, as shown in Figure 8 The time service accuracy is within 260 nanoseconds. Further tests verify that the PTP time service of the E1 link of the device is stable and reliable, and the master-slave time service accuracy test is convenient

[0109] The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the description.

[0110] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the protection scope of the present application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the protection scope of the present application.

Claims

1. An improved E1 link PTP timing device, characterized in that, The device includes: a PSoC processor, a clock drive module, and an E1 interface module; The PL terminal of the PSoC processor is used to measure the time difference between the 1PPS time base and the PTP1588 clock, and obtain the time difference measurement result; it is also used to multiply the reference clock by a PLL and use it as the reference for the PTP1588 clock, and establish the PTP1588 clock based on the PTP1588 clock reference and the 1PPS time base; it is also used to send and receive Ethernet data of PTP protocol messages using the AXI 1G / 2.5G EthernetSubsystem IP core, and to convert the Ethernet data and E1 link data of the PTP protocol messages to each other using the PTP packet transceiver module and the E1 codec processing module. In the E1 codec processing module, the received and transmitted PTP messages are re-timestamped according to the PTP1588 clock and the timestamp is recorded. The ARM processor on the PS side of the PSoC processor is used to run the PTP protocol and process the AXI 1G / 2.5G Ethernet Subsystem IP core of Ethernet MAC to receive PTP protocol data; it is also used to communicate with the PL side through the AXI4_Lite bus; the DDR3 memory controller on the PS side of the PSoC processor is used to receive and store TOD inputs and transmit the TOD inputs to the ARM processor. The clock driving module is used to drive the PTP1588 clock output. The E1 interface module is used to send and receive E1 link data; The PSoC processor's PL side includes: a 1PPS time difference measurement IP core, an internal PLL frequency multiplier IP core, a PTP1588 clock IP core with an AXI4_Lite bus interface, and a protocol conversion IP core; The 1PPS time difference measurement IP core is used to measure the time difference between the 1PPS time base and the PTP1588 clock, obtain the time difference measurement result, and transmit the time difference measurement result to the ARM processor at the PS end through the AXI4_Lite bus; The internal PLL multiplier IP core is used to multiply the output of the external PLL multiplier module by PLL and use it as a reference for the PTP1588 clock, and to transmit the PTP1588 clock reference to the PTP1588 clock IP core. The PTP1588 clock IP core is used to establish the PTP1588 clock based on the PTP1588 clock reference and the 1PPS time base. The protocol conversion IP core is used to communicate with the AXI 1G / 2.5G Ethernet Subsystem IP core through the GMII interface, and to send and receive data on the E1 link through the E1 interface; it is also used to convert PTP protocol data packets between MAC and E1 protocol, and when sending Ethernet data, it encapsulates the PTP protocol data packets into serial interface data of a preset format, so as to realize the full-time slot transmission of Ethernet data of PTP messages on the E1 link; The ARM processor on the PS side of the PSoC processor is also used to adjust and compensate the PTP1588 clock IP core.

2. The apparatus according to claim 1, characterized in that, The external PLL frequency multiplier module, the temperature-controlled crystal oscillator, the level conversion module, and the DAC module; The PS-side ARM processor of the PSoC processor is connected to the DAC module, the DAC module is connected to the voltage-controlled terminal of the thermostatic crystal oscillator, the output terminal of the thermostatic crystal oscillator is connected to the level conversion module, and the level conversion module is connected to the external PLL frequency multiplier module. The PLL frequency multiplier module is used to provide a working clock to the PL terminal of the PSoC processor, and also to provide the reference clock.

3. The apparatus according to claim 2, characterized in that, The specific steps by which the ARM processor on the PS side of the PSoC processor adjusts and compensates the PTP1588 clock IP core include: During the initial power-on phase of the device, the ARM processor on the PS side of the PSoC processor directly adjusts and modifies the second domain of the PTP1588 clock IP core via the AXI4_Lite bus. After the device is working stably, the ARM processor on the PS side of the PSoC processor reads the time difference measurement result from the 1PPS time difference measurement IP core through the AXI4_Lite bus, and adjusts the nanosecond of the PTP1588 clock IP core according to the time difference measurement result through the AXI4_Lite bus. Based on the time difference measurement results, the DAC module is controlled by the EMO, and finally the temperature-controlled crystal oscillator is tamed by the PID algorithm to compensate the nanosecond fractional domain of the PTP1588 clock IP core.

4. The apparatus according to claim 1, characterized in that, The protocol conversion IP core includes: a PTP packet transceiver processing module and an E1 encoding / decoding processing module; When sending Ethernet packets: The PTP message transceiver processing module and the E1 codec processing module parse the Ethernet data packets received from the AXI 1G / 2.5G Ethernet Subsystem IP core through the GMII interface to obtain HDB3 code data. In the E1 codec processing module, event messages that meet the PTP protocol type are re-timestamped according to the PTP1588 clock. After the timestamp is applied, the CRC32 check is recalculated, and the timestamp is stored in the PTP1588 clock register. The PS-side ARM processor of the PSoC processor reads the transmission timestamp of the PTP event message through the AXI4_Lite bus, and then sends the HDB3 code data to the E1 link through the E1 interface module. When receiving Ethernet packets: The E1 codec processing module receives HDB3 code data from the E1 interface module. It parses the PTP event message, records the reception time of the event message according to the PTP1588 clock, and stores the reception time in the PTP1588 clock register. The PS-side ARM processor reads the reception timestamp of the PTP event message via the AXI4_Lite bus. The E1 codec processing module restores the parsed Ethernet packet data from serial data to parallel data and sends it to the PTP message transceiver processing module's buffer. Then, the PTP message transceiver processing module sends the Ethernet packet data to the AXI 1G / 2.5G Ethernet Subsystem IP core.

5. The apparatus according to claim 1, characterized in that, The serial interface data in the preset format consists of: a pre-frame flag, an Ethernet frame, and a post-frame flag. The Ethernet frame includes: HDLC frame header, Ethernet frame start delimiter, destination address, source address, protocol type, PTP message data, CRC32 checksum, and HDLC frame header; The pre-frame flag and post-frame flag are not allowed to appear within the frame; they are implemented using a 0-bit insertion method.

6. The apparatus according to claim 2, characterized in that, The temperature-controlled crystal oscillator is a 10MHz temperature-controlled crystal oscillator with a frequency stability on the order of E-12.

7. The apparatus according to claim 1, characterized in that, The external PLL frequency multiplier module includes a first PLL frequency multiplier module and a second PLL frequency multiplier module; The first PLL frequency multiplier module is used to multiply the signal output by the temperature-controlled crystal oscillator to a first frequency signal, providing a working clock for the protocol conversion IP core; The second PLL frequency multiplier module is used to multiply the signal output by the isothermal crystal oscillator to a second frequency signal, and transmit the second frequency signal to the 1PPS time difference measurement IP core as a working clock, and also transmit the second frequency signal to the internal PLL frequency multiplier IP core as a reference clock.

8. The apparatus according to claim 1, characterized in that, When the device is the main time synchronization device: the 1PPS time reference is standard time information input from the TOD; When the device is a slave timekeeping device: the 1PPS time reference is output from the master timekeeping device.

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