Communication module and operating method thereof

Abstract

A communication module and an operating method thereof are provided, the communication module including: processing circuitry configured to control a transmission path of first data and first reliability data according to whether a plurality of input signals input in chronological order are retransmitted, the first data being generated based on phase difference data between the plurality of input signals, and the first reliability data being generated based on phase difference data between the plurality of input signals; the first reliability data corresponds to the first data; detecting an error in the first data block based on the first data and the first reliability data; performing a combination operation on the first data, the first reliability data, the storage data, and the storage reliability data to generate combined data and combined reliability data, the storage reliability data corresponding to the storage data, and the combined reliability data corresponding to the combined data; and performing a first error correction operation based on the combined data and the combined reliability data.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0061241, filed on May 9, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to communication modules and their operation methods. Background Technology

[0003] Packets in wireless communications (such as Bluetooth) may include data (such as cyclic redundancy check (CRC) codes) for error detection in the packet to detect data errors, and the receiving device uses the CRC codes to correct data errors in the packet.

[0004] In addition, the efficiency of packet reception in wireless communication is being improved by utilizing Hybrid Automatic Repeat Request (HARQ) technology, which requests packet retransmission when the receiving device cannot correct errors. Summary of the Invention

[0005] The embodiment provides a communication module and its operation method, wherein packet reception success rate is improved by performing error correction and error detection on retransmitted packets in a variety of ways.

[0006] The embodiment provides a communication module and its operating method, which improves packet reception success rate by effectively configuring components of HARQ technology.

[0007] Embodiments of this disclosure provide a communication module, the module including a processing circuit system configured to: control the transmission path of first data and first reliability data based on whether a plurality of input signals are retransmitted, the first data being generated based on phase difference data between the plurality of input signals input in chronological order, and the first reliability data corresponding to the first data; detect errors in a first data block based on the first data and the first reliability data; perform a combination operation on the first data, the first reliability data, stored data, and stored reliability data to generate combined data and combined reliability data, the stored reliability data corresponding to the stored data, and the combined reliability data corresponding to the combined data; and perform a first error correction operation based on the combined data and the combined reliability data.

[0008] An embodiment provides a communication module including a processing circuit system configured to: generate bit data and bit reliability data based on phase difference data between a plurality of input signals input in time sequence, wherein the bit reliability data corresponds to the bit data; control the transmission path of the bit data and bit reliability data according to whether the plurality of input signals are retransmitted; detect errors in a first data block based on the bit data and bit reliability data; perform a combination operation on the bit data and stored bit data to generate combined bit data, wherein the stored bit data corresponds to the bit data; perform a combination operation on the bit reliability data and stored bit reliability data to generate combined bit reliability data, wherein the stored bit reliability data corresponds to the bit reliability data; and perform an error correction operation based on the combined bit data and combined bit reliability data.

[0009] An embodiment provides an operation method for a communication module, the operation method comprising: generating first data and first reliability data based on phase difference data between a plurality of input signals input in time sequence, the first reliability data corresponding to the first data; detecting errors in a first data block based on the first data and the first reliability data in response to determining that the plurality of input signals are retransmitted; performing a combination operation on the first data, the first reliability data, stored data, and stored reliability data to generate combined data and combined reliability data in response to determining that the plurality of input signals are retransmitted, the stored reliability data corresponding to the stored data, and the combined reliability data corresponding to the combined data; performing an error correction operation based on the combined data and the combined reliability data to generate a combined data block; detecting errors in the combined data block; and requesting a retransmission based on whether at least one of error detection of the combined data block and error detection of the first data block is successful.

[0010] An embodiment provides an application processor, the application processor comprising: a system bus; a processor electrically connected to the system bus and including at least one processing core; and a communication module configured to receive phase difference data, perform error correction operations based on the phase difference data to generate data, and provide the data to the processor, wherein the communication module includes a processing circuit system configured to: control the transmission path of first data and first reliability data based on whether the phase difference data is retransmitted, the first data being generated based on the phase difference data and the first reliability data corresponding to the first data; detect errors in a first data block based on the first data and the first reliability data; combine the first data and stored data corresponding to the first data to generate combined data; combine the first reliability data and stored reliability data corresponding to the first reliability data to generate combined reliability data; and perform error correction operations based on the combined data and the combined reliability data. Attached Figure Description

[0011] Figure 1A block diagram of a communication system according to an embodiment is shown.

[0012] Figure 2 A block diagram of a demodulator module according to an embodiment is shown.

[0013] Figure 3 A block diagram of an error correction module according to an embodiment is shown.

[0014] Figure 4 A phase domain error correction unit according to an embodiment is shown.

[0015] Figure 5 A block diagram of an error correction module according to an embodiment is shown.

[0016] Figure 6 A flowchart illustrating the operation method of the demodulator module according to an embodiment is shown.

[0017] Figures 7 to 12 This is a diagram illustrating the operation method of the demodulator module according to an embodiment.

[0018] Figure 13 A block diagram of an error correction module according to an embodiment is shown.

[0019] Figure 14 A block diagram of a Cartesian domain error correction unit according to an embodiment is shown.

[0020] Figure 15 A block diagram of an error correction module according to an embodiment is shown.

[0021] Figure 16 A flowchart illustrating the operation method of the demodulator module according to an embodiment is shown.

[0022] Figure 17 This is a diagram illustrating the operation method of the demodulator module according to an embodiment.

[0023] Figure 18 This is a diagram used to describe a wireless communication device according to an embodiment.

[0024] Figure 19 This is a diagram used to describe a wireless communication device according to an embodiment. Detailed Implementation

[0025] In the following description, the present disclosure will be given more fully with reference to the accompanying drawings, in which embodiments of the disclosure are illustrated. As those skilled in the art will recognize, the embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure.

[0026] For the sake of clarity in describing this disclosure, parts or portions not related to the description are omitted, and identical or similar constituent elements are indicated by the same reference numerals (or similar reference numerals) throughout the specification.

[0027] Furthermore, unless explicitly stated otherwise, the words “including” and their variations shall be understood to imply inclusion of the stated elements but not exclusion of any other elements.

[0028] Those skilled in the art will further understand that if there is an intent to describe a particular number in the claims, such an intent will be explicitly stated in the claims, and without such a statement, such an intent does not exist. For example, to aid understanding, the appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce the claim statement. However, even when the same claim includes the introductory phrases “one or more” or “at least one” along with indefinite articles (such as “a” and / or “a”), the use of such phrases should not be construed as implying that introducing the claim statement by the indefinite articles (“a” and / or “a”) limits any particular claim containing such an introduced claim statement to an example of containing only one such statement (e.g., “a” and / or “a” should be interpreted as meaning “at least one” or “one or more”); the same applies to the use of definite articles used to introduce the claim statement.

[0029] Furthermore, in cases where conventions such as "at least one of A, B, or C" are used, such a structure is generally intended for those skilled in the art to understand the meaning of the convention (e.g., "a system having at least one of A, B, or C" will include, but is not limited to, systems having only A, only B, only C, A and B together, A and C together, B and C together, and / or systems having A, B, and C together). Those skilled in the art will further understand that any transitional words and / or phrases that actually present two or more alternative terms (whether in the specification, claims, or drawings) should be understood to consider the possibility of including one, any, or both of the terms. For example, the phrase "A or B" will be understood to include the possibility of "A" or "B" or "A and B".

[0030] In the disclosed embodiments, the terms "module," "unit," and / or "component" are terms used to denote an element that performs at least one function or operation, and may be implemented as hardware or a combination of hardware and software.

[0031] Figure 1 A block diagram of a communication system according to an embodiment is shown.

[0032] Reference Figure 1 The communication system 1 may include a first communication device 10 and a second communication device 20 that communicate wirelessly through a channel.

[0033] Communication system 1 can be any system used for wireless communication. In an embodiment, as a non-limiting example, communication system 1 can be a wireless communication system (such as a 5G system, a Long Term Evolution (LTE) system, Bluetooth, WiFi, etc.). According to an embodiment, communication system 1 can be a wired communication system (such as a storage system, a network system, etc.). Hereinafter, communication system 1 will be described with reference to wireless communication systems, but the technical concepts of this disclosure are not limited to the disclosed examples.

[0034] For example, the first communication device 10 may be a base station or a component included in a base station. A base station may refer to a fixed station that communicates with a terminal and / or other base stations, and may communicate with the terminal and / or other base stations to send / receive data and / or control information. A base station may be referred to as a Node B, Evolved Node B, Base Transceiver System (BTS), Access Point (AP), Relay Node, Remote Radio Header (RRH), Radio Unit (RU), Small Cell, etc.

[0035] For example, the second communication device 20 may be a terminal or a component included in a terminal. A terminal is a wireless communication device and can refer to various devices capable of sending and receiving data and / or control information by communicating with the first communication device 10. For example, a terminal may be referred to as a user equipment, mobile station (MS), mobile terminal (MT), user terminal (UT), subscription station (SS), wireless device, handheld device, etc. According to an embodiment, the first communication device 10 may be a terminal or a component included in a terminal, and the second communication device 20 may be a base station or a component included in a base station.

[0036] According to an embodiment, both the first communication device 10 and the second communication device 20 may be terminals or components included in terminals.

[0037] The wireless communication network between the first communication device 10 and the second communication device 20 can support multiple users to communicate by sharing available network resources. For example, in the wireless communication network, information can be transmitted in various ways, such as Code Division Multiple Access (CDMA), Frequency Division Multiple Access (FDMA), Time Division Multiple Access (TDMA), Orthogonal Frequency Division Multiple Access (OFDMA), Single Carrier Division Multiple Access (SC-FDMA), etc.

[0038] The first communication device 10 and the second communication device 20 can communicate with each other via uplink (UL) and downlink (DL). In wireless systems (such as LTE systems and LTE-advanced systems), the uplink and downlink can transmit control information via control channels (such as Physical Downlink Control Channel (PDCCH), Physical Control Format Indication Channel (PCFICH), Physical Hybrid Automatic Repeat Request (ARQ) Indication Channel (PHICH), Physical Uplink Control Channel (PUCCH), and Enhanced Physical Downlink Control Channel (EPDCCH)), and can transmit data via data channels (such as Physical Downlink Shared Channel (PDSCH) and Physical Uplink Shared Channel (PUSCH)). Furthermore, enhanced PDCCH or extended PDCCH can be used to transmit control information.

[0039] According to an embodiment, each of the first communication device 10 and the second communication device 20 may be a user equipment device and may transmit and receive information via communication methods such as Bluetooth and Near Field Communication (NFC). Each of the communication devices 10 and 20 may include a Bluetooth module for using Bluetooth and / or an NFC module for using NFC. The first communication device 10 may generate a radio frequency (RF) signal IN_R corresponding to the generated information and transmit the RF signal IN_R to an external location (e.g., outside the communication device 10) via at least one antenna. The second communication device 20 may receive the RF signal IN_R via at least one antenna and may provide the information corresponding to the RF signal IN_R to a processor included in the second communication device 20.

[0040] The first communication device 10 may include a modulator module 11, a transceiver 12, and / or an antenna. In embodiments, the modulator module 11 and the transceiver 12 may include, but are not limited to, some components of a Bluetooth module for using Bluetooth.

[0041] Modulator module 11 can convert digital data into analog signals. For example, when modulator module 11 uses differential phase shift keying (DPSK) to modulate digital data into an analog signal, modulator module 11 can generate an analog signal with a phase difference corresponding to the digital data.

[0042] Transceiver 12 can perform frequency-to-time conversion on transmitted signals or time-to-frequency conversion on received signals. In this embodiment, transceiver 12 can perform a frequency up-conversion operation to generate an RF signal IN_R. The first communication device 10 can transmit the RF signal IN_R via a transmitting antenna. In this embodiment, the frequency range of the RF signal IN_R can be between 2.3 GHz and 2.5 GHz, but the technical concept of this disclosure is not limited to the above frequency examples.

[0043] The second communication device 20 may include a demodulator module 21, a transceiver 22, and / or an antenna. The second communication device 20 may receive the RF signal IN_R via the receiving antenna. In embodiments, the demodulator module 21 and the transceiver 22 may include, but are not limited to, some components of a Bluetooth module for using Bluetooth.

[0044] The transceiver 22 of the second communication device 20 can obtain a signal of the frequency to be read by performing time-frequency conversion on the received RF signal IN_R. In an embodiment, the transceiver 22 may include an analog down-conversion mixer and can generate a baseband signal by down-converting the frequency of the received signal (or data signal).

[0045] In this embodiment, demodulator module 21 may receive the baseband signal obtained by transceiver 22 as input signal IN_P, and generate digital data based on input signal IN_P. For example, when demodulator module 21 demodulates digital data from an analog signal using differential phase shift keying (DPSK), the digital data may be generated based on the phase difference between analog signals received sequentially in time.

[0046] In this embodiment, demodulator module 21 may perform soft decision-making operations based on the phase difference during demodulation to generate digital data and corresponding reliability data. Demodulator module 21 may then perform error correction operations based on the reliability data.

[0047] In the embodiment, with Figure 1 The differences shown include that some components in the demodulator module 21 can be set up separately and included in the transceiver 22.

[0048] According to an embodiment, the first communication device 10 and the second communication device 20 can send and receive data in packets, thereby sending and receiving data blocks comprising multiple bits of data. According to an embodiment, the second communication device 20 can use HARQ technology to correct errors that occur in a corresponding data block during demodulation, or request a retransmission if correction is not feasible.

[0049] To show Figure 1The second communication device 20 can receive the RF signal IN_R from the first communication device 10, perform error correction on the data block on the RF signal IN_R, and when the error detection of the data block is not detected or error correction is performed without error, the second communication device 20 can provide the first communication device 10 with a positive acknowledgment ACK indicating successful packet transmission. When the error of the data block regarding the RF signal IN_R may not be corrected, the second communication device 20 can request retransmission by providing the first communication device 10 with a negative acknowledgment NACK including (e.g., indicating) packet transmission failure.

[0050] According to an embodiment, demodulator module 21 can detect errors in data blocks within retransmitted packets in parallel, perform a combination operation (or merging operation) with previously received packets, and then perform error correction to detect errors in the resulting data blocks. According to an embodiment, demodulator module 21 can perform error correction and error detection in parallel on retransmitted packets to improve the success rate of packet transmission reception.

[0051] Figure 2 A block diagram of a demodulator module according to an embodiment is shown.

[0052] Reference Figure 1 and Figure 2 The demodulator module 21 may include a phase difference calculation module 21_1 and an error correction module 21_2. According to an embodiment, the phase difference calculation module 21_1 and the error correction module 21_2 may be separated and disposed in different modules or different chips. For example, the phase difference calculation module 21_1 may be disposed in the transceiver 22, and the error correction module 21_2 may be disposed as a functional block in the application processor (AP). The error correction module 21_2 can perform demodulation operations by receiving phase difference data PD and an initial input selection signal INI_SEL output by the phase difference calculation module 21_1 disposed outside the application processor. According to an embodiment, each of the phase difference calculation module 21_1 and the error correction module 21_2 may be implemented as an independent communication module in the second communication device 20.

[0053] However, the technical concept of this disclosure is not limited to the above arrangement example, and in the embodiments, the phase difference calculation module 21_1 and the error correction module 21_2 may be disposed on a chip, or may be installed together in a package / module.

[0054] According to an embodiment, the phase difference calculation module 21_1 can receive an input signal IN_P as a baseband signal of the RF signal IN_R, calculate the phase difference for the input signal IN_P (e.g., to generate phase difference data PD), and generate an initial input selection signal INI_SEL for the phase difference data PD and the input signal IN_P. According to an embodiment, the input signal IN_P can be in the form of a packet in which "multiple signals are continuously input in a sequence in chronological order", and can include multiple symbol information (e.g., multiple symbol information).

[0055] According to an embodiment, the phase difference data PD may be information corresponding to the phase difference between consecutive input signals IN_P, and may include a symbol information (e.g., one of multiple symbol information). According to an embodiment, when the demodulator module 21 operates according to Bluetooth Enhanced Data Rate (EDR) 2 mode, the phase difference data PD may include one of four different types of symbol information. According to an embodiment, when the demodulator module 21 operates according to Bluetooth EDR3 mode, the phase difference data PD may include one of eight different types of symbol information.

[0056] According to an embodiment, the initial input selection signal INI_SEL may include (e.g., an indication) whether the input signal IN_P is retransmitted based on a negative acknowledgment (NACK) (e.g., whether the input signal IN_P indicates a retransmission based on a negative acknowledgment). The error correction module 21_2 may check whether the input signal IN_P for the phase difference data PD is retransmitted based on the initial input selection signal INI_SEL. According to an embodiment, the initial input selection signal INI_SEL may be included in the header of the packet for the input signal IN_P.

[0057] For example, when the initial input selection signal INI_SEL is logic high "1", the input signal IN_P can be a signal based on the packet of the initial input, and when the initial input selection signal INI_SEL is logic low "0", the input signal IN_P can be a signal based on the packet retransmitted based on the negative acknowledgment (NACK).

[0058] The error correction module 21_2 can receive phase difference data PD and an initial input selection signal INI_SEL, perform a soft decision operation based on the phase difference data PD, and perform an error correction operation based on the reliability data generated by the soft decision operation. According to an embodiment, the error correction module 21_2 can generate a data block DB for the input signal IN_P and error decision data DE for the input signal IN_P based on the error correction operation.

[0059] According to an embodiment, the error decision data DE may include (for example, an indication) whether to perform error correction on the data block DB, and the second communication device 20 may request a retransmission by providing a negative acknowledgment (NACK) to the first communication device 10 based on the error decision data DE.

[0060] Figure 3 A block diagram of an error correction module according to an embodiment is shown. Figure 4 A phase domain error correction unit according to an embodiment is shown. Figure 3 The error correction module 21_2a is Figure 2 Example of error correction module 21_2 (e.g., Figure 3 The error correction module 21_2a can be used to implement Figure 2 Error correction module 21_2).

[0061] Reference Figures 2 to 4 The error correction module 21_2a may include a symbol-by-symbol soft decision generator 210, a first phase domain error correction unit 211a, a second phase domain error correction unit 211b, a first error detector 212a, a second error detector 212b, a bit-by-bit soft decision generator 213, a memory 214, a combination unit 215, a bit-to-symbol soft decision converter 216, and / or a demultiplexer DMX.

[0062] The symbol-by-symbol soft decision generator 210 can perform soft decision operations based on phase difference data PD, thereby generating symbol data SYM in units of symbol and symbol reliability data SR for symbol data SYM.

[0063] According to an embodiment, the demodulator module 21 can receive the input signal IN_P in packets, and the symbol-by-symbol soft decision generator 210 can receive multiple phase difference data PDs received sequentially (e.g., multiple sequentially received phase difference data PDs). The symbol-by-symbol soft decision generator 210 can continuously generate multiple symbol data SYMs (e.g., multiple symbol data SYMs) and symbol reliability data SRs (e.g., multiple symbol reliability data SRs) based on the multiple phase difference data PDs. According to an embodiment, each symbol data SYM can be associated with a corresponding symbol reliability data SR.

[0064] According to an embodiment, when demodulator module 21 performs demodulation using the Quad Differential Phase Shift Keying (QDPSK) method, the symbol data SYM may include one of four different types of symbols, and a symbol data SYM (e.g., a symbol data SYM) may have a data size of two bits. According to an embodiment, when demodulator module 21 operates according to Bluetooth EDR2 mode, demodulator module 21 may use the QDPSK method to perform demodulation.

[0065] According to an embodiment, when demodulator module 21 performs demodulation using the 8-Differential Phase Shift Keying (8DPSK) method, the symbol data SYM may include one of eight different types of symbols, and a symbol data SYM (e.g., a symbol data SYM) may have a data size of 3 bits. According to an embodiment, when demodulator module 21 operates according to Bluetooth EDR3 mode, demodulator module 21 may use the 8DPSK method to perform demodulation.

[0066] Symbol reliability data (SR) is data that indicates the reliability value of a symbol to be included in the corresponding symbol data (SYM), and the symbol reliability data (SR) can be determined based on the phase difference of the phase difference data (PD). The symbol reliability data (SR) can be data with a predetermined (or optionally, given) number of bits.

[0067] According to an embodiment, as the reliability value increases, the probability of errors occurring in symbols included in the symbol data SYM can decrease, and as the reliability value decreases, the probability of errors occurring in symbols included in the symbol data SYM can increase.

[0068] Please refer to later Figure 7 and Figure 8 A detailed operational description of the symbol-by-symbol soft decision generator 210.

[0069] The demultiplexer DMX can operate as a data distributor to receive symbol data SYM, symbol reliability data SR, and initial input selection signal INI_SEL, and control the transmission path of symbol data SYM and symbol reliability data SR based on the initial input selection signal INI_SEL.

[0070] The demultiplexer (DMX) checks, based on the initial input selection signal INI_SEL, whether the input signal IN_P corresponding to the symbol data SYM is a packet received via a retransmission request. The DMX then selects the transmission path for the symbol data SYM and the symbol reliability data SR based on whether the corresponding input signal IN_P has been retransmitted.

[0071] For example, when the initial input selection signal INI_SEL is logic high "1", the demultiplexer DMX can check the input signal IN_P corresponding to the symbol data SYM and symbol reliability data SR as the signal of the packet based on the first input, and provide the symbol data SYM and symbol reliability data SR as the first symbol data (or initial symbol data) SYMi and the first symbol reliability data (or initial symbol reliability data) SRi to the first phase domain error correction unit 211a.

[0072] For example, when the initial input selection signal INI_SEL is logic low "0", the demultiplexer DMX can check the input signal IN_P corresponding to the symbol data SYM and symbol reliability data SR as a signal based on the retransmission packet, and provide the symbol data SYM and symbol reliability data SR as retransmission symbol data SYMre and retransmission symbol reliability data SRre to the bit-by-bit soft decision generator 213 and the second phase domain error correction unit 211b.

[0073] The first phase domain error correction unit 211a can receive first symbol data SYMi and first symbol reliability data SRi, or combined symbol data SYMcb and combined symbol reliability data SRcb, which will be described later, to perform error correction operations and output a first data block (or initial data block) DBi or a combined data block DBcb.

[0074] like Figure 4 As shown, the first phase domain error correction unit 211a may include a weakest symbol search unit 2111, a weakest bit processing unit 2112, multiple error detectors 2113a to 2113e, a multi-hash generator 2114 and / or a data block generator 2115.

[0075] According to an embodiment, the weakest symbol search unit 2111 may receive multiple initial symbol data SYMi (e.g., multiple initial symbol data SYMi) and multiple initial symbol reliability data SRi (e.g., multiple initial symbol reliability data SRi). The weakest symbol search unit 2111 may generate a data block DBpre and weakest symbol information WSdata before processing based on the multiple initial symbol data SYMi and the multiple initial symbol reliability data SRi.

[0076] According to an embodiment, the data block DBpre prior to processing may be a data block in which the initial symbol data SYMi, which are sequentially input to the first phase domain error correction unit 211a, are continuously concatenated. According to an embodiment, the data block DBpre prior to processing may include a CRC code. According to an embodiment, the weakest symbol information WSdata may include data arrangement information regarding the weakest initial symbol data in the data block DBpre prior to processing.

[0077] The weakest symbol search unit 2111 can select a predetermined (or optionally, given) number of weak initial symbol data (or weak symbol data) from multiple initial symbol reliability data SRi based on multiple initial symbol reliability data SRi. The weak initial symbol data can represent the symbol data corresponding to the reliability data with the smaller reliability value among the multiple initial symbol reliability data SRi.

[0078] The weakest bit processing unit 2112 can select a weak bit from the selected weak symbol data in the data block DBpre before processing based on the weakest symbol information WSdata, and can generate a data block by flipping a bit from the data block DBpre before processing.

[0079] Reference Figure 4 The weakest bit processing unit 2112 can select weak bits one by one from five weak symbol data (e.g., five weak symbol data lines and / or five weak symbol data bits) based on the weakest symbol information WSdata. The weakest bit processing unit 2112 can flip one of the different bits among the five selected weak bits to generate the a-th to e-th processed data blocks DBa through DBe. According to an embodiment, each of the a-th to e-th processed data blocks DBe can be a data block whose bits are flipped based on the data block DBpre before processing. In an embodiment, the a-th to e-th processed data blocks DBa through DBe can be different data blocks (e.g., they can correspond to different blocks within the data block DBpre before processing).

[0080] exist Figure 4 In this paper, the number of weak symbol data to be selected and the number of weak bits based on the weak symbol data are shown as 5, but the technical concept of this disclosure is not limited to this, and the number of weak symbol data to be selected and the number of weak bits may vary in the embodiments.

[0081] Multiple error detectors 2113a to 2113e can each receive the a-th processed data block DBa to the e-th processed data block DBe, and perform error detection on the data blocks to generate the a-th hash HASHa to the e-th hash HASHe as the result of the error detection on the a-th processed data block DBa to the e-th processed data block DBe. The generated a-th hash HASHa to the e-th hash HASHe can be provided to the multi-hash generator 2114.

[0082] According to an embodiment, the a-th hash HASHa to the e-th hash HASHe may have a predetermined (or optionally, given) number of bits, and the a-th hash HASHa to the e-th hash HASHe may each include the result of error detection regarding the a-th processed data block DBa to the e-th processed data block DBe.

[0083] According to an embodiment, the plurality of error detectors 2113a to 2113e are cyclic redundancy check (CRC) detectors, and can perform error detection operations on data based on divisor data for a predetermined (or optionally, given) CRC to generate hashes HASHa to HASHe. According to an embodiment, hashes HASHa to HASHe can be remainder values ​​generated by performing division operations on processed data blocks DBa to DBe with predetermined (or optionally, given) divisor data.

[0084] For example, when the a-th processed data block DBa passes an error detection operation (e.g., successfully) via the a-th error detector 2113a, all bits in the a-th hash HASHa based on the a-th processed data block DBa can be logical low "0". In the following text, the error detection operation can represent an error in a data block where the error detection target was not detected.

[0085] For example, when an error is detected in the a-processed data block DBa by the a-error detector 2113a, the a-hash HASHa based on the a-processed data block DBa may include a "1" as a logical high.

[0086] According to an embodiment, the multi-hash generator 2114 can generate multiple multi-hashes MHASH1 to MHASH31 by (e.g., individually) outputting each of the a-th hash HASHa to the e-th hash HASHe itself or by performing an XOR operation on at least a portion of the a-th hash HASHa to the e-th hash HASHe.

[0087] According to an embodiment, the plurality of multi-hashes MHASH1 to MHASH31 may include the result of error detection of a data block generated by flipping at least a portion of selected weak bits. For example, when all bits of one of the multi-hashes MHASH1 to MHASH31 are logic low "0", it may indicate that the data block corresponding to that multi-hash passed in the error detection operation.

[0088] The first phase domain error correction unit 211a can perform error detection operations through multiple multi-hash MHASH1 to MHASH31 for all cases where at least a portion of the weak bits selected by the weakest bit processing unit 2112 are flipped.

[0089] The data block generator 2115 can generate the first data block DBi by performing error correction operations on the data block DBpre before processing based on multiple multi-hash MHASH1 to MHASH31.

[0090] For example, when all bits of one of the multiple hashes MHASH1 to MHASH31 are logic low "0", the data block generator 2115 can generate the first data block DBi by performing a bit-flipping operation on the data block DBpre before processing based on that single hash. Furthermore, when all bits of the multiple hashes MHASH1 to MHASH31 include logic high "1", the data block generator 2115 can output the data block DBpre before processing as the initial data block DBi.

[0091] exist Figure 4 In the diagram, the first phase domain error correction unit 211a is only shown performing error correction operations based on the initial symbol data SYMi and the initial symbol reliability data SRi, but it is clear that... Figure 4 The components of the first phase domain error correction unit 211a can also perform error correction operations based on combined symbol data SYMcb and combined symbol reliability data SRcb. According to an embodiment, the first phase domain error correction unit 211a can generate a combined data block DBcb by performing error correction operations based on the combined symbol data SYMcb and the combined symbol reliability data SRcb.

[0092] Return to reference Figure 3 The first error detector 212a can perform error detection operations on the initial data block DBi or the combined data block DBcb to output the initial error decision data DEi or the combined error decision data DEcb.

[0093] According to an embodiment, each of the initial error decision data DEi and the combined error decision data DEcb may have a predetermined (or optionally, given) number of bits. According to an embodiment, the initial error decision data DEi (e.g., each initial error decision data DEi) and the combined error decision data DEcb (e.g., each combined error decision data DEcb) may include the results of error detection operations for the initial data block DBi and the combined data block DBcb.

[0094] According to an embodiment, when an error is detected in the initial data block DBi and the combined data block DBcb by the first error detector 212a, the second communication device 20 can provide a negative acknowledgment (NACK) to the first communication device 10.

[0095] The first error detector 212a can correspond to Figure 4 The error detectors 2113a to 2113e, and the initial error decision data DEi or the combined error decision data DEcb can correspond to Figure 4 The hashes from the a-th to the e-th hash. For better understanding and ease of description, the description of the first error detector 212a is replaced with... Figure 4Description of error detectors 2113a to 2113e.

[0096] The second phase domain error correction unit 211b can receive retransmission symbol data SYMre and retransmission symbol reliability data SRre to perform error correction operations and output retransmission data block DBre.

[0097] The second phase domain error correction unit 211b may correspond to the first phase domain error correction unit 211a, the retransmitted symbol data SYMre may correspond to the initial symbol data SYMi, the retransmitted symbol reliability data SRre may correspond to the initial symbol reliability data SRi, and the retransmitted data block DBre may correspond to the initial data block DBi. For better understanding and ease of description, the description of the second phase domain error correction unit 211b may be replaced with the description of the first phase domain error correction unit 211a (for example, the description of the second phase domain error correction unit 211b may be the same as or similar to the description of the first phase domain error correction unit 211a).

[0098] The second error detector 212b can perform error detection operations on the retransmitted data block DBre to output retransmission error decision data DEre.

[0099] According to an embodiment, the retransmission error decision data DEre may have a predetermined (or optionally, given) number of bits. According to an embodiment, the retransmission error decision data DEre may include the result of an error detection operation on the retransmission data block DBre.

[0100] According to an embodiment, when an error is detected in the retransmitted data block DBre by the second error detector 212b, the second communication device 20 can provide a negative acknowledgment (NACK) to the first communication device 10.

[0101] The second error detector 212b may correspond to the first error detector 212a, and the retransmission error decision data DEre may correspond to the initial error decision data DEi or the combined error decision data DEcb. For better understanding and ease of description, the description of the second error detector 212b may be replaced with the description of the first error detector 212a (e.g., the description of the second error detector 212b may be the same as or similar to the description of the first error detector 212a).

[0102] The bit-by-bit soft decision generator 213 can generate bit-by-bit retransmission bit data BITre and bit-by-bit retransmission reliability data BRre, corresponding to the retransmission symbol reliability data SRre. According to an embodiment, the bit-by-bit retransmission reliability data BRre can be a log-likelihood ratio, but the technical concept of this disclosure is not limited thereto.

[0103] According to an embodiment, when the demodulator module 21 performs demodulation using the QDPSK method, the bit-by-bit soft decision generator 213 can generate two retransmission bit data (BITre) corresponding to different bit numbers based on the retransmission symbol data SYMre, and can generate two retransmission bit reliability data (BRre) corresponding to the two retransmission bit data (BITre) (e.g., two retransmission bit reliability data BRre). One of the two retransmission bit reliability data BRre (e.g., one of the two retransmission bit reliability data BRre) can have a reliability value that is the same as (or similar to) the reliability value of the retransmission symbol reliability data SRre, and the other of the two retransmission bit reliability data BRre can have the largest (or highest) reliability value.

[0104] According to an embodiment, when the demodulator module 21 performs demodulation using the 8DPSK method, the bit-by-bit soft decision generator 213 can generate three retransmission bit data (BITre) corresponding to different bit digits based on the retransmission symbol data SYMre, and can generate three retransmission bit reliability data (BRre) corresponding to the three retransmission bit data (BITre) (e.g., three retransmission bit reliability data BRre). One of the three retransmission bit reliability data BRre (e.g., one of the three retransmission bit reliability data BRre) can have a reliability value that is the same as (or similar to) the reliability value of the retransmission symbol reliability data SRre, and the remaining retransmission bit reliability data BRre can have the largest (or highest) reliability value.

[0105] Please refer to later Figure 9 and Figure 10 A detailed operational description of the bitwise soft decision generator 213.

[0106] The memory 214 can store (for example, in bits) bit data (BITs) and bit reliability data (BRs) for storing the bit data (BITs).

[0107] Memory 214 may include memory elements, and according to embodiments, memory 214 may be non-volatile memory (such as, but not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), NAND flash memory, and NOR flash memory).

[0108] In the accompanying drawings, memory 214 is shown as being included in error correction module 21_2a, but the arrangement does not limit the technical concept of this disclosure. According to an embodiment, memory 214, located outside error correction module 21_2a, can store bit data (BITs) and bit reliability data (BRs), and then provide the bit data (BITs) and bit reliability data (BRs) to error correction module 21_2a via a read command.

[0109] Storage bit data (BITs) and storage bit reliability data (BRs) can be generated based on phase difference data for previously received packets. Storage bit data (BITs) and storage bit reliability data (BRs) can correspond to retransmission bit data (BITre) and retransmission bit reliability data (BRre), respectively.

[0110] According to an embodiment, the combination unit 215 can receive retransmission bit data BITre, retransmission bit reliability data BRre, storage bit data BITs, and storage bit reliability data BRs, and perform a combination operation on the retransmission bit data BITre, retransmission bit reliability data BRre, storage bit data BITs, and storage bit reliability data BRs. The combination unit 215 can perform the combination operation to generate (e.g., in bits) combined bit data BITcb and combined bit reliability data BRcb for combining the bit data BITcb. For example, the combination unit 215 can perform a combination operation on the retransmission bit data BITre and the storage bit data BITs corresponding to the retransmission bit data BITre to generate the combined bit data BITcb, and perform a combination operation on the retransmission bit reliability data BRre and the storage bit reliability data BRs corresponding to the retransmission bit reliability data BRre to generate the combined bit reliability data BRcb.

[0111] According to an embodiment, the combining unit 215 can perform a chase-combining operation. According to an embodiment, the combining unit 215 can change the sign of the reliability values ​​of the retransmitted bit reliability data BRre and the stored bit reliability data BRs based on the retransmitted bit data BITre and the stored bit data BITs, and can reflect the changed sign to add the corresponding reliability values ​​to each other. According to an embodiment, the combining unit 215 can generate combined bit reliability data BRcb by multiplying the added reliability values ​​by a predetermined (or optionally, given) scaling factor.

[0112] According to an embodiment, multiplication operations for predetermined (or optionally, given) scaling factors can be performed in the bit-to-symbol soft decision converter 216, which will be described later. When the bit-to-symbol soft decision converter 216 performs multiplication operations with the predetermined (or optionally, given) scaling factors, the bit-to-symbol soft decision converter 216 can perform multiplication operations on selected combined bit reliability data, which will be described later, to generate combined symbol reliability data.

[0113] For example, when a retransmission bit data BITre is logic low "0", the combination unit 215 can change the reliability value of the corresponding retransmission bit reliability data BRre to a negative value and perform a summation operation. If the summed reliability value is negative, the summed reliability value is changed to a positive value to generate combined bit reliability data BRcb, and the corresponding combined bit data BITcb can be "0" (logic low).

[0114] Later Figure 11 The description describes the specific operation of the combination unit 215.

[0115] The bit-to-symbol soft decision converter 216 can perform conversion operations on combined bit data BITcb and combined bit reliability data BRcb to generate combined symbol data SYMcb in units of symbols and combined symbol reliability data SRcb corresponding to the combined symbol data SYMcb. The bit-to-symbol soft decision converter 216 can provide the generated combined symbol data SYMcb and combined symbol reliability data SRcb to the first phase domain error correction unit 211a.

[0116] For example, when the demodulator module 21 operates according to the Bluetooth EDR2 mode, the combination unit 215 can perform a combination operation on the k-th symbol data (k is an integer equal to or greater than 0), generating the (k_1)th combination bit data and the (k_2)th combination bit data corresponding to different bit numbers, and generating the (k_1)th combination bit reliability data corresponding to the (k_1)th combination bit data and the (k_2)th combination bit reliability data corresponding to the (k_2)th combination bit data. The bit-to-symbol soft decision converter 216 can generate the k-th combination symbol data based on the (k_1)th combination bit data and the (k_2)th combination bit data, and can generate the k-th combination symbol reliability data by selecting the lower reliability value among the (k_1)th combination bit reliability data and the (k_2)th combination bit reliability data. According to an embodiment, the bit-to-symbol soft decision converter 216 can generate the k-th combination symbol reliability data by multiplying the combination bit reliability data selected from the (k_1)-th combination bit reliability data and the (k_2)-th combination bit reliability data with a predetermined (or optionally, given) scaling factor.

[0117] For example, when the demodulator module 21 operates according to Bluetooth EDR3 mode, the combination unit 215 can perform a combination operation on the k-th symbol data (k is an integer equal to or greater than 0), generating the (k_1)th combination bit data, the (k_2)th combination bit data, and the (k_3)th combination bit data corresponding to different bit numbers, and generating the (k_1)th combination bit reliability data, the (k_2)th combination bit reliability data, and the (k_3)th combination bit reliability data corresponding to the (k_1)th combination bit data. The bit-to-symbol soft decision converter 216 can generate the k-th combination symbol data based on the (k_1)th combination bit data, the (k_2)th combination bit data, and the (k_3)th combination bit data, and can generate the k-th combination symbol reliability data by selecting the lower reliability value among the (k_1)th combination bit reliability data to the (k_3)th combination bit reliability data. According to an embodiment, the bit-to-symbol soft decision converter 216 can generate the k-th combination symbol reliability data by multiplying the combination bit reliability data selected from the (k_1)-th combination bit reliability data to the (k_3)-th combination bit reliability data with a predetermined (or optionally, given) scaling factor.

[0118] According to an embodiment, the error correction module 21_2a can perform error detection on the retransmitted data block DBre generated by performing error correction operations on the retransmitted packets in parallel, and can detect errors in the combined data block DBcb generated by performing error correction operations after performing combination operations. According to an embodiment, the error correction module 21_2a can perform error correction and error detection on the retransmitted packets in parallel to improve the success rate of packet transmission reception.

[0119] According to an embodiment, the first phase domain error correction unit 211a can generate an initial data block DBi by performing error correction operations on the first input packet, and can generate a combined data block DBcb by performing error correction operations on the combined symbol data SYMcb and combined symbol reliability data SRcb generated based on retransmitted packets. According to an embodiment, the error correction module 21_2a includes the first phase domain error correction unit 211a, thereby improving the packet transmission reception success rate without adding separate configuration and without area overhead.

[0120] Figure 5 A block diagram of an error correction module according to an embodiment is shown. Figure 5 The error correction module 21_2b is Figure 2 An example of error correction module 21_2. For better understanding and ease of description, the focus will be on... Figure 3 To describe the differences between the error correction module 21_2a and the error correction module 21_2a. Figure 5 Error correction module 21_2b.

[0121] The second error detector 212b can receive retransmitted symbol data SYMre from the demultiplexer DMX without a separate error correction operation.

[0122] According to an embodiment, the second error detector 212b can receive retransmitted symbol data SYMre in the form of retransmitted data blocks DBre' input sequentially in time without performing error correction operations.

[0123] Error correction module 21_2b can detect errors in retransmitted data blocks DBre' in parallel based on retransmitted packets, and can also detect errors in combined data blocks DBcb generated by performing error correction operations after performing combination operations. According to an embodiment, error correction module 21_2b can improve the packet transmission reception success rate by performing error correction and error detection on retransmitted packets in parallel while arranging one phase domain error correction unit (e.g., using only one phase domain error correction unit). Through the arrangement of the phase domain error correction unit as described above, error correction module 21_2b can improve area overhead and increase the packet transmission reception success rate.

[0124] Figure 6 A flowchart illustrating the operation method of the demodulator module according to an embodiment is shown. Figures 7 to 12 This is a diagram illustrating the operation method of a demodulator module according to an embodiment. Specifically, Figure 6 The demodulation operation method for retransmitting packets is shown in the demodulator module 21.

[0125] Reference Figures 2 to 6 The phase difference calculation module 21_1 receives multiple input signals IN_P to generate phase difference data PD between the multiple input signals IN_P (S110).

[0126] The phase difference calculation module 21_1 can generate phase difference data PD by receiving multiple input signals IN_P that are continuously input in a time sequence. The phase difference data PD can be information corresponding to the phase difference between consecutive input signals IN_P.

[0127] The symbol-by-symbol soft decision generator 210 can perform soft decision operations based on phase difference data PD to generate symbol data SYM in units of symbols and symbol reliability data SR as reliability data for symbol data SYM (S120).

[0128] When the demodulator module 21 performs DPSK demodulation, the symbol-by-symbol soft decision generator 210 can perform soft decision operations based on the phase difference data PD.

[0129] Figure 7 An operational example of the symbol-by-symbol soft decision generator 210 in Bluetooth EDR2 mode is shown. See also... Figure 7When operating in Bluetooth EDR2 mode, the symbol-by-symbol soft decision generator 210 can perform soft decisions based on the x-axis and y-axis as decision boundaries. The positive portion of the x-axis can represent a phase difference value of 0, and the negative portion of the x-axis can represent a phase difference value of π. The positive portion of the y-axis can represent a phase difference value of π / 2, and the negative portion of the y-axis can represent a phase difference value of 3π / 2. According to an embodiment, the symbol-by-symbol soft decision generator 210 can determine one of the different first symbols S1 to fourth symbols S4 as symbol data based on the phase difference value of the phase difference data PD.

[0130] For example, when the phase difference value of the phase difference data PD is between the positive portion of the x-axis and the positive portion of the y-axis where the first symbol S1 is located, the symbol data generated based on the phase difference data PD may include information about the first symbol S1.

[0131] According to an embodiment, the symbol-by-symbol soft decision generator 210 can compare the phase difference values ​​of the first symbol S1 to the fourth symbol S4 with the phase difference values ​​of the phase difference data PD to generate symbol reliability data. In the following, reference will be made to... Figure 7 As an example, the first symbol S1 may have a phase difference of π / 4 and may include information "11" of size 2 bits. The second symbol S2 may have a phase difference of 3π / 4 and may include information "01" of size 2 bits. The third symbol S3 may have a phase difference of 5π / 4 and may include information "00" of size 2 bits. The fourth symbol S4 may have a phase difference of 7π / 4 and may include information "10" of size 2 bits.

[0132] According to the embodiment, as the phase difference value of the phase difference data PD approaches the phase difference value of each of the first symbols S1 to the fourth symbols S4, the reliability value of the symbol reliability data can increase, and as the phase difference value of the phase difference data PD approaches the x-axis and y-axis, which serve as decision boundaries, the reliability value of the symbol reliability data can decrease.

[0133] The symbol-by-symbol soft decision generator 210 can perform soft decision operations on the input first phase difference data PD1 and second phase difference data PD2 to generate symbol reliability data SR1 and SR2 for the first symbol data SYM1 and the second symbol data SYM2.

[0134] When the phase difference value of the first phase difference data PD1 is between the positive portion of the x-axis and the negative portion of the y-axis, the symbol-by-symbol soft decision generator 210 can determine the first symbol data SYM1 for the first phase difference data PD1 as the fourth symbol S4. The symbol-by-symbol soft decision generator 210 can generate first symbol reliability data SR1 with an sr1 value based on θ1, where θ1 is a value between the phase difference value of the first phase difference data PD1 and the phase difference value of the fourth symbol S4. According to an embodiment, θ1 can be within -π / 4 to π / 4, and θ1 can have a positive value, and accordingly, according to... Figure 7 For example, sr1 can have a positive value.

[0135] When the phase difference value of the second phase difference data PD2 is between the negative portion of the x-axis and the positive portion of the y-axis, the symbol-by-symbol soft decision generator 210 can determine the second symbol data SYM2 for the second phase difference data PD2 as the second symbol S2. The symbol-by-symbol soft decision generator 210 can generate second symbol reliability data SR2 with an sr2 value based on θ2, where θ2 is a value between the phase difference value of the second phase difference data PD2 and the phase difference value of the second symbol S2. According to an embodiment, θ2 can be within -π / 4 to π / 4, and θ2 can have a negative value, and accordingly, according to... Figure 7 For example, sr2 can have negative values.

[0136] exist Figure 7 In this document, the phase difference values ​​of the first symbol S1 to the fourth symbol S4 and the values ​​of the decision boundary are specified and described as predetermined (or optionally, given) values, but these are examples for the purpose of description, and the technical concept of this disclosure is not limited thereto.

[0137] Figure 8 An operational example of the symbol-by-symbol soft decision generator 210 in Bluetooth EDR3 mode is shown. See also... Figure 8 The symbol-by-symbol soft decision generator 210 can perform soft decisions based on a first decision boundary B1 to an eighth decision boundary B8. According to an embodiment, the first decision boundary B1 can represent a phase difference of π / 8, the second decision boundary B2 can represent a phase difference of 3π / 8, the third decision boundary B3 can represent a phase difference of 5π / 8, the fourth decision boundary B4 can represent a phase difference of 7π / 8, the fifth decision boundary B5 can represent a phase difference of 9π / 8, the sixth decision boundary B6 can represent a phase difference of 11π / 8, the seventh decision boundary B7 can represent a phase difference of 13π / 8, and the eighth decision boundary B8 can represent a phase difference of 15π / 8. According to an embodiment, the symbol-by-symbol soft decision generator 210 can determine one of the different first symbols S1' to eighth symbols S8' as symbol data based on the phase difference value of the phase difference data PD.

[0138] For example, when the phase difference value of the phase difference data PD is between the first decision boundary B1 and the eighth decision boundary B8 of the first symbol S1', the symbol data generated based on the phase difference data PD may include information about the first symbol S1'.

[0139] According to an embodiment, the symbol-by-symbol soft decision generator 210 can compare the phase difference values ​​of the first symbol S1' to the eighth symbol S8' with the phase difference values ​​of the phase difference data PD to generate symbol reliability data. In the following, reference will be made to... Figure 8 As an example, the first symbol S1' may have a phase difference value of 0 and may include information "111" of size 3 bits. The second symbol S2' may have a phase difference value of π / 4 and may include information "110" of size 3 bits. The third symbol S3' may have a phase difference value of π / 2 and may include information "010" of size 3 bits. The fourth symbol S4' may have a phase difference value of 3π / 4 and may include information "011" of size 3 bits. The fifth symbol S5' may have a phase difference value of π and may include information "001" of size 3 bits. According to an embodiment, the sixth symbol S6' may have a phase difference value of 5π / 4 and may include information "000" of size 3 bits. The seventh symbol S7' may have a phase difference value of 3π / 2 and may include information "100" of size 3 bits. The eighth symbol S8' may have a phase difference value of 7π / 4 and may include information "101" of size 3 bits.

[0140] According to the embodiment, as the phase difference value of the phase difference data PD approaches the phase difference value of each of the first symbol S1' to the eighth symbol S8', the reliability value of the symbol reliability data can increase, and as the phase difference value of the phase difference data PD approaches the first decision boundary B1 to the eighth decision boundary B8, which serve as decision boundaries, the reliability value of the symbol reliability data can decrease.

[0141] The symbol-by-symbol soft decision generator 210 can perform soft decision operations on the input third phase difference data PD3 and fourth phase difference data PD4 to generate symbol reliability data SR3 and SR4 for the third symbol data SYM3 and the fourth symbol data SYM4.

[0142] When the phase difference value of the third phase difference data PD3 is between the seventh decision boundary B7 and the eighth decision boundary B8, the symbol-by-symbol soft decision generator 210 can determine the third symbol data SYM3 for the third phase difference data PD3 as the eighth symbol S8'. The symbol-by-symbol soft decision generator 210 can generate third symbol reliability data SR3 with an sr3 value based on θ3, where θ3 is a value between the phase difference value of the third phase difference data PD3 and the phase difference value of the eighth symbol S8'. According to an embodiment, θ3 can be within -π / 8 to π / 8, and θ3 can have a positive value, and accordingly, according to... Figure 8 For example, sr3 can have a positive value.

[0143] The phase difference value of the fourth phase difference data PD4 lies between the fourth decision boundary B4 and the fifth decision boundary B5, enabling the symbol-by-symbol soft decision generator 210 to determine the fourth symbol data SYM4 for the fourth phase difference data PD4 as the fifth symbol S5'. The symbol-by-symbol soft decision generator 210 can generate fourth symbol reliability data SR4 with an sr4 value based on θ4, where θ4 is the value between the phase difference value of the fourth phase difference data PD4 and the phase difference value of the fifth symbol S5'. According to an embodiment, θ4 can be within -π / 8 to π / 8, and θ4 can have negative values, and correspondingly, according to... Figure 8 For example, sr4 can have negative values.

[0144] exist Figure 8 In this document, the phase difference values ​​of the first symbol S1' to the eighth symbol S8' and the values ​​of the first decision boundary B1 to the eighth decision boundary B8 are specified and described as predetermined (or optionally, given) values, but these are examples for the purpose of description, and the technical concept of this disclosure is not limited thereto.

[0145] Return to reference Figure 6 The demultiplexer DMX checks whether the input signal IN_P has been retransmitted based on the initial input selection signal INI_SEL (S130).

[0146] The demultiplexer DMX determines the transmission path for the generated symbol data SYM and symbol reliability data SR by checking whether the input signal IN_P has been retransmitted.

[0147] When the input signal IN_P is based on the initial input packet, the demultiplexer DMX can provide the generated symbol data SYM and symbol reliability data SR as the initial symbol data SYMi and initial symbol reliability data SRi to the first phase domain error correction unit 211a.

[0148] If the input signal IN_P is based on retransmitted packets, the demultiplexer DMX can provide the generated symbol data SYM and symbol reliability data SR in parallel. Figure 3In the error correction module 21_2a, the demultiplexer DMX can provide the generated symbol data SYM and symbol reliability data SR as retransmitted symbol data SYMre and retransmitted symbol reliability data SRre in parallel to the bit-by-bit soft decision generator 213 and the second phase domain error correction unit 211b. Figure 5 In the error correction module 21_2b, the demultiplexer DMX can provide the generated symbol data SYM and symbol reliability data SR as retransmitted symbol data SYMre and retransmitted symbol reliability data SRre in parallel to the bit-by-bit soft decision generator 213 and the second error detector 212b.

[0149] The second error detector 212b detects errors in retransmitted data (e.g., retransmitted data blocks DBre and DBre') (S140). For example, the second error detector 212b may detect errors in retransmitted data blocks DBre and DBre' based on symbol data SYM and symbol reliability data SR.

[0150] exist Figure 3 In the error correction module 21_2a, the retransmission data block DBre input to the second error detector 212b can be a data block generated by the second phase domain error correction unit 211b performing error correction operations based on the retransmission symbol data SYMre and the retransmission symbol reliability data SRre.

[0151] exist Figure 5 In the error correction module 21_2b, the retransmission data block DBre' input to the second error detector 212b can be a data block generated by continuously inputting retransmission symbol data SYMre in chronological order without performing error correction operations.

[0152] The second error detector 212b can receive retransmitted data blocks DBre and DBre', and perform error detection operations to generate retransmission error decision data DEre as the result of error detection on retransmitted data blocks DBre and DBre'.

[0153] According to an embodiment, the retransmission error decision data DEre may have a predetermined (or optionally, given) number of bits, and the retransmission error decision data DEre may include the results of error detection on retransmission data blocks DBre and DBre'.

[0154] According to an embodiment, the second error detector 212b may perform error detection based on divisor data for a predetermined (or optionally, given) CRC to generate retransmission error decision data DEre. According to an embodiment, the retransmission error decision data DEre may be a remainder value generated by performing a division operation on retransmission data blocks DBre and DBre' with predetermined (or optionally, given) divisor data.

[0155] For example, when an error detection operation by the second error detector 212b passes for retransmission data blocks DBre and DBre', all bits in the retransmission error decision data DEre can be logic low "0". Furthermore, when an error is detected in retransmission data blocks DBre and DBre' by the second error detector 212b, the retransmission error decision data DEre can include logic high "1".

[0156] The combination unit 215 receives retransmission bit data BITre, retransmission bit reliability data BRre, storage bit data BITs, and storage bit reliability data BRs, and performs a combination operation on a bit-by-bit basis (S150).

[0157] Before the combination operation of the combination unit 215, the bit-by-bit soft decision generator 213 can generate bit-by-bit retransmission bit data BITre and bit-by-bit reliability data BRre based on the retransmission symbol data SYMre and the retransmission symbol reliability data SRre.

[0158] Figure 9 An operational example of the bitwise soft decision generator 213 in Bluetooth EDR2 mode is shown. See also... Figure 9 When operating in Bluetooth EDR2 mode, the bit-by-bit soft decision generator 213 can perform soft decisions on a bit-by-bit basis based on the phase difference between the first symbol S1 and the fourth symbol S4. The phase difference between the first symbol S1 and the fourth symbol S4 can correspond to... Figure 7 The phase difference between the first symbol S1 and the fourth symbol S4.

[0159] In the following text, the operation of the bit-by-bit soft decision generator 213 will be described using the first retransmission symbol data SYMre1 and the first retransmission symbol reliability data SRre1 as examples. The first retransmission symbol data SYMre1 may be the fourth symbol S4, and the first retransmission symbol reliability data SRre1 may be sr1, and the value of sr1 may correspond to θ1.

[0160] The bit-by-bit soft decision generator 213 can generate the (1_1) retransmitted bit data BITre11 with "1" and the (1_2) retransmitted bit data BITre12 with "0" based on the fourth symbol S4.

[0161] The bit-by-bit soft decision generator 213 can generate, based on the fourth symbol S4 and sr1, the reliability data BRre11 of the (1_1)th retransmission bit with a predetermined (or optionally, given) maximum (or highest) reliability value max, and the reliability data BRre12 of the (1_2)th retransmission bit with the size of sr1 (e.g., the absolute value of sr1). The size of sr1 can be greater than 0 and less than or equal to max.

[0162] Based on the symbols of the fourth symbol S4 and sr1, the bit-by-bit soft decision generator 213 can select one of the retransmission bit reliability data corresponding to the weak bit from the (1_1) retransmission bit reliability data BRre11 and the (1_2) retransmission bit reliability data BRre12 to assign br1, which is the absolute value of sr1, as the reliability value of the selected retransmission bit reliability data, and can select another retransmission bit reliability data from the (1_1) retransmission bit reliability data BRre11 and the (1_2) retransmission bit reliability data BRre12 to assign max as the reliability value of the selected other retransmission bit reliability data.

[0163] Since the sign of sr1 becomes a positive value corresponding to θ1 which is greater than 0, the bit-by-bit soft decision generator 213 can assign max to the (1_1) retransmission bit reliability data BRre11 corresponding to the (1_1) retransmission bit data BITre11 which is a relatively strong bit, based on the fourth symbol S4 and the first symbol S1 which is adjacent to the fourth symbol S4 in the positive direction.

[0164] The bit-by-bit soft decision generator 213 can assign br1 to the (1_2) retransmission bit reliability data BRre12 corresponding to the (1_2) retransmission bit data BITre12, which is a relatively weak bit.

[0165] In the following text, the operation of the bit-by-bit soft decision generator 213 will be described using the second retransmission symbol data SYMre2 and the second retransmission symbol reliability data SRre2 as examples. The second retransmission symbol data SYMre2 may be the second symbol S2, and the second retransmission symbol reliability data SRre2 may be sr2, and the value of sr2 may correspond to θ2.

[0166] The bit-by-bit soft decision generator 213 can generate the (2_1)th retransmission bit data BITre21 with “0” and the (2_2)th retransmission bit data BITre22 with “1” based on the second symbol S2.

[0167] Based on the second symbols S2 and sr2, the bit-by-bit soft decision generator 213 can generate the reliability data BRre21 of the (2_1)th retransmission bit with the size of sr2 (e.g., the absolute value of sr2) and the reliability data BRre22 of the (2_2)th retransmission bit with the maximum (or highest) reliability value as a predetermined (or optionally, given) maximum (or highest) reliability value. The size of sr2 can be greater than 0 and less than or equal to max.

[0168] Based on the symbols of the second symbols S2 and sr2, the bit-by-bit soft decision generator 213 can select one of the retransmission bit reliability data corresponding to the weak bit from the (2_1) retransmission bit reliability data BRre21 and the (2_2) retransmission bit reliability data BRre22 to assign br2, which is the absolute value of sr2, as the reliability value of the selected retransmission bit reliability data, and can select another retransmission bit reliability data from the (2_1) retransmission bit reliability data BRre21 and the (2_2) retransmission bit reliability data BRre22 to assign max as the reliability value of the selected other retransmission bit reliability data.

[0169] Since the sign of sr2 becomes a negative value corresponding to θ2 which is less than 0, the bit-by-bit soft decision generator 213 can assign max to the (2_2) retransmission bit reliability data BRre22 corresponding to the (2_2) retransmission bit data BITre22 which is a relatively strong bit, based on the second symbol S2 and the first symbol S1 which is adjacent to the second symbol S2 in the negative direction.

[0170] The bit-by-bit soft decision generator 213 can assign br2 to the (2_1) retransmission bit reliability data BRre21 corresponding to the (2_1) retransmission bit data BITre21, which is a relatively weak bit.

[0171] exist Figure 9 In this document, the phase difference values ​​of the first symbol S1 to the fourth symbol S4 and the values ​​of the decision boundary are specified and described as predetermined (or optionally, given) values, but these are examples for the purpose of description, and the technical concept of this disclosure is not limited thereto.

[0172] Figure 10 An operational example of the bitwise soft decision generator 213 in Bluetooth EDR3 mode is shown. See also... Figure 10 When operating in Bluetooth EDR3 mode, the bit-by-bit soft decision generator 213 can perform soft decisions on a bit-by-bit basis based on the phase difference between the first symbol S1' and the eighth symbol S8'. The phase difference between the first symbol S1' and the eighth symbol S8' can correspond to... Figure 8 The phase difference between the first symbol S1' and the eighth symbol S8'.

[0173] In the following text, the operation of the bitwise soft decision generator 213 will be described using the third retransmission symbol data SYMre3 and the third retransmission symbol reliability data SRre3 as examples. The third retransmission symbol data SYMre3 can be the eighth symbol S8', and the third retransmission symbol reliability data SRre3 can be sr3, and the value of sr3 can correspond to θ3.

[0174] Based on the eighth symbol S8', the bitwise soft decision generator 213 can generate the (3_1)th retransmission bit data BITre31 with "1", the (3_2)th retransmission bit data BITre32 with "0" and the (3_3)th retransmission bit data BITre33 with "1".

[0175] Based on the eighth symbol S8' and sr3, the bit-by-bit soft decision generator 213 can generate the (3_1)th retransmission bit reliability data BRre31 with a predetermined (or optionally, given) maximum (or highest) reliability value max, the (3_2)th retransmission bit reliability data BRre32 with the size of sr3 (e.g., the absolute value of sr3), and the (3_3)th retransmission bit reliability data BRre33 with a predetermined (or optionally, given) maximum (or highest) reliability value max. The size of sr3 can be greater than 0 and less than or equal to max.

[0176] Based on the symbols of the eighth symbol S8' and sr3, the bit-by-bit soft decision generator 213 can select one retransmission bit reliability data corresponding to the weak bit from the (3_1) retransmission bit reliability data BRre31 to the (3_3) retransmission bit reliability data BRre33 to assign br3, which is the absolute value of sr3, as the reliability value of the selected retransmission bit reliability data, and can select the remaining retransmission bit reliability data from the (3_1) retransmission bit reliability data BRre31 to the (3_3) retransmission bit reliability data BRre33 to assign max as the reliability value of the selected remaining retransmission bit reliability data.

[0177] Since the sign of sr3 becomes a positive value corresponding to θ3 which is greater than 0, the bit-by-bit soft decision generator 213 can assign max to the (3_1) retransmission bit reliability data BRre31 and (3_3) retransmission bit reliability data BRre33, which are the (3_1) retransmission bit data BITre31 and (3_3) retransmission bit data BITre33, which are relatively strong bits, based on the eighth symbol S8' and the first symbol S1' which is adjacent to the eighth symbol S8' in the positive direction.

[0178] The bit-by-bit soft decision generator 213 can assign br3 to the (3_2) retransmission bit reliability data BRre32 corresponding to the (3_2) retransmission bit data BITre32, which is a relatively weak bit.

[0179] In the following text, the operation of the bit-by-bit soft decision generator 213 will be described using the fourth retransmission symbol data SYMre4 and the fourth retransmission symbol reliability data SRre4 as examples. The fourth retransmission symbol data SYMre4 can be the fifth symbol S5', and the fourth retransmission symbol reliability data SRre4 can be sr4, and the value of sr4 can correspond to θ4.

[0180] Based on the fifth symbol S5', the bit-by-bit soft decision generator 213 can generate the (4_1) retransmission bit data BITre41 with "0", the (4_2) retransmission bit data BITre42 with "0" and the (4_3) retransmission bit data BITre43 with "1".

[0181] Based on the fifth symbol S5' and sr4, the bit-by-bit soft decision generator 213 can generate the (4_1)th retransmission bit reliability data BRre41 with a predetermined (or optionally, given) maximum (or highest) reliability value max, the (4_2)th retransmission bit reliability data BRre42 with the size of sr4 (e.g., the absolute value of sr4), and the (4_3)th retransmission bit reliability data BRre43 with a predetermined (or optionally, given) maximum (or highest) reliability value max. The size of sr4 can be greater than 0 and less than or equal to max.

[0182] Based on the symbols of the fifth symbol S5' and sr4, the bit-by-bit soft decision generator 213 can select one retransmission bit reliability data corresponding to the weak bit from the (4_1) retransmission bit reliability data BRre41 to the (4_3) retransmission bit reliability data BRre43 to assign br4, which is the absolute value of sr4, as the reliability value of the selected retransmission bit reliability data, and can select the remaining retransmission bit reliability data from the (4_1) retransmission bit reliability data BRre41 to the (4_3) retransmission bit reliability data BRre43 to assign max as the reliability value of the selected remaining retransmission bit reliability data.

[0183] Since the sign of sr4 becomes a negative value corresponding to θ4 which is less than 0, the bit-by-bit soft decision generator 213 can assign max to the (4_1) retransmission bit reliability data BRre41 and the (4_3) retransmission bit reliability data BRre43, which are the (4_1) retransmission bit data BITre41 and the (4_3) retransmission bit data BITre43, which are relatively strong bits, based on the fifth symbol S5' and the fourth symbol S4' which is adjacent to the fifth symbol S5' in the negative direction.

[0184] The bit-by-bit soft decision generator 213 can assign br4 to the (4_2) retransmission bit reliability data BRre42 corresponding to the (4_2) retransmission bit data BITre42, which is a relatively weak bit.

[0185] exist Figure 10 In this document, the phase difference values ​​of the first symbol S1' to the eighth symbol S8' and the values ​​of the first decision boundary B1 to the eighth decision boundary B8 are specified and described as predetermined (or optionally, given) values, but these are examples for the purpose of description, and the technical concept of this disclosure is not limited thereto.

[0186] Return to reference Figure 6 The combination unit 215 can perform a combination operation on the retransmission bit data BITre and retransmission bit reliability data BRre generated based on the retransmission symbol data SYMre and the retransmission symbol reliability data SRre, as well as the corresponding storage bit data BITs and storage bit reliability data BRs, to generate combined bit data BITcb and combined bit reliability data BRcb (S150).

[0187] Figure 11 An operational example of the combination unit 215 is shown. Figure 11 The operation of the combination unit 215 in Bluetooth EDR2 mode is shown, but the technical concept of this disclosure is not limited thereto, and it is clear that... Figure 11 The description can also be applied to the operation of the combination unit 215 operating in Bluetooth EDR3 mode.

[0188] Alternatively refer to Figure 11 The combination unit 215 can receive multiple retransmission bit data BITre11 to BITren2 and multiple retransmission bit reliability data corresponding to the multiple retransmission bit data BITre11 to BITren2 from the bit-by-bit soft decision generator 213, and receive multiple storage bit data BITs11 to BITsn2 and multiple storage bit reliability data corresponding to the multiple storage bit data BITs11 to BITsn2 from the memory 214.

[0189] According to an embodiment, two consecutively arranged retransmission bit data (e.g., two or two retransmission bit data) can correspond to one retransmission symbol data. For example, the (1_1)th retransmission bit data BITre11 and the (1_2)th retransmission bit data BITre12 can correspond to the first retransmission symbol data SYMre1, and the (n_1)th retransmission bit data BITren1 and the (n_2)th retransmission bit data BITren2 can correspond to the nth retransmission symbol data SYMren.

[0190] Combination unit 215 can perform catch-up combination operations on retransmission bit data BITre, retransmission bit reliability data BRre, storage bit data BITs, and storage bit reliability data BRs. In the following description, the operation of combination unit 215 will be illustrated using (1_1) retransmission bit data BITre11, (1_1) retransmission bit reliability data BRre11, (1_1) storage bit data BITs11, and (1_1) storage bit reliability data BRs11 as examples.

[0191] The (1_1)th retransmission bit data BITre11 can have a "1", and the corresponding (1_1)th storage bit data BITs11 can have a "0". The (1_1)th retransmission bit reliability data BRre11 used for the (1_1)th retransmission bit data BITre11 can have a reliability value of max, and the (1_1)th storage bit reliability data BRs11 used for the corresponding (1_1)th storage bit data BITs11 can have a reliability value of br5. br5 can be greater than 0 and less than or equal to max.

[0192] Combination unit 215 can change the sign of the reliability data BRs11 of the (1_1)th storage bit data BITs11 with "0". Combination unit 215 can change the sign of the reliability data BRs11 of the (1_1)th storage bit, and then add the (1_1)th storage bit reliability data BRs11 with the changed sign to the (1_1)th retransmission bit reliability data BRre11. Combination unit 215 can multiply the sum by a predetermined (or optionally, given) scaling factor and generate the magnitude of the multiplied value (e.g., the absolute value of the multiplied value) as the reliability data BRcb11 of the (1_1)th combined bit. See reference. Figure 11 The reliability data BRcb11 of the (1_1)th combination can have an absolute value of (max-br5) / 2.

[0193] When the value multiplied by a predetermined (or optionally, given) scaling factor is positive, the combining unit 215 can generate combined bit data BITcb11 with "1". See reference. Figure 11 As an example, the (1_1)th combination bit data BITcb11 may have "1". If the value multiplied by a predetermined (or alternatively, given) scaling factor is negative, the combination unit 215 may generate the (1_1)th combination bit data BITcb11 with "0".

[0194] Following the operation of the combination unit 215, the bit-to-symbol soft decision converter 216 can perform a conversion operation on the combined bit data BITcb and the combined bit reliability data BRcb to generate combined symbol data SYMcb in symbol units and combined symbol reliability data SRcb corresponding to the combined symbol data SYMcb.

[0195] The bit-to-symbol soft decision converter 216 can generate first combined symbol data SYMcb1 based on the (1_1) combined bit data BITcb11 and the (1_2) combined bit data BITcb12, and can generate first combined symbol reliability data by selecting the lower reliability value between the (1_1) combined bit reliability data BRcb11 and the (1_2) combined bit reliability data used for the (1_2) combined bit data BITcb12.

[0196] Return to reference Figure 6 The first phase domain error correction unit 211a receives the combined symbol data SYMcb and the combined symbol reliability data SRcb to perform error correction operations and generate the combined data block DBcb (S160).

[0197] The first phase domain error correction unit 211a can generate a data block DBpre and the weakest symbol information WSdata before processing based on the combined symbol data SYMcb and the combined symbol reliability data SRcb.

[0198] Figure 12 An operational example of the first phase domain error correction unit 211a is shown. Figure 12 The operation of the first phase domain error correction unit 211a operating in Bluetooth EDR2 mode is shown, but this disclosure is not limited thereto, and it is clear that... Figure 12 The description can also be applied to the operation of the first phase domain error correction unit 211a operating in Bluetooth EDR3 mode.

[0199] Alternatively refer to Figure 12 The first phase domain error correction unit 211a can generate a data block DBpre before processing based on multiple consecutively input combined symbol data SYMcb1 to SYMcbn.

[0200] The first phase domain error correction unit 211a can generate the weakest symbol information WSdata for the data block DBpre before processing, based on multiple combined symbol data SYMcb1 to SYMcbn and combined symbol reliability data corresponding to the multiple combined symbol data SYMcb1 to SYMcbn.

[0201] Reference Figure 12As an example, the weakest symbol information WSdata may include information about the a-th weak symbol WSa to the e-th weak symbol WSe in the data block DBpre before processing. For example, the first phase domain error correction unit 211a may select the second combined symbol data SYMcb2 as the a-th weak symbol WSa, and the first phase domain error correction unit 211a may select the (n-1)-th combined symbol data SYMcbn-1 as the e-th weak symbol WSe.

[0202] The first phase domain error correction unit 211a can select weak bits from the selected a-th weak symbol WSa to the e-th weak symbol WSe. For example, the first phase domain error correction unit 211a can select the (2_2)th combination bit data BITcb22 as the a-th weak bit WBa in the second combination symbol data SYMcb2, and the first phase domain error correction unit 211a can select the (n-1_1)th combination bit data BITcbn-11 as the e-th weak bit WBe in the (n-1)th combination symbol data SYMcbn-1.

[0203] The first phase domain error correction unit 211a can flip one of the selected a-th weak bit WBa to the e-th weak bit WBe to generate the a-th processed data block DBa to the e-th processed data block DBe. (Refer to...) Figure 12 As an example, the first phase domain error correction unit 211a can generate the a-th processed data block DBa by flipping the (2_2)th combination bit data BITcb22 in the data block DBpre before processing.

[0204] The first phase domain error correction unit 211a can perform error detection on the a-th processed data block DBa to the e-th processed data block DBe respectively, so as to generate the a-th hash HASHa to the e-th hash HASHe as the result of the error detection on the a-th processed data block DBa to the e-th processed data block DBe.

[0205] According to an embodiment, the first phase domain error correction unit 211a can generate a plurality of multi-hashes MHASH1 to MHASH31 by generating each of the a-th hash HASHa to the e-th hash HASHe itself or by performing an XOR operation on at least a portion of the a-th hash HASHa to the e-th hash HASHe.

[0206] Each of the multiple multi-hashes MHASH1 to MHASH31 may include the result of error detection on a data block generated by flipping at least a portion of the weak bits of the selected weak symbols WSa to WSe. For example, when all bits of data of one of the multiple multi-hashes MHASH1 to MHASH31 are logic low "0", this may indicate that the data block corresponding to that one multi-hash has passed in the error detection operation.

[0207] The first phase domain error correction unit 211a can perform error detection operations through multiple multi-hash MHASH1 to MHASH31 for all cases where at least a portion of the weak bits selected by the weakest bit processing unit 2112 are flipped.

[0208] The first phase-domain error correction unit 211a can generate a combined data block DBcb by performing an error correction operation based on multiple multi-hash MHASH1 to MHASH31 to flip some bits of the data in the data block DBpre before processing. When the error correction operation cannot be performed (e.g., cannot be performed), the first phase-domain error correction unit 211a can generate the data block DBpre itself before processing as the combined data block DBcb.

[0209] The first error detector 212a detects errors in the combined data block DBcb (S170).

[0210] The first error detector 212a can receive the combined data block DBcb and perform error detection to generate combined error decision data DEcb as the result of error detection of the combined data block DBcb.

[0211] According to an embodiment, the combined error decision data DEcb may have a predetermined (or optionally, given) number of bits, and the combined error decision data DEcb may include the result of error detection of the combined data block DBcb.

[0212] According to an embodiment, the first error detector 212a may perform an error detection operation based on divisor data for a predetermined (or optionally, given) CRC to generate combined error decision data DEcb. According to an embodiment, the combined error decision data DEcb may be a remainder value generated by performing a division operation on the combined data block DBcb with the predetermined (or optionally, given) divisor data.

[0213] For example, when the combined data block DBcb passes the error detection operation via the first error detector 212a, all bits in the combined error decision data DEcb can be logic low "0". Furthermore, if the combined data block DBcb does not pass the error detection operation via the second error detector 212b, the combined error decision data DEcb can include logic high "1".

[0214] exist Figure 6 In the illustration, operation S140 is shown preceding operations S150 to S170; however, this order is for ease of description, and the technical concept of this disclosure is not limited thereto. According to embodiments, operations S150 to S170 may be performed before or together with operation S140.

[0215] Demodulator module 21 checks whether at least one of the retransmission data blocks DBre and DBre' and the combined data block DBcb has passed the error detection operation (e.g., operation successful) based on the retransmission error decision data DEre and the combined error decision data DEcb (S180).

[0216] When the retransmission error decision data DEre and the combined error decision data DEcb include (e.g., indicate) an error in retransmission data blocks DBre and DBre' and the combined data block DBcb, the second communication device 20 provides a negative acknowledgment (NACK) to the first communication device 10 to request retransmission (S190). According to an embodiment, in response to determining, based on the retransmission error decision data DEre and the combined error decision data DEcb, that at least one of the retransmission data blocks DBre and DBre' and the combined data block DBcb has passed an error detection operation (e.g., operation successful) (S180), the second communication device 20 may perform one or more further operations based on the received packet. For example, one or more further operations may include one or more of the following: providing packet data from the packet to an application running on the second communication device 20 (e.g., an application for performing services based on the packet data), storing the packet data, sending a response signal to the first communication device 10 based on the packet data, etc.

[0217] After providing a negative acknowledgment (NACK), the second communication device 20 may repeat operation S110 to operation S180.

[0218] According to the embodiment, error correction modules 21_2a and 21_2b can perform operations S140 and S150 to S170 in parallel for retransmitted packets to improve the success rate of packet transmission reception.

[0219] Figure 13 A block diagram of an error correction module according to an embodiment is shown. Figure 14 A block diagram of a Cartesian domain error correction unit according to an embodiment is shown. Figure 13 The error correction module 21_2c is Figure 2 Example of error correction module 21_2 (e.g., Figure 13 The error correction module 21_2c can be used to implement Figure 2 Error correction module 21_2). Figure 13 The bitwise soft decision generator 217, the first Cartesian domain error correction unit 218a, the second Cartesian domain error correction unit 218b, the first error detector 212a', the second error detector 212b', the memory 214', the combination unit (or catch-up combination unit) 215', and the demultiplexer DMX' can respectively correspond to Figure 3The system comprises a symbol-by-symbol soft decision generator 210, a first phase domain error correction unit 211a, a second phase domain error correction unit 211b, a first error detector 212a, a second error detector 212b, a memory 214, a combination unit 215, and a demultiplexer DMX. For better understanding and ease of description, the focus will be on... Figure 3 To describe the differences in the corresponding configurations. Figure 13 Error correction module 21_2c.

[0220] Reference Figure 2 , Figure 13 and Figure 14 The error correction module 21_2c may include a bitwise soft decision generator 217, a first Cartesian domain error correction unit 218a, a second Cartesian domain error correction unit 218b, a first error detector 212a', a second error detector 212b', a memory 214', a combination unit 215', and / or a demultiplexer DMX'.

[0221] The bit-by-bit soft decision generator 217 can perform soft decision operations based on phase difference data PD to generate bit data BIT in units and bit reliability data LLR as reliability data for bit data BIT.

[0222] According to an embodiment, demodulator module 21 can receive input signal IN_P in packets, and bit-by-bit soft decision generator 217 can receive multiple phase difference data PDs received sequentially (e.g., multiple phase difference data PDs received sequentially). Bit-by-bit soft decision generator 217 can continuously generate multiple bit data BITs (e.g., multiple bit data BITs) and bit reliability data LLRs (e.g., multiple bit reliability data LLRs) based on the multiple phase difference data PDs.

[0223] According to an embodiment, when the demodulator module 21 performs demodulation in QDPSK mode, the bit-by-bit soft decision generator 217 can generate two bit data (e.g., two bit data or two bit data) corresponding to different bit numbers based on a phase difference data PD (e.g., one phase difference data PD) input in symbol units. According to an embodiment, when the demodulator module 21 operates according to Bluetooth EDR2 mode, the demodulator module 21 can use the QDPSK method to perform demodulation.

[0224] According to an embodiment, when the demodulator module 21 performs demodulation in 8DPSK mode, the bit-by-bit soft decision generator 217 can generate three bit data (e.g., three bit data lines or three bit data lines) corresponding to different bit digits based on a phase difference data PD input in symbol units. According to an embodiment, when the demodulator module 21 operates according to Bluetooth EDR3 mode, the demodulator module 21 can perform demodulation using the 8DPSK method.

[0225] Bit reliability data LLR is data indicating the reliability value used for a corresponding bit data BIT, and in embodiments, bit reliability data LLR can be a log-likelihood ratio. Bit reliability data LLR can be determined based on the phase difference value of phase difference data PD, and bit-by-bit soft decision generator 217 can generate bit reliability data LLR by approximately calculating the log-likelihood ratio for each bit data BIT (e.g., per bit data BIT or per bit data BIT). According to embodiments, bit reliability data LLR can have a predetermined (or optionally, given) number of bits.

[0226] The log-likelihood ratio can be expressed as the logarithmic ratio of the posterior probability (APP) that the median bit is a logic high "1" to the posterior probability that the median bit is a logic low "0".

[0227] According to the embodiment, when the bit reliability data LLR has a positive value, the bit data BIT can have a logic high "1", and when the bit reliability data LLR has a negative value, the bit data BIT can have a logic low "0". Furthermore, the larger the value of the bit reliability data LLR, the lower the probability of errors occurring in the bit data BIT.

[0228] For example, when the demodulator module 21 operates according to the Bluetooth EDR2 mode, the bit-by-bit soft decision generator 217 can perform a soft decision operation on the k-th phase difference data (k is an integer equal to or greater than 0), generating the (k_1)-th bit data and the (k_2)-th bit data corresponding to different bit numbers, and generating the (k_1)-th bit reliability data corresponding to the (k_1)-th bit data and the (k_2)-th bit reliability data corresponding to the (k_2)-th bit data. For example, the bit-by-bit soft decision generator 217 can generate the (k_1)-th bit reliability data and the (k_2)-th bit reliability data by performing the operation shown in Equation 1 below.

[0229] (Equation 1)

[0230]

[0231] In equation 1, It is the phase difference value of the k-th phase difference data. This refers to the (k_1)th bit of the k-th phase difference data. This refers to the (k_2)th bit of the k-th phase difference data. It is bit reliability data used for bit data, and It is a pre-defined (or optionally, given) scaling factor.

[0232] For example, when the demodulator module 21 operates according to Bluetooth EDR3 mode, the bit-by-bit soft decision generator 217 can perform a soft decision operation on the k-th phase difference data (k is an integer equal to or greater than 0), generating the (k_1)th bit data, (k_2)th bit data, and (k_3)th bit data corresponding to different bit numbers, and generating the (k_1)th bit reliability data corresponding to the (k_1)th bit data, the (k_2)th bit reliability data corresponding to the (k_2)th bit data, and the (k_3)th bit reliability data corresponding to the (k_3)th bit data. For example, the bit-by-bit soft decision generator 217 can generate the (k_1)th bit reliability data to the (k_3)th bit reliability data by performing the operation shown in Equation 2 below.

[0233] (Equation 2)

[0234]

[0235]

[0236] In equation 2, It is the phase difference value of the k-th phase difference data. This refers to the (k_1)th bit of the k-th phase difference data. This refers to the (k_2)th bit of the k-th phase difference data. This refers to the (k_3)th bit of the k-th phase difference data. It is bit reliability data used for bit data, and It is a pre-defined (or optionally, given) scaling factor.

[0237] The demultiplexer DMX' can receive bit data (BIT), bit reliability data (LLR), and initial input selection signal (INI_SEL), and operates as a data distributor to control the transmission path of bit data (BIT) and bit reliability data (LLR) based on the initial input selection signal (INI_SEL).

[0238] For example, when the initial input selection signal INI_SEL is logic high "1", the demultiplexer DMX' can check the input signal IN_P corresponding to the bit data BIT and bit reliability data LLR as a signal based on the first input packet, and provide the bit data BIT and bit reliability data LLR as the first bit data (or initial bit data) BITi and the first reliability data (or initial bit reliability data) LLRi to the first Cartesian domain error correction unit 218a.

[0239] For example, when the initial input selection signal INI_SEL is logic low "0", the demultiplexer DMX' can check the input signal IN_P corresponding to the bit data BIT and bit reliability data LLR as a signal based on the retransmission packet, and can provide the bit data BIT and bit reliability data LLR as retransmission bit data BITre and retransmission bit reliability data LLRre to the combination unit 215' and the second Cartesian domain error correction unit 218b.

[0240] The first Cartesian domain error correction unit 218a can receive initial bit data BITi and initial bit reliability data LLRi, or combined bit data BITcb and combined bit reliability data LLRcb, which will be described later, to perform error correction operations and output an initial data block DBi or a combined data block DBcb.

[0241] like Figure 14 As shown, the first Cartesian domain error correction unit 218a may include the weakest bit processing unit 2182, multiple error detectors 2183a to 2183e, a multi-hash generator 2184, and / or a data block generator 2185. Figure 14 The weakest bit processing unit 2182, multiple error detectors 2183a to 2183e, multi-hash generator 2184, and data block generator 2185 can respectively correspond to Figure 4 The weakest bit processing unit 2112, multiple error detectors 2113a to 2113e, a multi-hash generator 2114, and a data block generator 2115.

[0242] The weakest bit processing unit 2182 can receive multiple initial bit data BITi (e.g., multiple initial bit data BITis) and multiple initial bit reliability data LLRi (e.g., multiple initial bit reliability data LLRis). According to an embodiment, the weakest bit processing unit 2182 can receive the initial bit data BITis in the form of a data block DBpre' prior to processing. The data block DBpre' prior to processing can be a data block of multiple initial bit data BITis that are sequentially input to the first Cartesian field error correction unit 218a and are contiguously linked, and may include a CRC code.

[0243] The weakest bit processing unit 2182 can select multiple weak bits in the data block DBpre' before processing based on multiple initial bit reliability data LLRi, and flip one bit in the data block DBpre' before processing to generate a data block.

[0244] For example, the weakest bit processing unit 2182 may select a predetermined (or optionally, given) number of weak initial bit data (e.g., a predetermined (or optionally, given) number of weak initial bit data) from multiple initial bit reliability data LLRi based on multiple initial bit reliability data BITi. The weak initial bit data may represent bit data corresponding to the reliability data with a smaller reliability value among the multiple initial bit reliability data LLRi.

[0245] The weakest bit processing unit 2182 can flip one of the five selected weak bits to generate the a-th to e-th processed data blocks DBa'. According to an embodiment, each of the a-th to e-th processed data blocks DBe' can be a data block whose bits are flipped based on the data block DBpre' before processing. In an embodiment, the a-th to e-th processed data blocks DBa' can be different data blocks.

[0246] exist Figure 14 In this paper, the number of weak bits selected is shown as 5, but the technical concept of this disclosure is not limited to this, and the number of weak bits selected may vary depending on the embodiment.

[0247] Multiple error detectors 2183a to 2183e can respectively receive the a-th processed data block DBa' to the e-th processed data block DBe', and perform error detection operations to generate the a-th hash HASHa' to the e-th hash HASHe' as the result of error detection for the a-th processed data block DBa' to the e-th processed data block DBe'. The generated a-th hash HASHa' to the e-th hash HASHe' can be provided to the multi-hash generator 2184. The a-th hash HASHa' to the e-th hash HASHe' can correspond to Figure 4 HASHa from the ath hash to the eth hash.

[0248] According to an embodiment, the multi-hash generator 2184 can generate multiple multi-hashes MHASH1' to MHASH31' by outputting each of the a-th hash HASHa' to e-th hash HASHe' itself or by performing an XOR operation on at least a portion of the a-th hash HASHa' to e-th hash HASHe'. The multiple multi-hashes MHASH1' to MHASH31' can correspond to... Figure 4 Multiple multi-hash MHASH1 to MHASH31.

[0249] exist Figure 14 In the diagram, the first Cartesian domain error correction unit 218a is shown only as performing error correction based on the initial bit data BITi and the initial bit reliability data LLRi, but it is clear that... Figure 14The components of the first Cartesian field error correction unit 218a can also perform error correction operations based on the combined bit data BITcb and the combined bit reliability data LLRcb. According to an embodiment, the first Cartesian field error correction unit 218a can generate a combined data block DBcb by performing error correction operations based on the combined bit data BITcb and the combined bit reliability data LLRcb.

[0250] Return to reference Figure 13 The first error detector 212a' can perform error detection operations on the initial data block DBi or the combined data block DBcb to output the initial error decision data DEi or the combined error decision data DEcb.

[0251] The first error detector 212a' can correspond to Figure 14 The error detectors 2183a to 2183e, and the initial error decision data DEi or the combined error decision data DEcb can correspond to Figure 14 The hashes from the a-th to the e-th hashes. For better understanding and ease of description, the description of the first error detector 212a' can be replaced with... Figure 14 Description of error detectors 2183a to 2183e.

[0252] The second Cartesian domain error correction unit 218b can receive retransmission bit data BITre and retransmission bit reliability data LLRre to perform error correction operations and output retransmission data block DBre.

[0253] The second Cartesian domain error correction unit 218b can correspond to the first Cartesian domain error correction unit 218a, the retransmitted bit data BITre can correspond to the initial bit data BITi, the retransmitted bit reliability data LLRre can correspond to the initial bit reliability data LLRi, and the retransmitted data block DBre can correspond to the initial data block DBi. For better understanding and ease of description, the description of the second Cartesian domain error correction unit 218b can be replaced with the description of the first Cartesian domain error correction unit 218a.

[0254] The second error detector 212b' can perform error detection operations on the retransmitted data block DBre to output retransmission error decision data DEre.

[0255] The memory 214' can store bit data (BITs) and bit reliability data (LLRs) for storing the bit data (BITs). According to an embodiment, the bit reliability data (LLRs) can be log-likelihood ratios and can have a predetermined (or optionally, given) number of bits.

[0256] According to an embodiment, the combining unit 215' can receive retransmission bit data BITre, retransmission bit reliability data LLRre, storage bit data BITs, and storage bit reliability data LLRs, and perform a combining operation. The combining unit 215 can perform the combining operation to generate combined bit data BITcb and combined bit reliability data LLRcb for combining the bit data BITcb. According to an embodiment, the combined bit reliability data LLRcb can be a log-likelihood ratio and can have a predetermined (or optionally, given) number of bits.

[0257] According to an embodiment, the combining unit 215' can perform a catch-up combining operation. According to an embodiment, the combining unit 215' can add retransmission bit reliability data LLRre and storage bit reliability data LLRs. According to an embodiment, the combining unit 215' can generate combined bit reliability data LLRcb by multiplying the added reliability value with a predetermined (or optionally, given) scaling factor.

[0258] Combination unit 215' can determine combination bit data BITcb based on the sign of combination bit reliability data LLRcb. For example, when combination bit reliability data LLRcb has a positive value, combination bit data BITcb can have a "1" as logic high, and when combination bit reliability data LLRcb has a negative value, combination bit data BITcb can have a "0" as logic low.

[0259] According to an embodiment, the error correction module 21_2c can perform error detection on the retransmitted data block DBre generated by performing error correction operations on the retransmitted packets in parallel, and can detect errors in the combined data block DBcb generated by performing error correction operations after performing combination operations. According to an embodiment, the error correction module 21_2c can perform error correction and error detection on the retransmitted packets in parallel to improve the success rate of packet transmission reception.

[0260] According to an embodiment, the first Cartesian domain error correction unit 218a can generate an initial data block DBi by performing error correction operations on the first incoming packet, and can generate a combined data block DBcb by performing error correction operations on the combined bit data BITcb and combined bit reliability data LLRcb generated based on retransmitted packets. According to an embodiment, the error correction module 21_2c includes the first Cartesian domain error correction unit 218a, thereby improving the packet transmission reception success rate without adding separate configuration and without area overhead.

[0261] According to the embodiment, the error correction module 21_2c generates bit data BIT and corresponding bit reliability data LLR based on the input phase difference data PD, and can perform combination operations and error correction operations bit by bit without separate conversion operations.

[0262] Figure 15 A block diagram of an error correction module according to an embodiment is shown. Figure 15 The error correction module 21_2d is Figure 2 Example of error correction module 21_2 (e.g., Figure 15 The error correction module 21_2d can be used to implement Figure 2 The error correction module 21_2). For better understanding and ease of description, the focus will be on the error correction module 21_2. Figure 13 To describe the differences between the error correction module 21_2c and the error correction module 21_2c. Figure 15 The error correction module 21_2d.

[0263] The second error detector 212b' can receive retransmitted bit data (BITre) from the demultiplexer DMX' without a separate error correction operation.

[0264] According to an embodiment, the second error detector 212b' can receive retransmitted bit data BITre in the form of retransmitted data blocks DBre' input sequentially in time without performing error correction operations.

[0265] Error correction module 21_2d can detect errors in retransmitted data blocks DBre' in parallel based on retransmitted packets, and can also detect errors in combined data blocks DBcb generated by performing error correction operations after performing combination operations. According to an embodiment, error correction module 21_2d can improve the packet transmission reception success rate by performing error correction and error detection on retransmitted packets in parallel while arranging one (e.g., only one) Cartesian domain error correction unit. Through the arrangement of the Cartesian domain error correction unit as described above, error correction module 21_2d can improve area overhead and increase the packet transmission reception success rate.

[0266] Figure 16 A flowchart illustrating the operation method of the demodulator module according to an embodiment is shown. Figure 17 This is a diagram illustrating the operation method of a demodulator module according to an embodiment. Specifically, Figure 16 The error correction operation method of the demodulator module 21 for retransmitting packets is shown. Figure 6 Operations S110 to S190 can respectively correspond to those described later. Figure 16 Operations S210 to S290. For better understanding and ease of description, the following will focus on... Figure 6 To describe the differences in the operation methods Figure 16 The operation method.

[0267] Reference Figure 2 and Figures 13 to 16 The phase difference calculation module 21_1 receives multiple input signals IN_P to generate phase difference data PD between the multiple input signals IN_P (S210).

[0268] The bit-by-bit soft decision generator 217 performs a soft decision operation based on the phase difference data PD to generate bit data BIT in units of bits and bit reliability data LLR as reliability data for the bit data BIT (S220).

[0269] According to an embodiment, when the demodulator module 21 performs demodulation in DPSK mode, the bit-by-bit soft decision generator 217 can generate multiple bit data BITs (e.g., multiple bit data BITs) corresponding to different bit numbers based on a phase difference data PD (e.g., one phase difference data PD) input in units of symbols.

[0270] According to the embodiment, the bit reliability data LLR, which is the reliability data of the bit data BIT, can be the log-likelihood ratio, and the bit-by-bit soft decision generator 217 can generate the reliability value of the bit reliability data LLR by approximately calculating the log-likelihood ratio based on the phase difference value of the phase difference data PD.

[0271] The demultiplexer DMX' checks whether the input signal IN_P has been retransmitted based on the initial input selection signal INI_SEL (S230).

[0272] The demultiplexer DMX' can determine the transmission path for the generated bit data BIT and bit reliability data LLR by checking whether the input signal IN_P has been retransmitted.

[0273] When the input signal IN_P is based on the packet of the initial input, the demultiplexer DMX' can provide the generated bit data BIT and bit reliability data LLR as the initial bit data BITi and initial bit reliability data LLRi to the first Cartesian domain error correction unit 218a.

[0274] When the input signal IN_P is based on retransmitted packets, the demultiplexer DMX' can provide the generated bit data (BIT) and bit reliability data (LLR) in parallel. Figure 13 In the error correction module 21_2c, the demultiplexer DMX' can provide the generated bit data BIT and bit reliability data LLR as retransmitted bit data BITre and retransmitted bit reliability data LLRre in parallel to the combination unit 215' and the second Cartesian domain error correction unit 218b. Figure 15 In the error correction module 21_2d, the demultiplexer DMX' can provide the generated bit data BIT and bit reliability data LLR as retransmitted bit data BITre and retransmitted bit reliability data LLRre in parallel to the combination unit 215' and the second error detector 212b'.

[0275] The second error detector 212b' detects errors in retransmitted data (e.g., retransmitted data blocks DBre and DBre') (S240). For example, the second error detector 212b' may detect errors in retransmitted data blocks DBre and DBre' based on bit data BIT and bit reliability data LLR.

[0276] exist Figure 13 In the error correction module 21_2c, the retransmission data block DBre input to the second error detector 212b' can be a data block generated by the second Cartesian domain error correction unit 218b performing error correction operations based on the retransmission bit data BITre and the retransmission bit reliability data LLRre.

[0277] exist Figure 15 In the error correction module 21_2d, the retransmission data block DBre' input to the second error detector 212b' can be a data block generated by continuously inputting retransmission bit data BITre in chronological order without performing error correction operations.

[0278] The retransmitted data blocks DBre and DBre' can correspond to Figure 3 retransmitted data blocks DBre and Figure 5 The retransmitted data block DBre', and the retransmitted error decision data DEre can correspond to Figure 3 and Figure 5 The retransmission error decision data DEre.

[0279] The combination unit 215' receives retransmission bit data BITre, retransmission bit reliability data LLRre, storage bit data BITs, and storage bit reliability data LLRs, and performs a combination operation on a bit-by-bit basis (S250).

[0280] The combination unit 215' can receive the retransmission bit data BITre and retransmission bit reliability data LLRre output from the demultiplexer DMX' as is.

[0281] The combination unit 215' can perform catch-up combination operations on retransmission bit data BITre, retransmission bit reliability data LLRre, storage bit data BITs, and storage bit reliability data LLRs. For example, the combination unit 215' can perform a combination operation on retransmission bit data BITre and the storage bit data BITs corresponding to retransmission bit data BITre to generate combined bit data BITcb, and perform a combination operation on retransmission bit reliability data LLRre and the storage bit reliability data LLRs corresponding to retransmission bit reliability data LLRre to generate combined bit reliability data LLRcb.

[0282] According to an embodiment, the combining unit 215' can add the retransmission bit reliability data LLRre and the corresponding storage bit reliability data LLRs. The combining unit 215' can multiply the added value with a predetermined (or optionally, given) scaling factor, and can generate the multiplied value as the combined bit reliability data LLRcb.

[0283] When the value multiplied by a predetermined (or optionally, given) scaling factor is positive, the combining unit 215' can generate combined bit data BITcb with "1". Conversely, when the value multiplied by a predetermined (or optionally, given) scaling factor is negative, the combining unit 215' can generate combined bit data BITcb with "0".

[0284] The combination unit 215' can provide the generated combination bit data BITcb and combination bit reliability data LLRcb to the first Cartesian domain error correction unit 218a without separate processing operations.

[0285] The first Cartesian field error correction unit 218a receives the combined bit data BITcb and the combined bit reliability data LLRcb to perform error correction operations and generate the combined data block DBcb (S260).

[0286] The first Cartesian domain error correction unit 218a can receive initial bit data BITi in the form of a data block DBpre' prior to processing, based on the combined bit data BITcb and the combined bit reliability data LLRcb.

[0287] Figure 17 An operational example of the first Cartesian domain error correction unit 211a is shown.

[0288] Alternatively refer to Figure 17 The first Cartesian field error correction unit 218a can generate a data block DBpre' before processing based on multiple consecutively input combined bit data BITcb1 to BITcbz (e.g., multiple combined bit data BITcb1 to BITcbz). The first Cartesian field error correction unit 218a can select weak bits based on the combined bit reliability data corresponding to the multiple combined bit data BITcb1 to BITcbz.

[0289] For example, the first Cartesian domain error correction unit 218a may select the second combination bit data BITcb2 as the a-th weak bit WBa, the third combination bit data BITcb3 as the b-th weak bit WBb, the fourth combination bit data BITcb4 as the c-th weak bit WBc, and the (z-1)-th combination bit data BITcbz-1 as the e-th weak bit WBe. According to an embodiment, the first Cartesian domain error correction unit 218a may select consecutive second combination bit data BITcb2 to fourth combination bit data BITcb4 as the a-th weak bit WBa to the c-th weak bit WBc.

[0290] The first Cartesian domain error correction unit 218a can flip one of the selected a-th weak bit WBa to the e-th weak bit WBe to generate the a-th processed data block DBa' to the e-th processed data block DBe'. (See reference...) Figure 17 As an example, the first Cartesian field error correction unit 218a can generate the a-th processed data block DBa' by flipping the second combination bit data BITcb2 in the data block DBpre' before processing.

[0291] The first Cartesian domain error correction unit 218a can perform error detection operations on the a-th processed data block DBa' to the e-th processed data block DBe' respectively, so as to generate the a-th hash HASHa' to the e-th hash HASHe' as the result of error detection on the a-th processed data block DBa' to the e-th processed data block DBe'.

[0292] According to an embodiment, the first Cartesian domain error correction unit 218a can generate a plurality of multi-hashes MHASH1' to MHASH31' by generating each of the a-th hash HASHa' to the e-th hash HASHe' itself or by performing an XOR operation on at least a portion of the a-th hash HASHa' to the e-th hash HASHe'.

[0293] The first Cartesian field error correction unit 218a can generate a composite data block DBcb by performing an error correction operation based on multiple multi-hash MHASH1' to MHASH31' that flips some bits of the data in the data block DBpre' before processing. When the error correction operation cannot be performed (e.g., cannot be performed), the first Cartesian field error correction unit 218a can generate the data block DBpre' itself before processing as the composite data block DBcb.

[0294] The first error detector 212a' detects errors in the combined data block DBcb (S270).

[0295] The first error detector 212a' can receive the combined data block DBcb and perform error detection to generate combined error decision data DEcb as the result of error detection of the combined data block DBcb.

[0296] exist Figure 16 In the illustration, operation S240 is shown before operations S250 to S270; however, this order is for ease of description, and the technical concept of this disclosure is not limited thereto. In embodiments, operations S250 to S270 may be performed before or simultaneously with operation S240.

[0297] Demodulator module 21 checks whether at least one of the retransmission data blocks DBre and DBre' and the combined data block DBcb has passed the error detection operation (S280) based on the retransmission error decision data DEre and the combined error decision data DEcb.

[0298] When the retransmission error decision data DEre and the combined error decision data DEcb include (for example, an indication) an error in the retransmission data blocks DBre and DBre' and the combined data block DBcb, the second communication device 20 provides a negative acknowledgment NACK to the first communication device 10 to request a retransmission (S290).

[0299] After providing a negative acknowledgment (NACK), the second communication device 20 may repeat operations S210 to S280.

[0300] According to the embodiment, error correction modules 21_2c and 21_2d can perform operations S240 and S250 to S270 in parallel for retransmitted packets to improve the success rate of packet transmission reception.

[0301] Figure 18 This is a diagram used to describe a wireless communication device according to an embodiment.

[0302] Reference Figure 18 The wireless communication device 1000a may include an application processor 1100a (hereinafter referred to as AP), a memory 1200, a display 1300, and / or an RF module 1410a. Furthermore, the wireless communication device 1000a may also include various components such as lenses, sensors, audio modules, etc.

[0303] The AP 1100a can be implemented as a System-on-Chip (SoC) and may include a processor 1110, random access memory (RAM) 1120, a power management unit (PMU) 1130, a memory interface 1140, a display controller (DCON) 1150, a communication module (CM) 1160a, and / or a bus (or system bus) 1170. The AP 1100a may also include various intellectual property (IP) blocks. The processor 1110, RAM 1120, PMU 1130, memory interface 1140, display controller 1150, and / or communication module 1160a can be interconnected via the bus 1170 and can perform internal data communication. Because the functionality of the communication module chip is integrated into the AP 1100a, the AP 1100a may be referred to as a ModAP.

[0304] The processor 1110 controls the overall operation of the AP 1100a and the wireless communication device 1000a. The processor 1110 also controls the operation of each component of the AP 1100a. Furthermore, the processor 1110 may include at least one processing core (e.g., a multi-core). A multi-core may be a computing component with two or more independent cores.

[0305] RAM 1120 may temporarily store programs, data, or instructions. For example, programs and / or data stored in memory 1200 may be temporarily stored in RAM 1120 according to the control or boot code of processor 1110. RAM 1120 may be implemented as DRAM or SRAM.

[0306] The PMU 1130 manages the power of each component of the AP 1100a. The PMU 1130 can also determine the operating status of each component of the AP 1100a and control the operation of each component of the AP 1100a.

[0307] The memory interface 1140 controls the overall operation of the memory 1200 and controls the data exchange between each component of the AP 1100a and the memory 1200. The memory interface 1140 can write data to or read data from the memory 1200 according to requests from the processor 1110.

[0308] The display controller 1150 can send image data to be displayed on the display 1300. The display 1300 can be implemented as a flat panel display or a flexible display (such as a liquid crystal display (LCD), an organic light-emitting diode (OLED), etc.).

[0309] For wireless communication, the communication module 1160a can modulate the data to be transmitted to suit the wireless environment and demodulate the received data. According to an embodiment, the demodulated data can be provided to the processor 1110.

[0310] The communication module 1160a can perform digital communication with the RF module 1410a, and may include features for partially performing modulation or demodulation operations. Figures 1 to 17 The error correction module 21_2. The communication module 1160a can be accessed via... Figures 1 to 17 The error correction module 21_2 performs error correction and error detection on retransmitted packets in a parallel manner to improve the success rate of packet transmission reception.

[0311] RF module 1410a can correspond to Figure 1 The transceivers 12 and 22. RF module 1410a can convert RF signals received through the antenna into baseband signals, and partially demodulate the converted baseband signals to generate phase difference data PD. The phase difference data PD can be provided to communication module 1160a. Furthermore, RF module 1410a can modulate the phase difference data PD received from communication module 1160a into a baseband signal, convert the baseband signal into an RF signal, and transmit the converted RF signal to the outside of wireless communication device 1000a through the antenna. Additionally, RF module 1410a can amplify or filter the signal.

[0312] Figure 19 This is a diagram used to describe a wireless communication device according to an embodiment. Figure 19 The wireless communication device 1000b can correspond to Figure 18 The wireless communication device 1000a, and Figure 19 The AP 1100b, communication module 1160b, and RF module 1410b can respectively correspond to Figure 18 The AP 1100a, communication module 1160a, and RF module 1410a. For better understanding and ease of description, the focus will be on... Figure 18 To describe the differences Figure 19 Wireless communication device 1000b.

[0313] Reference Figure 19 The wireless communication device 1000b may include an AP 1100b, a memory 1200, a display 1300 and / or an RF module 1410b, and the AP 1100b may include a processor 1110, a RAM 1120, a PMU 1130, a memory interface 1140, a display controller 1150, a communication module 1160b and / or a bus 1170.

[0314] The communication module 1160b can perform digital communication with the RF module 1410b, and may include functions for performing modulation or demodulation operations. Figures 1 to 17 The modulator module 11 and demodulator module 21. The communication module 1160b can communicate via... Figures 1 to 17 The demodulator module 21 performs error correction and error detection on retransmitted packets in parallel to improve the success rate of packet transmission reception.

[0315] RF module 1410b can correspond to Figure 1 The transceivers 12 and 22. RF module 1410b can convert RF signals received through the antenna into baseband signals and generate an input signal IN_P as the converted baseband signal. The input signal IN_P can be provided to communication module 1160b. Furthermore, RF module 1410b can convert the input signal IN_P, which is the baseband signal received from communication module 1160a, into an RF signal and transmit the converted RF signal to the outside of wireless communication device 1000b through the antenna. Additionally, RF module 1410b can amplify or filter the signal.

[0316] Conventional apparatuses and methods for performing error detection on received packets involve performing Cyclic Redundancy Check (CRC) based on the corresponding code in the received packet and performing Hybrid Automatic Repeat Request (HARQ) based on the detection of uncorrectable errors. However, conventional apparatuses and methods cannot use CRC codes to perform error correction on packets that have already been retransmitted according to HARQ. Therefore, conventional apparatuses and methods suffer from insufficient packet reception success rate.

[0317] However, according to embodiments, improved apparatus and methods are provided for performing error detection on received packets. For example, the improved apparatus and methods include performing error correction (e.g., CRC correction) on retransmitted packets individually and / or performing error correction (e.g., CRC correction) on retransmitted packets combined with data from previously received packets. Therefore, the improved apparatus and methods overcome the shortcomings of conventional apparatus and methods to at least improve packet reception success rate.

[0318] According to an embodiment, the device described herein comprises a communication system 1, a first communication device 10, a second communication device 20, a modulator module 11, a transceiver 12, a demodulator module 21, a transceiver 22, a phase difference calculation module 21_1, an error correction module 21_2, a symbol-by-symbol soft decision generator 210, each of a first phase domain error correction unit 211a and a second phase domain error correction unit 211b, each of a first error detector 212a and a second error detector 212b, a bit-by-bit soft decision generator 213, a combination unit 215, a bit-to-symbol soft decision converter 216, a demultiplexer DMX, a weakest symbol search unit 2111, a weakest bit processing unit 2112, and each of a plurality of error detectors 2113a to 2113e. The multi-hash generator 2114, data block generator 2115, error correction module 21_2b, error correction module 21_2c, bit-by-bit soft decision generator 217, each of the first Cartesian domain error correction unit 218a and the second Cartesian domain error correction unit 218b, each of the first error detector 212a' and the second error detector 212b', combination unit 215', demultiplexer DMX', error correction module 21_2d, wireless communication device 1000a, application processor 1100a, RF module 1410a, processor 1110, power management unit (PMU) 1130, memory interface 1140, display controller 1150, communication module 1160a, wireless communication device 1000b, AP 1100b, RF module 1410b and / or communication module 1160b can be executed by the processing circuitry system. As used in this disclosure, the term "processing circuit system" can mean, for example, hardware that includes logic circuitry; a hardware / software combination (such as a processor that executes software); or a combination thereof. For example, a processing circuit system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), and the like.

[0319] The various operations of the above-described methods can be performed by any suitable device capable of performing the operations (such as the processing circuitry system discussed above). For example, as discussed above, the operations of the above-described methods can be performed by various hardware and / or software implemented in some form of hardware (e.g., processor, ASIC, etc.).

[0320] The software may include an ordered list of executable instructions for implementing logical functions and may be implemented in any "processor-readable medium" for use by or in conjunction with an instruction execution system, device, or apparatus (such as a single-core or multi-core processor or a system containing a processor).

[0321] The methods or algorithms and / or functional blocks or operations described in conjunction with the embodiments disclosed herein may be implemented directly in hardware, as software modules executed by a processor, or a combination of both. If implemented in software, the functionality may be stored as one or more instructions or code on or transferred through a tangible, non-transitory computer-readable medium. The software module may reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0322] While embodiments of this disclosure have been described in conjunction with what are now considered practical examples, it should be understood that the disclosure is not limited to the disclosed examples, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A communication module, comprising: The processing circuit system is configured as follows: Based on whether multiple input signals input in chronological order are retransmitted, the transmission path of the control first data and the first reliability data is determined. The first data is generated based on the phase difference data between the multiple input signals, and the first reliability data corresponds to the first data. Errors in the first data block are detected based on the first data and the first reliability data. A combination operation is performed on the first data, the first reliability data, the stored data, and the stored reliability data to generate combined data and combined reliability data, wherein the stored reliability data corresponds to the stored data, and the combined reliability data corresponds to the combined data. The first error correction operation is performed based on the combined data and the combined reliability data.

2. The communication module as described in claim 1, wherein, The processing circuit system is configured to generate first data and first reliability data based on phase difference data, wherein the first data is in symbol units.

3. The communication module as described in claim 2, wherein, The processing circuit system is configured to generate first bit data, second bit data, first bit reliability data and second bit reliability data based on first data and first reliability data, wherein the first bit data and second bit data are in bits, the first bit reliability data corresponds to the first bit data and the second bit reliability data corresponds to the second bit data.

4. The communication module as described in claim 3, wherein, The stored data includes first storage bit data and second storage bit data, which are stored in units of bits. The storage reliability data includes first storage reliability data corresponding to the first storage bit data and second storage reliability data corresponding to the second storage bit data; and The processing circuitry is configured to perform a combination operation on the first bit data and the first storage bit data, the first storage bit data corresponding to the first bit data.

5. The communication module as described in claim 4, further comprising: The memory is configured to store first storage bit data, second storage bit data, first storage reliability data, and second storage reliability data.

6. The communication module as described in claim 2, wherein, The processing circuitry is configured to perform a second error correction operation based on the first data and the first reliability data to generate a first data block.

7. The communication module as described in claim 6, wherein, The combined data includes a first combination of bit data and a second combination of bit data, in units of bits; and The combined reliability data includes first combined bit reliability data corresponding to the first combined bit data and second combined bit reliability data corresponding to the second combined bit data.

8. The communication module as described in claim 7, wherein, The processing circuit system is configured as follows: Combined symbol data and combined symbol reliability data are generated based on the first combination bit data, the second combination bit data, the first combination bit reliability data, and the second combination bit reliability data. The combined symbol data is in units of symbols, and the combined symbol reliability data corresponds to the combined symbol data. The first error correction operation is performed based on the combined symbol data and the combined symbol reliability data to generate a combined data block.

9. The communication module as described in claim 2, wherein, The first data corresponds to one of the first to fourth symbols, and each of the first to fourth symbols is different from the others.

10. The communication module as described in claim 2, wherein, The first data corresponds to one of the first to eighth symbols, and each of the first to eighth symbols is different from the other.

11. The communication module as described in claim 1, wherein, The processing circuitry is configured to: control the transmission path of the first data and the first reliability data based on a selection signal, and to detect errors in the first data block and perform a combination operation based on the selection signal being in a first logic state.

12. The communication module as described in claim 11, wherein, The processing circuit system is configured to: control the transmission path of first data and first reliability data based on a selection signal, and perform a third error correction operation to generate a second data block based on a second logic state that is different from the first logic state of the selection signal, the third error correction operation being based on the first data and the first reliability data.

13. The communication module as described in claim 1, wherein, The processing circuit system is configured to generate first data and first reliability data based on phase difference data, wherein the first data is in bits.

14. A communication module, comprising: The processing circuit system is configured as follows: Bit data and bit reliability data are generated based on the phase difference data between multiple input signals input in time sequence. The bit reliability data corresponds to the bit data. Based on the transmission path of whether the multiple input signals are retransmitted to control bit data and bit reliability data. Errors in the first data block are detected based on bit data and bit reliability data. Perform a combination operation on the bit data and the stored bit data to generate combined bit data, where the stored bit data corresponds to the bit data. A combination operation is performed on the bit reliability data and the storage bit reliability data to generate combined bit reliability data, where the storage bit reliability data corresponds to the bit reliability data, and Error correction is performed based on combined bit data and combined bit reliability data.

15. The communication module as described in claim 14, wherein, Bit reliability data, storage bit reliability data, and combined bit reliability data are log-likelihood ratios.

16. The communication module as described in claim 15, wherein, The bit data includes first bit data and second bit data generated based on phase difference data, and the first bit data and second bit data correspond to different bit numbers; The bit reliability data includes first-bit reliability data for the first bit data and second-bit reliability data for the second bit data; and The reliability data is calculated using the following equation. In the equation, This is bit reliability data. It is the phase difference value of the k-th phase difference data, where k is an integer greater than or equal to 0. It refers to the first data point of the k-th phase difference data. It is the second bit of data for the k-th phase difference data, and It is the scaling factor.

17. The communication module as described in claim 15, wherein, The bit data includes first bit data, second bit data, and third bit data generated based on phase difference data, with the first bit data, second bit data, and third bit data corresponding to different bit numbers; The bit reliability data includes first-bit reliability data for the first bit data, second-bit reliability data for the second bit data, and third-bit reliability data for the third bit data; and The reliability data is calculated using the following equation. In the equation, This is bit reliability data. It is the phase difference value of the k-th phase difference data, where k is an integer greater than or equal to 0. It refers to the first data point of the k-th phase difference data. It refers to the second bit of the k-th phase difference data. It refers to the third bit of the k-th phase difference data, and It is the scaling factor.

18. A method for operating a communication module, comprising: First data and first reliability data are generated based on the phase difference data between multiple input signals input in time sequence, and the first reliability data corresponds to the first data; In response to determining that the plurality of input signals have been retransmitted, an error in the first data block is detected based on the first data and the first reliability data; In response to determining that the plurality of input signals are retransmitted, a combination operation is performed on the first data, the first reliability data, the stored data, and the stored reliability data to generate combined data and combined reliability data, wherein the stored reliability data corresponds to the stored data, and the combined reliability data corresponds to the combined data. Perform error correction operations based on combined data and combined reliability data to generate combined data blocks; Detect errors in combined data blocks; as well as A retransmission is requested based on whether at least one of the error detections for the combined data block and the first data block is successful.

19. The method of operating the communication module as described in claim 18, wherein, The first data is data in units of symbols; Data is stored in units of bits; and The combined operation includes generating first data, second data, first reliability data and second reliability data based on first data and first reliability data. The first data and second data are in units of bits, the first reliability data corresponds to the first data, and the second reliability data corresponds to the second data.

20. The method of operating the communication module as described in claim 18, wherein, The first data is data in bits; and The first reliability data is the log-likelihood ratio.

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