Pulse acquisition and CAN communication circuit and backboard

Abstract

The invention relates to the field of circuit design, and provides a pulse acquisition and CAN communication circuit and a backboard. The pulse acquisition and CAN communication circuit comprises an I2C bus counter, a bus buffer, a first CAN transceiver and a second CAN transceiver; the I2C bus counter is connected with the bus buffer through a serial data line and a serial clock line; the bus buffer is connected with the first CAN transceiver through a first data transmission line; the first CAN transceiver is connected with the second CAN transceiver through a second data transmission line; the first CAN transceiver is connected with the backboard through a first CAN bus; the second CAN transceiver is connected with the backboard through a second CAN bus.

Description

Technical Field

[0001] This invention relates to the field of circuit design, and more particularly to a pulse acquisition and CAN communication circuit and a backplane. Background Technology

[0002] When using large equipment, such as monitoring equipment, data transmission equipment, configuration management equipment, and power distribution equipment, the equipment chassis contains various functional boards, which are combined into one unit through slots on the chassis's backplane. Typically, the pin definitions of these boards differ depending on their individual functions. Therefore, in practical applications, the slot positions of these boards are generally fixed. Incorrect insertion can lead to board malfunction or even damage to the equipment. In complex installation and debugging environments, board errors occur frequently, posing significant risks and safety hazards to installation and debugging work.

[0003] Furthermore, in rail transit equipment, circuit boards typically employ clock pulse signal acquisition and CAN communication functions. The conventional clock pulse signal acquisition and CAN communication mode uses an MCU plus a CAN transceiver. Boards using this mode require programming the MCU and debugging the embedded software, as well as external auxiliary circuitry, resulting in high development time and costs. Therefore, a redesign of the chassis backplane is necessary to ensure accurate slot placement for functional boards in large equipment, reducing installation and debugging risks, while also simplifying the clock pulse signal acquisition and CAN communication circuitry, thus reducing development time and costs. Summary of the Invention

[0004] This invention aims to at least partially solve one of the technical problems in related technologies. To this end, the first objective of this invention is to provide a pulse acquisition and CAN communication circuit, including an I2C bus counter, a bus buffer, a first CAN transceiver, and a second CAN transceiver; the I2C bus counter is connected to the bus buffer via a serial data line and a serial clock line; the bus buffer is connected to the first CAN transceiver via a first data transmission line and to the second CAN transceiver via a second data transmission line; the first CAN transceiver is connected to a backplane via a first CAN bus; and the second CAN transceiver is connected to the backplane via a second CAN bus. The pulse acquisition and CAN communication circuit provided in this invention provides a unified pin configuration for the chassis backplane slots, enabling mixed insertion of various types of boards, saving materials, and reducing manufacturing costs. Simultaneously, the power bus, communication bus, configuration bus, and other I / O lines are centrally arranged in designated areas, resulting in clear backplane hierarchies and neat wiring, allowing for flexible configuration or debugging as needed. Furthermore, this invention employs a purely hardware-based clock pulse signal acquisition and CAN communication circuit, simplifying the hardware structure, reducing costs, and eliminating the need for MCUs and embedded software, thereby saving development costs, reducing debugging time, and improving system reliability.

[0005] The second objective of this invention is to provide a backplate.

[0006] To achieve the above objectives, a first aspect of the present invention provides a pulse acquisition and CAN communication circuit, characterized in that it includes an I2C bus counter, a bus buffer, a first CAN transceiver, and a second CAN transceiver; the I2C bus counter is connected to the bus buffer via a serial data line and a serial clock line; the bus buffer is connected to the first CAN transceiver via a first data transmission line and to the second CAN transceiver via a second data transmission line; the first CAN transceiver is connected to a backplane via a first CAN bus; and the second CAN transceiver is connected to the backplane via a second CAN bus.

[0007] In addition, the pulse acquisition and CAN communication circuit according to the above embodiments of the present invention may also have the following additional technical features:

[0008] According to the pulse acquisition and CAN communication circuit proposed in the embodiment of the present invention, the I2C bus counter includes a reset signal input terminal, an external clock pulse signal input terminal, an output terminal of the serial data line, and an input terminal of the serial clock line;

[0009] The I2C bus counter is used for: receiving a reset signal via the reset signal input terminal; resetting the count to 0 in response to a low reset signal and enabling the incrementing count of pulses for an external clock pulse signal in response to a high reset signal; receiving an external clock pulse signal via the external clock pulse signal input terminal; incrementing the count of pulses for an external clock pulse signal by 1 in response to the external clock pulse signal changing from low to high; transmitting the pulse count to the serial data line via the serial data line output terminal; and receiving timing signals sent by the bus buffer via the serial clock line input terminal. The timing signals are used to control the acquisition timing of the external clock pulse signal.

[0010] According to the pulse acquisition and CAN communication circuit proposed in the embodiment of the present invention, the bus buffer includes an input terminal of a serial data line, an output terminal of a serial clock line, a transmitting terminal of a first data transmitting line, and a transmitting terminal of a second data transmitting line.

[0011] The bus buffer is used to: receive the number of pulses transmitted by the serial data line through the input terminal of the serial data line, perform differential processing on the number of pulses to obtain a first differential pulse number and a second differential pulse number, transmit the first differential pulse number to the first data transmission line through the transmitting terminal of the first data transmission line, transmit the second differential pulse number to the second data transmission line through the transmitting terminal of the second data transmission line; and output timing signals to the serial data line through the output terminal of the serial clock line for transmission.

[0012] According to the pulse acquisition and CAN communication circuit proposed in the embodiment of the present invention, the first CAN transceiver includes a receiving end of the first data transmission line;

[0013] The first CAN transceiver is used to: receive the first differential pulse count transmitted by the first data transmission line through the receiving end of the first data transmission line, and send the first differential pulse count to the first CAN bus for transmission.

[0014] According to the pulse acquisition and CAN communication circuit proposed in the embodiment of the present invention, the second CAN transceiver includes a receiving end of the second data transmission line;

[0015] The second CAN transceiver is used to: receive the second differential pulse count transmitted by the second data transmission line through the receiving end of the second data transmission line, and send the second differential pulse count to the second CAN bus for transmission.

[0016] To achieve the above objectives, a second aspect of the present invention provides a backplane, which includes a power bus, a communication bus, a configuration bus, and other I / O lines. The communication bus is connected to a pulse acquisition and CAN communication circuit as described in any one of claims 1-4. The power bus, communication bus, configuration bus, and other I / O lines are respectively provided with slots. The slots are used to connect functional boards with different functions, and functional boards with different functions can be mixed and matched between the slots.

[0017] According to the backplane proposed in the embodiment of the present invention, the communication bus includes a first CAN bus receiving port, which is connected to a first CAN transceiver of the pulse acquisition and CAN communication circuit through the first CAN bus, and receives the first differential pulse number sent by the first CAN transceiver.

[0018] According to the backplane proposed in the embodiment of the present invention, the communication bus includes a second CAN bus receiving port, which is connected to a second CAN transceiver of the pulse acquisition and CAN communication circuit through the second CAN bus, and receives the second differential pulse number sent by the second CAN transceiver.

[0019] The backplane proposed according to an embodiment of the present invention further includes a first configuration resistor and a second configuration resistor, wherein the first configuration resistor is connected to the input terminal of the communication bus and the second configuration resistor is connected to the output terminal of the communication bus.

[0020] The backplane proposed according to an embodiment of the present invention further includes a configuration switch, which is connected to the input terminal of the communication bus.

[0021] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only for this invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of the overall structure of the chassis provided in an embodiment of the present invention.

[0024] Figure 2 This is a schematic diagram of the chassis function boards and bus layout provided in an embodiment of the present invention.

[0025] Figure 3 This is a schematic diagram of the backplane slot bus arrangement provided in an embodiment of the present invention.

[0026] Figure 4 This is a schematic diagram of the pulse acquisition and CAN communication circuit framework provided in an embodiment of the present invention.

[0027] Figure 5 This is a schematic diagram of the pulse acquisition and CAN communication circuit bus provided in an embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0029] It should be noted that, unless otherwise defined, the technical or scientific terms used in this invention should have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "first," "second," and similar terms used in this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0030] As described in the background section, when using large-scale equipment for operation monitoring and data transmission, the chassis typically integrates multiple functional boards, which are combined via slots on the chassis backplane. Since each board has different functions and pin definitions, and the slot positions are usually fixed, inserting the wrong board can lead to malfunction or equipment damage, posing risks and hidden dangers to installation and debugging. This is especially true in rail transit equipment, where boards generally utilize clock pulse signal acquisition and CAN (Controller Area Network) communication. However, conventional circuit setups require MCU (Microcontroller Unit) programming, debugging, and peripheral circuit operation, resulting in high development costs and time. Therefore, the chassis backplane needs to be redesigned to ensure accurate board slot positions, reduce installation and debugging risks, and simplify clock pulse signal acquisition and CAN communication circuits to lower development costs and time.

[0031] In the process of developing this invention, the applicant discovered that there are some improvements to the current issues regarding the insertion of functional boards in the chassis: different width slots can be provided for different functional boards in the chassis and chassis backplane. For example, the width of the power supply board can be set to twice that of other boards, while allowing boards with the same function to be interchanged and mixed. However, boards with different functions cannot be interchanged with boards set in this way. In addition, an MCU is required as the main control chip, with an on-chip CAN communication interface circuit and a clock circuit, watchdog circuit, and JTAG (Joint Test Action Group) debugging circuit set on the periphery. Two CAN communication circuits are formed by connecting the board and two CAN transceivers through a serial cable. Communication between the board and the backplane is achieved through complex operating logic. In practical applications, this still requires a lot of material costs and development time costs.

[0032] The technical solution of the present invention will be further described in detail below through specific embodiments.

[0033] refer to Figure 1 This is a schematic diagram of the chassis external structure provided in an embodiment of the present invention.

[0034] Figure 1 This can be seen as a typical combination and installation layout diagram of the chassis's functional boards. The chassis mainly consists of two power supply boards, one main control board, and several other functional boards. The positions of the various boards inside the chassis are not fixed. Users can freely adjust the positions of these boards according to the appearance of the chassis, their personal usage habits, required functions, or ease of installation, thereby achieving arbitrary mixing and matching of boards.

[0035] refer to Figure 2 This is a schematic diagram of the chassis function boards and bus layout provided in an embodiment of the present invention.

[0036] Figure 2The diagram shows the chassis functional boards and bus layout provided in an embodiment of the present invention, including: configuration resistors, configuration switches, power buses, communication buses, and other I / O (Input / Output) lines. The configuration resistors are used for bus termination matching; adding a resistor of a certain value ensures impedance matching in the circuit, thereby optimizing signal transmission and improving circuit performance. The configuration switches are used to configure the IDs of the functional boards, identifying different boards. The power bus transmits power and energy data, enabling the main control board to monitor the power supply's operating status and the energy consumption of each board within the chassis, and adjust the current and voltage accordingly. The communication bus is a set of signal lines for communication between boards or between boards and external devices, responsible for transmitting various instructions and data to ensure collaborative operation between systems. The configuration bus is used for internal configuration and management of the boards, including but not limited to setting board operating parameters and reading board status information. Other I / O lines are mainly used to connect the CPU and external devices (such as hard drives, keyboards, and monitors) to achieve data transmission and control signal exchange between them. By partitioning and centrally arranging the buses on the backplane, the backplane hierarchy is clearly defined, facilitating backplane wiring during subsequent use. Simultaneously, the configuration resistors are uniformly matched on the backplane, eliminating the need for individual matching on each function board, thus simplifying the work for installation and commissioning personnel. Furthermore, the unified configuration of switches on the backplane eliminates the need to send board IDs via software or modify resistors on individual function boards, allowing for flexible switch configuration based on actual usage needs, greatly enhancing ease of use.

[0037] refer to Figure 3 This is a schematic diagram of the backplane slot bus arrangement provided in an embodiment of the present invention.

[0038] Figure 3 The diagram shows the bus arrangement of any slot on the backplane according to an embodiment of the present invention. The slots are divided into different areas based on the function of different buses, including a power bus area, a communication bus area, a configuration bus area, and other I / O line areas. Specifically, the power bus area is divided into a power bus negative terminal and a power bus positive terminal; the input and output terminals of the communication bus are respectively connected to a first configuration resistor and a second configuration resistor; the configuration bus is connected to a configuration switch. The pin definitions of other slots on the backplane adopt the same method, ensuring that various types of boards can be inserted into any slot, thereby achieving flexible configuration and efficient interchangeability of functional boards.

[0039] refer to Figure 4 This is a schematic diagram of the pulse acquisition and CAN communication circuit provided in an embodiment of the present invention.

[0040] Figure 4The diagram shows a pulse acquisition and CAN communication circuit provided in an embodiment of the present invention, including: an I2C bus counter, a bus buffer, a first CAN transceiver, and a second CAN transceiver; wherein, the I2C bus counter is connected to the bus buffer via a serial data line and a serial clock line; the bus buffer is connected to the first CAN transceiver via a first data transmission line and to the second CAN transceiver via a second data transmission line; the first CAN transceiver is connected to the backplane via a first CAN bus; and the second CAN transceiver is connected to the backplane via a second CAN bus.

[0041] Specifically, the clock pulse signal first enters the I2C bus counter, which is responsible for accurately acquiring these signals and converting them into digital signals. Subsequently, the I2C bus counter sends the acquired data to the bus buffer through the two signal lines of the I2C bus—SCL (serial clock line) and SDA (serial data line). The bus buffer acts as a data relay and signal amplification device, ensuring that the data remains intact and stable during transmission. When the data arrives at the bus buffer, it is quickly forwarded to the CAN transceiver. The CAN transceiver is an interface device for CAN bus communication. It can convert the I2C bus data format to the CAN bus data format and achieve electrical isolation and signal amplification to ensure reliable data transmission on the CAN bus. Two CAN bus transceivers (corresponding to the first CAN transceiver and the second CAN transceiver, respectively) send the processed data to the CAN data interface on the backplane in high and low levels, respectively. In this way, the main control board can receive clock pulse data acquired by the clock pulse signal acquisition circuit via the CAN bus, thereby realizing precise time control and synchronization of the entire board system. The whole process realizes a complete link from clock pulse signal acquisition, processing to transmission, ensuring the accuracy and real-time performance of the data.

[0042] refer to Figure 5 This is a schematic diagram of the pulse acquisition and CAN communication circuit provided in an embodiment of the present invention.

[0043] As an optional embodiment, the I2C bus counter includes a reset signal input terminal, an external clock pulse signal input terminal, a serial data line output terminal, and a serial clock line input terminal. The I2C bus counter is used to: receive a reset signal through the reset signal input terminal; in response to the reset signal being low, control the count to reset to 0; in response to the reset signal being high, start the increment counting of the number of pulses for the external clock pulse signal; receive an external clock pulse signal through the external clock pulse signal input terminal; in response to the external clock pulse signal changing from low to high, increment the count of the number of pulses for the external clock pulse signal by 1; send the pulse count to the serial data line for transmission through the serial data line output terminal; and receive a timing signal sent by the bus buffer through the serial clock line input terminal; wherein, the timing signal is used to control the acquisition timing of the external clock pulse signal.

[0044] Specifically, such as Figure 5As shown, the I2C bus counter (X1) includes 8 pins: The RST (Reset) pin (X1-1) is the pin reset pin, used to receive a reset signal. When the reset signal is "L" (low level), it controls the counter to reset to 0. When the reset signal is "H" (high level), it starts the incrementing count of the number of pulses for the external clock pulse signal. The main function of the RST pin is to restore the device or system to its initial state or default settings. Through the RST function, some faults, errors, or configuration problems can be resolved, allowing the device to work normally again. The NC (Not Connected) pin (X1-2) is a non-connected pin and usually does not need to be connected to any external circuitry. The CLKIN (Clock Input) pin (X1-3) is the clock input pin, used to receive an external clock pulse signal. This clock pulse signal is usually periodic, and its frequency and phase determine the counter's counting rate and starting point. When the CLKIN input signal changes from "L" (low level) to "H" (high level), the counter counts by 1. VSS (Voltage Source) The Source (X1-4) pin is the circuit's ground pin or reference 0-level pin, providing ground potential and current loop for the circuit, which plays a crucial role in maintaining stable operation and performance reliability. The VDD (Voltage Drain) pin (X1-8) provides a stable operating voltage for the circuit, driving the various components in the circuit to operate normally. In this embodiment, the VDD voltage is preferably 5V. The SCL (Serial Clock Line) pin (X1-7) is the serial clock line input terminal on the I2C bus, generally used for synchronizing data transmission between devices. In this embodiment, the I2C bus counter receives the timing signal sent by the bus buffer through the serial clock line input terminal. The timing signal is used to control the acquisition timing of the external clock pulse signal. The SCL pin and the SDA (Serial Data Line) pin (X1-6) together realize serial communication between devices. The SDA pin (X1-6) is the serial data line input terminal, used for communication between the I2C bus counter and the bus buffer. Data is transmitted between the SDA pins. Normally, the data transmission between the SDA pins is bidirectional. In this embodiment of the invention, serial data is mainly sent from the output of the SDA pin of the I2C bus counter to the bus buffer, or it can be sent from the bus buffer to the I2C bus counter. The LOOP pin (X1-5) is the technical cycle mark output. In this embodiment of the invention, it can be a 24-bit counter with a counting range from 0 to 16,777,215. Whenever the value of the counter reaches 16,777,215 and returns to 0, the LOOP terminal will switch. It is usually used to record the number of pulses.

[0045] As an optional embodiment, the bus buffer includes an input terminal of a serial data line, an output terminal of a serial clock line, a transmitting terminal of a first data transmitting line, and a transmitting terminal of a second data transmitting line. The bus buffer is used to: receive the number of pulses transmitted by the serial data line through the input terminal of the serial data line, perform differential processing on the number of pulses to obtain a first differential pulse number and a second differential pulse number, transmit the first differential pulse number to the first data transmitting line through the transmitting terminal of the first data transmitting line, transmit the second differential pulse number to the second data transmitting line through the transmitting terminal of the second data transmitting line, and output a timing signal to the serial data line through the output terminal of the serial clock line for transmission.

[0046] Specifically, such as Figure 5 As shown, the bus buffer (X2) includes 8 pins: the SDA pin (X2-1) is the input terminal of the serial data line, used to receive the number of pulses transmitted by the serial data line through the input terminal of the serial data line, and to perform differential processing on the number of pulses to obtain the first differential pulse number and the second differential pulse number; the RX1 pin (X2-2) and TX1 pin (X2-3) can be collectively referred to as the transmitting terminal of the first data transmitting line, which is connected to the first CAN transceiver. The first differential pulse number is transmitted to the first data transmitting line through the transmitting terminal of the first data transmitting line for transmission; the GND (Ground) pin (X2-4) is the ground pin. In the circuit, GND is used to connect to the negative terminal of the external power supply to form the reference zero potential point in the circuit; VCC (Volt) The CurrentCondenser pin (X2-8) is used to connect to the positive terminal of the external power supply to provide the power required for the circuit to operate. In this embodiment of the invention, the VCC voltage is preferably 5V. The SCL pin (X2-7) is the output terminal of the serial clock line. The bus buffer can output timing signals to the serial data line for transmission through the output terminal of the serial clock line. The RX2 pin (X2-6) and the TX1 pin (X2-5) are collectively referred to as the second data transmission line bus, which is connected to the second CAN transceiver. The second differential pulse count is transmitted to the second data transmission line through the transmitting terminal of the second data transmission line for transmission.

[0047] As an optional embodiment, the first CAN transceiver includes a receiving end of a first data transmission line; the first CAN transceiver is configured to: receive a first differential pulse count transmitted by the first data transmission line through the receiving end of the first data transmission line, and transmit the first differential pulse count to a first CAN bus for transmission.

[0048] Specifically, such as Figure 5As shown, the first CAN transceiver (X3) includes 8 pins: TXD1 (X3-1) and RXD1 (X3-4) can be collectively referred to as the receiving end of the first data transmission line, which is connected to the bus buffer. The first CAN transceiver receives the first differential pulse count transmitted by the first data transmission line through the receiving end of the first data transmission line; CAN1H pin (X3-7) and CAN1L pin (X3-6) are the high-level signal pin and low-level signal pin of the CAN bus, respectively. In CAN communication, CAN1H and CAN1L together form a differential signal pair, which is used to send the first differential pulse count to the first CAN bus for transmission. This differential signal transmission method improves the anti-interference capability and reliability of communication; STB pin (X3-8) is usually used to control the working mode of the transceiver. In this embodiment of the invention, the STB pin is grounded, which is the normal working mode (also known as the high-speed mode). In this mode, the CAN transceiver can send and receive data through the CAN1H pin and CAN1L pin of the bus; the functions of the other pins are the same as those of the pins in the I2C bus counter or bus buffer mentioned above, and will not be described again here.

[0049] As an optional embodiment, the second CAN transceiver includes a receiving end of the second data transmission line; the second CAN transceiver is used to: receive the second differential pulse count transmitted by the second data transmission line through the receiving end of the second data transmission line, and send the second differential pulse count to the second CAN bus for transmission.

[0050] Specifically, such as Figure 5 As shown, the second CAN transceiver (X4) includes 8 pins: TXD2 (X4-1) and RXD2 (X4-4) can be collectively referred to as the receiving end of the second data transmission line, which is connected to the bus buffer. The second CAN transceiver receives the second differential pulse count transmitted by the second data transmission line through the receiving end of the second data transmission line; the CANH pin (X4-7) and CANL pin (X4-6) are the high-level signal pin and low-level signal pin of the CAN bus, respectively. In CAN communication, CANH and CANL together form a differential signal pair, which is used to send the second differential pulse count to the second CAN bus for transmission. This differential signal transmission method improves the anti-interference capability and reliability of communication; the STB pin (X4-8) is usually used to control the working mode of the transceiver. In this embodiment of the invention, the STB pin is grounded, which is the normal working mode (also known as the high-speed mode). In this mode, the CAN transceiver can send and receive data through the bus CANH pin and CANL pin; the functions of the other pins are the same as those of the pins in the I2C bus counter or bus buffer mentioned above, and will not be described again here.

[0051] As can be seen from the above, the pulse acquisition and CAN communication circuit provided by the embodiments of the present invention simplifies the hardware circuit design, eliminating the need for MCU communication and thus eliminating the need to develop embedded software. This not only reduces material costs in terms of hardware circuits but also reduces development and testing time costs in terms of software. At the same time, the application of pure hardware circuits can effectively improve the feasibility of system operation. In addition, the unified definition of interface pins makes the partitioning clear, the hierarchy distinct, and the wiring convenient. It allows functional boards to be used in non-fixed positions inside the chassis, and different arrangement methods can be adopted according to appearance, habits, functions, and other requirements. This not only reduces material costs but also reduces the possibility of errors during installation and debugging, providing great convenience for installation and debugging personnel.

[0052] It should be noted that the above description describes some embodiments of the present invention. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims may be performed in a different order than that shown in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0053] Based on the same inventive concept, corresponding to the pulse acquisition and CAN communication circuit provided in any of the above embodiments, the present invention also provides a backplane, including a power bus, a communication bus, a configuration bus and other I / O lines, wherein the communication bus connects to the pulse acquisition and CAN communication circuit, and the power bus, communication bus, configuration bus and other I / O lines are respectively provided with slots, which are used to connect functional boards with different functions, and functional boards with different functions can be mixed and matched between the slots.

[0054] Specifically, such as Figure 3 As shown, the slot is divided into multiple areas according to the functions of different buses, specifically including a power bus area, a communication bus area, a configuration bus area, and other I / O line areas. This bus partitioning arrangement not only provides a clear hierarchy but also centralizes functions, greatly facilitating wiring. Furthermore, the pin definitions of other slots on the backplane follow the same design philosophy.

[0055] In practical applications, function boards can connect to the corresponding buses on their slots via their onboard buses. If a function board does not have a bus corresponding to a specific area on the slot, the corresponding pins will remain unconnected. This design ensures that any type of function board can be flexibly inserted into each slot, enabling mixed-insertion functionality. Since the positions of the function boards are not fixed, they can be flexibly arranged according to actual needs, usage habits, functional divisions, and ease of debugging, greatly improving the system's versatility and flexibility. Simultaneously, this design effectively solves the problem of incorrect insertion during on-site installation and debugging, reducing installation and debugging risks and further enhancing the system's reliability and stability.

[0056] As an optional embodiment, the communication bus includes a first CAN bus receiving port, which is connected to a first CAN transceiver of the pulse acquisition and CAN communication circuit via the first CAN bus, and receives the first differential pulse number sent by the first CAN transceiver.

[0057] Specifically, such as Figure 3 As shown, pins 11 and 12 in the backplane communication bus can be the first CAN bus receiving port. The first CAN bus is connected to the first CAN transceiver of the pulse acquisition and CAN communication circuit, i.e., pins 11 and 12 and... Figure 4 Pins 7 and 6 of the first CAN transceiver (X3) are connected to receive the first differential pulse count transmitted by the first CAN transceiver. This data transmission method significantly enhances the data reception capability of the communication bus, enabling the backplane to acquire data information from the first CAN transceiver more quickly and accurately. At the same time, by adopting the differential pulse count transmission method, the backplane's resistance to external electromagnetic interference is improved, thereby ensuring the stability and reliability of the data transmission of the first CAN transceiver.

[0058] As an optional embodiment, the communication bus includes a second CAN bus receiving port, which is connected to a second CAN transceiver of the pulse acquisition and CAN communication circuit via the second CAN bus, and receives the second differential pulse number sent by the second CAN transceiver.

[0059] Specifically, such as Figure 3 As shown, pins 13 and 14 in the backplane communication bus can be the second CAN bus receiving port. The second CAN bus is connected to the first CAN transceiver of the pulse acquisition and CAN communication circuit, i.e., pins 11 and 12. Figure 4Pins 7 and 6 of the second CAN transceiver (X4) are connected to receive the second differential pulse count transmitted by the second CAN transceiver. This data transmission method significantly enhances the data reception capability of the communication bus, enabling the backplane to acquire data information from the second CAN transceiver more quickly and accurately. Simultaneously, by employing a differential pulse count transmission method, the backplane's resistance to external electromagnetic interference is improved, thereby ensuring the stability and reliability of the second CAN transceiver's data transmission.

[0060] As an optional embodiment, the backplane also includes a first configuration resistor and a second configuration resistor, the first configuration resistor being connected to the input terminal of the communication bus and the second configuration resistor being connected to the output terminal of the communication bus.

[0061] Specifically, such as Figure 3 As shown, the backplane is equipped with configuration resistors. There can be two sets of configuration resistors, each containing several resistors. The first configuration resistor can be connected to the input terminal of the communication bus, and the second configuration resistor can be connected to the output terminal of the communication bus. Connecting configuration resistors to the communication bus not only enables unified identification and matching of functional boards, but also achieves impedance matching and absorption of reflected signals, improves anti-interference capabilities, facilitates debugging and maintenance, adapts to different communication protocols and requirements, and optimizes signal transmission performance. In practical applications, a suitable resistor configuration scheme needs to be selected based on specific communication requirements and bus standards.

[0062] As an optional embodiment, the backplane also includes a configuration switch connected to an input of the configuration bus.

[0063] Specifically, such as Figure 3 As shown, the configuration switch is connected to the input terminal of the configuration bus. This not only enables the control or status change of external devices, but also allows for the implementation of complex control logic. For example, multiple switches can be combined, and different switch states can be encoded to correspond to different control commands or operating modes. During system startup or operation, it may be necessary to configure certain system parameters or modes or initialize the system using the switches. Furthermore, connecting the configuration switch to the bus input terminal also enables safety control functions to prevent accidental operation. Simultaneously, by connecting the configuration switch to the bus input terminal, input devices can be flexibly added or removed as needed, allowing the backplane to adjust the number of devices according to increasing or changing demands, making the system more intelligent and flexible in responding to changes in external signals and user needs.

[0064] According to an embodiment of the present invention, a backplane is provided that allows for flexible configuration by uniformly configuring switches on the backplane, and the state of these switches can be adjusted as needed. Simultaneously, the backplane eliminates the need for embedded software to verify board IDs, avoiding the need to change configuration resistors on any functional board. By setting configuration resistors on the backplane, unified matching of functions across all functional boards is achieved, eliminating the step of individually matching each functional board with the backplane, thus simplifying design and facilitating debugging. Furthermore, the backplane is functionally divided into power bus, communication bus, configuration bus, and other I / O line areas. This partitioned arrangement provides a clear hierarchy, which is beneficial for backplane wiring and the work of installation and debugging personnel.

[0065] The backplane of the above embodiments includes the corresponding pulse acquisition and CAN communication circuits in any of the foregoing embodiments, and has the beneficial effects of the corresponding pulse acquisition and CAN communication circuit embodiments, which will not be repeated here.

[0066] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this invention should have the ordinary meaning understood by those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of this invention do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word covers the element or object listed after the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0067] While the spirit and principles of the invention have been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for ease of description. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the appended claims is to be interpreted in the broadest sense, thereby encompassing all such modifications and equivalent structures and functions.

Claims

1. A pulse acquisition and CAN communication circuit, characterized in that, It includes an I2C bus counter, a bus buffer, a first CAN transceiver, and a second CAN transceiver; The I2C bus counter is connected to the bus buffer via a serial data line and a serial clock line. The bus buffer is connected to the first CAN transceiver via a first data transmission line and to the second CAN transceiver via a second data transmission line. The first CAN transceiver is connected to the backplane via the first CAN bus; The second CAN transceiver is connected to the backplane via the second CAN bus.

2. The pulse acquisition and CAN communication circuit according to claim 1, characterized in that, The I2C bus counter includes a reset signal input terminal, an external clock pulse signal input terminal, an output terminal of the serial data line, and an input terminal of the serial clock line; The I2C bus counter is used for: The system receives a reset signal through the reset signal input terminal. In response to the reset signal being low, the count is reset to 0. In response to the reset signal being high, the system starts incrementing the count of pulses for the external clock pulse signal. The external clock pulse signal is received through the external clock pulse signal input terminal. In response to the external clock pulse signal changing from low level to high level, the count of the pulses of the external clock pulse signal is incremented by 1. The pulse count is transmitted to the serial data line via the output terminal of the serial data line. The timing signal sent by the bus buffer is received through the input terminal of the serial clock line; wherein, the timing signal is used to control the acquisition timing of the external clock pulse signal.

3. The pulse acquisition and CAN communication circuit according to claim 2, characterized in that, The bus buffer includes the input terminal of the serial data line, the output terminal of the serial clock line, the transmitting terminal of the first data transmitting line, and the transmitting terminal of the second data transmitting line. The bus buffer is used for: The pulse count transmitted by the serial data line is received through the input terminal of the serial data line, and the pulse count is differentially processed to obtain a first differential pulse count and a second differential pulse count. The first differential pulse count is transmitted to the first data transmission line through the transmitting terminal of the first data transmission line, and the second differential pulse count is transmitted to the second data transmission line through the transmitting terminal of the second data transmission line. The timing signal is output from the output terminal of the serial clock line to the serial data line for transmission.

4. The pulse acquisition and CAN communication circuit according to claim 3, characterized in that, The first CAN transceiver includes a receiving end of the first data transmission line; The first CAN transceiver is used for: The receiver of the first data transmission line receives the first differential pulse count transmitted by the first data transmission line and sends the first differential pulse count to the first CAN bus for transmission.

5. The pulse acquisition and CAN communication circuit according to claim 3, characterized in that, The second CAN transceiver includes a receiving end of the second data transmission line; The second CAN transceiver is used for: The receiver of the second data transmission line receives the second differential pulse count transmitted by the second data transmission line and sends the second differential pulse count to the second CAN bus for transmission.

6. A backplate, characterized in that, It includes a power bus, a communication bus, a configuration bus, and other I / O lines. The communication bus is connected to the pulse acquisition and CAN communication circuit as described in any one of claims 1-4. The power bus, the communication bus, the configuration bus, and the other I / O lines each have a corresponding slot. The slots are used to connect function boards with different functions, and the function boards with different functions can be mixed and matched between the slots.

7. The backplate according to claim 6, characterized in that, The communication bus includes a first CAN bus receiving port, which is connected to the first CAN transceiver of the pulse acquisition and CAN communication circuit via the first CAN bus, and receives the first differential pulse number sent by the first CAN transceiver.

8. The backplate according to claim 6, characterized in that, The communication bus includes a second CAN bus receiving port, which is connected to the second CAN transceiver of the pulse acquisition and CAN communication circuit via the second CAN bus, and receives the second differential pulse number sent by the second CAN transceiver.

9. The backplate according to claim 6, characterized in that, It also includes a first configuration resistor and a second configuration resistor, the first configuration resistor being connected to the input terminal of the communication bus and the second configuration resistor being connected to the output terminal of the communication bus.

10. The backplate according to claim 6, characterized in that, It also includes a configuration switch, which is connected to the input of the configuration bus.

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