Starting time sequence control circuit and control chip

Abstract

The invention is suitable for the technical field of LED backlight driving, and provides a starting time sequence control circuit and a control chip. The starting time sequence control circuit comprises a switching module, a comparison module, a threshold adjusting module and a switch module, the comparison module is electrically connected with the switching module, the threshold adjusting module and the switch module, the switching module is electrically connected with the detection selection module and the error amplification module, and the comparison module is electrically connected with the feedback module. The threshold adjusting module is electrically connected with the logic driving module, and the switch module is electrically connected with the logic driving module and the control module. According to the starting time sequence control circuit provided by the embodiment of the invention, the error amplification module is configured as the unity gain buffer in the starting stage, and the error amplification module and the control module are connected to the closed loop when the output voltage is close to the target value; and the over-current protection threshold value is gradually increased through the threshold value adjusting module so as to relax the staged cooperative control logic of the current limitation, so that the stable rise of the output voltage is realized.

Description

Technical Field

[0001] This application belongs to the field of LED backlight driving technology, and in particular relates to a startup timing control circuit and control chip. Background Technology

[0002] LEDs (Light-Emitting Diodes), with their high brightness, low power consumption, and long lifespan, have become the core component of LCD (Liquid Crystal Display) backlight systems. The startup control performance of their driving circuits directly affects the system's safety and stability. Existing startup timing control circuits typically employ methods such as limiting the switching current of the power transistors, gradually increasing the current limit, or controlling the charging rate of the compensation capacitor. However, these methods may lead to overcharging of the inductor current during Boost startup. Summary of the Invention

[0003] This application provides a startup timing control circuit and control chip, which can solve the problem of inductor current overcharging during Boost startup.

[0004] In a first aspect, embodiments of this application provide a startup timing control circuit, including a switching module, a comparison module, a threshold adjustment module, and a switch module. The comparison module is electrically connected to the switching module, the threshold adjustment module, and the switch module, respectively. The switching module is electrically connected to a detection selection module and an error amplification module, respectively. The comparison module is electrically connected to a feedback module. The threshold adjustment module is electrically connected to a logic drive module. The switch module is electrically connected to the logic drive module and a control module, respectively. When the feedback voltage output by the feedback module is less than a preset voltage, the comparison module outputs a first comparison signal to the switching module, the threshold adjustment module, and the switch module; the switching module is used to turn on the first input terminal and the output terminal of the error amplification module according to the first comparison signal; the switch module is used to turn off according to the first comparison signal, thereby disconnecting the control module from the logic drive module; the threshold adjustment module is used to output an overcurrent protection signal to the logic drive module according to the first comparison signal, the reference signal, and the sampling signal. When the feedback voltage is greater than or equal to the preset voltage, the comparison module outputs a second comparison signal to the switching module, the threshold adjustment module, and the switch module; the switching module is used to turn on the first input terminal of the error amplification module and the detection selection module according to the second comparison signal; the switch module is used to turn on the control module and the logic drive module according to the second comparison signal; the threshold adjustment module is used to gradually increase the threshold of the overcurrent protection signal according to the second comparison signal, the reference signal, and the sampling signal.

[0005] In one possible implementation of the first aspect, the switching module includes a first transmission gate, a first end of which is electrically connected to a first input terminal of the error amplification module, a second end of which is electrically connected to the detection selection module, a third end of which is electrically connected to the output terminal of the error amplification module, and a control terminal of which is electrically connected to the comparison module. In one possible implementation of the first aspect, the comparison module includes a first comparator, a first input terminal of the first comparator being electrically connected to the feedback module, a second input terminal of the first comparator being used to receive the preset voltage, and an output terminal of the first comparator being electrically connected to the switching module, the threshold adjustment module, and the switch module, respectively. In one possible implementation of the first aspect, the threshold adjustment module includes a reference voltage generation unit, a current mirror unit, a first switching unit, a second switching unit, a third switching unit, an energy storage unit, and a comparison output unit. The current mirror unit is electrically connected to the reference voltage generation unit, the first switching unit, the third switching unit, the energy storage unit, and the comparison output unit, respectively. The comparison output unit is electrically connected to the second switching unit and the third switching unit, respectively. The reference voltage generating unit is used to provide a reference voltage signal to the current mirror unit; when the feedback voltage output by the feedback module is less than a preset voltage, the first switching unit is turned on, the second switching unit is turned on, and the third switching unit is turned off; the current mirror unit is used to output a first current to the comparison output unit according to the reference voltage signal; the comparison output unit is used to output an overcurrent protection signal to the logic driving module according to the first current, the node voltage, the reference signal, and the sampling signal; the node voltage is the voltage at the common terminal of the comparison output unit and the second switching unit. When the feedback voltage is greater than or equal to the preset voltage, the first switching unit is turned off, the second switching unit is turned off, and the third switching unit is turned on. The current mirror unit is used to output charging current to the energy storage unit according to the reference voltage signal. The energy storage unit is used to store energy according to the charging current, so that the node voltage gradually increases. In one possible implementation of the first aspect, the reference voltage generating unit includes a first resistor and a current source, a first end of the first resistor is electrically connected to the current mirror unit, a first end of the current source is electrically connected to a second end of the first resistor and the current mirror unit, and the second end of the current source is grounded. The current mirror unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The gate of the first transistor is electrically connected to the drain of the second transistor, the reference voltage generating unit, the gate of the third transistor, and the gate of the fifth transistor, respectively. The sources of the first transistor, the third transistor, and the fifth transistor are all electrically connected to the power supply. The drain of the first transistor is electrically connected to the source of the second transistor. The gate of the fourth transistor is electrically connected to the gate of the second transistor, the reference voltage generating unit, and the gate of the sixth transistor, respectively. The source of the fourth transistor is electrically connected to the drain of the third transistor. The drain of the fourth transistor is electrically connected to the first switching unit, the third switching unit, and the energy storage unit, respectively. The source of the sixth transistor is electrically connected to the drain of the fifth transistor. The drain of the sixth transistor is electrically connected to the comparison output unit. In one possible implementation of the first aspect, the first switching unit includes a first switching transistor, the gate of the first switching transistor is electrically connected to the comparison module, the drain of the first switching transistor is electrically connected to the current mirror unit, the third switching unit and the energy storage unit respectively, and the source of the first switching transistor is grounded. The second switching unit includes a second switching transistor, the gate of which is electrically connected to the comparison module, the source of which is electrically connected to the power supply, and the drain of which is electrically connected to the third switching unit and the comparison output unit, respectively. The third switching unit includes a third switching transistor and a fourth switching transistor. The gates of the third switching transistor and the fourth switching transistor are both electrically connected to the comparator module. The drain of the third switching transistor is electrically connected to the drain of the fourth switching transistor, the current mirror unit, the first switching unit, and the energy storage unit, respectively. The source of the third switching transistor is electrically connected to the source of the fourth switching transistor, the second switching unit, and the comparator output unit, respectively. In one possible implementation of the first aspect, the energy storage unit includes a first capacitor, a first terminal of which is electrically connected to the first switching unit, the third switching unit and the current mirror unit, respectively, and a second terminal of the first capacitor is grounded. In one possible implementation of the first aspect, the comparison output unit includes a fifth switch, a seventh transistor, an eighth transistor, a second resistor, a third resistor, and a second comparator. The gate of the fifth switch is electrically connected to the second switch unit and the third switch unit, respectively. The source of the fifth switch is electrically connected to the source of the seventh transistor, the source of the eighth transistor, and the current mirror unit, respectively. The drain of the fifth switch is electrically connected to the drain of the seventh transistor, the first terminal of the second resistor, and the first input terminal of the second comparator, respectively. The gate of the seventh transistor is used to receive the reference signal, the gate of the eighth transistor is used to receive the sampling signal, and the drain of the eighth transistor is electrically connected to the first terminal of the third resistor and the second input terminal of the second comparator, respectively. The output terminal of the second comparator is used to be electrically connected to the logic driving module, and the second terminals of the second resistor and the second terminals of the third resistor are both grounded.

[0006] In one possible implementation of the first aspect, the switch module includes a control switch, the control terminal of which is electrically connected to the comparison module, a first terminal of which is electrically connected to the control module, and a second terminal of which is electrically connected to the logic drive module. Secondly, embodiments of this application provide a control chip, including a detection and selection module, an error amplification module, a feedback module, a logic driving module, a first switch module, a control module, and a startup timing control circuit as described in any one of the first aspects. The detection and selection module and the error amplification module are both electrically connected to the switching module in the startup timing control circuit. The control module is electrically connected to the error amplification module, the first switch module, and the switch module in the startup timing control circuit. The logic driving module is electrically connected to the first switch module, the feedback module, the threshold adjustment module in the startup timing control circuit, and the switch module. The feedback module is electrically connected to the comparison module in the startup timing control circuit.

[0007] The beneficial effects of the embodiments in this application compared with the prior art are: The startup timing control circuit provided in this application includes a switching module, a comparison module, a threshold adjustment module, and a switching module. When the feedback voltage is less than a preset voltage, it indicates that the output voltage is low. At this time, the comparison module outputs a first comparison signal. The switching module turns on the first input and output terminals of the error amplification module according to the first comparison signal, that is, the error amplification module is configured as a unity-gain buffer, and the compensation capacitor can be charged by the first reference voltage received at the second input terminal of the error amplification module. Since the first reference voltage is less than the steady-state reference voltage, it can be ensured that the voltage at the output terminal of the error amplification module (i.e., the COMP voltage) starts from a lower voltage, thereby indirectly achieving a soft-start effect. During this process, the switching module is turned off, the threshold adjustment module outputs an overcurrent protection signal and transmits it to the logic drive module, which drives the first switching module to turn off, thereby increasing the output voltage of the Boost and causing the feedback voltage to gradually increase.

[0008] As the feedback voltage gradually increases, when it exceeds or equals the preset voltage, it indicates that the Boost's output voltage is approaching the target voltage. At this point, the comparator module outputs a second comparison signal. The switching module, based on this second comparison signal, activates the first input of the error amplifier and the detection selection module, thus connecting the error amplifier module to the loop and enabling it to operate in a closed-loop configuration. During this process, the switching module is activated, the control module is also connected to the loop, and the threshold adjustment module gradually increases the overcurrent protection signal threshold, causing the current limit to gradually loosen as the circuit stabilizes. This design effectively avoids sudden changes in COMP voltage caused by the charging and discharging characteristics of the compensation capacitor when the error amplifier module is connected to the loop, as well as the resulting sudden increase in duty cycle and inductor current surge, thereby ensuring a synchronous and stable rise in voltage and current.

[0009] Therefore, the startup timing control circuit provided in this application embodiment configures the error amplification module as a unity-gain buffer during the startup phase, uses a lower first reference voltage to charge the compensation capacitor to achieve COMP voltage soft start, combines a low threshold overcurrent protection signal to limit the current, and connects both the error amplification module and the control module to the closed loop when the output voltage approaches the target value. The phased collaborative control logic, which gradually increases the overcurrent protection threshold through the threshold adjustment module to relax the current limit, effectively solves the problem of inductor current overcharging that may occur during Boost startup and achieves a smooth rise in output voltage. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the application circuit of an existing LED backlight driver start-up control scheme; Figure 2 This is a schematic diagram of the chip circuit for an existing LED backlight driver startup control scheme. Figure 3 This is the internal block diagram of the existing adaptive control Boost; Figure 4 This is a schematic diagram of a startup timing control circuit provided in an embodiment of this application; Figure 5 This is a circuit connection diagram of a startup timing control circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of a threshold adjustment module provided in an embodiment of this application; Figure 7 This is a circuit connection diagram of a threshold adjustment module provided in an embodiment of this application; Figure 8 This is a schematic flowchart of the startup timing control provided in an embodiment of this application.

[0012] In the diagram: 101, Switching module; 102, Comparison module; 103, Threshold adjustment module; 1031, Reference voltage generation unit; 1032, Current mirror unit; 1033, First switching unit; 1034, Second switching unit; 1035, Third switching unit; 1036, Energy storage unit; 1037, Comparison output unit; 104, Switching module; 100, Detection selection module; 200, Error amplification module; 300, Feedback module; 400, Logic drive module; 500, Control module; 600, First switching module. Detailed Implementation

[0013] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0014] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0015] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0016] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0017] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0018] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0019] like Figure 1 As shown, a common application circuit uses a boost converter to increase the input voltage and then drive LED strings. The number of strings varies from 1 to 6 depending on the application, with each string containing 6 to 10 LEDs. For example... Figure 2As shown, traditional LED backlight driver startup schemes typically send the minimum value of the LED's headroom voltage (CH1~CH6) to the input of the Boost error amplifier, and then adjust the Boost's output voltage. The Boost usually employs asynchronous rectification, using an external Schottky diode and an internally integrated N-type pull-down transistor. Due to the characteristics of the LED load, when the Boost output voltage is insufficient to turn on the LED, the voltages of CH1~CH6 are essentially equal to ground. If the Boost loop is not controlled, it will continuously operate at its maximum duty cycle, resulting in excessive inductor current, causing whistling or device burnout.

[0020] Another common method for controlling the voltages of LEDs CH1~CH6 involves internally setting two threshold voltages, LOW_REF and MID_REF. A comparator compares CH1~CH6 with LOW_REF and MID_REF. If any voltage of CH1~CH6 falls below LOW_REF, the Boost output voltage increases, with the adjustment step size and adjustment time set by an internal register. When all voltages of CH1~CH6 are above MID_REF, the Boost output voltage decreases. The ultimate goal is to limit the lowest values ​​of CH1~CH6 to between LOW_REF and MID_REF. The internal implementation of the Boost is as follows... Figure 3 As shown, an internal resistor string is used to detect the VBOOST voltage, and the rise and fall of the VBOOST voltage is adjusted by regulating the magnitude of the active load current.

[0021] In summary, existing startup timing control circuits typically employ methods such as limiting the switching current of the power transistor, gradually increasing the current limit, or controlling the charging rate of the compensation capacitor. However, these methods may lead to overcharging of the inductor current during Boost startup.

[0022] Based on the above problems, the startup timing control circuit provided in this application includes a switching module, a comparison module, a threshold adjustment module, and a switching module. When the feedback voltage is less than a preset voltage, it indicates that the output voltage is low. At this time, the comparison module outputs a first comparison signal. The switching module turns on the first input and output terminals of the error amplification module according to the first comparison signal, that is, the error amplification module is configured as a unity-gain buffer, and the compensation capacitor can be charged by the first reference voltage received at the second input terminal of the error amplification module. Since the first reference voltage is less than the steady-state reference voltage, it can be ensured that the voltage at the output terminal of the error amplification module (i.e., the COMP voltage) starts from a lower voltage, thereby indirectly achieving a soft-start effect. During this process, the switching module is turned off, the threshold adjustment module outputs an overcurrent protection signal and transmits it to the logic drive module, which drives the first switching module to turn off, thereby increasing the output voltage of the Boost and causing the feedback voltage to gradually increase.

[0023] As the feedback voltage gradually increases, when it exceeds or equals the preset voltage, it indicates that the Boost's output voltage is approaching the target voltage. At this point, the comparator module outputs a second comparison signal. The switching module, based on this second comparison signal, activates the first input of the error amplifier and the detection selection module, thus connecting the error amplifier module to the loop and enabling it to operate in a closed-loop configuration. During this process, the switching module is activated, the control module is also connected to the loop, and the threshold adjustment module gradually increases the overcurrent protection signal threshold, causing the current limit to gradually loosen as the circuit stabilizes. This design effectively avoids sudden changes in COMP voltage caused by the charging and discharging characteristics of the compensation capacitor when the error amplifier module is connected to the loop, as well as the resulting sudden increase in duty cycle and inductor current surge, thereby ensuring a synchronous and stable rise in voltage and current.

[0024] Therefore, the startup timing control circuit provided in this application embodiment configures the error amplification module as a unity-gain buffer during the startup phase, uses a lower first reference voltage to charge the compensation capacitor to achieve COMP voltage soft start, combines a low threshold overcurrent protection signal to limit the current, and connects both the error amplification module and the control module to the closed loop when the output voltage approaches the target value. The phased collaborative control logic, which gradually increases the overcurrent protection threshold through the threshold adjustment module to relax the current limit, effectively solves the problem of inductor current overcharging that may occur during Boost startup and achieves a smooth rise in output voltage.

[0025] To illustrate the technical solution described in this application, specific embodiments are provided below.

[0026] Figure 4 A schematic diagram of a startup timing control circuit according to an embodiment of this application is shown. See also... Figure 4As shown, the startup timing control circuit includes a switching module 101, a comparison module 102, a threshold adjustment module 103, and a switch module 104. The comparison module 102 is electrically connected to the switching module 101, the threshold adjustment module 103, and the switch module 104, respectively. The switching module 101 is electrically connected to the detection selection module 100 and the error amplification module 200, respectively. The comparison module 102 is electrically connected to the feedback module 300. The threshold adjustment module 103 is electrically connected to the logic drive module 400, and the switch module 104 is electrically connected to the logic drive module 400 and the control module 500, respectively.

[0027] Specifically, when the feedback voltage VFB is less than the preset voltage Vref2, it indicates that the output voltage VOUT is low. At this time, the comparison module 102 outputs a first comparison signal. The switching module 101 turns on the first input and output terminals of the error amplification module 200 according to the first comparison signal, that is, the error amplification module 200 is configured as a unity-gain buffer, and the compensation capacitor can be charged by the first reference voltage Vref1 received at the second input terminal of the error amplification module 200. Since the first reference voltage Vref1 is less than the steady-state reference voltage, it can be ensured that the voltage at the output terminal of the error amplification module 200 (i.e., the COMP voltage) starts from a lower voltage, thereby indirectly achieving a soft-start effect. During this process, the switching module 104 is turned off, the threshold adjustment module 103 outputs an overcurrent protection signal OCP and transmits it to the logic drive module 400, which drives the first switching module 600 to turn off, thereby increasing the output voltage VOUT of the Boost, and causing the feedback voltage VFB to gradually increase.

[0028] As the feedback voltage VFB gradually increases, when VFB is greater than or equal to the preset voltage Vref2, it indicates that the Boost output voltage VOUT is close to the target voltage (e.g., the output voltage VOUT is 2.5V lower than the target voltage). At this time, the comparison module 102 outputs a second comparison signal. The switching module 101 turns on the first input terminal of the error amplifier EA and the detection selection module 100 according to the second comparison signal, that is, the error amplifier module 200 is connected to the loop, so that it starts to work in a closed-loop form. During this process, the switching module 104 is turned on, the control module 500 is also connected to the loop, and the threshold adjustment module 103 gradually increases the threshold of the overcurrent protection signal OCP, so that the current limit is gradually relaxed as the circuit stabilizes. This design can effectively avoid the COMP voltage change that may be caused by the charging and discharging characteristics of the compensation capacitor when the error amplifier module 200 is connected to the loop, as well as the resulting sudden increase in duty cycle and inductor current surge, thereby ensuring that the voltage and current rise synchronously and smoothly.

[0029] Therefore, the startup timing control circuit provided in this application embodiment effectively solves the problem of inductor current overcharging that may occur during Boost startup, and achieves a smooth rise in output voltage VOUT by configuring the error amplification module 200 as a unity-gain buffer during the startup phase, charging the compensation capacitor with a lower first reference voltage Vref1, achieving COMP voltage soft start, combining the low threshold overcurrent protection signal OCP to limit the current, and connecting both the error amplification module 200 and the control module 500 into the closed loop when the output voltage VOUT approaches the target value, and gradually increasing the overcurrent protection threshold through the threshold adjustment module 103 to relax the current limit in a phased collaborative control logic.

[0030] It should be noted that during the startup phase, the error amplification module 200 is configured as a unity-gain buffer. The compensation capacitor is charged using a lower first reference voltage Vref1, ensuring that the output voltage (i.e., the COMP voltage) of the error amplification module 200 starts from a lower voltage (since the bandwidth of the Boost circuit is typically not large, a large capacitor is connected to the COMP terminal, and the transconductance of the error amplification module 200 is also relatively small), thus indirectly achieving a soft-start effect. However, soft-start is not always effective, especially when a large resistor is connected in series with the compensation capacitor (to obtain a faster response speed). When the error amplification module 200 is connected from the unity buffer to the Boost loop, the current generated by the error amplification module 200 flowing through the compensation resistor causes a sudden change in the COMP voltage, resulting in a sharp increase in the Boost duty cycle and consequently a rapid increase in the inductor current. Therefore, this application adds a threshold adjustment module 103, which gradually increases the threshold of the overcurrent protection signal OCP as the output voltage VOUT approaches the target voltage, gradually relaxing the current limit as the circuit stabilizes.

[0031] It should be noted that when using this circuit for actual control, the control module 500 needs to be electrically connected to the error amplifier module 200 and the first switch module 600 respectively, and the logic drive module 400 needs to be electrically connected to the first switch module 600 and the feedback module 300 respectively. The detection selection module 100 can detect the voltage at the output terminals of multiple LED strings and output the detection voltage to the switching module 101. The connection status of each LED string can be confirmed by judging whether the value of the first voltage is within the preset range. If the voltage at the output terminal of each LED string is within the preset range, it indicates that all LED strings are connected normally. At this time, the switching module 101 turns on the first input terminal and the output terminal of the error amplifier module 200, that is, the error amplifier module 200 is configured as a unity-gain buffer, and the first reference voltage Vref1 received by the second input terminal of the error amplifier module 200 is used to charge the compensation capacitor to obtain the COMP voltage. The feedback module 300 outputs a feedback voltage VFB to the comparison module 102 based on the output voltage VOUT. When the feedback voltage VFB is less than the preset voltage Vref2, the logic drive module 400 outputs a drive signal to the first switch module 600 based on the oscillation signal OSC, the feedback signal, and the overcurrent protection signal OCP, so that the first switch module 600 is turned off, thereby increasing the output voltage VOUT of the Boost and causing the feedback voltage VFB to gradually increase.

[0032] Since the switch module 104 is turned off during the startup phase, and the control module 500 and the logic drive module 400 are not connected, the control module 500 will not output control signals to the logic drive module 400, thereby controlling the turn-on and turn-off timing of the first switch module 600.

[0033] It should be noted that the detection selection module 100 may include LED open-circuit detection and minimum LED selection. LED open-circuit detection is used to monitor the connection status of each LED string in real time. Specifically, by detecting abnormal changes in the voltage at the output terminals of the LED strings (such as a sudden rise in voltage to near the Boost output voltage VOUT), it determines whether the corresponding LED string has an open-circuit or short-circuit fault, providing a basis for subsequent fault protection and preventing circuit abnormalities caused by open or short circuits. Minimum LED selection is used to select the minimum value from the output voltages of multiple LED strings and transmit it to the error amplification module 200. This is because the voltage at the minimum output terminal of the LED string directly reflects the state of the string that most needs the Boost output voltage VOUT to be increased. If this minimum value is greater than the set value, it means that the voltage of all LED strings is greater than the set value. It's important to note that due to the large size of the compensation capacitor, the design must ensure that the charging completion time of COMP is less than the rise time of the output voltage VOUT. This can be achieved by increasing the charging current capability of the error amplifier module 200, or by waiting for a period of time after the Boost output voltage VOUT rises, to ensure that the COMP voltage reaches the design target. That is, after ensuring that the Boost output voltage VOUT is sufficient to activate the current ramp of the LED string (the LED string current increases from zero to the target value), the voltage may have just reached the threshold and is not yet fully stable. Therefore, it is necessary to wait for a preset time (e.g., 4 milliseconds) to ensure that the Boost output voltage VOUT further stabilizes under closed-loop control and that the charge distribution of the compensation capacitor tends to be balanced. Only then can the current ramp be activated, allowing the Boost to more stably support the LED current demand and preventing the current output from deviating from the preset pattern (such as linear or exponential characteristics) due to voltage fluctuations.

[0034] The following is combined Figure 5 The specific implementation methods of the error amplification module 200, control module 500, logic drive module 400, first switch module 600, feedback module 300 and comparison module 102 are described in detail.

[0035] like Figure 5 As shown, the error amplification module 200 includes an error amplifier EA. The first input terminal of the error amplifier EA is electrically connected to the switching module 101. The second input terminal of the error amplifier EA is used to receive the first reference voltage Vref1. The output terminal of the error amplifier EA is electrically connected to the control module 500 and the switching module 101, respectively.

[0036] Specifically, the inverting input of error amplifier EA serves as the first input, and the non-inverting input serves as the second input, used to receive the first reference voltage Vref1. During the Boost enable phase, switching module 101 directly connects the inverting input of error amplifier EA to its output (COMP terminal), configuring error amplifier EA as a unity-gain buffer. At this time, the first reference voltage Vref1 received by the non-inverting input directly drives the compensation capacitor to charge through the buffer. Upon entering the switching phase, switching module 101 disconnects the inverting input from the COMP terminal and connects it to the output of detection selection module 100. At this time, both error amplifier EA and control module 500 are connected to a closed-loop control circuit. The non-inverting input of error amplifier EA still receives the first reference voltage Vref1, while the inverting input receives the detection voltage. Error amplifier EA adjusts the COMP voltage by comparing the difference between the two. Control module 500 outputs a control signal to logic drive module 400 based on the COMP voltage, ultimately achieving the goal of controlling the Boost output voltage VOUT to match the changes in LED string current in real time.

[0037] like Figure 5 As shown, the control module 500 includes a first operational amplifier, a PWM (Pulse Width Modulation) controller, an accumulator, and a slope compensation. The negative input terminal of the first operational amplifier is electrically connected to the output terminal of the accumulator, and the positive input terminal of the first operational amplifier is electrically connected to the output terminal of the error amplifier EA for receiving a reference voltage. The output terminal of the first operational amplifier is electrically connected to the PWM controller. The first input terminal of the accumulator is electrically connected to the first switching module 600, and the second input terminal of the accumulator is electrically connected to the slope compensation. The slope compensation is used to receive the oscillation signal OSC output by the oscillator.

[0038] Specifically, the accumulator is used to accumulate the compensation signal output by the ramp compensation and the current signal flowing through the first switching module 600, and outputs the accumulated signal to the negative input terminal of the first operational amplifier. The first operational amplifier outputs a first operational amplifier signal to the PWM controller based on the accumulated signal and the reference signal. The PWM controller outputs a PWM signal based on the first operational amplifier signal.

[0039] It should be noted that since the design of the control module 500 is a conventional design architecture for switching power supplies, this type of design is relatively mature in the field of switching power supplies, and the relevant principles are in line with the conventional design logic of the industry, so it will not be elaborated on here.

[0040] like Figure 5 As shown, the logic driving module 400 includes an OR gate and a first flip-flop. The first input of the OR gate is electrically connected to the threshold adjustment module 103, the second input of the OR gate is electrically connected to the feedback module 300, the third input of the OR gate is electrically connected to the switch module 104, the output of the OR gate is electrically connected to the first input of the first flip-flop, the second input of the first flip-flop is used to receive the oscillation signal OSC, and the output of the first flip-flop is electrically connected to the first switch module 600.

[0041] Specifically, during the Boost startup phase, the first input of the OR gate receives the overcurrent protection signal OCP, and the second input receives the feedback signal. The OR gate outputs a first logic signal to the first input of the first flip-flop based on the overcurrent protection signal OCP and the feedback signal. The first flip-flop outputs a first drive signal based on the first logic signal and the oscillation signal OSC to turn off the first switching module 600. During the switching phase, the first input of the OR gate receives the PWM signal output by the PWM controller. The OR gate outputs a second logic signal to the first input of the first flip-flop based on the PWM signal, the feedback signal, and the overcurrent protection signal OCP. The first flip-flop outputs a second drive signal based on the second logic signal and the oscillation signal OSC to turn the first switching module 600 on or off.

[0042] It should be noted that a driver is also provided between the first trigger and the first switch module 600 to improve the driving capability of the first switch module 600.

[0043] For example, the first trigger may be an RS trigger.

[0044] like Figure 5 As shown, the first switching module 600 includes a lower switching transistor Q1. The gate of the lower switching transistor Q1 is electrically connected to the logic driving module 400. The drain of the lower switching transistor Q1 is used to be electrically connected to the anode of the inductor and the diode in the Boost circuit, respectively. The source of the lower switching transistor Q1 is grounded through a resistor.

[0045] Specifically, the lower switch Q1 acts as a switching device, used to turn on or off according to the drive signal received at the gate. During the Boost startup phase, the lower switch Q1 turns off according to the first drive signal, causing the Boost output voltage VOUT to rise. During the switching phase, the lower switch Q1 turns on or off according to the second drive signal to adjust the Boost output voltage VOUT to match the current ramp requirements of the LED string.

[0046] For example, designers can select the type of the lower switch Q1 according to the actual situation, that is, they can use fully controllable power devices such as metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors. For example, the lower switch Q1 can be selected as an NMOS transistor.

[0047] like Figure 5 As shown, the feedback module 300 includes two voltage divider resistors and a feedback comparator. The positive input terminal of the feedback comparator is connected to the common terminal of the two voltage divider resistors, the negative input terminal of the feedback comparator is used to receive a reference value (1.2V), and the output terminal of the feedback comparator is used to output a feedback signal.

[0048] Specifically, two voltage divider resistors are used to divide the output voltage VOUT and transmit the divided voltage (feedback voltage VFB) to the feedback comparator. The feedback comparator compares the divided voltage with the 1.2V voltage and outputs a feedback signal.

[0049] like Figure 5 As shown, the comparison module 102 includes a first comparator CMP1. The first input terminal of the first comparator CMP1 is electrically connected to the feedback module 300. The second input terminal of the first comparator CMP1 is used to receive a preset voltage Vref2. The output terminal of the first comparator CMP1 is electrically connected to the switching module 101, the threshold adjustment module 103 and the switch module 104 respectively.

[0050] Specifically, the positive input of the first comparator CMP1 is used to receive the feedback voltage VFB, and the negative input of the first comparator CMP1 is used to receive the preset voltage Vref2. The first comparator CMP1 is used to compare the feedback voltage VFB and the preset voltage Vref2. When the feedback voltage VFB is less than the preset voltage Vref2, it indicates that the output voltage VOUT is low, and the first comparator CMP1 outputs a first comparison signal, i.e., VBOOST_OK=0; when the feedback voltage VFB is greater than or equal to the preset voltage Vref2, it indicates that the output voltage VOUT is close to the target voltage, and the first comparator CMP1 outputs a second comparison signal, i.e., VBOOST_OK=1.

[0051] In one embodiment of this application, the switching module 101 includes a first transmission gate, the first end of which is electrically connected to the first input end of the error amplification module 200, the second end of which is electrically connected to the detection selection module 100, the third end of which is electrically connected to the output end of the error amplification module 200, and the control end of which is electrically connected to the comparison module 102.

[0052] Specifically, by receiving the first comparison signal and the second comparison signal, the first transmission gate can switch between two states. Specifically, during the Boost startup phase, the first transmission gate receives the first comparison signal and connects the output terminal and the inverting input terminal of the error amplifier EA, forming a unity-gain buffer, allowing the error amplifier EA to establish the COMP voltage at a lower voltage in open-loop mode. During the switching phase, the first transmission gate receives the second comparison signal and connects the detection selection module 100 to the inverting input terminal of the error amplifier EA, causing the error amplifier EA to enter a closed-loop control state, adjusting the COMP voltage based on the detected voltage and the first reference voltage Vref1.

[0053] In one embodiment of this application, the switch module 104 includes a control switch, the control terminal of which is electrically connected to the comparison module 102, the first terminal of which is electrically connected to the control module 500, and the second terminal of which is electrically connected to the logic drive module 400. Specifically, the control switch can be turned on or off based on the received first and second comparison signals. Specifically, during the Boost startup phase, the control switch receives the first comparison signal, turns off, and the PWM signal cannot be transmitted to the logic driver module 400. The logic driver module 400 then drives the first switch module 600 to turn off. During the switching phase, the control switch receives the second comparison signal, turns on, and the PWM signal can be transmitted to the logic driver module 400 to control the switching timing of the first switch module 600. This allows the Boost output voltage VOUT to be dynamically adjusted according to the LED string current ramp requirements, achieving precise control of the LED string current. Through this switching, the system achieves overcurrent protection during startup and restores the normal control loop during switching, ensuring the safety and stability of the Boost circuit under different operating conditions.

[0054] The following is combined Figure 6 and Figure 7 The working principle of the threshold adjustment module 103 is described in detail.

[0055] In one embodiment of this application, such as Figure 6 As shown, the threshold adjustment module 103 includes a reference voltage generation unit 1031, a current mirror unit 1032, a first switch unit 1033, a second switch unit 1034, a third switch unit 1035, an energy storage unit 1036, and a comparison output unit 1037. The current mirror unit 1032 is electrically connected to the reference voltage generation unit 1031, the first switch unit 1033, the third switch unit 1035, the energy storage unit 1036, and the comparison output unit 1037, respectively. The comparison output unit 1037 is electrically connected to the second switch unit 1034 and the third switch unit 1035, respectively.

[0056] Specifically, the reference voltage generation unit 1031 provides a reference voltage signal to the current mirror unit 1032. When the feedback voltage VFB is less than the preset voltage Vref2, the comparison module 102 outputs a first comparison signal, i.e., VBOOST_OK=0. At this time, the first switching unit 1033 is turned on, the second switching unit 1034 is turned on, and the third switching unit 1035 is turned off. The current mirror unit 1032 is used to output a first current to the comparison output unit 1037 based on the reference voltage signal. The comparison output unit 1037 is used to output an overcurrent protection signal OCP to the logic drive module 400 based on the first current, the node voltage (P-point voltage), the reference signal VREF, and the sampling signal Vs. When the feedback voltage VFB is greater than or equal to the preset voltage Vref2, the comparison module 102 outputs a second comparison signal, i.e., VBOOST_OK=1. At this time, the first switch unit 1033 is turned off, the second switch unit 1034 is turned off, the third switch unit 1035 is turned on, and the current mirror unit 1032 is used to output charging current to the energy storage unit 1036 according to the reference voltage signal. The energy storage unit 1036 is used to store energy according to the charging current, so that the node voltage gradually increases.

[0057] In one embodiment of this application, such as Figure 7 As shown, the reference voltage generating unit 1031 includes a first resistor R1 and a current source. The first end of the first resistor R1 is electrically connected to the current mirror unit 1032. The first end of the current source is electrically connected to the second end of the first resistor R1 and the current mirror unit 1032, respectively. The second end of the current source is grounded.

[0058] Specifically, the current source can provide a stable current. The current output by the current source flows through the first resistor R1. Based on Ohm's law, a certain voltage drop will be generated across the first resistor R1. This voltage drop is used as a reference voltage signal and is transmitted to the current mirror unit 1032.

[0059] In one embodiment of this application, such as Figure 7 As shown, the current mirror unit 1032 includes a first transistor M20, a second transistor M21, a third transistor M22, a fourth transistor M23, a fifth transistor M24, and a sixth transistor M25. The gate of the first transistor M20 is electrically connected to the drain of the second transistor M21, the gate of the reference voltage generation unit 1031, the gate of the third transistor M22, and the gate of the fifth transistor M24, respectively. The sources of the first transistor M20, the third transistor M22, and the fifth transistor M24 are all electrically connected to the power supply VDD. The drain of the first transistor M20 is connected to... The source of the second transistor M21 is electrically connected. The gate of the fourth transistor M23 is electrically connected to the gate of the second transistor M21, the reference voltage generation unit 1031, and the gate of the sixth transistor M25, respectively. The source of the fourth transistor M23 is electrically connected to the drain of the third transistor M22. The drain of the fourth transistor M23 is electrically connected to the first switching unit 1033, the third switching unit 1035, and the energy storage unit 1036, respectively. The source of the sixth transistor M25 is electrically connected to the drain of the fifth transistor M24. The drain of the sixth transistor M25 is electrically connected to the comparator output unit 1037.

[0060] Specifically, the first transistor M20, the third transistor M22, and the fifth transistor M24 form a current mirror. Their gates are connected and connected to the drain of the reference voltage generation unit 1031 and the second transistor M21. Their sources are all connected to the power supply VDD. Through unified control of the gate voltage, the third transistor M22 and the fifth transistor M24 mirror the current characteristics of the first transistor M20, providing the subsequent circuit with an operating current proportional to the reference current. The second transistor M21, the fourth transistor M23, and the sixth transistor M25 form another current mirror. Through synchronous control of the gate voltage, the fourth transistor M23 and the sixth transistor M25 mirror the current characteristics of the second transistor M21.

[0061] Specifically, the third transistor M22 and the fourth transistor M23 output charging current to the energy storage unit 1036 when the first switching unit 1033 is off, the second switching unit 1034 is off, and the third switching unit 1035 is on, so that the energy storage unit 1036 charges and stores energy, and the node voltage gradually increases. The fifth transistor M24 and the sixth transistor M25 output a first current to the comparison output unit 1037 when the first switching unit 1033 is on, the second switching unit 1034 is on, and the third switching unit 1035 is off, providing a current reference for the generation of the overcurrent protection signal OCP. The precise matching of each transistor through the current mirror structure ensures the stable replication and on-demand allocation of the reference current, providing reliable support for the current control of the threshold adjustment module 103 in different operating stages.

[0062] For example, designers can select the types of the first transistor M20, the second transistor M21, the third transistor M22, the fourth transistor M23, the fifth transistor M24, and the sixth transistor M25 according to the actual situation. That is, all can be fully controllable power devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or insulated-gate bipolar transistors (IGBTs). For instance, the first transistor M20, the second transistor M21, the third transistor M22, the fourth transistor M23, the fifth transistor M24, and the sixth transistor M25 can all be selected as PMOS transistors.

[0063] In one embodiment of this application, such as Figure 7 As shown, the first switching unit 1033 includes a first switching transistor M29. The gate of the first switching transistor M29 is electrically connected to the comparator module 102. The drain of the first switching transistor M29 is electrically connected to the current mirror unit 1032, the third switching unit 1035 and the energy storage unit 1036 respectively. The source of the first switching transistor M29 is grounded.

[0064] Specifically, the first switching transistor M29 acts as a switching device, turning on or off according to the comparison signal (first comparison signal or second comparison signal) received at its gate. When the feedback voltage VFB is less than the preset voltage Vref2, the comparison module 102 outputs the first comparison signal, i.e., VBOOST_OK=0, and correspondingly, The first switching transistor M29 is turned on. When the feedback voltage VFB is greater than or equal to the preset voltage Vref2, the comparator module 102 outputs the second comparison signal, i.e., VBOOST_OK=1. Correspondingly, The first switch transistor M29 is turned off.

[0065] In one embodiment of this application, such as Figure 7 As shown, the second switching unit 1034 includes a second switching transistor M30. The gate of the second switching transistor M30 is electrically connected to the comparator module 102. The source of the second switching transistor M30 is electrically connected to the power supply VDD. The drain of the second switching transistor M30 is electrically connected to the third switching unit 1035 and the comparator output unit 1037, respectively.

[0066] Specifically, the second switch M30 acts as a switching device, turning on or off according to the comparison signal (first comparison signal or second comparison signal) received at its gate. When the feedback voltage VFB is less than the preset voltage Vref2, the comparison module 102 outputs the first comparison signal, i.e., VBOOST_OK=0. The second switch M30 is turned on, pulling the node voltage up to the power supply voltage VDD. When the feedback voltage VFB is greater than or equal to the preset voltage Vref2, the comparator module 102 outputs the second comparison signal, i.e., VBOOST_OK=1. The second switch M30 is turned off.

[0067] In one embodiment of this application, such as Figure 7 As shown, the third switching unit 1035 includes a third switching transistor M31 and a fourth switching transistor M32. The gates of the third switching transistor M31 and the fourth switching transistor M32 are both electrically connected to the comparator module 102. The drain of the third switching transistor M31 is electrically connected to the drain of the fourth switching transistor M32, the current mirror unit 1032, the first switching unit 1033, and the energy storage unit 1036, respectively. The source of the third switching transistor M31 is electrically connected to the source of the fourth switching transistor M32, the second switching unit 1034, and the comparator output unit 1037, respectively.

[0068] Specifically, both the third switch M31 and the fourth switch M32 function as switching devices, turning on or off based on the comparison signal (first comparison signal or second comparison signal) received at their gates. When the feedback voltage VFB is less than the preset voltage Vref2, the comparison module 102 outputs the first comparison signal, i.e., VBOOST_OK = 0. Both the third switch M31 and the fourth switch M32 are turned off. When the feedback voltage VFB is greater than or equal to the preset voltage Vref2, the comparator module 102 outputs the second comparison signal, i.e., VBOOST_OK=1. Both the third switch M31 and the fourth switch M32 are turned on, and the node voltage is determined by the voltage at the first terminal of the energy storage unit 1036.

[0069] In summary, the four switching transistors, in conjunction with the comparator module 102, precisely control the on / off state of the current path, ensuring that the threshold adjustment module 103 operates according to the expected logic under different feedback states, thereby achieving dynamic switching of the overcurrent protection threshold. For example, designers can select the types of the first switch M29, the second switch M30, the third switch M31, and the fourth switch M32 according to the actual situation; that is, all of them can be fully controlled power devices such as metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors. For example, the first switch M29 and the fourth switch M32 can be selected as NMOS transistors, and the second switch M30 and the third switch M31 can be selected as PMOS transistors.

[0070] In one embodiment of this application, such as Figure 7 As shown, the energy storage unit 1036 includes a first capacitor C0. The first end of the first capacitor C0 is electrically connected to the first switching unit 1033, the third switching unit 1035 and the current mirror unit 1032, respectively, and the second end of the first capacitor C0 is grounded.

[0071] Specifically, the first capacitor C0, as the core component of the energy storage unit 1036, mainly undertakes the functions of charge storage and voltage gradual change. When the feedback voltage VFB is less than the preset voltage Vref2, both the first switch M29 and the second switch M30 are turned on, while the third switch M31 and the fourth switch M32 are turned off. The voltage at the first terminal of the first capacitor C0 is pulled down to ground, and the node voltage is pulled up to the power supply voltage VDD, maintaining a high level, thus not affecting the output of the overcurrent protection signal OCP by the comparison output unit 1037 during the startup phase. When the feedback voltage VFB is greater than or equal to the preset voltage Vref2, both the first switch M29 and the second switch M30 are turned off, while the third switch M31 and the fourth switch M32 are turned on. The small current (charging current) flowing through the third transistor M22 and the fourth transistor M23 can charge the first capacitor C0, allowing it to gradually charge and store energy. The node voltage slowly increases with the accumulation of charge. This gradual increase in voltage, in conjunction with the comparator output unit 1037, is directly translated into a gradual increase in the overcurrent protection threshold, achieving a smooth transition from the startup phase to the steady-state phase. This avoids current surges that may be caused by sudden threshold changes and provides a crucial timing buffer for stable circuit startup.

[0072] In one embodiment of this application, such as Figure 7 As shown, the comparison output unit 1037 includes a fifth switch M26, a seventh transistor M27, an eighth transistor M28, a second resistor R2, a third resistor R3, and a second comparator CMP2. The gate of the fifth switch M26 is electrically connected to the second switch unit 1034 and the third switch unit 1035, respectively. The source of the fifth switch M26 is electrically connected to the source of the seventh transistor M27, the source of the eighth transistor M28, and the current mirror unit 1032, respectively. The drain of the fifth switch M26 is electrically connected to the drain of the seventh transistor M27, the first terminal of the second resistor R2, and the first input terminal of the second comparator CMP2, respectively. The gate of the seventh transistor M27 is used to receive the reference signal VREF, and the gate of the eighth transistor M28 is used to receive the sampling signal Vs. The drain of the eighth transistor M28 is electrically connected to the first terminal of the third resistor R3 and the second input terminal of the second comparator CMP2, respectively. The output terminal of the second comparator CMP2 is electrically connected to the logic drive module 400. The second terminals of the second resistor R2 and the second terminals of the third resistor R3 are both grounded.

[0073] Specifically, the fifth switch M26 acts as a switching device, turning on or off based on the node voltage received at its gate. When the feedback voltage VFB is less than the preset voltage Vref2, both the first switch M29 and the second switch M30 are turned on, while the third switch M31 and the fourth switch M32 are turned off. The node voltage is pulled up to the power supply voltage VDD and maintained at a high level, thus not affecting the output of the overcurrent protection signal OCP by the comparison output unit 1037 during the startup phase. When the feedback voltage VFB is greater than or equal to the preset voltage Vref2, both the first switch M29 and the second switch M30 are turned off, while the third switch M31 and the fourth switch M32 are turned on. The small current (charging current) flowing through the third transistor M22 and the fourth transistor M23 can charge the first capacitor C0, gradually charging it and storing energy. The node voltage slowly increases with the accumulation of charge, thereby gradually increasing the threshold of the overcurrent protection signal OCP.

[0074] The gate of the seventh transistor M27 receives the reference signal VREF (the reference voltage when OCP is operating normally), and the gate of the eighth transistor M28 receives the sampling signal Vs (the voltage converted from the sampling current of the power transistor flowing through the resistor). Their sources are connected and then connected to the sixth transistor M25, forming a current comparison branch based on the reference signal VREF and the sampling signal Vs. The current of the seventh transistor M27 corresponds to the reference signal VREF, and the current of the eighth transistor M28 corresponds to the sampling signal Vs. The second resistor R2 and the third resistor R3 are connected to the drains of the seventh transistor M27 and the eighth transistor M28, respectively, with their other ends grounded, converting the transistor currents into voltage signals. The second comparator CMP2 compares the sampling signal Vs with the reference signal VREF / node voltage (if the voltage of the reference signal VREF is less than the node voltage, the second comparator CMP2 compares the sampling signal Vs with the reference signal VREF; if the voltage of the reference signal VREF is greater than the node voltage, the second comparator CMP2 compares the sampling signal Vs with the node voltage), and outputs an overcurrent protection signal OCP to the logic driver module 400. By charging the first capacitor C0 with a small current through the third transistor M22 and the fourth transistor M23, the node voltage gradually increases, which allows the reference input of the second comparator CMP2 to gradually increase from 0.

[0075] For example, designers can select the types of the fifth switch M26, the seventh transistor M27, and the eighth transistor M28 according to the actual situation; that is, they can all be fully controllable power devices such as metal-oxide-semiconductor field-effect transistors or insulated-gate bipolar transistors. For instance, the fifth switch M26, the seventh transistor M27, and the eighth transistor M28 can all be selected as PMOS transistors.

[0076] It should be noted that, compared to the approach of gradually increasing the OCP threshold from the beginning, this application does not require the OCP threshold to be limited for a long time, because the output voltage VOUT is already very close to the target voltage. This makes the requirements for the value of the first capacitor C0 and the current of the third transistor M22 much more lenient.

[0077] The following is combined Figures 4 to 8 The principle and startup process of the startup timing control provided in the embodiments of this application are described in detail.

[0078] Phase 1: Pre-startup detection and protection (Boost not started, state preparation) After the LED backlight is powered on, it first loads the Efuse or MTP value. Once loading is complete (i.e., LOAD_OK), it enters the IDLE state.

[0079] Phase Two: Boost Start-up and COMP Voltage Precharge (Voltage Setup, Preparing for Ramp) The system enters the Boost startup phase (i.e., EN_BST=1). When the feedback voltage VFB is less than the preset voltage Vref2, that is, the voltage of VBOOST is lower than the internally set threshold, the comparison module 102 outputs the first comparison signal, i.e., VBOOST_OK=0. Under the action of the first comparison signal, the switching module 101 connects the inverting input terminal of the error amplifier module 200 to its output terminal through the first transmission gate, so that the error amplifier EA is configured as a unity-gain buffer. At this time, the non-inverting input terminal of the error amplifier EA receives the first reference voltage Vref1 (lower than the steady-state reference voltage). The compensation capacitor is charged through this low reference voltage to ensure that the COMP voltage is established from a lower voltage, thereby indirectly achieving the soft-start effect. At the same time, the switching module 104 is turned off, the threshold adjustment module 103 outputs the overcurrent protection signal OCP and transmits it to the logic drive module 400. The logic drive module 400 drives the first switching module 600 to turn off, thereby increasing the output voltage VOUT of the Boost, which in turn drives the feedback voltage VFB to gradually increase.

[0080] Phase 3: Loop switching and current ramp start-up (LED string conduction, current ramp) As the Boost output voltage VOUT and feedback voltage VFB increase, when the feedback voltage VFB is greater than or equal to the preset voltage Vref2, it indicates that the Boost output voltage VOUT is close to the target voltage (e.g., the output voltage VOUT is 2.5V lower than the target voltage). At this time, the comparator module 102 outputs a second comparator signal, i.e., VBOOST_OK=1. Under the action of the second comparator signal, the switching module 101 disconnects the connection between the inverting input and output of the error amplifier EA and connects it to the output of the detection selection module 100. That is, the error amplifier EA switches from unity-gain buffer mode to closed-loop control mode. At the same time, the switching module 104 is turned on, the control module 500 is also connected to the loop, and the threshold adjustment module 103 gradually increases the threshold of the overcurrent protection signal OCP, so that the current limit is gradually relaxed as the circuit stabilizes. After waiting for a fixed period of time (e.g., 4ms), the LED current ramp begins.

[0081] Phase 4: Steady-state switching and normal operation (current meets standards, stable output) When the LED string current reaches the target current, the redundancy of the Boost output voltage VOUT is reduced to lower power consumption (i.e., ACTIVE state). The error amplifier module 200 maintains closed-loop control, stabilizing the Boost output voltage VOUT at a level that meets the LED target current. The control module 500 maintains PWM signal stability through conventional mechanisms, ensuring long-term stable LED current output, and the control process is completed.

[0082] In addition, both the third and fourth stages require real-time monitoring of the LED string connections to ensure the system's safety and reliability.

[0083] The entire startup process achieves a smooth rise in the Boost output voltage VOUT through the timing coordination and mode switching of each module, avoiding sudden changes in inductor current during startup.

[0084] This application also discloses a control chip, including a detection selection module 100, an error amplification module 200, a feedback module 300, a logic drive module 400, a first switch module 600, a control module 500, and the aforementioned startup timing control circuit. The detection selection module 100 and the error amplification module 200 are both electrically connected to the switching module 101 in the startup timing control circuit. The control module 500 is electrically connected to the error amplification module 200, the first switch module 600, and the switch module 104 in the startup timing control circuit. The logic drive module 400 is electrically connected to the first switch module 600, the feedback module 300, the threshold adjustment module 103 in the startup timing control circuit, and the switch module 104. The feedback module 300 is electrically connected to the comparison module 102 in the startup timing control circuit. The control chip adopts the above-mentioned startup timing control circuit, which can dynamically adjust the overcurrent protection threshold and the working mode of the error amplification module 200 in stages to achieve a stable establishment of the output voltage VOUT and current. This effectively avoids device damage or voltage fluctuation caused by overcharging of inductor current during startup, while simplifying the configuration of external components and improving the startup reliability, adaptability and overall working efficiency of the control chip in scenarios such as LED backlight driving.

[0085] This application also discloses a power supply system, including multiple LED strings and the aforementioned control chip, with each LED string electrically connected to the control chip. The power supply system, utilizing the control chip's built-in startup timing control circuit, provides stable and precise power supply support to the multiple LED strings, ensuring that the LED string current rises stably and synchronously with the circuit, achieving a smooth brightness transition. Therefore, the power supply system can meet the high dynamic dimming requirements of large-size LCD displays and is also suitable for scenarios sensitive to startup speed, such as automotive screens and VR devices. This power supply system, which deeply integrates the intelligent control chip with multiple LED strings, provides a complete solution for high-definition, high-energy-efficiency display applications through collaborative optimization of startup timing and dynamic response.

[0086] Since the processing and functions implemented by the power supply system and control chip in this embodiment are basically the same as the embodiments, principles and examples of the aforementioned startup timing control circuit, any details not covered in this embodiment can be found in the relevant descriptions in the aforementioned embodiments, and will not be repeated here.

[0087] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A startup timing control circuit, characterized in that, It includes a switching module, a comparison module, a threshold adjustment module, and a switch module. The comparison module is electrically connected to the switching module, the threshold adjustment module, and the switch module, respectively. The switching module is electrically connected to the detection selection module and the error amplification module, respectively. The comparison module is electrically connected to the feedback module. The threshold adjustment module is electrically connected to the logic drive module. The switch module is electrically connected to the logic drive module and the control module, respectively. When the feedback voltage output by the feedback module is less than the preset voltage, the comparison module outputs a first comparison signal to the switching module, the threshold adjustment module, and the switch module; the switching module is used to turn on the first input terminal and the output terminal of the error amplification module according to the first comparison signal; the switch module is used to turn off according to the first comparison signal, thereby disconnecting the control module from the logic drive module. The threshold adjustment module is used to output an overcurrent protection signal to the logic drive module based on the first comparison signal, the reference signal, and the sampling signal. When the feedback voltage is greater than or equal to the preset voltage, the comparison module outputs a second comparison signal to the switching module, the threshold adjustment module, and the switch module; the switching module is used to turn on the first input terminal of the error amplification module and the detection selection module according to the second comparison signal; the switch module is used to turn on according to the second comparison signal to connect the control module and the logic drive module; the threshold adjustment module is used to gradually increase the threshold of the overcurrent protection signal according to the second comparison signal, the reference signal, and the sampling signal.

2. The startup timing control circuit according to claim 1, characterized in that, The switching module includes a first transmission gate, a first end of which is electrically connected to the first input end of the error amplification module, a second end of which is electrically connected to the detection selection module, a third end of which is electrically connected to the output end of the error amplification module, and a control end of which is electrically connected to the comparison module.

3. The startup timing control circuit according to claim 1, characterized in that, The comparison module includes a first comparator, a first input terminal of which is electrically connected to the feedback module, a second input terminal of which is used to receive the preset voltage, and an output terminal of which is electrically connected to the switching module, the threshold adjustment module, and the switch module, respectively.

4. The startup timing control circuit according to claim 1, characterized in that, The threshold adjustment module includes a reference voltage generation unit, a current mirror unit, a first switch unit, a second switch unit, a third switch unit, an energy storage unit, and a comparison output unit. The current mirror unit is electrically connected to the reference voltage generation unit, the first switch unit, the third switch unit, the energy storage unit, and the comparison output unit, respectively. The comparison output unit is electrically connected to the second switch unit and the third switch unit, respectively. The reference voltage generating unit is used to provide a reference voltage signal to the current mirror unit; When the feedback voltage output by the feedback module is less than the preset voltage, the first switch unit is turned on, the second switch unit is turned on, and the third switch unit is turned off. The current mirror unit is used to output a first current to the comparison output unit according to the reference voltage signal. The comparison output unit is used to output an overcurrent protection signal to the logic drive module according to the first current, the node voltage, the reference signal, and the sampling signal. The node voltage is the voltage at the common terminal of the comparison output unit and the second switch unit. When the feedback voltage is greater than or equal to the preset voltage, the first switching unit is turned off, the second switching unit is turned off, and the third switching unit is turned on. The current mirror unit is used to output charging current to the energy storage unit according to the reference voltage signal. The energy storage unit is used to store energy according to the charging current, so that the node voltage gradually increases.

5. The startup timing control circuit according to claim 4, characterized in that, The reference voltage generating unit includes a first resistor and a current source. The first end of the first resistor is electrically connected to the current mirror unit. The first end of the current source is electrically connected to the second end of the first resistor and the current mirror unit, respectively. The second end of the current source is grounded. The current mirror unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The gate of the first transistor is electrically connected to the drain of the second transistor, the reference voltage generating unit, the gate of the third transistor, and the gate of the fifth transistor, respectively. The sources of the first transistor, the third transistor, and the fifth transistor are all electrically connected to the power supply. The drain of the first transistor is electrically connected to the source of the second transistor. The gate of the fourth transistor is electrically connected to the gate of the second transistor, the reference voltage generating unit, and the gate of the sixth transistor, respectively. The source of the fourth transistor is electrically connected to the drain of the third transistor. The drain of the fourth transistor is electrically connected to the first switching unit, the third switching unit, and the energy storage unit, respectively. The source of the sixth transistor is electrically connected to the drain of the fifth transistor. The drain of the sixth transistor is electrically connected to the comparison output unit.

6. The startup timing control circuit according to claim 4, characterized in that, The first switching unit includes a first switching transistor, the gate of which is electrically connected to the comparator module, the drain of which is electrically connected to the current mirror unit, the third switching unit and the energy storage unit, respectively, and the source of which is grounded. The second switching unit includes a second switching transistor, the gate of which is electrically connected to the comparison module, the source of which is electrically connected to the power supply, and the drain of which is electrically connected to the third switching unit and the comparison output unit, respectively. The third switching unit includes a third switching transistor and a fourth switching transistor. The gates of the third switching transistor and the fourth switching transistor are both electrically connected to the comparator module. The drain of the third switching transistor is electrically connected to the drain of the fourth switching transistor, the current mirror unit, the first switching unit, and the energy storage unit, respectively. The source of the third switching transistor is electrically connected to the source of the fourth switching transistor, the second switching unit, and the comparator output unit, respectively.

7. The startup timing control circuit according to claim 4, characterized in that, The energy storage unit includes a first capacitor, the first terminal of which is electrically connected to the first switching unit, the third switching unit and the current mirror unit, respectively, and the second terminal of the first capacitor is grounded.

8. The startup timing control circuit according to claim 4, characterized in that, The comparison output unit includes a fifth switch, a seventh transistor, an eighth transistor, a second resistor, a third resistor, and a second comparator. The gate of the fifth switch is electrically connected to the second switch unit and the third switch unit, respectively. The source of the fifth switch is electrically connected to the source of the seventh transistor, the source of the eighth transistor, and the current mirror unit, respectively. The drain of the fifth switch is electrically connected to the drain of the seventh transistor, the first terminal of the second resistor, and the first input terminal of the second comparator, respectively. The gate of the seventh transistor is used to receive the reference signal, and the gate of the eighth transistor is used to receive the sampling signal. The drain of the eighth transistor is electrically connected to the first terminal of the third resistor and the second input terminal of the second comparator, respectively. The output terminal of the second comparator is electrically connected to the logic driving module. The second terminals of the second resistor and the second terminals of the third resistor are both grounded.

9. The startup timing control circuit according to claim 1, characterized in that, The switch module includes a control switch, the control terminal of which is electrically connected to the comparison module, the first terminal of which is electrically connected to the control module, and the second terminal of which is electrically connected to the logic drive module.

10. A control chip, characterized in that, The device includes a detection selection module, an error amplification module, a feedback module, a logic drive module, a first switch module, a control module, and a startup timing control circuit as described in any one of claims 1-9. The detection selection module and the error amplification module are both electrically connected to a switching module in the startup timing control circuit. The control module is electrically connected to the error amplification module, the first switch module, and the switch module in the startup timing control circuit. The logic drive module is electrically connected to the first switch module, the feedback module, the threshold adjustment module in the startup timing control circuit, and the switch module. The feedback module is electrically connected to a comparison module in the startup timing control circuit.

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