A manufacturing method of a double-sided buried wire printed circuit board

Abstract

The application discloses a manufacturing method of a double-sided buried wire printed circuit board, which comprises the following steps: inner layer processing; insulation layer pressing; through-hole manufacturing; using a film pasting mode to paste a photosensitive insulation layer on the surface of a board; using a pattern transfer technology to transfer a circuit pattern to the insulation layer, removing unnecessary parts by developing, and then completely solidifying the insulation layer by using a heating solidification mode; using a chemical copper deposition or sputtering copper mode to manufacture a thin copper through layer on the surface of the board; film pasting: pasting a circuit dry film on the surface of the board; using the pattern transfer technology to transfer the pattern to the dry film again; filling the pattern area by electroplating until the insulation layer is filled, so as to form a buried wire structure; film removing; etching; and finally completing the manufacturing of the buried wire printed circuit board. The buried wire circuit board manufactured by the application can be processed from both sides, can manufacture a double-sided buried wire structure, has a shortened production cycle, and is not easy to produce warping due to the existence of a core board and good mechanical strength of the board.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of printed circuit board manufacturing, and particularly relates to a manufacturing method of double-sided buried wire printed circuit board. BACKGROUND

[0002] With the development of electronic devices towards high density and miniaturization, buried wire substrate as a key carrier for realizing three-dimensional circuit interconnection plays an important role in modern electronic manufacturing field. This technology can realize complex circuit layout in limited space, and directly determines the performance and market competitiveness of high-end electronic products.

[0003] In the prior art, taking a 4-layer buried wire printed circuit board as an example, its manufacturing process is as shown in the figure Figures 2-1 through 2-10 , and specifically comprises the following steps:

[0004] A copper foil is pasted on a support plate; a line dry film is pasted on the copper foil; a line pattern is transferred to the dry film by using a pattern transfer technology, and the unnecessary part is removed by developing; the pattern area is filled by electroplating; the line dry film is removed by using a film removing liquid; the buried wire structure is formed by using lamination technology for pressing; the other layers of line processing are continued according to the conventional process of printed circuit board; the processing is continued until the target number of layers is reached; the completed board is peeled off from the support plate; the copper surface of the buried wire layer is etched to expose the line, and the finished buried wire board is manufactured.

[0005] The above manufacturing process has the following problems:

[0006] The technical purpose of the buried wire substrate is to protect the line width after lamination of the insulating layer when using the semi-additive method for processing, to etch the copper layer from the bottom to make the copper layer conductive, and to protect the line width from being damaged during etching, thereby further improving the processing capability of fine lines; however, this processing method can only realize single-sided buried wire processing, and a support plate is required, that is, a coreless substrate process is used, which has certain processing difficulty and waste of support plate cost, and the single-sided processing mode has a long processing cycle, and the finished board lacks a core plate, and is prone to insufficient support and plate warping problems. SUMMARY

[0007] The technical problem to be solved by the present application is to provide a manufacturing method of double-sided buried wire printed circuit board, which solves the above problems in the prior art, and the buried wire circuit board manufactured by the method can be processed from both sides to manufacture double-sided buried wire structure, the production cycle is shortened, and the board has good mechanical strength due to the existence of the core plate, and is not prone to warping.

[0008] To solve the above technical problems, the technical scheme adopted by the present application is as follows: a manufacturing method of double-sided buried wire printed circuit board, comprising the following steps:

[0009] Inner layer processing: using the conventional process of printed circuit board, processing the inner layer core board;

[0010] Insulation lamination: using lamination process to laminate the insulation layer;

[0011] Through-hole making: using laser drilling to make through-hole;

[0012] Insulation layer film pasting: using film pasting method to paste the photosensitive insulation layer on the surface of the board;

[0013] Pattern transfer and post-curing: using pattern transfer technology to transfer the circuit pattern to the insulation layer, removing the unnecessary part using development, and then using heating curing method to completely cure the insulation layer;

[0014] Making through layer: using chemical copper deposition or sputtering copper method to make a thin copper through layer on the surface of the board;

[0015] Film pasting: pasting the circuit dry film on the surface of the board;

[0016] Pattern transfer: using pattern transfer technology to transfer the pattern to the dry film again, removing the unnecessary part using development;

[0017] Pattern plating: using plating to fill the pattern area until the insulation layer is filled, forming a buried wire structure;

[0018] Film removal: using film removal liquid to remove the circuit dry film;

[0019] Etching: using etching technology to remove the through layer on the surface of the insulation layer, finally completing the production of buried wire printed circuit board.

[0020] The above-mentioned method for producing a double-sided buried wire printed circuit board uses laser drilling to make through-hole, and the specific process is as follows:

[0021] High-resolution camera is used to collect image of the insulation layer pattern structure;

[0022] The edge contrast of the through-hole is enhanced by image preprocessing algorithm;

[0023] The contour boundary of the through-hole is identified by edge detection algorithm;

[0024] The geometric center coordinates of the through-hole contour are calculated;

[0025] The conversion relationship between pixel coordinates and actual physical coordinates is established;

[0026] If the position deviation of the through-hole exceeds the allowed range, record the deviation data and generate position correction instructions;

[0027] Statistical analysis is performed on the measurement results to evaluate the overall position accuracy;

[0028] constructing a dataset containing the exact coordinates of all vias;

[0029] The via is made by laser drilling.

[0030] The above-mentioned method for manufacturing a double-sided buried wire printed circuit board uses a pattern transfer technique to transfer a circuit pattern to an insulating layer, including: using a pre-set pattern transfer control strategy to perform pattern transfer processing on the insulating layer, and using a precise lithography technique to form a predetermined circuit pattern on the surface of the insulating layer.

[0031] The above-mentioned method for manufacturing a double-sided buried wire printed circuit board, the specific process of pre-setting the pattern transfer control strategy is:

[0032] Obtain the thickness distribution data of the insulating layer on the surface of the inner core board, and use laser scanning measurement technology to detect the thickness of each point on the surface of the substrate to obtain a standardized data matrix of the thickness distribution.

[0033] According to the thickness distribution data matrix, a mapping relationship model between the insulating layer and the via layer is established using a multi-layer perception algorithm to obtain a targeted pattern transfer control strategy.

[0034] The above-mentioned method for manufacturing a double-sided buried wire printed circuit board uses laser scanning measurement technology to detect the thickness of each point on the surface of the substrate, including:

[0035] The surface of the substrate is scanned by a laser beam, the time difference of the laser reflection signal is measured, and the thickness value of each measurement point is calculated.

[0036] If the detected thickness change exceeds the pre-set threshold range, an adaptive threshold segmentation algorithm is used to mark and identify the abnormal area.

[0037] The measured thickness data is normalized to eliminate the influence of system error.

[0038] A two-dimensional thickness distribution matrix is constructed to record the coordinate position and corresponding thickness value of each measurement point.

[0039] The abnormal area is repeatedly measured and verified to confirm the authenticity of the thickness anomaly.

[0040] A visual image of the thickness distribution is generated to identify the range of the thickness change area.

[0041] The above-mentioned method for manufacturing a double-sided buried wire printed circuit board uses a multi-layer perception algorithm to establish a mapping relationship model between the insulating layer and the via layer, including:

[0042] Collecting correlation data between pattern transfer accuracy and material property changes in historical manufacturing data.

[0043] A multi-layer neural network structure is constructed, and an input layer is set to receive thickness distribution data;

[0044] Through the hidden layer, complex nonlinear mapping relationships are handled, and key feature parameters are extracted;

[0045] In the output layer, the prediction result of the optimal process parameter combination is generated;

[0046] The network weight is trained using the back propagation algorithm, and the model prediction accuracy is optimized;

[0047] The generalization ability of the model is evaluated through cross-validation method;

[0048] The similarity between the current substrate state and the historical data is analyzed to determine the applicability of the model;

[0049] Generate personalized process parameter recommendations for the current substrate characteristics.

[0050] The above-mentioned method for manufacturing a double-sided buried wire printed circuit board uses precise photoetching technology to form a predetermined line pattern on the surface of the insulating layer, which includes:

[0051] A photosensitive adhesive layer is coated on the surface of the insulating layer to control the uniformity of the coating thickness;

[0052] According to the control strategy, set the exposure parameters, including exposure time and light intensity;

[0053] Through the mask, the photosensitive adhesive layer is selectively exposed to form a latent image pattern;

[0054] Developing treatment is carried out to remove the unexposed or exposed photosensitive adhesive part;

[0055] The definition of the pattern edge and the line width accuracy are detected;

[0056] If the definition of the pattern edge is lower than the quality standard, adjust the exposure parameters and re-perform the pattern transfer;

[0057] Through etching process, the pattern is transferred to the insulating layer to form the final pattern structure.

[0058] The above-mentioned method for manufacturing a double-sided buried wire printed circuit board uses electroplating to fill the pattern area until the insulating layer is filled, forming a buried wire structure, and the specific process is as follows:

[0059] Prepare the chemical plating solution and control the metal ion concentration;

[0060] Pretreat the surface of the insulating layer to enhance the adhesion of the metal;

[0061] Immerse the substrate in the chemical plating solution to start the autocatalytic reaction;

[0062] Control the plating solution temperature and pH value to maintain the stability of the reaction;

[0063] Real-time monitoring thickness change during deposition process;

[0064] If the deposition thickness is not uniform degree exceeds the preset standard, adjust the plating solution concentration and reaction time parameters;

[0065] Through ultrasonic wave auxiliary improves the compactness and uniformity of plating layer;

[0066] After the insulating layer is filled, cleaning and drying treatment are carried out, and a buried wire structure is formed.

[0067] Compared with the prior art, the present application has the following advantages:

[0068] 1. The prior art is to first make a line layer structure and then use an insulating layer to press and form a buried wire structure. The present application is to make a conductor cavity in the insulating layer and then perform electroplating filling to form a buried wire structure. The prior art buried wire circuit board structure is to use a support plate to perform single-sided pressing on a copper foil and then remove the conductive copper layer at the bottom. The present application is to use chemical copper or sputtering copper to form a conductive layer on the surface of the insulating layer, and finally remove the conductive layer from the front. The prior art buried wire circuit board structure can only make a single-sided buried wire structure due to the absence of a core plate and single-sided pressing, and the production cycle is long and the board is prone to warping. The buried wire circuit board made by the present application can be processed from both sides to make a double-sided buried wire structure, the production cycle is shortened, and the mechanical strength of the board is good due to the presence of the core plate, and the board is not prone to warping.

[0069] 2. Compared with the traditional printed circuit board process, the biggest advantage of the buried wire printed circuit board is that the insulating layer can be used to protect the circuit to achieve the purpose of making fine lines. The prior art buried wire circuit board process can only realize fine line processing on the outer single layer. The processing method of the present application can be applied to any layer, thereby improving the fine line processing capability of the circuit board as a whole.

[0070] 3. The present application realizes accurate control of the preparation process of the insulating layer and the conductive layer, improves the manufacturing precision and consistency of the multilayer printed circuit board, effectively solves the problems of insufficient pattern transfer precision and uneven conductive hole filling in the traditional process, and provides technical support for the manufacturing of high-density interconnection printed circuit boards.

[0071] The technical solutions of the present application will be further described in detail below with reference to the drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0072] Figure 1 The method flowchart of the present application is shown in the figure;

[0073] Figures 2-1 through 2-10 The manufacturing flowchart of the prior art is shown in the figure.

[0074] Figures 3-1 through 3-11 The flow chart of the manufacturing process of the present application;

[0075] Figure 4 The structure comparison chart of the product in the prior art and the product of the present application. DETAILED DESCRIPTION

[0076] As shown in Figure 1 and Figures 3-1 through 3-11 The manufacturing method of the double-sided buried wire printed circuit board of the present application comprises the following steps:

[0077] Step S1, inner layer processing: using the conventional process of printed circuit board to process the inner layer core board;

[0078] Step S2, insulation lamination: using lamination process to laminate the insulation layer;

[0079] Step S3, via hole manufacturing: using laser drilling to manufacture the via hole;

[0080] In this embodiment, the via hole manufacturing in step S3 is performed by using laser drilling, and the specific process is as follows:

[0081] Step S301, using a high-resolution camera to collect images of the pattern structure of the insulation layer;

[0082] The high-resolution camera is configured with a pixel resolution of not less than 2048x2048, and the lens focal length is selected from a fixed-focus lens in the range of 25mm to 50mm according to the size of the detection area, so as to ensure that the physical size corresponding to a single pixel is controlled within 1 micron;

[0083] Step S302, enhancing the edge contrast of the via hole by using an image preprocessing algorithm; the specific process is as follows:

[0084] Step S30201, performing gray scale conversion processing on the collected original image, converting the RGB color image into an 8-bit gray scale image, and the gray scale value range is 0 to 255; the conversion process adopts a weighted average method, in which the red channel weight is 0.299, the green channel weight is 0.587, and the blue channel weight is 0.114, so as to ensure that the converted gray scale image can maintain the brightness information of the original image;

[0085] Step S30202, using a Gaussian filter to perform noise suppression processing on the gray scale image; the filter kernel size is set to 3x3 or 5x5, and the standard deviation parameter is adjusted in the range of 0.5 to 2.0 according to the image noise level; the filtering process is realized by convolution operation, and the new gray scale value of each pixel point is calculated by its neighborhood pixels according to the Gaussian distribution weight, so as to effectively reduce the random noise in the image and the electronic noise generated in the collection process;

[0086] Step S30203, the histogram equalization algorithm is applied to enhance the overall contrast of the image; the algorithm first counts the number of pixels of each gray level in the image, calculates the cumulative distribution function, and then maps the original gray value to a new gray range; the mapping function is that the new gray value is equal to 255 times the cumulative probability, so that the gray distribution of the processed image is more uniform, and the contrast between the via hole and the insulating layer background is significantly improved;

[0087] Step S30204, edge enhancement processing is performed by using a Laplace operator; the Laplace operator kernel is a 3*3 matrix, the center element is 8, and the surrounding 8 elements are-1; the edge information in the image is highlighted through convolution operation; the Laplace response image after processing is added to the original image to obtain an edge enhanced image, so that the boundary of the via hole is clearer and sharper;

[0088] Step S303, an edge detection algorithm is used to identify the contour boundary of the via hole; the specific process is as follows:

[0089] Step S30301, the Canny edge detection algorithm is applied to extract the edge of the via hole; the algorithm first calculates the gradient amplitude and direction of the image using the Sobel operator; the gradient amplitude represents the edge strength, and the gradient direction is used for subsequent non-maximum suppression; the Sobel operator includes two 3*3 convolution kernels in the horizontal and vertical directions, respectively, for detecting the edges in the horizontal and vertical directions;

[0090] Step S30302, non-maximum suppression processing is performed, the gradient amplitudes of adjacent pixels are compared along the gradient direction, the local maximum points are retained, and the non-maximum points are suppressed, so that the edge lines become refined; in the suppression process, the gradient direction is quantized into four main directions of 0 degrees, 45 degrees, 90 degrees and 135 degrees, and each pixel point is compared with two adjacent pixels in its gradient direction;

[0091] Step S30303, a double-threshold processing is used to determine the edge pixels; a high threshold and a low threshold are set, the high threshold is usually 2 to 3 times the low threshold, the pixels with gradient amplitude higher than the high threshold are directly marked as edge points, the pixels with gradient amplitude lower than the low threshold are marked as non-edge points, and the pixels with gradient amplitude between the two thresholds need to be determined whether they are edge points through connectivity analysis;

[0092] Step S30304, an edge connection algorithm is used to form a complete via hole contour; the algorithm uses an 8-connected neighborhood search method to search adjacent edge points along the edge direction from the determined edge points, and connects the broken edge segments into a complete closed contour; during the connection process, a gap of no more than 2 pixels is allowed to be crossed to ensure the integrity of the via hole contour;

[0093] Step S304, the geometric center coordinates of the via hole contour are calculated;

[0094] According to the detected contour boundary point coordinates, the geometric center is determined by using the centroid calculation method. The centroid coordinates are obtained by averaging the horizontal coordinates and vertical coordinates of all contour points. During the calculation process, the coordinates of all pixel points in the region are counted by pixel traversal of the region inside the contour;

[0095] Step S305, establish the conversion relationship between pixel coordinates and actual physical coordinates; the specific process is:

[0096] Step S451, camera calibration is performed using a standard calibration board, which contains circular or square marker points with known physical dimensions, and the marker point spacing accuracy reaches sub-micron level; during the calibration process, the calibration board image is captured at different positions and angles to obtain multiple sets of corresponding relationship data of pixel coordinates and physical coordinates;

[0097] Step S452, calculate the camera intrinsic matrix and distortion coefficient; the intrinsic matrix includes focal length, principal point coordinates and pixel size, etc., and the distortion coefficient describes the radial distortion and tangential distortion characteristics of the lens; the least squares method is used to fit the calibration data to obtain the optimal values of the intrinsic matrix and the distortion coefficient;

[0098] Step S453, establish a coordinate conversion mathematical model; the conversion model considers camera intrinsic parameters, distortion correction and extrinsic transformation to convert the via center coordinates in the pixel coordinate system to the actual position coordinates in the substrate physical coordinate system; the conversion process first performs distortion correction, and then applies a perspective transformation matrix to complete the coordinate system conversion;

[0099] Step S306, if the via position deviation exceeds the allowed range, record the deviation data and generate a position correction instruction;

[0100] Compare the measured actual position of the via with the designed position to calculate the horizontal and vertical components of the position deviation; when the Euclidean distance of the deviation exceeds the pre-set allowed range, record the direction and size information of the deviation, and generate a position correction instruction containing the correction direction and correction amount;

[0101] Step S307, statistical analysis is performed on the measurement results to evaluate the overall position accuracy;

[0102] Calculate the mean, standard deviation and maximum deviation value of all via position deviations, and statistically analyze the histogram of the deviation distribution to evaluate the consistency and reliability of the measurement accuracy; the analysis results are used to judge the stability of the detection process and the overall level of the insulating layer pattern transfer quality;

[0103] Step S308, construct a data set containing the accurate coordinates of all vias;

[0104] The via center coordinates after coordinate conversion are organized into a data set in a predetermined format, which contains information such as via number, horizontal coordinate, vertical coordinate, measurement timestamp, and quality rating, providing basic data support for subsequent via fabrication;

[0105] Step S309, laser drilling is used for via fabrication.

[0106] In an embodiment, the image preprocessing process employs adaptive parameter adjustment for different types of insulating layer materials.

[0107] For example, for a polyimide insulating layer, due to its low surface reflectivity, the image gain parameter needs to be increased to 1.2 times, and the clipping limit of histogram equalization is set to 2.0 to avoid noise amplification caused by excessive enhancement. For an epoxy insulating layer, its surface smoothness is high, which is prone to light reflection. A polarizing filter is needed to reduce light reflection interference, and the standard deviation parameter of Gaussian filtering is adjusted to 1.5 to ensure that the edge information remains clear while suppressing light reflection noise.

[0108] Specifically, the double-threshold setting of the edge detection algorithm is dynamically adjusted according to the via size. For vias with a diameter in the range of 50-100 microns, the high threshold is set to the 85th percentile of the gradient amplitude distribution, and the low threshold is set to 0.4 times the high threshold. For vias with a diameter in the range of 100-200 microns, the high threshold is reduced to the 75th percentile of the gradient amplitude distribution due to the relatively flat edge gradient change, and the low threshold is adjusted to 0.3 times, ensuring that the complete via profile can be detected.

[0109] In a possible implementation, the coordinate conversion process uses a piecewise linear interpolation method to improve conversion accuracy. The detection area is divided into multiple sub-areas, and independent conversion parameters are established for each sub-area to eliminate nonlinear errors in a large field of view.

[0110] For example, for a 20mm x 20mm detection area, it is divided into 4x4 = 16 sub-areas, and the conversion accuracy of each sub-area can reach 0.5 microns, which is about 30% higher than the global conversion method.

[0111] It should be noted that the generation of the position correction instruction takes into account the adjustable range of the manufacturing process. When the via position deviation is detected, the correction instruction not only contains the numerical information of the deviation, but also contains the adjustment suggestion for the subsequent process parameters.

[0112] For example, if the via is shifted in a certain direction, the instruction contains the correction parameters for the lithography alignment system, and if the deviation shows a random distribution characteristic, the exposure dose or development time parameter is suggested to be adjusted, fundamentally improving the position accuracy of pattern transfer.

[0113] Step S4, Insulating Layer Application: Apply a photosensitive insulating layer to the surface of the board using a film application method;

[0114] Step S5, Curing after Pattern Transfer: Using pattern transfer technology, the circuit pattern is transferred onto the insulating layer. Unwanted parts are removed using development, and then the insulating layer is completely cured using heat curing.

[0115] In this embodiment, step S5 uses pattern transfer technology to transfer the circuit pattern onto the insulating layer, including: performing pattern transfer processing on the insulating layer using a pre-set pattern transfer control strategy, and forming a predetermined circuit pattern on the surface of the insulating layer using precision photolithography.

[0116] In this embodiment, the specific process of pre-setting the graphics transfer control strategy is as follows:

[0117] The thickness distribution data of the insulation layer on the surface of the inner core board is obtained, and the thickness is measured point by point on the substrate surface using laser scanning measurement technology to obtain a standardized data matrix of the thickness distribution.

[0118] Based on the thickness distribution data matrix, a mapping relationship model between the insulating layer and the conductive layer is established using a multilayer perceptron algorithm to obtain a targeted pattern transfer control strategy.

[0119] In this embodiment, laser scanning measurement technology is used to perform point-by-point thickness detection on the substrate surface, including:

[0120] Step S501: Scan the substrate surface with a laser beam, measure the time difference of the laser reflection signal, and calculate the thickness value at each measurement point; the specific process is as follows:

[0121] In step S50101, the laser emitter generates a red laser beam with a wavelength of 635 nanometers and a laser beam power set to 5 milliwatts. The laser beam is focused into a spot with a diameter of 10 micrometers through a precision optical lens group. The laser beam illuminates the substrate surface at a perpendicular angle. When the laser encounters the surface of the insulating layer, a first reflection signal is generated. When it continues to penetrate the insulating layer and reaches the surface of the inner core board, a second reflection signal is generated.

[0122] In step S50102, the photodetector receives two reflected signals and records the time interval Δt between the two reflected signals using a high-precision time measurement circuit. Based on the laser propagation speed v in the insulating layer material, the insulation layer thickness d is calculated using the formula d = v × Δt / 2, where dividing by 2 is because the round-trip path length of the laser is twice the thickness.

[0123] Step S50103, the scanning control device drives the laser beam to perform point-by-point scanning on the substrate surface according to the preset grid path, and the scanning step is set to 50 microns to ensure sufficient spatial resolution between adjacent measurement points. The scanning time of each measurement point is 10 milliseconds, including the complete cycle of signal acquisition, data processing and position movement.

[0124] Step S502, if the thickness change exceeds the preset threshold range, an adaptive threshold segmentation algorithm is used to mark and identify the abnormal area; the specific process is as follows:

[0125] Step S50201, an evaluation mechanism for thickness change rate is established, and the thickness difference between each measurement point and its eight adjacent points is calculated. When the thickness difference exceeds 15% of the standard thickness, the abnormal detection process is triggered. The adaptive threshold segmentation algorithm first calculates the mean value μ and the standard deviation σ of the thickness values in the local area, and then dynamically determines the segmentation threshold T according to the formula T = μ + k × σ, where k is the adjustment coefficient, and the initial value is set to 1.5.

[0126] Step S50202, for the measurement points with thickness values exceeding the dynamic threshold T, the algorithm marks them as potential abnormal points, and checks the distribution density of abnormal points in the 3x3 neighborhood around the point. When the number of abnormal points in the neighborhood exceeds 5, the entire neighborhood region is marked as an abnormal region, and the adjustment coefficient k value is adjusted to dynamically change between 0.8 and 2.5 to adapt to the thickness change characteristics of different regions.

[0127] Step S50203, after the abnormal region marking is completed, the algorithm generates marking data containing the boundary coordinates, area size and average thickness deviation of the abnormal region, providing accurate position information and abnormality degree evaluation basis for subsequent repeated measurement verification.

[0128] Step S503, the measured thickness data is normalized to eliminate system error;

[0129] The Z-score standardization method is used to normalize the original thickness data, and the thickness value is converted to a standardized value by the formula Z = (X - μ) / σ, where X is the original thickness value, μ is the global mean value, and σ is the global standard deviation.

[0130] Step S504, a two-dimensional thickness distribution matrix is constructed to record the coordinate position and corresponding thickness value of each measurement point; the specific process is as follows:

[0131] Step S50401, according to the actual size of the substrate and the scanning step, an m x n dimensional thickness distribution matrix M is created, where m and n correspond to the number of measurement points in the X and Y directions of the substrate respectively. Each element M(i, j) in the matrix contains three attribute values: X coordinate, Y coordinate and standardized thickness value.

[0132] Step S50402, establish coordinate mapping relationship, convert the measurement point position in the physical coordinate system to the matrix index position. Through the coordinate transformation formula i=floor(x / step_x) and j=floor(y / step_y), the continuous physical coordinates (x, y) are mapped to discrete matrix indexes (i, j), wherein step_x and step_y are the scanning step length in X-axis and Y-axis directions respectively.

[0133] Step S50403, mark the position information of the abnormal area in the thickness distribution matrix, distinguish the abnormal measurement points from the normal measurement points by setting special identifiers, and form a complete data structure containing spatial position, thickness value and abnormal state.

[0134] Step S505, repeat measurement verification on the abnormal area to confirm the authenticity of the thickness abnormality; the specific process is:

[0135] Step S50501, for the marked abnormal area, the laser scanning device is repositioned to the center position of the abnormal area, and secondary scanning is carried out with higher measurement accuracy. The laser power of the secondary scanning is increased to 8 milliwatts, the scanning step length is reduced to 25 microns, and the measurement time is extended to 20 milliseconds, so as to obtain more accurate thickness data.

[0136] Step S50502, compare the consistency of the primary measurement result and the secondary measurement result, and calculate the relative error between the two measurement values. When the relative error is less than 5%, it is confirmed that the abnormal area exists; when the relative error exceeds 5%, it is determined that it is measurement noise or system interference, and the area is removed from the abnormal mark.

[0137] Step S50503, for the confirmed real abnormal area, record its abnormal type, severity and possible cause analysis, and establish an abnormal area database to provide reference for subsequent process parameter optimization. The abnormal type includes three basic types of thickness too thin, thickness too thick and thickness uneven, and the severity is divided into three levels of slight, medium and severe according to the deviation amplitude.

[0138] Step S506, generate a visual image of the thickness distribution, and mark the area range of the thickness change.

[0139] Based on the thickness distribution matrix, a pseudo-color image is generated, and a color mapping scheme is adopted to correspond different thickness values to different colors. The normal thickness range is displayed in green, the thickness thin area is displayed in blue, and the thickness thick area is displayed in red.

[0140] In one embodiment, when there is a small particle contamination on the substrate surface during the laser scanning measurement process, an additional scattering component will appear in the laser reflection signal. At this time, signal filtering technology needs to be used to remove the influence of scattering noise, and by setting a signal intensity threshold, the scattering signal with too low intensity is filtered out, and the main reflection signal is retained for thickness calculation.

[0141] For example, when it is detected that the reflection signal intensity is lower than 70% of the set threshold, the system automatically starts the signal enhancement mode, increases the laser power and prolongs the signal acquisition time, to ensure that reliable thickness measurement data is obtained.

[0142] Exemplarily, the adaptive threshold segmentation algorithm needs to dynamically adjust the segmentation parameters according to local features when processing areas with large thickness variation gradients. In the edge area of the substrate, due to the limitations of the manufacturing process, the thickness variation is usually more severe than in the central area. The algorithm adjusts the adjustment coefficient k value to 2.0 when the distance from the measurement point to the edge of the substrate is less than 5 mm, improves the tolerance to thickness variation in the edge area, and avoids misjudging normal edge effects as abnormal areas.

[0143] In one possible implementation, the construction process of the two-dimensional thickness distribution matrix needs to consider the actual shape and size variation of the substrate. For a non-rectangular substrate, by establishing a mathematical model of the substrate contour, the boundary range of the effective measurement area is determined. The elements outside the substrate contour in the matrix are set to invalid values, and only the elements within the effective measurement area record the actual thickness data. This processing method can accurately reflect the real thickness distribution characteristics of the substrate and avoid interference of invalid areas on overall data analysis.

[0144] Specifically, the repeated measurement verification mechanism of the abnormal area can effectively improve the reliability of the measurement results. When the initial scanning finds that the thickness value of a certain area deviates significantly from the normal range, the system will automatically trigger the verification process. In the verification process, different scanning parameters and measurement angles are used, and through cross-verification of multi-angle measurement data, measurement errors caused by changes in surface reflection characteristics or local contamination are excluded.

[0145] For example, if it is found in the verification process that the measurement results of a certain abnormal point at different angles have significant differences, it is determined that the abnormality is caused by surface contamination, rather than real thickness variation.

[0146] In this embodiment, a multi-layer perception algorithm is used to establish a mapping relationship model between the insulating layer and the conductive layer, including:

[0147] Step S507, collect the correlation data of pattern transfer accuracy and material property variation in the historical manufacturing data;

[0148] Complete process records including insulating layer thickness, exposure energy, development time, etc. are extracted from the production database.

[0149] Step S508, constructing a multi-layer neural network structure, setting the input layer to receive thickness distribution data; comprising:

[0150] Step S50801, setting the input layer to 12 nodes, corresponding to the 12 key area measurement values of the thickness distribution data matrix.

[0151] Step S50802, configuring 3 hidden layers, respectively using ReLU, Sigmoid and Tanh activation functions to process different dimensional nonlinear features.

[0152] Step S50803, the output layer is designed as 6 nodes, corresponding to the key process parameters such as exposure time and developer concentration.

[0153] Step S509, through the hidden layer to process the complex nonlinear mapping relationship, extract the key feature parameters;

[0154] Step S50901, the first hidden layer extracts the spatial gradient features of the thickness distribution, and calculates the thickness change rate of adjacent areas.

[0155] Step S50902, the second hidden layer combines the material dielectric constant data to establish the correlation weight between thickness fluctuation and dielectric performance.

[0156] Step S50903, the third hidden layer integrates the outputs of the previous two layers to generate a 32-dimensional feature vector intermediate representation.

[0157] Step S5010, generating a prediction result of the optimal process parameter combination in the output layer;

[0158] Convert the feature vector output by the hidden layer into process parameter values, and output specific numerical values through a linear activation function.

[0159] Step S5011, using the back propagation algorithm to train the network weight, optimizing the model prediction accuracy;

[0160] Using mean square error as the loss function, setting the initial learning rate to 0.001, and after 500 iterations, the loss value converges to below 0.05.

[0161] Step S5012, evaluate the generalization ability of the model through cross-validation method;

[0162] Divide the data set into 5 subsets, the average prediction accuracy reaches 92.3%, and the standard deviation is less than 1.8%.

[0163] Step S5013, analyze the similarity between the current substrate state and the historical data, and judge the model applicability;

[0164] Calculate the Euclidean distance of the current thickness distribution and the historical sample; when the similarity is higher than 85%, directly call the historical parameters, and when it is lower than 70%, start the retraining process.

[0165] Step S5014, generate personalized process parameter suggestions for the current substrate characteristics.

[0166] Exemplarily, for a substrate with a thickness fluctuation within ±3μm, the output optimization combination is an exposure time of 45 seconds and a developer temperature of 28℃.

[0167] In an embodiment, the feature extraction process of step S50901 specifically includes dividing the 12x12 thickness matrix into 9 4x4 overlapping regions and calculating the thickness variance of each region as a primary feature.

[0168] Preferably, when it is detected that the variance of a certain region exceeds 0.5μm², the weight coefficient of the region is automatically increased to 1.2 times.

[0169] It can be understood that the similarity calculation adopts a dynamic weighting method, and the central region which has the greatest impact on the pattern transfer accuracy is given a weight coefficient of 0.4, and the edge region coefficient is set to 0.1.

[0170] Specifically, when the central region similarity reaches 90%, even if the overall similarity is 75%, it is still determined to be applicable.

[0171] In an embodiment, the parameter suggestion generation process of step S5014 includes a safety check mechanism. For example, when the predicted exposure time exceeds the upper limit of the device, the values of other parameters are automatically adjusted in proportion to keep the total energy unchanged. This mechanism makes the feasibility of the parameter combination reach more than 99.6%.

[0172] In this embodiment, a predetermined line pattern is formed on the surface of the insulating layer by using a precision lithography technology, which includes:

[0173] Step S5015, coating a photosensitive adhesive layer on the surface of the insulating layer, and controlling the uniformity of the coating thickness; the specific process is:

[0174] Step S11, forming a photosensitive adhesive layer on the surface of the insulating layer by a spin coating process, and adjusting the spin coating speed parameter according to the thickness distribution data matrix of the surface of the insulating layer. When it is detected that the thickness of the insulating layer changes in a region exceeding a preset threshold range, a segmented speed control method is used, the spin coating speed is reduced to 1500 revolutions per minute in the region with thinner thickness, and the spin coating speed is increased to 3000 revolutions per minute in the region with thicker thickness, so as to ensure that the thickness uniformity of the photosensitive adhesive layer is controlled within ±0.1 microns.

[0175] Step S12, the thickness of the photosensitive adhesive layer is monitored in real time by using a laser interference measurement method, and the thickness distribution characteristic data is obtained by multi-point sampling. When the thickness standard deviation exceeds 0.05 microns, a secondary coating compensation program is started, and local re-coating is performed in the area with insufficient thickness to form a photosensitive adhesive layer structure with uniform thickness.

[0176] Step S5016, set the exposure parameters according to the control strategy, including exposure time and light intensity; the specific process is:

[0177] Step S501601, determine the optimal exposure parameter combination under the current substrate state based on the output result of the mapping relationship model established based on the multi-layer perception algorithm. The multi-layer perception algorithm analyzes the correlation mode between the insulating layer thickness distribution and the pattern transfer accuracy in the historical manufacturing data, establishes a neural network structure containing thickness distribution characteristic values and material characteristic parameters in the input layer, uses ReLU activation function in the hidden layer to process the non-linear mapping relationship, and generates the optimized values of exposure time and light intensity in the output layer.

[0178] Step S501602, adjust the spatial distribution setting of the exposure parameters according to the photosensitive adhesive layer thickness uniformity detection result. For the standard area with a thickness of 2.5 microns, set the exposure time to 8 seconds and the light intensity to 25 milliwatts per square centimeter. For the area with a thickness deviation of more than 0.1 microns, adjust the exposure time according to the thickness compensation coefficient, extend the exposure time by 1 second when the thickness increases by 0.05 microns, and shorten the exposure time by 1 second when the thickness decreases by 0.05 microns.

[0179] Step S501603, establish the dynamic response relationship between the exposure parameters and the material characteristic changes of the insulating layer. When the dielectric constant of the insulating layer material changes, calculate the degree of change of the photosensitive characteristics of the photosensitive adhesive by measuring the dielectric constant offset, adjust the basic light intensity parameter, and ensure the consistency of the exposure effect under different material characteristics.

[0180] Step S5017, perform selective exposure of the photosensitive adhesive layer through the mask, and form a latent image pattern;

[0181] A high-precision alignment device is used to ensure accurate positioning of the mask and the insulating layer pattern structure, and the alignment accuracy is controlled within ±0.5 microns. Selective exposure is performed by using an ultraviolet light source.

[0182] Step S5018, perform development processing to remove the unexposed or exposed photosensitive adhesive part;

[0183] An alkaline developer is used to chemically develop the exposed photosensitive adhesive layer, and the development time is determined according to the type and thickness of the photosensitive adhesive, forming a clear pattern profile structure.

[0184] Step S5019, detect the clarity of the pattern edge and the line width accuracy; the specific process is:

[0185] At step S501901, edge sharpness of the developed pattern structure is measured by a high-precision visual detection device. The visual detection device uses a high-resolution CCD camera combined with a microscope lens to obtain a gray scale change curve of the pattern edge, and calculates an edge sharpness value as an evaluation index of sharpness. The edge sharpness value is determined by measuring the distance corresponding to the change of gray scale from 10% to 90% in the edge transition region. The smaller the distance, the clearer the edge.

[0186] At step S501902, a line width measurement algorithm is used to detect the accuracy of the key dimensions of the pattern structure. The line width measurement obtains the line width value by identifying the position of the pattern edge and calculating the distance between the edges. The measurement accuracy reaches 0.1 microns. When the line width deviation exceeds ±5% of the design value, the deviation position and value are recorded, and a quality evaluation report is generated.

[0187] At step S501903, a pattern quality evaluation system is established, and the edge sharpness and line width accuracy data are combined to form a quality score. The quality score uses a weighted average method, with the edge sharpness weight being 0.6 and the line width accuracy weight being 0.4. When the comprehensive score is lower than 85 points, it is determined that the quality is unqualified.

[0188] At step S50110, if the pattern edge sharpness is lower than the quality standard, adjust the exposure parameters and re-perform the pattern transfer; the specific process is as follows:

[0189] At step S501101, when the edge sharpness value is greater than 2 microns or the line width deviation exceeds ±8%, the parameter adjustment program is started. According to the quality detection result, the specific reasons for underexposure or overexposure are analyzed, the exposure time is increased or the light intensity is increased when underexposure, and the exposure parameters are correspondingly reduced when overexposure.

[0190] At step S501102, the parameter adjustment is performed by using an iterative optimization method, and the adjustment amplitude is controlled within 10% of the original parameter value. The complete process of photosensitive glue coating, exposure and development is performed again until the pattern quality meets the standard requirements.

[0191] At step S50111, the pattern is transferred to the insulating layer by etching process to form the final pattern structure. The specific process is as follows:

[0192] At step S501111, dry etching technology is used to transfer the pattern to the insulating layer. Dry etching removes the insulating layer material not protected by photosensitive glue through plasma chemical reaction. The etching gas is selected according to the type of insulating layer material. For polyimide insulating layer, oxygen plasma is used, and the etching rate is controlled at 50 nanometers per minute.

[0193] Step S501112, real-time monitoring of etching depth and sidewall profile, detecting etching process by optical interference measurement technology. When the etching depth reaches the design requirements, stop the etching process to avoid pattern distortion caused by over-etching. After etching, remove the residual photoresist to obtain the precise insulating layer pattern structure.

[0194] Step S501113, final quality inspection of the pattern structure after etching, measuring pattern size accuracy and surface roughness. The pattern size accuracy is required to be controlled within ±3% of the design value, and the surface roughness is less than 50 nanometers, ensuring the accuracy requirements of subsequent via preparation process.

[0195] In one embodiment, the photoresist layer thickness uniformity control is achieved by using a multi-stage spin coating process. First, pre-coat at a low speed of 1000 revolutions per minute to form a base glue layer, then according to the abnormal area marker results of the insulating layer thickness distribution data matrix, perform local re-coating in areas with large thickness deviation. The re-coating process uses a micro-droplet dispensing device, with a volume control of 0.01 microliters per time, and multiple re-coatings are required to achieve the thickness uniformity requirement.

[0196] For example, when the thickness of a certain area of the insulating layer is 0.2 microns thinner than the standard thickness, the photoresist coating in that area needs to be thickened by 0.15 microns to compensate for the thickness impact in subsequent processes. By reducing the spin coating speed of this area to 1200 revolutions per minute and extending the spin coating time to 45 seconds, the local thickening effect is achieved.

[0197] In one possible implementation, the setting of the exposure parameters is dynamically adjusted based on the output results of the multi-layer perception algorithm. The input layer of the multi-layer perception algorithm contains 12 nodes, corresponding to the insulating layer thickness mean value, standard deviation, maximum deviation, material dielectric constant, thermal expansion coefficient and other characteristic parameters. The hidden layer is set to two layers, the first layer contains 20 nodes, the second layer contains 15 nodes, and the output layer contains 3 nodes, which respectively output the optimal exposure time, light intensity and exposure mode selection.

[0198] Specifically, when the input insulating layer thickness standard deviation is 0.08 microns and the dielectric constant is 3.2, the multi-layer perception algorithm outputs an exposure time of 9.2 seconds and a light intensity of 28 milliwatts per square centimeter. This parameter combination can achieve the best pattern transfer accuracy under the current substrate state, with an edge definition of 1.2 microns of sharpness value.

[0199] It should be noted that the graphic edge definition detection adopts a sub-pixel level edge detection algorithm to improve the measurement accuracy. The algorithm determines the accurate position of the edge by analyzing the gray scale gradient change near the edge of the graphic, and the measurement accuracy can reach 0.05 microns. When the edge definition is insufficient, the algorithm can automatically identify whether the problem is caused by underexposure or overexposure, and give corresponding parameter adjustment suggestions.

[0200] Preferably, the etching process adopts an inductively coupled plasma etching device to realize precise control of etching rate and anisotropy by independently controlling radio frequency power and bias power. Radio frequency power controls plasma density, affecting etching rate, and bias power controls ion bombardment energy, affecting etching directionality. For a line width of 5 microns, the radio frequency power is set to 800 watts, and the bias power is set to 200 watts, which can realize a high-quality etching profile with a perpendicularity greater than 85 degrees.

[0201] Step S6, making a conductive layer: a thin copper conductive layer is made on the surface of the plate by chemical copper deposition or sputtering copper;

[0202] Step S7, film pasting: dry film is pasted on the surface of the plate;

[0203] Step S8, pattern transfer: the pattern is transferred to the dry film again using pattern transfer technology, and the unnecessary part is removed by development;

[0204] Step S9, pattern plating: the pattern area is filled by electroplating until the insulating layer is filled, forming a buried wire structure;

[0205] In this embodiment, the pattern area is filled by electroplating in step S9 until the insulating layer is filled, forming a buried wire structure, and the specific process is as follows:

[0206] Step S901, prepare a chemical plating solution and control the metal ion concentration; including:

[0207] Step S90101, calculate the required metal ion molar concentration according to the geometric size and depth-to-diameter ratio of the through hole. By measuring the geometric parameters of the through hole with a diameter ranging from 50 microns to 200 microns and a depth ranging from 100 microns to 500 microns, the mass transfer rate of metal ions in the hole is calculated using the Stokes diffusion equation to determine that the copper ion concentration needs to be maintained within the range of 0.02 mol / L to 0.08 mol / L, and the nickel ion concentration is controlled between 0.01 mol / L and 0.04 mol / L.

[0208] Step S90102, prepare the electroless plating solution components containing reducing agent and complexing agent. Sodium hypophosphite is used as the main reducing agent, with a concentration of 0.15 mol / L to 0.25 mol / L, and sodium citrate is added as the complexing agent, with a concentration of 0.1 mol / L to 0.2 mol / L, to stabilize the existence of metal ions in the solution through complexation reaction and prevent hydrolysis and precipitation of metal ions.

[0209] Step S90103, adjust the concentration of buffer and stabilizer in the plating solution. Add sodium acetate buffer to maintain the pH value of the solution in the range of 4.5 to 5.5, and add thiourea stabilizer with a concentration of 1 mg / L to 5 mg / L to inhibit the spontaneous decomposition reaction of the plating solution and prolong the service life of the plating solution.

[0210] Step S902, pretreat the surface of the insulating layer to enhance the adhesion of the metal; including:

[0211] Step S90201, use plasma cleaning to remove organic contaminants on the surface of the insulating layer. In an oxygen plasma environment, set the radio frequency power to 100 W to 300 W, and the processing time to 30 seconds to 120 seconds, to completely remove surface grease and organic residues through oxidation reaction of active oxygen atoms in the plasma.

[0212] Step S90202, perform surface roughening treatment to increase the surface area and adhesion points. Use potassium permanganate solution with a concentration of 2 g / L to 8 g / L, and treat at a temperature of 60 degrees Celsius to 80 degrees Celsius for 5 minutes to 15 minutes, to form a micro-rough structure on the surface of the insulating layer through oxidation reaction, increasing the mechanical anchoring effect of the metal plating layer.

[0213] Step S903, immerse the substrate in the electroless plating solution and start the autocatalytic reaction;

[0214] Immerse the pretreated substrate vertically into the prepared electroless plating solution, ensuring that the through-hole is completely immersed in the plating solution, and start the metal deposition process on the surface of the insulating layer and the inner wall of the through-hole through the redox reaction of the reducing agent and metal ions.

[0215] Step S904, control the plating solution temperature and pH value to maintain the stability of the reaction; including:

[0216] Step S90401, set the plating solution temperature control system to maintain a constant reaction temperature. The plating solution temperature is accurately controlled in the range of 75 degrees Celsius to 85 degrees Celsius, with a temperature fluctuation amplitude of not more than plus or minus 1 degree Celsius, and the temperature is accurately adjusted through a constant temperature water bath circulation system to ensure the stability of the chemical reaction rate.

[0217] Step S90402, real-time monitoring and adjusting the pH value of the plating solution. An online pH sensor is used to continuously monitor the acidity and alkalinity of the plating solution. When the pH value deviates from the set range, sodium hydroxide or hydrochloric acid solution is automatically added for adjustment, maintaining the pH value within the optimal reaction interval of 4.8 to 5.2.

[0218] Step S905, real-time monitoring of thickness change during deposition; including:

[0219] Step S90501, real-time change of plating thickness is measured by electrochemical impedance spectroscopy. By setting reference electrode and working electrode on the substrate, the change rule of electrochemical impedance with the growth of plating thickness is measured, and the linear relationship model between impedance value and plating thickness is established to realize online monitoring of thickness.

[0220] Step S90502, the uniformity of the plating layer on the inner wall of the through hole is detected by optical interference method. White light interference microscope is used to scan and measure the cross section of the through hole, and the thickness of the plating layer at different positions is calculated by analyzing the change of interference fringes, and two-dimensional mapping data of thickness distribution is obtained.

[0221] Step S90503, the uniformity index value of the thickness distribution of the plating layer is calculated. The measured thickness data is statistically analyzed to calculate the standard deviation and coefficient of variation of the thickness distribution. When the standard deviation exceeds 15% of the average thickness, it is determined that the thickness distribution is uneven.

[0222] Step S906, if the deposition thickness is not uniform, adjust the plating solution concentration and reaction time parameters; including:

[0223] Step S90601, adjust the metal ion concentration according to the thickness distribution deviation. When the thickness of the plating layer at the bottom of the through hole is significantly smaller than the thickness at the hole, increase the metal ion concentration by 10% to 20%, increase the metal deposition rate at the deep part of the hole, and improve the uniformity of the thickness distribution.

[0224] Step S90602, optimize the reaction time and plating solution circulation parameters. Prolong the chemical plating time by 15 to 30 minutes, and increase the circulation flow rate of the plating solution. By forced convection, improve the mass transfer conditions in the hole, and promote the diffusion and transmission of metal ions to the hole bottom.

[0225] Step S907, improve the compactness and uniformity of the plating layer by ultrasonic assistance; including:

[0226] Step S90701, set the frequency and power parameters of the ultrasonic generator. Ultrasonic waves with a frequency of 40 kHz to 80 kHz and a power density of 0.5 W / cm² to 2.0 W / cm² are used to promote the micro-stirring of the plating solution in the through hole by cavitation effect.

[0227] Step S90702, control the time interval and duration of ultrasonic action. Adopt intermittent ultrasonic treatment mode, stop for 10 seconds after each action of 30 seconds, avoid over strong ultrasonic energy to cause damage to the formed coating, at the same time keep the uniform mixing state of plating solution.

[0228] Step S90703, monitor the influence effect of ultrasonic treatment on the microstructure of the coating. Observe the grain size and density of the coating by scanning electron microscope, the grain size of the coating after ultrasonic treatment is reduced by 20% to 40%, the density of the coating is increased by 5% to 15%, which significantly improves the mechanical properties and electrical properties of the coating.

[0229] Step S908, after the insulating layer is filled, cleaning and drying treatment is carried out to form a buried wire structure.

[0230] In one embodiment, the preparation process of the electroless plating solution needs to strictly control the addition order and mixing method of each component. First, deionized water is heated to a preset temperature, then complexing agent, buffer and metal salt are added in sequence, and finally reducing agent is added to start the chemical reaction. This sequence can avoid the premature reduction of metal ions, ensuring the stability of the plating solution and the controllability of the reaction.

[0231] Specifically, when the diameter of the through hole is 100 microns and the depth is 300 microns, the depth-diameter ratio reaches 3:1, at which time special attention needs to be paid to the mass transfer efficiency in the hole. By increasing the complexing agent concentration to 0.18 mol / L, the solubility and stability of metal ions can be improved, while appropriately reducing the reducing agent concentration to 0.18 mol / L, the reaction rate is slowed down, giving metal ions sufficient time to diffuse to the bottom of the hole, achieving uniform coating distribution.

[0232] Illustratively, in actual production, when it is detected that the coating thickness on the upper part of the through hole is 8 microns and the bottom is only 4 microns, it indicates that there is a significant thickness gradient. At this time, ultrasonic assisted treatment is adopted, the frequency is set to 60 kHz, the power density is 1.2 W / cm², and the intermittent action mode is used for 20 minutes, which can reduce the thickness difference to within 1 micron, significantly improving the uniformity of the coating.

[0233] In one possible implementation, electrochemical impedance spectroscopy monitoring adopts a three-electrode system, taking the plated substrate as the working electrode, platinum wire as the counter electrode, and saturated calomel electrode as the reference electrode. By applying a small amplitude AC voltage signal, the impedance response at different frequencies is measured, and a linear relationship between the real part of the impedance and the coating thickness is established. When the coating thickness increases from 2 microns to 10 microns, the real part of the impedance shows a linear downward trend, and the correlation coefficient reaches more than 0.98, providing a reliable technical means for real-time thickness monitoring.

[0234] It should be noted that the ultrasonic cavitation effect plays an important role in the electroless plating process. When the ultrasonic wave propagates in the plating solution, micro-bubbles are generated in the negative pressure phase, and the bubbles break in the positive pressure phase to generate local high temperature and high pressure. This micro-mechanical stirring effect can break the concentration boundary layer in the via hole, promote the contact of fresh plating solution with the hole wall, and at the same time remove the gas adsorbed on the surface of the plating layer, thereby improving the compactness and adhesion of the plating layer.

[0235] Step S10, film removal: using a film removal solution to remove the line dry film;

[0236] Step S11, etching: using an etching technique to remove the conductive layer on the surface of the insulating layer, and finally complete the production of the buried line printed circuit board.

[0237] Figure 4 For a comparison chart of the conventional processing method (left) and the processing method of the present application (right), the buried line circuit board produced by the method of the present application is processed from both sides, and a double-sided buried line structure can be produced, the production cycle is shortened, and due to the presence of the core plate, the mechanical strength of the board is good, and warping is not easy to occur.

[0238] The above is only a preferred embodiment of the present application, and does not limit the present application in any way. Any simple modification, change and equivalent structural change made according to the technical essence of the present application to the above embodiment are still within the protection scope of the technical solution of the present application.

Claims

1. A method for manufacturing a double-sided buried wiring printed circuit board, characterized by, The method comprises the following steps: Inner layer processing: using the conventional process of printed circuit board to process the inner layer core board; Insulation lamination: using lamination process to laminate the insulation layer; Through hole making: using laser drilling to make through hole; Insulation layer film pasting: using film pasting to paste the photosensitive insulation layer on the surface of the board; Pattern transfer post-curing: using pattern transfer technology to transfer the circuit pattern to the insulation layer, using developing to remove the unnecessary part, and then using heating curing to completely cure the insulation layer; The pattern transfer technology comprises the following steps: The specific process of pre-setting the pattern transfer control strategy comprises the following steps: Obtaining the thickness distribution data of the insulation layer on the surface of the inner layer core board, using laser scanning measurement technology to detect the thickness of each point on the substrate surface, and obtaining the standardized data matrix of the thickness distribution; According to the standardized data matrix of the thickness distribution, a mapping relationship model between the insulation layer and the through layer is established by using a multilayer perception algorithm to obtain a targeted pattern transfer control strategy; Making the through layer: using chemical copper deposition or sputtering copper to make a thin copper through layer on the surface of the board; Film pasting: pasting the circuit dry film on the surface of the board; Pattern transfer: using pattern transfer technology to transfer the pattern to the dry film again, and using developing to remove the unnecessary part; Pattern plating: using plating to fill the pattern area until the insulation layer is filled, and forming a buried wire structure; Film removing: using film removing liquid to remove the circuit dry film; Etching: using etching technology to remove the through layer on the surface of the insulation layer, and finally completing the manufacturing of the buried wire printed circuit board.

2. The method of claim 1, wherein: the first and second conductive layers are formed by a plating process; and the first and second conductive layers are formed by a plating process. The specific process of using laser drilling to make through hole comprises the following steps: Using a high-resolution camera to collect images of the insulation layer pattern structure; Enhancing the edge contrast of the through hole by using an image preprocessing algorithm; Identifying the contour boundary of the through hole by using an edge detection algorithm; Calculating the geometric center coordinates of the through hole contour; Establishing the conversion relationship between the pixel coordinates and the actual physical coordinates; If the position deviation of the through hole exceeds the allowed range, record the deviation data and generate a position correction instruction; Statistically analyzing the measurement results to evaluate the overall position accuracy; Constructing a data set containing all the accurate coordinates of the through holes; Using laser drilling to make through hole; The specific process of pre-setting the pattern transfer control strategy comprises the following steps: Obtaining the thickness distribution data of the insulation layer on the surface of the inner layer core board, using laser scanning measurement technology to detect the thickness of each point on the substrate surface, and obtaining the standardized data matrix of the thickness distribution; According to the thickness distribution data matrix, a mapping relationship model between the insulation layer and the through layer is established by using a multilayer perception algorithm to obtain a targeted pattern transfer control strategy. The laser scanning measurement technology comprises the following steps:

3. The method of claim 1, wherein: the first and second conductive layers are formed by a plating process; and the first and second conductive layers are formed by a single plating process. Scanning the substrate surface by using a laser beam, measuring the time difference of the laser reflection signal, and calculating the thickness value of each measurement point; ​ If the thickness change exceeds the preset threshold range, an adaptive threshold segmentation algorithm is used to mark and identify the abnormal area; The measured thickness data is normalized to eliminate system error; A two-dimensional thickness distribution matrix is constructed to record the coordinate position and corresponding thickness value of each measurement point; The abnormal area is repeatedly measured and verified to confirm the authenticity of the thickness anomaly; A visual image of the thickness distribution is generated to identify the range of thickness change.

4. The method of claim 1, wherein: the first and second conductive layers are formed by a plating process; and the first and second conductive layers are formed by a single plating process. The multi-layer perceptron algorithm is used to establish a mapping relationship model between the insulation layer and the conducting layer, including: Collecting historical manufacturing data related to pattern transfer accuracy and material property changes; Building a multi-layer neural network structure and setting the input layer to receive thickness distribution data; Through the hidden layer, the complex nonlinear mapping relationship is handled, and the key feature parameters are extracted; In the output layer, the prediction result of the optimal process parameter combination is generated; The backpropagation algorithm is used to train the network weights to optimize the model prediction accuracy; The generalization ability of the model is evaluated through cross-validation method; The similarity between the current substrate state and historical data is analyzed to determine the applicability of the model; Generate personalized process parameter recommendations for the current substrate characteristics.

5. A method for manufacturing a double-sided embedded wire printed circuit board according to claim 1, characterized in that: The precision lithography technology is used to form a predetermined line pattern on the surface of the insulation layer, including: Coating a photosensitive adhesive layer on the surface of the insulation layer to control the uniformity of the coating thickness; Setting the exposure parameters according to the control strategy, including exposure time and light intensity; Through the mask, the photosensitive adhesive layer is selectively exposed to form a latent image pattern; Developing treatment to remove the unexposed or exposed photosensitive adhesive parts; Detecting the clarity of the pattern edge and the line width accuracy; If the clarity of the pattern edge is lower than the quality standard, adjust the exposure parameters and re-perform the pattern transfer; Through etching process, the pattern is transferred to the insulation layer to form the final pattern structure.

6. The method of claim 1, wherein: The pattern area is filled by electroplating until the insulation layer is filled, forming a buried wire structure, the specific process is as follows: ​ Prepare the chemical plating solution and control the metal ion concentration; Pretreat the surface of the insulation layer to enhance the adhesion of the metal; Immerse the substrate in the chemical plating solution to start the autocatalytic reaction; Control the plating solution temperature and pH value to maintain the stability of the reaction; Real-time monitor the thickness change during deposition; If the degree of uneven deposition thickness exceeds the preset standard, adjust the plating solution concentration and reaction time parameters; Improve the density and uniformity of the plating layer by ultrasonic assistance; After the insulation layer is filled, clean and dry the buried wire structure.

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