Flash memory device and preparation method thereof
By adjusting the etching process and mask pattern, and employing non-selective plasma etching and high-selective chemical dry etching, the etching damage problem in flash memory devices was solved, thereby improving the reliability and performance of the devices.
Patent Information
- Application Number
- CN202511052838.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-29
- Publication Date
- 2025-11-11
AI Technical Summary
In the fabrication process of flash memory devices, traditional plasma etching damages the polysilicon side surface of the bit lines, leading to leakage current, while chemical dry etching damages the polysilicon sidewalls of the outermost word lines of the memory cell, resulting in device reliability issues.
By employing a non-selectivity plasma etching process and a high-selectivity chemical dry etching process, and adjusting the mask pattern, only the bit line polysilicon of the memory region and the lead-out region is etched to avoid damage to the floating gate layer and the sidewalls of the memory cell.
It improves the reliability of flash memory devices, avoids problems such as leakage and abnormal contact, and improves the overall performance of the devices.
Smart Images
Figure CN120936032A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, specifically to a flash memory device and its fabrication method. Background Technology
[0002] In Nord Flash memory devices, the film quality on the sides of the floating gate layer can affect device reliability. During conventional plasma etching of bit line and word line polysilicon, excessive plasma pressure can damage the side surfaces of the bit line (BL) polysilicon, leading to leakage paths. This leakage manifests as electron loss from the floating gate layer when BL voltage is applied. Furthermore, conventional plasma etching of bit line and word line polysilicon can open up the word line polysilicon in the lead-out area. Chemical dry etching (CDE) can damage the sidewalls of the word line polysilicon in the outermost memory cell, causing side-hole defects. This results in contact abnormalities in the conductive plugs formed in the second trench after etching the word line polysilicon in the conventional fabrication process. Summary of the Invention
[0003] This application provides a flash memory device and its fabrication method, which can solve at least one of the following problems during the plasma etching process of bit lines and word lines polysilicon: excessive plasma damages the side surface of bit line polysilicon, leading to device leakage; and chemical dry etching damages the sidewall of word line polysilicon in the outermost memory cell at the junction of the memory region and the lead-out region, resulting in side-hole defects.
[0004] On one hand, embodiments of this application provide a method for fabricating a flash memory device, including:
[0005] A substrate is provided, the substrate comprising at least: a storage region and a lead-out region, wherein a gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer and a first dielectric layer are formed on the substrate of the storage region and the lead-out region, wherein the first dielectric layer, the control gate layer and the ONO film layer form staggered first trenches and second trenches, the sidewalls of the first trenches are covered with a first sidewall structure, the sidewalls of the second trenches are covered with a second sidewall structure, the remaining space of the first trenches is filled with bit line polysilicon, and the remaining space of the second trenches is filled with word line polysilicon;
[0006] A photoresist layer is coated on the surfaces of the first dielectric layer, the bit line polysilicon, and the word line polysilicon.
[0007] Using photolithography, etching patterns are defined on a photoresist layer above the bit line polysilicon of the memory region and the lead-out region and above the first dielectric layer near both sides of the bit line polysilicon to form a patterned photoresist layer, wherein the patterned photoresist layer covers the word line polysilicon of the memory region and the lead-out region.
[0008] Using the patterned photoresist layer as a mask, a non-selective plasma etching process is used to etch a portion of the thickness of the bit line polysilicon and a portion of the thickness of the first dielectric layer near both sides of the bit line polysilicon in the memory region and the lead-out region, so as to form an opening at the first trench location, wherein the opening is larger in width than the first trench.
[0009] The remaining thickness of the bit-line polysilicon in the first trench below the opening is removed by etching using a high-selectivity chemical dry etching process;
[0010] Remove the patterned photoresist layer.
[0011] Optionally, in the method for fabricating the flash memory device, before coating the first dielectric layer, the bit line polysilicon, and the word line polysilicon surface with a photoresist layer, the bit line polysilicon surface and the word line polysilicon surface are further covered with a protective layer.
[0012] Optionally, in the method for fabricating the flash memory device, the ONO film layer comprises: a stacked first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer, wherein the first silicon oxide layer covers the floating gate layer, the first silicon nitride layer covers the first silicon oxide layer, and the second silicon oxide layer covers the first silicon nitride layer.
[0013] Optionally, in the method for fabricating the flash memory device, after removing the patterned photoresist layer, the method further includes:
[0014] A second dielectric layer is formed, which fills the opening at the location where the bit line polysilicon is removed;
[0015] The second dielectric layer and the gate oxide layer of the storage region and the lead-out region are etched to form contact holes in the second dielectric layer and the gate oxide layer;
[0016] A metal layer is filled into the contact hole to obtain a conductive plug in the storage area that contacts the surface of the substrate.
[0017] Optionally, in the method for fabricating the flash memory device, the material of the first dielectric layer is silicon dioxide.
[0018] Optionally, in the method for fabricating the flash memory device, the protective layer is made of silicon dioxide.
[0019] Optionally, in the method for fabricating the flash memory device, the first sidewall structure includes: a third silicon oxide layer, a second silicon nitride layer, and a fourth silicon oxide layer, wherein the third silicon oxide layer covers the sidewall of the first trench, the second silicon nitride layer covers the third silicon oxide layer, and the fourth silicon oxide layer covers the second silicon nitride layer.
[0020] Optionally, in the method for fabricating the flash memory device, the second sidewall structure includes: a fifth silicon oxide layer, a third silicon nitride layer, and a sixth silicon oxide layer, wherein the fifth silicon oxide layer covers the sidewall of the second trench, the third silicon nitride layer covers the fifth silicon oxide layer, and the sixth silicon oxide layer covers the third silicon nitride layer.
[0021] On the other hand, embodiments of this application also provide a flash memory device, including:
[0022] A substrate comprising at least a storage region and an exit region, wherein a gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer and a first dielectric layer are formed on the substrate of the storage region and the exit region, wherein the first dielectric layer, the control gate layer and the ONO film layer are formed with staggered first trenches and second trenches, the sidewalls of the first trenches are covered with a first sidewall structure, the sidewalls of the second trenches are covered with a second sidewall structure, the remaining space of the first trenches is filled with bit line polysilicon, and the second trenches are filled with word line polysilicon;
[0023] A plurality of openings are spaced apart in the first dielectric layer and the bit line polysilicon at the top of the first trench to open the bit line polysilicon of the memory region and the lead-out region at intervals, wherein the size of the opening in width is greater than the size of the first trench in width, and the bit line polysilicon in the first trench at the bottom of the opening is etched away.
[0024] The technical solution of this application has at least the following advantages:
[0025] In the flash memory device fabrication method provided in this application, the mask layout for traditional bit line and word line polysilicon etching is modified. Only the bit line polysilicon in the memory region and the lead-out region is exposed, while the word line polysilicon in the lead-out region is not exposed. At the same time, a non-selectivity plasma etching process is used to etch a portion of the bit line polysilicon thickness in the memory region and the lead-out region, as well as a portion of the first dielectric layer thickness near both sides of the bit line polysilicon. Then, a high-selectivity chemical dry etching process is used to etch and remove the remaining bit line polysilicon thickness in the first trench below the opening. This avoids the problem of excessive plasma damage to the floating gate layer on the bit line polysilicon side, which leads to device leakage, in the traditional fabrication process of plasma etching of bit line and word line polysilicon. It reduces the damage to the floating gate layer film on the bit line polysilicon side and improves the reliability of the flash memory device.
[0026] Furthermore, in the flash memory device fabrication method provided in this application, since the mask layout for traditional bit line and word line polysilicon etching is modified, the word line polysilicon in the lead-out area is still covered by the photoresist layer. Therefore, the word line polysilicon in the second trench of the lead-out area is not etched, thereby avoiding damage to the sidewall of the word line polysilicon in the outermost memory cell at the junction of the memory area and the lead-out area caused by the subsequent high selectivity chemical dry etching process, thus avoiding the side-hole defect. This also avoids the contact abnormality of the conductive plug formed in the second trench after etching the word line polysilicon in the traditional fabrication process. Attached Figure Description
[0027] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0028] Figure 1 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention;
[0029] Figures 2-7 This is a schematic diagram of the semiconductor structure in each process step of fabricating a flash memory device according to an embodiment of the present invention;
[0030] The reference numerals in the attached figures are explained as follows:
[0031] 10-Substrate, 20-Gate oxide layer, 30-Floating gate layer, 40-ONO film layer, 50-Control gate layer, 60-First dielectric layer, 61-First trench, 62-Second trench, 63-Opening, 71-First sidewall structure, 72-Second sidewall structure, 81-Bit line polysilicon, 82-Word line polysilicon, 90-Protective layer, 91-Patterned photoresist layer. Detailed Implementation
[0032] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0033] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0034] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0035] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0036] This application provides a method for fabricating a flash memory device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention. The method for fabricating the flash memory device includes:
[0037] First, perform step S1: Refer to Figure 2 and Figure 3 , Figure 2This is a schematic diagram of the semiconductor structure after the formation of the first sidewall structure and the second sidewall structure according to an embodiment of this application. Figure 3 This is a schematic diagram of the semiconductor structure after the formation of bit line polysilicon, word line polysilicon, and protective layer according to an embodiment of this application. A substrate 10 is provided, which includes at least a memory region and an exit region. A gate oxide layer 20, a floating gate layer 30, an ONO film layer 40, a control gate layer 50, and a first dielectric layer 60 are formed on the substrate 10 of the memory region and the exit region. The first dielectric layer 60, the control gate layer 50, and the ONO film layer 40 are formed with staggered first trenches 61 and second trenches 62. The sidewalls of the first trenches 61 are covered with a first sidewall structure 71, and the sidewalls of the second trenches 62 are covered with a second sidewall structure 72. The remaining space of the first trenches 61 is filled with bit line polysilicon 81, and the remaining space of the second trenches 62 is filled with word line polysilicon 82.
[0038] Preferably, the ONO film layer 40 includes: a stacked first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer (not shown), wherein the first silicon oxide layer covers the floating gate layer 30, the first silicon nitride layer covers the first silicon oxide layer, and the second silicon oxide layer covers the first silicon nitride layer.
[0039] In this embodiment, the first dielectric layer 60 is made of silicon dioxide.
[0040] Preferably, the first sidewall structure 71 includes a third silicon oxide layer, a second silicon nitride layer, and a fourth silicon oxide layer, wherein the third silicon oxide layer covers the sidewall of the first trench 61, the second silicon nitride layer covers the third silicon oxide layer, and the fourth silicon oxide layer covers the second silicon nitride layer.
[0041] Furthermore, the second sidewall structure 72 includes a fifth silicon oxide layer, a third silicon nitride layer, and a sixth silicon oxide layer, wherein the fifth silicon oxide layer covers the sidewall of the second trench 62, the third silicon nitride layer covers the fifth silicon oxide layer, and the sixth silicon oxide layer covers the third silicon nitride layer.
[0042] Preferably, before the photoresist layer is coated on the surface of the first dielectric layer 60, the bit line polysilicon 81 and the word line polysilicon 82 (step S2), the surface of the bit line polysilicon 81 and the surface of the word line polysilicon 82 are also covered with a protective layer 90.
[0043] Specifically, the protective layer 90 is made of silicon dioxide.
[0044] Then, proceed to step S2: (Refer to...) Figure 4 , Figure 4This is a schematic diagram of the semiconductor structure after the formation of a patterned photoresist layer according to an embodiment of this application. The photoresist layer is coated on the surface of the first dielectric layer 60, the bit line polysilicon 81, and the word line polysilicon 82.
[0045] Next, proceed to step S3: Continue to refer to Figure 4 Through photolithography, etching patterns are defined on the photoresist layer above the bit line polysilicon 81 of the memory region and the lead-out region and on the first dielectric layer 60 near both sides of the bit line polysilicon 81 to form a patterned photoresist layer 91, wherein the patterned photoresist layer 91 covers the word line polysilicon 82 of the memory region and the lead-out region.
[0046] Further, proceed to step S4: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after the opening is formed according to an embodiment of this application. Using the patterned photoresist layer 91 as a mask, a non-selective plasma etching process is used to etch a portion of the thickness of the bit line polysilicon 81 and the first dielectric layer 60 near both sides of the bit line polysilicon 81 to form an opening 63 at the location of the first trench 61. The opening 63 is larger in width than the first trench 61.
[0047] Next, proceed to step S5: (Refer to...) Figure 6 , Figure 6 This is a schematic diagram of the semiconductor structure after etching away the remaining thickness of the bit-line polysilicon 81 in the first trench 61 below the opening 63, according to an embodiment of this application. A high-selectivity chemical dry etching process is used to etch away the remaining thickness of the bit-line polysilicon 81 in the first trench 61 below the opening 63. The chemical dry etching process is characterized by ion-free, isotropic etching. The consumption of the first dielectric layer 60 and the first sidewall structure 71 during the etching of the remaining thickness of the bit-line polysilicon 81 in the first trench 61 below the opening 63 is negligible. Therefore, it can be considered that the chemical dry etching is only performed on the bit-line polysilicon 81.
[0048] It is worth noting that the bit line polysilicon 81 (first trench 61) is elongated, and the opening 63 opens the bit line polysilicon 81 at intervals. It does not completely remove all the bit line polysilicon 81 in the first trench 61. After step S5, the first trench 61 between adjacent openings 63 is still filled with bit line polysilicon 81. This part of the retained bit line polysilicon 81 is covered by a mask layer such as a photoresist layer in step S5.
[0049] Finally, proceed to step S6: (Refer to...) Figure 7 , Figure 7 This is a schematic diagram of the semiconductor structure after the patterned photoresist layer 91 has been removed, according to an embodiment of this application.
[0050] Furthermore, after removing the patterned photoresist layer 91, the method for fabricating the flash memory device may further include:
[0051] Step S7.1: Form a second dielectric layer (not shown), the second dielectric layer filling the opening at the location where the bit line polysilicon is removed;
[0052] Step S7.2: Etch the second dielectric layer and the gate oxide layer (not shown) of the storage region and the lead-out region to form contact holes in the second dielectric layer and the gate oxide layer;
[0053] Step S7.3: Fill the contact hole with a metal layer (not shown) to obtain a conductive plug in the storage area that contacts the surface of the substrate.
[0054] In this application, the mask layout for traditional bit-line polysilicon and word-line polysilicon etching is modified. Only the bit-line polysilicon in the memory region and the lead-out region is exposed, while the word-line polysilicon in the lead-out region is not exposed. At the same time, a non-selectivity plasma etching process is used to etch a portion of the bit-line polysilicon thickness in the memory region and the lead-out region, as well as a portion of the first dielectric layer near both sides of the bit-line polysilicon. Then, a high-selectivity chemical dry etching process is used to etch and remove the remaining bit-line polysilicon thickness in the first trench below the opening. This avoids the problem of excessive plasma damage to the floating gate layer on the bit-line polysilicon side, which leads to device leakage, in the traditional preparation process of bit-line and word-line polysilicon plasma etching. This reduces the damage to the floating gate layer film on the bit-line polysilicon side and improves the reliability of the flash memory device. Furthermore, because this application modifies the mask layout for traditional bit line and word line polysilicon etching, the word line polysilicon in the lead-out region is still covered by the photoresist layer. Therefore, the word line polysilicon in the second trench of the lead-out region is not etched, which avoids the subsequent high selectivity chemical dry etching process from damaging the sidewall of the word line polysilicon in the outermost memory cell at the junction of the memory region and the lead-out region, thus avoiding side-hole defects. This also avoids the contact abnormality of the conductive plug formed in the second trench after etching the word line polysilicon in the traditional fabrication process.
[0055] Based on the same inventive concept, this application also provides a flash memory device, see reference. Figure 7 The flash memory device includes:
[0056] The substrate 10 includes at least a storage region and an exit region. A gate oxide layer 20, a floating gate layer 30, an ONO film layer 40, a control gate layer 50, and a first dielectric layer 60 are formed on the substrate of the storage region and the exit region. The first dielectric layer 60, the control gate layer 50, and the ONO film layer 40 are formed with staggered first trenches 61 and second trenches 62. The sidewalls of the first trenches 61 are covered with first sidewall structures 71, and the sidewalls of the second trenches 62 are covered with second sidewall structures 72. The remaining space of the first trenches 61 is filled with bit line polysilicon 81, and the second trenches 62 are filled with word line polysilicon 82.
[0057] A plurality of openings 63 are spaced apart in the first dielectric layer 60 and the bit line polysilicon 81 at the top of the first trench 61 to space apart the bit line polysilicon 81 of the memory region and the lead-out region, wherein the opening 93 is larger in width than the first trench 61, and the bit line polysilicon 81 in the first trench 61 at the bottom of the opening 63 is etched away.
[0058] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A method for fabricating a flash memory device, characterized in that, include: A substrate is provided, the substrate comprising at least: a storage region and a lead-out region, wherein a gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer and a first dielectric layer are formed on the substrate of the storage region and the lead-out region, wherein the first dielectric layer, the control gate layer and the ONO film layer form staggered first trenches and second trenches, the sidewalls of the first trenches are covered with a first sidewall structure, the sidewalls of the second trenches are covered with a second sidewall structure, the remaining space of the first trenches is filled with bit line polysilicon, and the remaining space of the second trenches is filled with word line polysilicon; A photoresist layer is coated on the surfaces of the first dielectric layer, the bit line polysilicon, and the word line polysilicon. Using photolithography, etching patterns are defined on a photoresist layer above the bit line polysilicon of the memory region and the lead-out region and above the first dielectric layer near both sides of the bit line polysilicon to form a patterned photoresist layer, wherein the patterned photoresist layer covers the word line polysilicon of the memory region and the lead-out region. Using the patterned photoresist layer as a mask, a non-selective plasma etching process is used to etch a portion of the thickness of the bit line polysilicon and a portion of the thickness of the first dielectric layer near both sides of the bit line polysilicon in the memory region and the lead-out region, so as to form an opening at the first trench location, wherein the opening is larger in width than the first trench. The remaining thickness of the bit-line polysilicon in the first trench below the opening is removed by etching using a high-selectivity chemical dry etching process; Remove the patterned photoresist layer.
2. The method for fabricating a flash memory device according to claim 1, characterized in that, Before the photoresist layer is coated on the first dielectric layer, the bit line polysilicon, and the word line polysilicon, the bit line polysilicon and the word line polysilicon are also covered with a protective layer.
3. The method for fabricating a flash memory device according to claim 1, characterized in that, The ONO film layer includes: a stacked first silicon oxide layer, a first silicon nitride layer, and a second silicon oxide layer, wherein the first silicon oxide layer covers the floating gate layer, the first silicon nitride layer covers the first silicon oxide layer, and the second silicon oxide layer covers the first silicon nitride layer.
4. The method for fabricating a flash memory device according to claim 1, characterized in that, After removing the patterned photoresist layer, the method for fabricating the flash memory device further includes: A second dielectric layer is formed, which fills the opening at the location where the bit line polysilicon is removed; The second dielectric layer and the gate oxide layer of the storage region and the lead-out region are etched to form contact holes in the second dielectric layer and the gate oxide layer; A metal layer is filled into the contact hole to obtain a conductive plug in the storage area that contacts the surface of the substrate.
5. The method for fabricating a flash memory device according to claim 1, characterized in that, The first dielectric layer is made of silicon dioxide.
6. The method for fabricating a flash memory device according to claim 2, characterized in that, The protective layer is made of silicon dioxide.
7. The method for fabricating a flash memory device according to claim 1, characterized in that, The first sidewall structure includes a third silicon oxide layer, a second silicon nitride layer, and a fourth silicon oxide layer. The third silicon oxide layer covers the sidewall of the first trench, the second silicon nitride layer covers the third silicon oxide layer, and the fourth silicon oxide layer covers the second silicon nitride layer.
8. The method for fabricating a flash memory device according to claim 1, characterized in that, The second sidewall structure includes a fifth silicon oxide layer, a third silicon nitride layer, and a sixth silicon oxide layer. The fifth silicon oxide layer covers the sidewall of the second trench, the third silicon nitride layer covers the fifth silicon oxide layer, and the sixth silicon oxide layer covers the third silicon nitride layer.
9. A flash memory device, characterized in that, include: A substrate comprising at least a storage region and an exit region, wherein a gate oxide layer, a floating gate layer, an ONO film layer, a control gate layer and a first dielectric layer are formed on the substrate of the storage region and the exit region, wherein the first dielectric layer, the control gate layer and the ONO film layer are formed with staggered first trenches and second trenches, the sidewalls of the first trenches are covered with a first sidewall structure, the sidewalls of the second trenches are covered with a second sidewall structure, the remaining space of the first trenches is filled with bit line polysilicon, and the second trenches are filled with word line polysilicon; A plurality of openings are spaced apart in the first dielectric layer and the bit line polysilicon at the top of the first trench to open the bit line polysilicon of the memory region and the lead-out region at intervals, wherein the size of the opening in width is greater than the size of the first trench in width, and the bit line polysilicon in the first trench at the bottom of the opening is etched away.