Structure and method for improving TDDB of Cu MIM capacitor

Abstract

The invention discloses a structure and method for improving TDDB of a Cu MIM capacitor. The MIM capacitor comprises an upper metal pole plate, a lower metal pole plate and a dielectric layer located between the upper metal pole plate and the lower metal pole plate. The dielectric layer is a composite layer and comprises a silicon nitride layer located on the lower layer and an oxide layer located on the upper layer. The ALD oxide layer is additionally deposited on the traditional dielectric layer SiN, the ALD oxide layer can serve as a buffer layer between the SiN and the upper metal pole plate TiN by means of the excellent film quality, and the TDDB service life of the MIM capacitor is greatly prolonged.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device design and manufacturing, and in particular to a structure and method for improving the TDDB of Cu MIM capacitors. Background Technology

[0002] Integrated circuit capacitor structures can be broadly classified into the following four categories: MOS (Metal-oxide-semiconductor) capacitors, PN junction capacitors, PIP (poly-insulator-poly) capacitors, and MIM (Metal-Insulator-Metal) capacitors are respectively as follows: Figures 1-4 As shown, a MOS capacitor consists of a metal, a semiconductor substrate, and an oxide dielectric layer between them; a PN junction capacitor is a capacitor formed by a PN junction of P-type and N-type materials, with a potential barrier region at the junction. Changes in voltage across the junction cause changes in the amount of charge accumulated in this region, thus exhibiting a capacitance effect; while PIP capacitors and MIM capacitors differ mainly in the material of their capacitor plates, being polycrystalline silicon and metal, respectively. Different types of capacitors have different characteristics.

[0003] MOS capacitors and PN junction capacitors based on substrates and underlying devices are greatly affected by the operating voltage and current of transistors, and the capacitors are prone to instability in circuits; PIP electrode plates are made of polycrystalline silicon, with high contact resistance and large parasitic capacitance, requiring more thermal processes, which has a significant impact on devices; MIM capacitors, by using metal electrodes, effectively reduce the contact resistance and parasitic capacitance between the capacitor and the interconnect, thus the high capacitance density MIM capacitors with strong conductivity and no loss have become a new type of capacitor to replace traditional integrated circuit capacitors.

[0004] Development of high TDDB MIM devices: The time-dependent dielectric breakdown (TDDB) characteristic of the MIM dielectric layer can be used to characterize a range of issues related to the lifetime of MIM devices, and is of great significance in discussing device reliability. Especially for MIM devices operating at high voltages, their TDDB lifespan is typically shorter because TDDB lifespan is inversely proportional to the operating voltage; the higher the operating voltage, the more prone to breakdown, and the lower the TDDB. Therefore, improving TDDB is of paramount importance. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a structure and process method for improving the TDDB life of MIM capacitors.

[0006] To address the above problems, the present invention provides an improved MIM capacitor, wherein the capacitor comprises upper and lower metal plates and a dielectric layer located between the upper and lower metal plates; The dielectric layer is a composite layer, comprising a silicon nitride layer at the bottom and an oxide layer at the top.

[0007] Furthermore, the lower metal plate is made of copper, and the upper metal plate is made of TiN.

[0008] Furthermore, in the dielectric layer, the upper oxide layer is an ALD oxide layer.

[0009] Furthermore, the ALD oxide layer serves as a buffer layer between the silicon nitride layer and the upper metal electrode TiN, thereby improving device lifespan.

[0010] The present invention discloses a process method for manufacturing a MIM capacitor, comprising: First, a Cu metal layer is deposited on a semiconductor substrate as the lower metal plate of the capacitor; A silicon nitride layer is formed on the lower metal electrode plate; Further deposit an oxide layer on the silicon nitride layer; The first metal layer is deposited as the upper metal plate of the capacitor; The first metal layer, oxide layer, silicon nitride layer, and Cu metal layer are etched to form a MIM capacitor.

[0011] Furthermore, the thickness of the silicon nitride layer is 420 Å.

[0012] Furthermore, the oxide layer is an ALD oxide layer with a thickness of 25 Å.

[0013] Furthermore, the formation process of the ALD oxide layer is as follows: the AR_AMPDS gas flow rate is 500-2000 sccm, the N2O flow rate is 700-13000 sccm, the O2 flow rate is 2000-7000 sccm, the high-frequency HF power is 2000-5000W, and the reaction temperature is 300-400℃.

[0014] Furthermore, the first metal layer is TiN with a thickness of 1000 Å.

[0015] The MIM capacitor described in this invention, by depositing an additional ALD oxide layer on the conventional dielectric layer SiN, utilizes the excellent thin film quality of the ALD oxide layer to serve as a buffer layer between SiN and the upper metal plate TiN, thus significantly improving the TDDB lifetime of the MIM capacitor. Attached Figure Description

[0016] Figure 1 This is a cross-sectional view of a MOS capacitor.

[0017] Figure 2 This is a cross-sectional view of a PN junction capacitor.

[0018] Figure 3 This is a cross-sectional view of a PIP capacitor.

[0019] Figure 4 This is a cross-sectional view of a MIM capacitor.

[0020] Figure 5 This is a cross-sectional view of the improved MIM capacitor structure of the present invention. Detailed Implementation

[0021] The following detailed description, in conjunction with the accompanying drawings, provides specific embodiments of the present invention and clearly and completely describes the technical solutions of the present invention. However, the present invention is not limited to the following embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise ratios, and are only used for the purpose of conveniently and clearly illustrating the embodiments of the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0022] It should be understood that the present invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated, and the same reference numerals denote the same elements throughout. It should be understood that when an element or layer is referred to as “on,” “adjacent to,” “connected to,” or “coupled to” other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part.

[0023] The present invention provides a MIM capacitor structure having a composite intermediate dielectric layer comprising an ALD oxide layer and a silicon nitride layer.

[0024] This invention addresses the problem of short TDDB lifespan in copper-plated MIM capacitors by studying the relationship between the dielectric layer and TDDB in the MIM structure capacitor, and provides a new MIM capacitor structure with high TDDB.

[0025] Taking a conventional copper-plated MIM capacitor as an example, its lower metal plate is copper, the upper metal plate is a TiN metal layer, and the middle is a silicon nitride dielectric layer. For a 1.5fF MIM capacitor, the thickness of the silicon nitride dielectric layer is approximately 470 Å, and the thickness of the upper TiN metal plate is 1000 Å.

[0026] like Figure 5 As shown, the improved MIM capacitor of this invention replaces the middle dielectric layer with a composite layer, comprising the original silicon nitride layer at the bottom and a newly added oxide layer. The oxide layer is an ALD oxide layer.

[0027] Atomic Layer Deposition (ALD) is a precise thin film deposition technique. Its core principle utilizes the self-limiting nature of chemical reactions to grow thin films layer by layer, at the atomic or molecular level. Only one atomic layer is deposited per cycle, and through repeated cycles, a uniform film of the desired thickness is gradually formed. ALD-deposited films are dense and free of micropores, ensuring excellent sealing and isolation properties. This is because each cycle deposits only one atomic layer, allowing the deposition process to fill in minute defects in the film and maintain its integrity. These defect-free films are widely used in high-performance electronic devices (such as gate oxide layers), anti-corrosion coatings, and gas barriers.

[0028] In the MIM capacitor structure of this invention, the lower electrode is a copper metal electrode, the middle layer is a composite dielectric layer, namely the lower layer of conventional silicon nitride and the upper layer of ALD oxide, and the upper electrode is TiN.

[0029] The overall thickness of the resulting composite dielectric layer can be comparable to that of an existing single dielectric layer, or, due to the superior quality of the ALD oxide layer, the overall dielectric layer thickness can be slightly thinner than that of an existing dielectric layer. Taking a 1.5fF MIM capacitor as an example, the original single silicon nitride dielectric layer has a thickness of 470 Å. When replaced with the composite dielectric layer structure of this invention, the thickness of the lower silicon nitride dielectric layer is 420 Å, the thickness of the upper ALD oxide layer is 25 Å, and the overall composite dielectric layer thickness is 445 Å, thinner than the original 470 Å.

[0030] The main difference between this invention and the process for fabricating a MIM capacitor lies in the fabrication method for the intermediate composite dielectric layer. Fabrication of a 1.5fF MIM capacitor: First, a layer of copper metal is deposited on a semiconductor substrate as the lower metal plate of the capacitor.

[0031] A silicon nitride layer is deposited on the copper metal layer. The thickness of the silicon nitride layer is 420 Å, which is less than the thickness of silicon nitride in existing processes.

[0032] A further oxide layer is deposited on the silicon nitride layer. This oxide layer is an ALD oxide layer, which has excellent film quality. The thickness of the ALD oxide layer is approximately 25 Å, and together with the silicon nitride layer deposited in the previous process, it forms the composite dielectric layer of the MIM capacitor.

[0033] The process conditions for the ALD oxide layer are as follows: the flow rate of AR_AMPDS (ampoule modular precursor delivery system) gas is 500-2000 sccm, of which the flow rate of N2O gas is 700-13000 sccm, the flow rate of O2 is 2000-7000 sccm, the power of high-frequency HF is 2000-5000W, and the reaction temperature is 300-400℃.

[0034] Another TiN layer with a thickness of about 1000 Å is deposited as the upper metal plate of the capacitor.

[0035] The TiN layer, ALD oxide layer, silicon nitride layer, and copper metal layer are etched to form a MIM capacitor structure.

[0036] This invention replaces the traditional single SiN dielectric layer with a composite dielectric layer formed by a SiN dielectric layer and an ALD oxide layer, and significantly improves the TDDB of the MIM structure by utilizing the excellent film quality of the ALD oxide layer.

[0037] The table below shows a comparison of the TDDB test results of the 1.5fF copper structure MIM capacitor fabricated using this invention and existing single-dielectric-layer MIM capacitors. By depositing an ALD oxide layer on SiN, the excellent film quality of the ALD oxide layer allows it to act as a buffer layer between SiN and the upper electrode TiN, significantly improving the TDDB of the MIM SiN. The test results show a very significant improvement in TDDB.

[0038] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A structure for improving the TDDB of Cu MIM capacitors, characterized in that: The capacitor includes upper and lower metal plates and a dielectric layer located between the upper and lower metal plates; The dielectric layer is a composite layer, comprising a silicon nitride layer at the bottom and an oxide layer at the top.

2. The structure for improving the TDDB of Cu MIM capacitors as described in claim 1, characterized in that: The lower and upper metal plates are made of copper and TiN, respectively.

3. The structure for improving the TDDB of Cu MIM capacitors as described in claim 1, characterized in that: The dielectric layer, wherein the upper oxide layer is an ALD oxide layer.

4. The structure for improving the TDDB of Cu MIM capacitor as described in claim 3, characterized in that: The ALD oxide layer serves as a buffer layer between the silicon nitride layer and the upper metal electrode TiN, improving device lifespan.

5. A method for improving the TDDB of Cu MIM capacitors, characterized in that: Include: First, a Cu metal layer is deposited on a semiconductor substrate as the lower metal plate of the capacitor; A silicon nitride layer is formed on the lower metal electrode plate; Further deposit an oxide layer on the silicon nitride layer; The first metal layer is deposited as the upper metal plate of the capacitor; The first metal layer, oxide layer, silicon nitride layer, and Cu metal layer are etched to form a MIM capacitor.

6. The method for improving the TDDB of Cu MIM capacitor as described in claim 1, characterized in that: The silicon nitride layer has a thickness of 420 Å.

7. The method for improving the TDDB of Cu MIM capacitor as described in claim 1, characterized in that: The oxide layer is an ALD oxide layer with a thickness of 25 Å.

8. The method for improving the TDDB of Cu MIM capacitor as described in claim 7, characterized in that: The ALD oxide layer is formed by an AR_AMPDS gas flow rate of 500–2000 sccm, wherein the N2O flow rate is 700–13000 sccm, the O2 flow rate is 2000–7000 sccm, the HF power is 2000–5000 W, and the reaction temperature is 300–400℃.

9. The method for improving the TDDB of Cu MIM capacitor as described in claim 5, characterized in that: The first metal layer is TiN with a thickness of 1000 Å.

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